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sys/dev/dpaa2/dpaa2_ni.h
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1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright © 2021-2022 Dmitry Salychev 5 * Copyright © 2022 Mathew McBride 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #ifndef _DPAA2_NI_H 30 #define _DPAA2_NI_H 31 32 #include <sys/rman.h> 33 #include <sys/bus.h> 34 #include <sys/queue.h> 35 #include <sys/taskqueue.h> 36 #include <sys/mbuf.h> 37 #include <sys/param.h> 38 #include <sys/socket.h> 39 #include <sys/buf_ring.h> 40 #include <sys/proc.h> 41 #include <sys/mutex.h> 42 43 #include <net/if.h> 44 #include <net/ethernet.h> 45 #include <net/if_media.h> 46 47 #include "dpaa2_types.h" 48 #include "dpaa2_mcp.h" 49 #include "dpaa2_swp.h" 50 #include "dpaa2_io.h" 51 #include "dpaa2_mac.h" 52 #include "dpaa2_ni_dpkg.h" 53 54 /* Name of the DPAA2 network interface. */ 55 #define DPAA2_NI_IFNAME "dpni" 56 57 /* Maximum resources per DPNI: 16 DPIOs + 16 DPCONs + 1 DPBP + 1 DPMCP. */ 58 #define DPAA2_NI_MAX_RESOURCES 34 59 60 #define DPAA2_NI_MSI_COUNT 1 /* MSIs per DPNI */ 61 #define DPAA2_NI_MAX_CHANNELS 16 /* to distribute ingress traffic to cores */ 62 #define DPAA2_NI_MAX_TCS 8 /* traffic classes per DPNI */ 63 #define DPAA2_NI_MAX_POOLS 8 /* buffer pools per DPNI */ 64 65 /* Maximum number of Rx buffers. */ 66 #define DPAA2_NI_BUFS_INIT (50u * DPAA2_SWP_BUFS_PER_CMD) 67 #define DPAA2_NI_BUFS_MAX (1 << 15) /* 15 bits for buffer index max. */ 68 69 /* Maximum number of buffers allocated per Tx ring. */ 70 #define DPAA2_NI_BUFS_PER_TX (1 << 7) 71 #define DPAA2_NI_MAX_BPTX (1 << 8) /* 8 bits for buffer index max. */ 72 73 /* Number of the DPNI statistics counters. */ 74 #define DPAA2_NI_STAT_COUNTERS 7u 75 #define DPAA2_NI_STAT_SYSCTLS 9u 76 77 /* Error and status bits in the frame annotation status word. */ 78 #define DPAA2_NI_FAS_DISC 0x80000000 /* debug frame */ 79 #define DPAA2_NI_FAS_MS 0x40000000 /* MACSEC frame */ 80 #define DPAA2_NI_FAS_PTP 0x08000000 81 #define DPAA2_NI_FAS_MC 0x04000000 /* Ethernet multicast frame */ 82 #define DPAA2_NI_FAS_BC 0x02000000 /* Ethernet broadcast frame */ 83 #define DPAA2_NI_FAS_KSE 0x00040000 84 #define DPAA2_NI_FAS_EOFHE 0x00020000 85 #define DPAA2_NI_FAS_MNLE 0x00010000 86 #define DPAA2_NI_FAS_TIDE 0x00008000 87 #define DPAA2_NI_FAS_PIEE 0x00004000 88 #define DPAA2_NI_FAS_FLE 0x00002000 /* Frame length error */ 89 #define DPAA2_NI_FAS_FPE 0x00001000 /* Frame physical error */ 90 #define DPAA2_NI_FAS_PTE 0x00000080 91 #define DPAA2_NI_FAS_ISP 0x00000040 92 #define DPAA2_NI_FAS_PHE 0x00000020 93 #define DPAA2_NI_FAS_BLE 0x00000010 94 #define DPAA2_NI_FAS_L3CV 0x00000008 /* L3 csum validation performed */ 95 #define DPAA2_NI_FAS_L3CE 0x00000004 /* L3 csum error */ 96 #define DPAA2_NI_FAS_L4CV 0x00000002 /* L4 csum validation performed */ 97 #define DPAA2_NI_FAS_L4CE 0x00000001 /* L4 csum error */ 98 99 /* Mask for errors on the ingress path. */ 100 #define DPAA2_NI_FAS_RX_ERR_MASK (DPAA2_NI_FAS_KSE | \ 101 DPAA2_NI_FAS_EOFHE | \ 102 DPAA2_NI_FAS_MNLE | \ 103 DPAA2_NI_FAS_TIDE | \ 104 DPAA2_NI_FAS_PIEE | \ 105 DPAA2_NI_FAS_FLE | \ 106 DPAA2_NI_FAS_FPE | \ 107 DPAA2_NI_FAS_PTE | \ 108 DPAA2_NI_FAS_ISP | \ 109 DPAA2_NI_FAS_PHE | \ 110 DPAA2_NI_FAS_BLE | \ 111 DPAA2_NI_FAS_L3CE | \ 112 DPAA2_NI_FAS_L4CE \ 113 ) 114 115 /* Option bits to select specific queue configuration options to apply. */ 116 #define DPAA2_NI_QUEUE_OPT_USER_CTX 0x00000001 117 #define DPAA2_NI_QUEUE_OPT_DEST 0x00000002 118 #define DPAA2_NI_QUEUE_OPT_FLC 0x00000004 119 #define DPAA2_NI_QUEUE_OPT_HOLD_ACTIVE 0x00000008 120 #define DPAA2_NI_QUEUE_OPT_SET_CGID 0x00000040 121 #define DPAA2_NI_QUEUE_OPT_CLEAR_CGID 0x00000080 122 123 /* DPNI link configuration options. */ 124 #define DPAA2_NI_LINK_OPT_AUTONEG ((uint64_t) 0x01u) 125 #define DPAA2_NI_LINK_OPT_HALF_DUPLEX ((uint64_t) 0x02u) 126 #define DPAA2_NI_LINK_OPT_PAUSE ((uint64_t) 0x04u) 127 #define DPAA2_NI_LINK_OPT_ASYM_PAUSE ((uint64_t) 0x08u) 128 #define DPAA2_NI_LINK_OPT_PFC_PAUSE ((uint64_t) 0x10u) 129 130 /* 131 * Number of times to retry a frame enqueue before giving up. Value determined 132 * empirically, in order to minimize the number of frames dropped on Tx. 133 */ 134 #define DPAA2_NI_ENQUEUE_RETRIES 10 135 136 enum dpaa2_ni_queue_type { 137 DPAA2_NI_QUEUE_RX = 0, 138 DPAA2_NI_QUEUE_TX, 139 DPAA2_NI_QUEUE_TX_CONF, 140 DPAA2_NI_QUEUE_RX_ERR 141 }; 142 143 enum dpaa2_ni_dest_type { 144 DPAA2_NI_DEST_NONE = 0, 145 DPAA2_NI_DEST_DPIO, 146 DPAA2_NI_DEST_DPCON 147 }; 148 149 enum dpaa2_ni_ofl_type { 150 DPAA2_NI_OFL_RX_L3_CSUM = 0, 151 DPAA2_NI_OFL_RX_L4_CSUM, 152 DPAA2_NI_OFL_TX_L3_CSUM, 153 DPAA2_NI_OFL_TX_L4_CSUM, 154 DPAA2_NI_OFL_FLCTYPE_HASH /* FD flow context for AIOP/CTLU */ 155 }; 156 157 /** 158 * @brief DPNI ingress traffic distribution mode. 159 */ 160 enum dpaa2_ni_dist_mode { 161 DPAA2_NI_DIST_MODE_NONE = 0, 162 DPAA2_NI_DIST_MODE_HASH, 163 DPAA2_NI_DIST_MODE_FS 164 }; 165 166 /** 167 * @brief DPNI behavior in case of errors. 168 */ 169 enum dpaa2_ni_err_action { 170 DPAA2_NI_ERR_DISCARD = 0, 171 DPAA2_NI_ERR_CONTINUE, 172 DPAA2_NI_ERR_SEND_TO_ERROR_QUEUE 173 }; 174 175 struct dpaa2_ni_channel; 176 struct dpaa2_ni_fq; 177 178 /** 179 * @brief Attributes of the DPNI object. 180 * 181 * options: ... 182 * wriop_ver: Revision of the underlying WRIOP hardware block. 183 */ 184 struct dpaa2_ni_attr { 185 uint32_t options; 186 uint16_t wriop_ver; 187 struct { 188 uint16_t fs; 189 uint8_t mac; 190 uint8_t vlan; 191 uint8_t qos; 192 } entries; 193 struct { 194 uint8_t queues; 195 uint8_t rx_tcs; 196 uint8_t tx_tcs; 197 uint8_t channels; 198 uint8_t cgs; 199 } num; 200 struct { 201 uint8_t fs; 202 uint8_t qos; 203 } key_size; 204 }; 205 206 /** 207 * @brief Tx ring. 208 * 209 * fq: Parent (TxConf) frame queue. 210 * fqid: ID of the logical Tx queue. 211 * mbuf_br: Ring buffer for mbufs to transmit. 212 * mbuf_lock: Lock for the ring buffer. 213 */ 214 struct dpaa2_ni_tx_ring { 215 struct dpaa2_ni_fq *fq; 216 uint32_t fqid; 217 uint32_t txid; /* Tx ring index */ 218 219 /* Ring buffer for indexes in "buf" array. */ 220 struct buf_ring *idx_br; 221 struct mtx lock; 222 223 /* Buffers to DMA load/unload Tx mbufs. */ 224 struct dpaa2_buf buf[DPAA2_NI_BUFS_PER_TX]; 225 }; 226 227 /** 228 * @brief A Frame Queue is the basic queuing structure used by the QMan. 229 * 230 * It comprises a list of frame descriptors (FDs), so it can be thought of 231 * as a queue of frames. 232 * 233 * NOTE: When frames on a FQ are ready to be processed, the FQ is enqueued 234 * onto a work queue (WQ). 235 * 236 * fqid: Frame queue ID, can be used to enqueue/dequeue or execute other 237 * commands on the queue through DPIO. 238 * txq_n: Number of configured Tx queues. 239 * tx_fqid: Frame queue IDs of the Tx queues which belong to the same flowid. 240 * Note that Tx queues are logical queues and not all management 241 * commands are available on these queue types. 242 * qdbin: Queue destination bin. Can be used with the DPIO enqueue 243 * operation based on QDID, QDBIN and QPRI. Note that all Tx queues 244 * with the same flowid have the same destination bin. 245 */ 246 struct dpaa2_ni_fq { 247 int (*consume)(struct dpaa2_ni_channel *, 248 struct dpaa2_ni_fq *, struct dpaa2_fd *); 249 250 struct dpaa2_ni_channel *chan; 251 uint32_t fqid; 252 uint16_t flowid; 253 uint8_t tc; 254 enum dpaa2_ni_queue_type type; 255 256 /* Optional fields (for TxConf queue). */ 257 struct dpaa2_ni_tx_ring tx_rings[DPAA2_NI_MAX_TCS]; 258 uint32_t tx_qdbin; 259 } __aligned(CACHE_LINE_SIZE); 260 261 /** 262 * @brief QBMan channel to process ingress traffic (Rx, Tx conf). 263 * 264 * NOTE: Several WQs are organized into a single WQ Channel. 265 */ 266 struct dpaa2_ni_channel { 267 device_t ni_dev; 268 device_t io_dev; 269 device_t con_dev; 270 uint16_t id; 271 uint16_t flowid; 272 273 /* For debug purposes only! */ 274 uint64_t tx_frames; 275 uint64_t tx_dropped; 276 277 /* Context to configure CDAN. */ 278 struct dpaa2_io_notif_ctx ctx; 279 280 /* Channel storage (to keep responses from VDQ command). */ 281 struct dpaa2_buf store; 282 uint32_t store_sz; /* in frames */ 283 uint32_t store_idx; /* frame index */ 284 285 /* Recycled buffers to release back to the pool. */ 286 uint32_t recycled_n; 287 bus_addr_t recycled[DPAA2_SWP_BUFS_PER_CMD]; 288 289 /* Frame queues */ 290 uint32_t rxq_n; 291 struct dpaa2_ni_fq rx_queues[DPAA2_NI_MAX_TCS]; 292 struct dpaa2_ni_fq txc_queue; 293 }; 294 295 /** 296 * @brief Configuration of the network interface queue. 297 * 298 * NOTE: This configuration is used to obtain information of a queue by 299 * DPNI_GET_QUEUE command and update it by DPNI_SET_QUEUE one. 300 * 301 * It includes binding of the queue to a DPIO or DPCON object to receive 302 * notifications and traffic on the CPU. 303 * 304 * user_ctx: (r/w) User defined data, presented along with the frames 305 * being dequeued from this queue. 306 * flow_ctx: (r/w) Set default FLC value for traffic dequeued from this queue. 307 * Please check description of FD structure for more information. 308 * Note that FLC values set using DPNI_ADD_FS_ENTRY, if any, take 309 * precedence over values per queue. 310 * dest_id: (r/w) The ID of a DPIO or DPCON object, depending on 311 * DEST_TYPE (in flags) value. This field is ignored for DEST_TYPE 312 * set to 0 (DPNI_DEST_NONE). 313 * fqid: (r) Frame queue ID, can be used to enqueue/dequeue or execute 314 * other commands on the queue through DPIO. Note that Tx queues 315 * are logical queues and not all management commands are available 316 * on these queue types. 317 * qdbin: (r) Queue destination bin. Can be used with the DPIO enqueue 318 * operation based on QDID, QDBIN and QPRI. 319 * type: Type of the queue to set configuration to. 320 * tc: Traffic class. Ignored for QUEUE_TYPE 2 and 3 (Tx confirmation 321 * and Rx error queues). 322 * idx: Selects a specific queue out of the set of queues in a TC. 323 * Accepted values are in range 0 to NUM_QUEUES–1. This field is 324 * ignored for QUEUE_TYPE 3 (Rx error queue). For access to the 325 * shared Tx confirmation queue (for Tx confirmation mode 1), this 326 * field must be set to 0xff. 327 * cgid: (r/w) Congestion group ID. 328 * chan_id: (w) Channel index to be configured. Used only when QUEUE_TYPE is 329 * set to DPNI_QUEUE_TX. 330 * priority: (r/w) Sets the priority in the destination DPCON or DPIO for 331 * dequeued traffic. Supported values are 0 to # of priorities in 332 * destination DPCON or DPIO - 1. This field is ignored for 333 * DEST_TYPE set to 0 (DPNI_DEST_NONE), except if this DPNI is in 334 * AIOP context. In that case the DPNI_SET_QUEUE can be used to 335 * override the default assigned priority of the FQ from the TC. 336 * options: Option bits selecting specific configuration options to apply. 337 * See DPAA2_NI_QUEUE_OPT_* for details. 338 * dest_type: Type of destination for dequeued traffic. 339 * cgid_valid: (r) Congestion group ID is valid. 340 * stash_control: (r/w) If true, lowest 6 bits of FLC are used for stash control. 341 * Please check description of FD structure for more information. 342 * hold_active: (r/w) If true, this flag prevents the queue from being 343 * rescheduled between DPIOs while it carries traffic and is active 344 * on one DPIO. Can help reduce reordering if one queue is services 345 * on multiple CPUs, but the queue is also more likely to be trapped 346 * in one DPIO, especially when congested. 347 */ 348 struct dpaa2_ni_queue_cfg { 349 uint64_t user_ctx; 350 uint64_t flow_ctx; 351 uint32_t dest_id; 352 uint32_t fqid; 353 uint16_t qdbin; 354 enum dpaa2_ni_queue_type type; 355 uint8_t tc; 356 uint8_t idx; 357 uint8_t cgid; 358 uint8_t chan_id; 359 uint8_t priority; 360 uint8_t options; 361 362 enum dpaa2_ni_dest_type dest_type; 363 bool cgid_valid; 364 bool stash_control; 365 bool hold_active; 366 }; 367 368 /** 369 * @brief Buffer layout attributes. 370 * 371 * pd_size: Size kept for private data (in bytes). 372 * fd_align: Frame data alignment. 373 * head_size: Data head room. 374 * tail_size: Data tail room. 375 * options: ... 376 * pass_timestamp: Timestamp is included in the buffer layout. 377 * pass_parser_result: Parsing results are included in the buffer layout. 378 * pass_frame_status: Frame status is included in the buffer layout. 379 * pass_sw_opaque: SW annotation is activated. 380 * queue_type: Type of a queue this configuration applies to. 381 */ 382 struct dpaa2_ni_buf_layout { 383 uint16_t pd_size; 384 uint16_t fd_align; 385 uint16_t head_size; 386 uint16_t tail_size; 387 uint16_t options; 388 bool pass_timestamp; 389 bool pass_parser_result; 390 bool pass_frame_status; 391 bool pass_sw_opaque; 392 enum dpaa2_ni_queue_type queue_type; 393 }; 394 395 /** 396 * @brief Buffer pools configuration for a network interface. 397 */ 398 struct dpaa2_ni_pools_cfg { 399 uint8_t pools_num; 400 struct { 401 uint32_t bp_obj_id; 402 uint16_t buf_sz; 403 int backup_flag; /* 0 - regular pool, 1 - backup pool */ 404 } pools[DPAA2_NI_MAX_POOLS]; 405 }; 406 407 /** 408 * @brief Errors behavior configuration for a network interface. 409 * 410 * err_mask: The errors mask to configure. 411 * action: Desired action for the errors selected in the mask. 412 * set_err_fas: Set to true to mark the errors in frame annotation 413 * status (FAS); relevant for non-discard actions only. 414 */ 415 struct dpaa2_ni_err_cfg { 416 uint32_t err_mask; 417 enum dpaa2_ni_err_action action; 418 bool set_err_fas; 419 }; 420 421 /** 422 * @brief Link configuration. 423 * 424 * options: Mask of available options. 425 * adv_speeds: Speeds that are advertised for autoneg. 426 * rate: Rate in Mbps. 427 */ 428 struct dpaa2_ni_link_cfg { 429 uint64_t options; 430 uint64_t adv_speeds; 431 uint32_t rate; 432 }; 433 434 /** 435 * @brief Link state. 436 * 437 * options: Mask of available options. 438 * adv_speeds: Speeds that are advertised for autoneg. 439 * sup_speeds: Speeds capability of the PHY. 440 * rate: Rate in Mbps. 441 * link_up: Link state (true if link is up, false otherwise). 442 * state_valid: Ignore/Update the state of the link. 443 */ 444 struct dpaa2_ni_link_state { 445 uint64_t options; 446 uint64_t adv_speeds; 447 uint64_t sup_speeds; 448 uint32_t rate; 449 bool link_up; 450 bool state_valid; 451 }; 452 453 /** 454 * @brief QoS table configuration. 455 * 456 * kcfg_busaddr: Address of the buffer in I/O virtual address space which 457 * holds the QoS table key configuration. 458 * default_tc: Default traffic class to use in case of a lookup miss in 459 * the QoS table. 460 * discard_on_miss: Set to true to discard frames in case of no match. 461 * Default traffic class will be used otherwise. 462 * keep_entries: Set to true to keep existing QoS table entries. This 463 * option will work properly only for DPNI objects created 464 * with DPNI_OPT_HAS_KEY_MASKING option. 465 */ 466 struct dpaa2_ni_qos_table { 467 uint64_t kcfg_busaddr; 468 uint8_t default_tc; 469 bool discard_on_miss; 470 bool keep_entries; 471 }; 472 473 /** 474 * @brief Context to add multicast physical addresses to the filter table. 475 * 476 * ifp: Network interface associated with the context. 477 * error: Result of the last MC command. 478 * nent: Number of entries added. 479 */ 480 struct dpaa2_ni_mcaddr_ctx { 481 struct ifnet *ifp; 482 int error; 483 int nent; 484 }; 485 486 struct dpaa2_eth_dist_fields { 487 uint64_t rxnfc_field; 488 enum net_prot cls_prot; 489 int cls_field; 490 int size; 491 uint64_t id; 492 }; 493 494 struct dpni_mask_cfg { 495 uint8_t mask; 496 uint8_t offset; 497 } __packed; 498 499 struct dpni_dist_extract { 500 uint8_t prot; 501 uint8_t efh_type; /* EFH type is in the 4 LSBs. */ 502 uint8_t size; 503 uint8_t offset; 504 uint32_t field; 505 uint8_t hdr_index; 506 uint8_t constant; 507 uint8_t num_of_repeats; 508 uint8_t num_of_byte_masks; 509 uint8_t extract_type; /* Extraction type is in the 4 LSBs */ 510 uint8_t _reserved[3]; 511 struct dpni_mask_cfg masks[4]; 512 } __packed; 513 514 struct dpni_ext_set_rx_tc_dist { 515 uint8_t num_extracts; 516 uint8_t _reserved[7]; 517 struct dpni_dist_extract extracts[DPKG_MAX_NUM_OF_EXTRACTS]; 518 } __packed; 519 520 /** 521 * @brief Software context for the DPAA2 Network Interface driver. 522 */ 523 struct dpaa2_ni_softc { 524 device_t dev; 525 struct resource *res[DPAA2_NI_MAX_RESOURCES]; 526 uint16_t api_major; 527 uint16_t api_minor; 528 uint64_t rx_hash_fields; 529 uint16_t tx_data_off; 530 uint16_t tx_qdid; 531 uint32_t link_options; 532 int link_state; 533 534 uint16_t buf_align; 535 uint16_t buf_sz; 536 537 /* For debug purposes only! */ 538 uint64_t rx_anomaly_frames; 539 uint64_t rx_single_buf_frames; 540 uint64_t rx_sg_buf_frames; 541 uint64_t rx_enq_rej_frames; 542 uint64_t rx_ieoi_err_frames; 543 uint64_t tx_single_buf_frames; 544 uint64_t tx_sg_frames; 545 546 /* Attributes of the DPAA2 network interface. */ 547 struct dpaa2_ni_attr attr; 548 549 /* Helps to send commands to MC. */ 550 struct dpaa2_cmd *cmd; 551 uint16_t rc_token; 552 uint16_t ni_token; 553 554 /* For network interface and miibus. */ 555 struct ifnet *ifp; 556 uint32_t if_flags; 557 struct mtx lock; 558 device_t miibus; 559 struct mii_data *mii; 560 boolean_t fixed_link; 561 struct ifmedia fixed_ifmedia; 562 int media_status; 563 564 /* DMA resources */ 565 bus_dma_tag_t bp_dmat; /* for buffer pool */ 566 bus_dma_tag_t tx_dmat; /* for Tx buffers */ 567 bus_dma_tag_t st_dmat; /* for channel storage */ 568 bus_dma_tag_t rxd_dmat; /* for Rx distribution key */ 569 bus_dma_tag_t qos_dmat; /* for QoS table key */ 570 bus_dma_tag_t sgt_dmat; /* for scatter/gather tables */ 571 572 struct dpaa2_buf qos_kcfg; /* QoS table key config. */ 573 struct dpaa2_buf rxd_kcfg; /* Rx distribution key config. */ 574 575 /* Channels and RxError frame queue */ 576 uint32_t chan_n; 577 struct dpaa2_ni_channel *channels[DPAA2_NI_MAX_CHANNELS]; 578 struct dpaa2_ni_fq rxe_queue; /* one per network interface */ 579 580 /* Rx buffers for buffer pool. */ 581 struct dpaa2_atomic buf_num; 582 struct dpaa2_atomic buf_free; /* for sysctl(9) only */ 583 struct dpaa2_buf buf[DPAA2_NI_BUFS_MAX]; 584 585 /* Interrupts */ 586 int irq_rid[DPAA2_NI_MSI_COUNT]; 587 struct resource *irq_res; 588 void *intr; /* interrupt handle */ 589 590 /* Tasks */ 591 struct taskqueue *bp_taskq; 592 struct task bp_task; 593 594 /* Callouts */ 595 struct callout mii_callout; 596 597 struct { 598 uint32_t dpmac_id; 599 uint8_t addr[ETHER_ADDR_LEN]; 600 device_t phy_dev; 601 int phy_loc; 602 } mac; /* Info about connected DPMAC (if exists). */ 603 }; 604 605 extern struct resource_spec dpaa2_ni_spec[]; 606 607 #endif /* _DPAA2_NI_H */
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