1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright © 2021-2022 Dmitry Salychev
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 */
27
28 #ifndef _DPAA2_TYPES_H
29 #define _DPAA2_TYPES_H
30
31 #include <machine/atomic.h>
32
33 /**
34 * @brief Types of the DPAA2 devices.
35 */
36 enum dpaa2_dev_type {
37 DPAA2_DEV_MC = 7500, /* Management Complex (firmware bus) */
38 DPAA2_DEV_RC, /* Resource Container (firmware bus) */
39 DPAA2_DEV_IO, /* I/O object (to work with QBMan portal) */
40 DPAA2_DEV_NI, /* Network Interface */
41 DPAA2_DEV_MCP, /* MC portal */
42 DPAA2_DEV_BP, /* Buffer Pool */
43 DPAA2_DEV_CON, /* Concentrator */
44 DPAA2_DEV_MAC, /* MAC object */
45 DPAA2_DEV_MUX, /* MUX (Datacenter bridge) object */
46 DPAA2_DEV_SW, /* Ethernet Switch */
47
48 DPAA2_DEV_NOTYPE /* Shouldn't be assigned to any DPAA2 device. */
49 };
50
51 /**
52 * @brief Types of the DPAA2 buffers.
53 */
54 enum dpaa2_buf_type {
55 DPAA2_BUF_RX = 75, /* Rx buffer */
56 DPAA2_BUF_TX, /* Tx buffer */
57 DPAA2_BUF_STORE /* Channel storage, key configuration */
58 };
59
60 /**
61 * @brief DMA-mapped buffer (for Rx/Tx buffers, channel storage, etc.).
62 */
63 struct dpaa2_buf {
64 enum dpaa2_buf_type type;
65 union {
66 struct {
67 bus_dma_tag_t dmat; /* DMA tag for this buffer */
68 bus_dmamap_t dmap;
69 bus_addr_t paddr;
70 void *vaddr;
71
72 struct mbuf *m; /* associated mbuf */
73 } rx;
74 struct {
75 bus_dma_tag_t dmat; /* DMA tag for this buffer */
76 bus_dmamap_t dmap;
77 bus_addr_t paddr;
78 void *vaddr;
79
80 struct mbuf *m; /* associated mbuf */
81 uint64_t idx;
82
83 /* for scatter/gather table */
84 bus_dma_tag_t sgt_dmat;
85 bus_dmamap_t sgt_dmap;
86 bus_addr_t sgt_paddr;
87 void *sgt_vaddr;
88 } tx;
89 struct {
90 bus_dma_tag_t dmat; /* DMA tag for this buffer */
91 bus_dmamap_t dmap;
92 bus_addr_t paddr;
93 void *vaddr;
94 } store;
95 };
96 };
97
98 struct dpaa2_atomic {
99 volatile int counter;
100 };
101
102 /* Handy wrappers over atomic operations. */
103 #define DPAA2_ATOMIC_XCHG(a, val) \
104 (atomic_swap_int(&(a)->counter, (val)))
105 #define DPAA2_ATOMIC_READ(a) \
106 (atomic_load_acq_int(&(a)->counter))
107 #define DPAA2_ATOMIC_ADD(a, val) \
108 (atomic_add_acq_int(&(a)->counter, (val)))
109
110 /* Convert DPAA2 type to/from string. */
111 const char *dpaa2_ttos(enum dpaa2_dev_type type);
112 enum dpaa2_dev_type dpaa2_stot(const char *str);
113
114 #endif /* _DPAA2_TYPES_H */
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