i915_drv.h

Version: - FREEBSD - FREEBSD-13-STABLE - FREEBSD-13-0 - FREEBSD-12-STABLE - FREEBSD-12-0 - FREEBSD-11-STABLE - FREEBSD-11-0 - FREEBSD-10-STABLE - FREEBSD-10-0 - FREEBSD-9-STABLE - FREEBSD-9-0 - FREEBSD-8-STABLE - FREEBSD-8-0 - FREEBSD-7-STABLE - FREEBSD-7-0 - FREEBSD-6-STABLE - FREEBSD-6-0 - FREEBSD-5-STABLE - FREEBSD-5-0 - FREEBSD-4-STABLE - FREEBSD-3-STABLE - FREEBSD22 - l41 - OPENBSD - linux-2.6 - MK84 - PLAN9 - xnu-8792
SearchContext: - none - 3 - 10
    1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
    2  */
    3 /*
    4  * 
    5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
    6  * All Rights Reserved.
    7  * 
    8  * Permission is hereby granted, free of charge, to any person obtaining a
    9  * copy of this software and associated documentation files (the
   10  * "Software"), to deal in the Software without restriction, including
   11  * without limitation the rights to use, copy, modify, merge, publish,
   12  * distribute, sub license, and/or sell copies of the Software, and to
   13  * permit persons to whom the Software is furnished to do so, subject to
   14  * the following conditions:
   15  * 
   16  * The above copyright notice and this permission notice (including the
   17  * next paragraph) shall be included in all copies or substantial portions
   18  * of the Software.
   19  * 
   20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
   21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
   22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
   23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
   24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
   25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
   26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
   27  * 
   28  */
   29 
   30 #include <sys/cdefs.h>
   31 __FBSDID("$FreeBSD: releng/6.4/sys/dev/drm/i915_drv.h 166475 2007-02-03 20:01:54Z flz $");
   32 
   33 #ifndef _I915_DRV_H_
   34 #define _I915_DRV_H_
   35 
   36 /* General customization:
   37  */
   38 
   39 #define DRIVER_AUTHOR           "Tungsten Graphics, Inc."
   40 
   41 #define DRIVER_NAME             "i915"
   42 #define DRIVER_DESC             "Intel Graphics"
   43 #define DRIVER_DATE             "20060119"
   44 
   45 /* Interface history:
   46  *
   47  * 1.1: Original.
   48  * 1.2: Add Power Management
   49  * 1.3: Add vblank support
   50  * 1.4: Fix cmdbuffer path, add heap destroy
   51  * 1.5: Add vblank pipe configuration
   52  */
   53 #define DRIVER_MAJOR            1
   54 #define DRIVER_MINOR            5
   55 #define DRIVER_PATCHLEVEL       0
   56 
   57 typedef struct _drm_i915_ring_buffer {
   58         int tail_mask;
   59         unsigned long Start;
   60         unsigned long End;
   61         unsigned long Size;
   62         u8 *virtual_start;
   63         int head;
   64         int tail;
   65         int space;
   66         drm_local_map_t map;
   67 } drm_i915_ring_buffer_t;
   68 
   69 struct mem_block {
   70         struct mem_block *next;
   71         struct mem_block *prev;
   72         int start;
   73         int size;
   74         DRMFILE filp;           /* 0: free, -1: heap, other: real files */
   75 };
   76 
   77 typedef struct drm_i915_private {
   78         drm_local_map_t *sarea;
   79         drm_local_map_t *mmio_map;
   80 
   81         drm_i915_sarea_t *sarea_priv;
   82         drm_i915_ring_buffer_t ring;
   83 
   84         drm_dma_handle_t *status_page_dmah;
   85         void *hw_status_page;
   86         dma_addr_t dma_status_page;
   87         unsigned long counter;
   88 
   89         int back_offset;
   90         int front_offset;
   91         int current_page;
   92         int page_flipping;
   93         int use_mi_batchbuffer_start;
   94 
   95         wait_queue_head_t irq_queue;
   96         atomic_t irq_received;
   97         atomic_t irq_emitted;
   98 
   99         int tex_lru_log_granularity;
  100         int allow_batchbuffer;
  101         struct mem_block *agp_heap;
  102         unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;
  103         int vblank_pipe;
  104 } drm_i915_private_t;
  105 
  106 extern drm_ioctl_desc_t i915_ioctls[];
  107 extern int i915_max_ioctl;
  108 
  109                                 /* i915_dma.c */
  110 extern void i915_kernel_lost_context(drm_device_t * dev);
  111 extern int i915_driver_load(struct drm_device *, unsigned long flags);
  112 extern void i915_driver_lastclose(drm_device_t * dev);
  113 extern void i915_driver_preclose(drm_device_t * dev, DRMFILE filp);
  114 extern int i915_driver_device_is_agp(drm_device_t * dev);
  115 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
  116                               unsigned long arg);
  117 
  118 /* i915_irq.c */
  119 extern int i915_irq_emit(DRM_IOCTL_ARGS);
  120 extern int i915_irq_wait(DRM_IOCTL_ARGS);
  121 
  122 extern int i915_driver_vblank_wait(drm_device_t *dev, unsigned int *sequence);
  123 extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS);
  124 extern void i915_driver_irq_preinstall(drm_device_t * dev);
  125 extern void i915_driver_irq_postinstall(drm_device_t * dev);
  126 extern void i915_driver_irq_uninstall(drm_device_t * dev);
  127 extern int i915_vblank_pipe_set(DRM_IOCTL_ARGS);
  128 extern int i915_vblank_pipe_get(DRM_IOCTL_ARGS);
  129 
  130 /* i915_mem.c */
  131 extern int i915_mem_alloc(DRM_IOCTL_ARGS);
  132 extern int i915_mem_free(DRM_IOCTL_ARGS);
  133 extern int i915_mem_init_heap(DRM_IOCTL_ARGS);
  134 extern int i915_mem_destroy_heap(DRM_IOCTL_ARGS);
  135 extern void i915_mem_takedown(struct mem_block **heap);
  136 extern void i915_mem_release(drm_device_t * dev,
  137                              DRMFILE filp, struct mem_block *heap);
  138 
  139 #define I915_READ(reg)          DRM_READ32(dev_priv->mmio_map, (reg))
  140 #define I915_WRITE(reg,val)     DRM_WRITE32(dev_priv->mmio_map, (reg), (val))
  141 #define I915_READ16(reg)        DRM_READ16(dev_priv->mmio_map, (reg))
  142 #define I915_WRITE16(reg,val)   DRM_WRITE16(dev_priv->mmio_map, (reg), (val))
  143 
  144 #define I915_VERBOSE 0
  145 
  146 #define RING_LOCALS     unsigned int outring, ringmask, outcount; \
  147                         volatile char *virt;
  148 
  149 #define BEGIN_LP_RING(n) do {                           \
  150         if (I915_VERBOSE)                               \
  151                 DRM_DEBUG("BEGIN_LP_RING(%d) in %s\n",  \
  152                                  (n), __FUNCTION__);           \
  153         if (dev_priv->ring.space < (n)*4)                      \
  154                 i915_wait_ring(dev, (n)*4, __FUNCTION__);      \
  155         outcount = 0;                                   \
  156         outring = dev_priv->ring.tail;                  \
  157         ringmask = dev_priv->ring.tail_mask;            \
  158         virt = dev_priv->ring.virtual_start;            \
  159 } while (0)
  160 
  161 #define OUT_RING(n) do {                                        \
  162         if (I915_VERBOSE) DRM_DEBUG("   OUT_RING %x\n", (int)(n));      \
  163         *(volatile unsigned int *)(virt + outring) = (n);               \
  164         outcount++;                                             \
  165         outring += 4;                                           \
  166         outring &= ringmask;                                    \
  167 } while (0)
  168 
  169 #define ADVANCE_LP_RING() do {                                          \
  170         if (I915_VERBOSE) DRM_DEBUG("ADVANCE_LP_RING %x\n", outring);   \
  171         dev_priv->ring.tail = outring;                                  \
  172         dev_priv->ring.space -= outcount * 4;                           \
  173         I915_WRITE(LP_RING + RING_TAIL, outring);                       \
  174 } while(0)
  175 
  176 extern int i915_wait_ring(drm_device_t * dev, int n, const char *caller);
  177 
  178 #define GFX_OP_USER_INTERRUPT           ((0<<29)|(2<<23))
  179 #define GFX_OP_BREAKPOINT_INTERRUPT     ((0<<29)|(1<<23))
  180 #define CMD_REPORT_HEAD                 (7<<23)
  181 #define CMD_STORE_DWORD_IDX             ((0x21<<23) | 0x1)
  182 #define CMD_OP_BATCH_BUFFER  ((0x0<<29)|(0x30<<23)|0x1)
  183 
  184 #define INST_PARSER_CLIENT   0x00000000
  185 #define INST_OP_FLUSH        0x02000000
  186 #define INST_FLUSH_MAP_CACHE 0x00000001
  187 
  188 #define BB1_START_ADDR_MASK   (~0x7)
  189 #define BB1_PROTECTED         (1<<0)
  190 #define BB1_UNPROTECTED       (0<<0)
  191 #define BB2_END_ADDR_MASK     (~0x7)
  192 
  193 #define I915REG_HWSTAM          0x02098
  194 #define I915REG_INT_IDENTITY_R  0x020a4
  195 #define I915REG_INT_MASK_R      0x020a8
  196 #define I915REG_INT_ENABLE_R    0x020a0
  197 
  198 #define SRX_INDEX               0x3c4
  199 #define SRX_DATA                0x3c5
  200 #define SR01                    1
  201 #define SR01_SCREEN_OFF         (1<<5)
  202 
  203 #define PPCR                    0x61204
  204 #define PPCR_ON                 (1<<0)
  205 
  206 #define DVOB                    0x61140
  207 #define DVOB_ON                 (1<<31)
  208 #define DVOC                    0x61160
  209 #define DVOC_ON                 (1<<31)
  210 #define LVDS                    0x61180
  211 #define LVDS_ON                 (1<<31)
  212 
  213 #define ADPA                    0x61100
  214 #define ADPA_DPMS_MASK          (~(3<<10))
  215 #define ADPA_DPMS_ON            (0<<10)
  216 #define ADPA_DPMS_SUSPEND       (1<<10)
  217 #define ADPA_DPMS_STANDBY       (2<<10)
  218 #define ADPA_DPMS_OFF           (3<<10)
  219 
  220 #define NOPID                   0x2094
  221 #define LP_RING                 0x2030
  222 #define HP_RING                 0x2040
  223 #define RING_TAIL               0x00
  224 #define TAIL_ADDR               0x001FFFF8
  225 #define RING_HEAD               0x04
  226 #define HEAD_WRAP_COUNT         0xFFE00000
  227 #define HEAD_WRAP_ONE           0x00200000
  228 #define HEAD_ADDR               0x001FFFFC
  229 #define RING_START              0x08
  230 #define START_ADDR              0x0xFFFFF000
  231 #define RING_LEN                0x0C
  232 #define RING_NR_PAGES           0x001FF000
  233 #define RING_REPORT_MASK        0x00000006
  234 #define RING_REPORT_64K         0x00000002
  235 #define RING_REPORT_128K        0x00000004
  236 #define RING_NO_REPORT          0x00000000
  237 #define RING_VALID_MASK         0x00000001
  238 #define RING_VALID              0x00000001
  239 #define RING_INVALID            0x00000000
  240 
  241 #define GFX_OP_SCISSOR         ((0x3<<29)|(0x1c<<24)|(0x10<<19))
  242 #define SC_UPDATE_SCISSOR       (0x1<<1)
  243 #define SC_ENABLE_MASK          (0x1<<0)
  244 #define SC_ENABLE               (0x1<<0)
  245 
  246 #define GFX_OP_SCISSOR_INFO    ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
  247 #define SCI_YMIN_MASK      (0xffff<<16)
  248 #define SCI_XMIN_MASK      (0xffff<<0)
  249 #define SCI_YMAX_MASK      (0xffff<<16)
  250 #define SCI_XMAX_MASK      (0xffff<<0)
  251 
  252 #define GFX_OP_SCISSOR_ENABLE    ((0x3<<29)|(0x1c<<24)|(0x10<<19))
  253 #define GFX_OP_SCISSOR_RECT      ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)
  254 #define GFX_OP_COLOR_FACTOR      ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)
  255 #define GFX_OP_STIPPLE           ((0x3<<29)|(0x1d<<24)|(0x83<<16))
  256 #define GFX_OP_MAP_INFO          ((0x3<<29)|(0x1d<<24)|0x4)
  257 #define GFX_OP_DESTBUFFER_VARS   ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)
  258 #define GFX_OP_DRAWRECT_INFO     ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
  259 
  260 #define GFX_OP_DRAWRECT_INFO_I965  ((0x7900<<16)|0x2)
  261 
  262 #define MI_BATCH_BUFFER         ((0x30<<23)|1)
  263 #define MI_BATCH_BUFFER_START   (0x31<<23)
  264 #define MI_BATCH_BUFFER_END     (0xA<<23)
  265 #define MI_BATCH_NON_SECURE     (1)
  266 
  267 #define MI_WAIT_FOR_EVENT       ((0x3<<23))
  268 #define MI_WAIT_FOR_PLANE_A_FLIP      (1<<2)
  269 #define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)
  270 
  271 #define MI_LOAD_SCAN_LINES_INCL  ((0x12<<23))
  272 
  273 #define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)
  274 #define ASYNC_FLIP                (1<<22)
  275 
  276 #define CMD_OP_DESTBUFFER_INFO   ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
  277 
  278 #define READ_BREADCRUMB(dev_priv)  (((u32*)(dev_priv->hw_status_page))[5])
  279 
  280 #endif
Cache object: dedbfa0aca6f3c45a21929580ea5bfbd
[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]
This page is part of the FreeBSD/Linux Linux Kernel Cross-Reference, and was automatically generated using a modified version of the LXR engine.
FreeBSD/Linux Kernel Cross Reference sys/dev/drm/i915_drv.h

FreeBSD/Linux Kernel Cross Reference
sys/dev/drm/i915_drv.h
