Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/dev/drm/mga_drv.h
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1 /* mga_drv.h -- Private header for the Matrox G200/G400 driver -*- linux-c -*- 2 * Created: Mon Dec 13 01:50:01 1999 by jhartmann@precisioninsight.com 3 * 4 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. 5 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 6 * All rights reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice (including the next 16 * paragraph) shall be included in all copies or substantial portions of the 17 * Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 22 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 25 * OTHER DEALINGS IN THE SOFTWARE. 26 * 27 * Authors: 28 * Gareth Hughes <gareth@valinux.com> 29 * 30 * $FreeBSD: releng/5.0/sys/dev/drm/mga_drv.h 97683 2002-05-31 23:19:50Z anholt $ 31 */ 32 33 #ifndef __MGA_DRV_H__ 34 #define __MGA_DRV_H__ 35 36 #ifndef u8 37 #define u8 u_int8_t 38 #define u16 u_int16_t 39 #define u32 u_int32_t 40 #endif 41 42 typedef struct drm_mga_primary_buffer { 43 u8 *start; 44 u8 *end; 45 int size; 46 47 u32 tail; 48 int space; 49 volatile long wrapped; 50 51 volatile u32 *status; 52 53 u32 last_flush; 54 u32 last_wrap; 55 56 u32 high_mark; 57 58 spinlock_t list_lock; 59 } drm_mga_primary_buffer_t; 60 61 typedef struct drm_mga_freelist { 62 struct drm_mga_freelist *next; 63 struct drm_mga_freelist *prev; 64 drm_mga_age_t age; 65 drm_buf_t *buf; 66 } drm_mga_freelist_t; 67 68 typedef struct { 69 drm_mga_freelist_t *list_entry; 70 int discard; 71 int dispatched; 72 } drm_mga_buf_priv_t; 73 74 typedef struct drm_mga_private { 75 drm_mga_primary_buffer_t prim; 76 drm_mga_sarea_t *sarea_priv; 77 78 drm_mga_freelist_t *head; 79 drm_mga_freelist_t *tail; 80 81 unsigned int warp_pipe; 82 unsigned long warp_pipe_phys[MGA_MAX_WARP_PIPES]; 83 84 int chipset; 85 int usec_timeout; 86 87 u32 clear_cmd; 88 u32 maccess; 89 90 unsigned int fb_cpp; 91 unsigned int front_offset; 92 unsigned int front_pitch; 93 unsigned int back_offset; 94 unsigned int back_pitch; 95 96 unsigned int depth_cpp; 97 unsigned int depth_offset; 98 unsigned int depth_pitch; 99 100 unsigned int texture_offset; 101 unsigned int texture_size; 102 103 drm_map_t *sarea; 104 drm_map_t *fb; 105 drm_map_t *mmio; 106 drm_map_t *status; 107 drm_map_t *warp; 108 drm_map_t *primary; 109 drm_map_t *buffers; 110 drm_map_t *agp_textures; 111 } drm_mga_private_t; 112 113 /* mga_dma.c */ 114 extern int mga_dma_init( DRM_OS_IOCTL ); 115 extern int mga_dma_flush( DRM_OS_IOCTL ); 116 extern int mga_dma_reset( DRM_OS_IOCTL ); 117 extern int mga_dma_buffers( DRM_OS_IOCTL ); 118 119 extern int mga_do_wait_for_idle( drm_mga_private_t *dev_priv ); 120 extern int mga_do_dma_idle( drm_mga_private_t *dev_priv ); 121 extern int mga_do_dma_reset( drm_mga_private_t *dev_priv ); 122 extern int mga_do_engine_reset( drm_mga_private_t *dev_priv ); 123 extern int mga_do_cleanup_dma( drm_device_t *dev ); 124 125 extern void mga_do_dma_flush( drm_mga_private_t *dev_priv ); 126 extern void mga_do_dma_wrap_start( drm_mga_private_t *dev_priv ); 127 extern void mga_do_dma_wrap_end( drm_mga_private_t *dev_priv ); 128 129 extern int mga_freelist_put( drm_device_t *dev, drm_buf_t *buf ); 130 131 /* mga_state.c */ 132 extern int mga_dma_clear( DRM_OS_IOCTL ); 133 extern int mga_dma_swap( DRM_OS_IOCTL ); 134 extern int mga_dma_vertex( DRM_OS_IOCTL ); 135 extern int mga_dma_indices( DRM_OS_IOCTL ); 136 extern int mga_dma_iload( DRM_OS_IOCTL ); 137 extern int mga_dma_blit( DRM_OS_IOCTL ); 138 139 /* mga_warp.c */ 140 extern int mga_warp_install_microcode( drm_mga_private_t *dev_priv ); 141 extern int mga_warp_init( drm_mga_private_t *dev_priv ); 142 143 #define mga_flush_write_combine() DRM_OS_READMEMORYBARRIER 144 145 #define MGA_BASE( reg ) ((unsigned long)(dev_priv->mmio->handle)) 146 #define MGA_ADDR( reg ) (MGA_BASE(reg) + reg) 147 148 #define MGA_DEREF( reg ) *(volatile u32 *)MGA_ADDR( reg ) 149 #define MGA_DEREF8( reg ) *(volatile u8 *)MGA_ADDR( reg ) 150 151 #ifdef __alpha__ 152 #define MGA_READ( reg ) (_MGA_READ((u32 *)MGA_ADDR(reg))) 153 #define MGA_WRITE( reg, val ) do { wmb(); MGA_DEREF( reg ) = val; } while (0) 154 #define MGA_WRITE8( reg, val ) do { wmb(); MGA_DEREF8( reg ) = val; } while (0) 155 156 static inline u32 _MGA_READ(u32 *addr) 157 { 158 mb(); 159 return *(volatile u32 *)addr; 160 } 161 162 #else 163 #define MGA_READ( reg ) MGA_DEREF( reg ) 164 #define MGA_WRITE( reg, val ) do { MGA_DEREF( reg ) = val; } while (0) 165 #define MGA_WRITE8( reg, val ) do { MGA_DEREF8( reg ) = val; } while (0) 166 #endif 167 168 #define DWGREG0 0x1c00 169 #define DWGREG0_END 0x1dff 170 #define DWGREG1 0x2c00 171 #define DWGREG1_END 0x2dff 172 173 #define ISREG0(r) (r >= DWGREG0 && r <= DWGREG0_END) 174 #define DMAREG0(r) (u8)((r - DWGREG0) >> 2) 175 #define DMAREG1(r) (u8)(((r - DWGREG1) >> 2) | 0x80) 176 #define DMAREG(r) (ISREG0(r) ? DMAREG0(r) : DMAREG1(r)) 177 178 179 180 /* ================================================================ 181 * Helper macross... 182 */ 183 184 #define MGA_EMIT_STATE( dev_priv, dirty ) \ 185 do { \ 186 if ( (dirty) & ~MGA_UPLOAD_CLIPRECTS ) { \ 187 if ( dev_priv->chipset == MGA_CARD_TYPE_G400 ) { \ 188 mga_g400_emit_state( dev_priv ); \ 189 } else { \ 190 mga_g200_emit_state( dev_priv ); \ 191 } \ 192 } \ 193 } while (0) 194 195 #define LOCK_TEST_WITH_RETURN( dev ) \ 196 do { \ 197 if ( !_DRM_LOCK_IS_HELD( dev->lock.hw_lock->lock ) || \ 198 dev->lock.pid != DRM_OS_CURRENTPID ) { \ 199 DRM_ERROR( "%s called without lock held\n", __func__ ); \ 200 return DRM_OS_ERR(EINVAL); \ 201 } \ 202 } while (0) 203 204 #define WRAP_TEST_WITH_RETURN( dev_priv ) \ 205 do { \ 206 if ( test_bit( 0, &dev_priv->prim.wrapped ) ) { \ 207 if ( mga_is_idle( dev_priv ) ) { \ 208 mga_do_dma_wrap_end( dev_priv ); \ 209 } else if ( dev_priv->prim.space < \ 210 dev_priv->prim.high_mark ) { \ 211 if ( MGA_DMA_DEBUG ) \ 212 DRM_INFO( "%s: wrap...\n", __func__ ); \ 213 return DRM_OS_ERR(EBUSY); \ 214 } \ 215 } \ 216 } while (0) 217 218 #define WRAP_WAIT_WITH_RETURN( dev_priv ) \ 219 do { \ 220 if ( test_bit( 0, &dev_priv->prim.wrapped ) ) { \ 221 if ( mga_do_wait_for_idle( dev_priv ) ) { \ 222 if ( MGA_DMA_DEBUG ) \ 223 DRM_INFO( "%s: wrap...\n", __func__ ); \ 224 return DRM_OS_ERR(EBUSY); \ 225 } \ 226 mga_do_dma_wrap_end( dev_priv ); \ 227 } \ 228 } while (0) 229 230 231 /* ================================================================ 232 * Primary DMA command stream 233 */ 234 235 #define MGA_VERBOSE 0 236 237 #define DMA_LOCALS unsigned int write; volatile u8 *prim; 238 239 #define DMA_BLOCK_SIZE (5 * sizeof(u32)) 240 241 #define BEGIN_DMA( n ) \ 242 do { \ 243 if ( MGA_VERBOSE ) { \ 244 DRM_INFO( "BEGIN_DMA( %d ) in %s\n", \ 245 (n), __func__ ); \ 246 DRM_INFO( " space=0x%x req=0x%x\n", \ 247 dev_priv->prim.space, (n) * DMA_BLOCK_SIZE ); \ 248 } \ 249 prim = dev_priv->prim.start; \ 250 write = dev_priv->prim.tail; \ 251 } while (0) 252 253 #define BEGIN_DMA_WRAP() \ 254 do { \ 255 if ( MGA_VERBOSE ) { \ 256 DRM_INFO( "BEGIN_DMA() in %s\n", __func__ ); \ 257 DRM_INFO( " space=0x%x\n", dev_priv->prim.space ); \ 258 } \ 259 prim = dev_priv->prim.start; \ 260 write = dev_priv->prim.tail; \ 261 } while (0) 262 263 #define ADVANCE_DMA() \ 264 do { \ 265 dev_priv->prim.tail = write; \ 266 if ( MGA_VERBOSE ) { \ 267 DRM_INFO( "ADVANCE_DMA() tail=0x%05x sp=0x%x\n", \ 268 write, dev_priv->prim.space ); \ 269 } \ 270 } while (0) 271 272 #define FLUSH_DMA() \ 273 do { \ 274 if ( 0 ) { \ 275 DRM_INFO( "%s:\n", __func__ ); \ 276 DRM_INFO( " tail=0x%06x head=0x%06lx\n", \ 277 dev_priv->prim.tail, \ 278 MGA_READ( MGA_PRIMADDRESS ) - \ 279 dev_priv->primary->offset ); \ 280 } \ 281 if ( !test_bit( 0, &dev_priv->prim.wrapped ) ) { \ 282 if ( dev_priv->prim.space < \ 283 dev_priv->prim.high_mark ) { \ 284 mga_do_dma_wrap_start( dev_priv ); \ 285 } else { \ 286 mga_do_dma_flush( dev_priv ); \ 287 } \ 288 } \ 289 } while (0) 290 291 /* Never use this, always use DMA_BLOCK(...) for primary DMA output. 292 */ 293 #define DMA_WRITE( offset, val ) \ 294 do { \ 295 if ( MGA_VERBOSE ) { \ 296 DRM_INFO( " DMA_WRITE( 0x%08x ) at 0x%04x\n", \ 297 (u32)(val), write + (offset) * sizeof(u32) ); \ 298 } \ 299 *(volatile u32 *)(prim + write + (offset) * sizeof(u32)) = val; \ 300 } while (0) 301 302 #define DMA_BLOCK( reg0, val0, reg1, val1, reg2, val2, reg3, val3 ) \ 303 do { \ 304 DMA_WRITE( 0, ((DMAREG( reg0 ) << 0) | \ 305 (DMAREG( reg1 ) << 8) | \ 306 (DMAREG( reg2 ) << 16) | \ 307 (DMAREG( reg3 ) << 24)) ); \ 308 DMA_WRITE( 1, val0 ); \ 309 DMA_WRITE( 2, val1 ); \ 310 DMA_WRITE( 3, val2 ); \ 311 DMA_WRITE( 4, val3 ); \ 312 write += DMA_BLOCK_SIZE; \ 313 } while (0) 314 315 316 /* Buffer aging via primary DMA stream head pointer. 317 */ 318 319 #define SET_AGE( age, h, w ) \ 320 do { \ 321 (age)->head = h; \ 322 (age)->wrap = w; \ 323 } while (0) 324 325 #define TEST_AGE( age, h, w ) ( (age)->wrap < w || \ 326 ( (age)->wrap == w && \ 327 (age)->head < h ) ) 328 329 #define AGE_BUFFER( buf_priv ) \ 330 do { \ 331 drm_mga_freelist_t *entry = (buf_priv)->list_entry; \ 332 if ( (buf_priv)->dispatched ) { \ 333 entry->age.head = (dev_priv->prim.tail + \ 334 dev_priv->primary->offset); \ 335 entry->age.wrap = dev_priv->sarea_priv->last_wrap; \ 336 } else { \ 337 entry->age.head = 0; \ 338 entry->age.wrap = 0; \ 339 } \ 340 } while (0) 341 342 343 #define MGA_ENGINE_IDLE_MASK (MGA_SOFTRAPEN | \ 344 MGA_DWGENGSTS | \ 345 MGA_ENDPRDMASTS) 346 #define MGA_DMA_IDLE_MASK (MGA_SOFTRAPEN | \ 347 MGA_ENDPRDMASTS) 348 349 #define MGA_DMA_DEBUG 0 350 351 352 353 /* A reduced set of the mga registers. 354 */ 355 #define MGA_CRTC_INDEX 0x1fd4 356 357 #define MGA_ALPHACTRL 0x2c7c 358 #define MGA_AR0 0x1c60 359 #define MGA_AR1 0x1c64 360 #define MGA_AR2 0x1c68 361 #define MGA_AR3 0x1c6c 362 #define MGA_AR4 0x1c70 363 #define MGA_AR5 0x1c74 364 #define MGA_AR6 0x1c78 365 366 #define MGA_CXBNDRY 0x1c80 367 #define MGA_CXLEFT 0x1ca0 368 #define MGA_CXRIGHT 0x1ca4 369 370 #define MGA_DMAPAD 0x1c54 371 #define MGA_DSTORG 0x2cb8 372 #define MGA_DWGCTL 0x1c00 373 # define MGA_OPCOD_MASK (15 << 0) 374 # define MGA_OPCOD_TRAP (4 << 0) 375 # define MGA_OPCOD_TEXTURE_TRAP (6 << 0) 376 # define MGA_OPCOD_BITBLT (8 << 0) 377 # define MGA_OPCOD_ILOAD (9 << 0) 378 # define MGA_ATYPE_MASK (7 << 4) 379 # define MGA_ATYPE_RPL (0 << 4) 380 # define MGA_ATYPE_RSTR (1 << 4) 381 # define MGA_ATYPE_ZI (3 << 4) 382 # define MGA_ATYPE_BLK (4 << 4) 383 # define MGA_ATYPE_I (7 << 4) 384 # define MGA_LINEAR (1 << 7) 385 # define MGA_ZMODE_MASK (7 << 8) 386 # define MGA_ZMODE_NOZCMP (0 << 8) 387 # define MGA_ZMODE_ZE (2 << 8) 388 # define MGA_ZMODE_ZNE (3 << 8) 389 # define MGA_ZMODE_ZLT (4 << 8) 390 # define MGA_ZMODE_ZLTE (5 << 8) 391 # define MGA_ZMODE_ZGT (6 << 8) 392 # define MGA_ZMODE_ZGTE (7 << 8) 393 # define MGA_SOLID (1 << 11) 394 # define MGA_ARZERO (1 << 12) 395 # define MGA_SGNZERO (1 << 13) 396 # define MGA_SHIFTZERO (1 << 14) 397 # define MGA_BOP_MASK (15 << 16) 398 # define MGA_BOP_ZERO (0 << 16) 399 # define MGA_BOP_DST (10 << 16) 400 # define MGA_BOP_SRC (12 << 16) 401 # define MGA_BOP_ONE (15 << 16) 402 # define MGA_TRANS_SHIFT 20 403 # define MGA_TRANS_MASK (15 << 20) 404 # define MGA_BLTMOD_MASK (15 << 25) 405 # define MGA_BLTMOD_BMONOLEF (0 << 25) 406 # define MGA_BLTMOD_BMONOWF (4 << 25) 407 # define MGA_BLTMOD_PLAN (1 << 25) 408 # define MGA_BLTMOD_BFCOL (2 << 25) 409 # define MGA_BLTMOD_BU32BGR (3 << 25) 410 # define MGA_BLTMOD_BU32RGB (7 << 25) 411 # define MGA_BLTMOD_BU24BGR (11 << 25) 412 # define MGA_BLTMOD_BU24RGB (15 << 25) 413 # define MGA_PATTERN (1 << 29) 414 # define MGA_TRANSC (1 << 30) 415 # define MGA_CLIPDIS (1 << 31) 416 #define MGA_DWGSYNC 0x2c4c 417 418 #define MGA_FCOL 0x1c24 419 #define MGA_FIFOSTATUS 0x1e10 420 #define MGA_FOGCOL 0x1cf4 421 #define MGA_FXBNDRY 0x1c84 422 #define MGA_FXLEFT 0x1ca8 423 #define MGA_FXRIGHT 0x1cac 424 425 #define MGA_ICLEAR 0x1e18 426 # define MGA_SOFTRAPICLR (1 << 0) 427 #define MGA_IEN 0x1e1c 428 # define MGA_SOFTRAPIEN (1 << 0) 429 430 #define MGA_LEN 0x1c5c 431 432 #define MGA_MACCESS 0x1c04 433 434 #define MGA_PITCH 0x1c8c 435 #define MGA_PLNWT 0x1c1c 436 #define MGA_PRIMADDRESS 0x1e58 437 # define MGA_DMA_GENERAL (0 << 0) 438 # define MGA_DMA_BLIT (1 << 0) 439 # define MGA_DMA_VECTOR (2 << 0) 440 # define MGA_DMA_VERTEX (3 << 0) 441 #define MGA_PRIMEND 0x1e5c 442 # define MGA_PRIMNOSTART (1 << 0) 443 # define MGA_PAGPXFER (1 << 1) 444 #define MGA_PRIMPTR 0x1e50 445 # define MGA_PRIMPTREN0 (1 << 0) 446 # define MGA_PRIMPTREN1 (1 << 1) 447 448 #define MGA_RST 0x1e40 449 # define MGA_SOFTRESET (1 << 0) 450 # define MGA_SOFTEXTRST (1 << 1) 451 452 #define MGA_SECADDRESS 0x2c40 453 #define MGA_SECEND 0x2c44 454 #define MGA_SETUPADDRESS 0x2cd0 455 #define MGA_SETUPEND 0x2cd4 456 #define MGA_SGN 0x1c58 457 #define MGA_SOFTRAP 0x2c48 458 #define MGA_SRCORG 0x2cb4 459 # define MGA_SRMMAP_MASK (1 << 0) 460 # define MGA_SRCMAP_FB (0 << 0) 461 # define MGA_SRCMAP_SYSMEM (1 << 0) 462 # define MGA_SRCACC_MASK (1 << 1) 463 # define MGA_SRCACC_PCI (0 << 1) 464 # define MGA_SRCACC_AGP (1 << 1) 465 #define MGA_STATUS 0x1e14 466 # define MGA_SOFTRAPEN (1 << 0) 467 # define MGA_DWGENGSTS (1 << 16) 468 # define MGA_ENDPRDMASTS (1 << 17) 469 #define MGA_STENCIL 0x2cc8 470 #define MGA_STENCILCTL 0x2ccc 471 472 #define MGA_TDUALSTAGE0 0x2cf8 473 #define MGA_TDUALSTAGE1 0x2cfc 474 #define MGA_TEXBORDERCOL 0x2c5c 475 #define MGA_TEXCTL 0x2c30 476 #define MGA_TEXCTL2 0x2c3c 477 # define MGA_DUALTEX (1 << 7) 478 # define MGA_G400_TC2_MAGIC (1 << 15) 479 # define MGA_MAP1_ENABLE (1 << 31) 480 #define MGA_TEXFILTER 0x2c58 481 #define MGA_TEXHEIGHT 0x2c2c 482 #define MGA_TEXORG 0x2c24 483 # define MGA_TEXORGMAP_MASK (1 << 0) 484 # define MGA_TEXORGMAP_FB (0 << 0) 485 # define MGA_TEXORGMAP_SYSMEM (1 << 0) 486 # define MGA_TEXORGACC_MASK (1 << 1) 487 # define MGA_TEXORGACC_PCI (0 << 1) 488 # define MGA_TEXORGACC_AGP (1 << 1) 489 #define MGA_TEXORG1 0x2ca4 490 #define MGA_TEXORG2 0x2ca8 491 #define MGA_TEXORG3 0x2cac 492 #define MGA_TEXORG4 0x2cb0 493 #define MGA_TEXTRANS 0x2c34 494 #define MGA_TEXTRANSHIGH 0x2c38 495 #define MGA_TEXWIDTH 0x2c28 496 497 #define MGA_WACCEPTSEQ 0x1dd4 498 #define MGA_WCODEADDR 0x1e6c 499 #define MGA_WFLAG 0x1dc4 500 #define MGA_WFLAG1 0x1de0 501 #define MGA_WFLAGNB 0x1e64 502 #define MGA_WFLAGNB1 0x1e08 503 #define MGA_WGETMSB 0x1dc8 504 #define MGA_WIADDR 0x1dc0 505 #define MGA_WIADDR2 0x1dd8 506 # define MGA_WMODE_SUSPEND (0 << 0) 507 # define MGA_WMODE_RESUME (1 << 0) 508 # define MGA_WMODE_JUMP (2 << 0) 509 # define MGA_WMODE_START (3 << 0) 510 # define MGA_WAGP_ENABLE (1 << 2) 511 #define MGA_WMISC 0x1e70 512 # define MGA_WUCODECACHE_ENABLE (1 << 0) 513 # define MGA_WMASTER_ENABLE (1 << 1) 514 # define MGA_WCACHEFLUSH_ENABLE (1 << 3) 515 #define MGA_WVRTXSZ 0x1dcc 516 517 #define MGA_YBOT 0x1c9c 518 #define MGA_YDST 0x1c90 519 #define MGA_YDSTLEN 0x1c88 520 #define MGA_YDSTORG 0x1c94 521 #define MGA_YTOP 0x1c98 522 523 #define MGA_ZORG 0x1c0c 524 525 /* This finishes the current batch of commands 526 */ 527 #define MGA_EXEC 0x0100 528 529 /* Warp registers 530 */ 531 #define MGA_WR0 0x2d00 532 #define MGA_WR1 0x2d04 533 #define MGA_WR2 0x2d08 534 #define MGA_WR3 0x2d0c 535 #define MGA_WR4 0x2d10 536 #define MGA_WR5 0x2d14 537 #define MGA_WR6 0x2d18 538 #define MGA_WR7 0x2d1c 539 #define MGA_WR8 0x2d20 540 #define MGA_WR9 0x2d24 541 #define MGA_WR10 0x2d28 542 #define MGA_WR11 0x2d2c 543 #define MGA_WR12 0x2d30 544 #define MGA_WR13 0x2d34 545 #define MGA_WR14 0x2d38 546 #define MGA_WR15 0x2d3c 547 #define MGA_WR16 0x2d40 548 #define MGA_WR17 0x2d44 549 #define MGA_WR18 0x2d48 550 #define MGA_WR19 0x2d4c 551 #define MGA_WR20 0x2d50 552 #define MGA_WR21 0x2d54 553 #define MGA_WR22 0x2d58 554 #define MGA_WR23 0x2d5c 555 #define MGA_WR24 0x2d60 556 #define MGA_WR25 0x2d64 557 #define MGA_WR26 0x2d68 558 #define MGA_WR27 0x2d6c 559 #define MGA_WR28 0x2d70 560 #define MGA_WR29 0x2d74 561 #define MGA_WR30 0x2d78 562 #define MGA_WR31 0x2d7c 563 #define MGA_WR32 0x2d80 564 #define MGA_WR33 0x2d84 565 #define MGA_WR34 0x2d88 566 #define MGA_WR35 0x2d8c 567 #define MGA_WR36 0x2d90 568 #define MGA_WR37 0x2d94 569 #define MGA_WR38 0x2d98 570 #define MGA_WR39 0x2d9c 571 #define MGA_WR40 0x2da0 572 #define MGA_WR41 0x2da4 573 #define MGA_WR42 0x2da8 574 #define MGA_WR43 0x2dac 575 #define MGA_WR44 0x2db0 576 #define MGA_WR45 0x2db4 577 #define MGA_WR46 0x2db8 578 #define MGA_WR47 0x2dbc 579 #define MGA_WR48 0x2dc0 580 #define MGA_WR49 0x2dc4 581 #define MGA_WR50 0x2dc8 582 #define MGA_WR51 0x2dcc 583 #define MGA_WR52 0x2dd0 584 #define MGA_WR53 0x2dd4 585 #define MGA_WR54 0x2dd8 586 #define MGA_WR55 0x2ddc 587 #define MGA_WR56 0x2de0 588 #define MGA_WR57 0x2de4 589 #define MGA_WR58 0x2de8 590 #define MGA_WR59 0x2dec 591 #define MGA_WR60 0x2df0 592 #define MGA_WR61 0x2df4 593 #define MGA_WR62 0x2df8 594 #define MGA_WR63 0x2dfc 595 # define MGA_G400_WR_MAGIC (1 << 6) 596 # define MGA_G400_WR56_MAGIC 0x46480000 /* 12800.0f */ 597 598 599 #define MGA_ILOAD_ALIGN 64 600 #define MGA_ILOAD_MASK (MGA_ILOAD_ALIGN - 1) 601 602 #define MGA_DWGCTL_FLUSH (MGA_OPCOD_TEXTURE_TRAP | \ 603 MGA_ATYPE_I | \ 604 MGA_ZMODE_NOZCMP | \ 605 MGA_ARZERO | \ 606 MGA_SGNZERO | \ 607 MGA_BOP_SRC | \ 608 (15 << MGA_TRANS_SHIFT)) 609 610 #define MGA_DWGCTL_CLEAR (MGA_OPCOD_TRAP | \ 611 MGA_ZMODE_NOZCMP | \ 612 MGA_SOLID | \ 613 MGA_ARZERO | \ 614 MGA_SGNZERO | \ 615 MGA_SHIFTZERO | \ 616 MGA_BOP_SRC | \ 617 (0 << MGA_TRANS_SHIFT) | \ 618 MGA_BLTMOD_BMONOLEF | \ 619 MGA_TRANSC | \ 620 MGA_CLIPDIS) 621 622 #define MGA_DWGCTL_COPY (MGA_OPCOD_BITBLT | \ 623 MGA_ATYPE_RPL | \ 624 MGA_SGNZERO | \ 625 MGA_SHIFTZERO | \ 626 MGA_BOP_SRC | \ 627 (0 << MGA_TRANS_SHIFT) | \ 628 MGA_BLTMOD_BFCOL | \ 629 MGA_CLIPDIS) 630 631 /* Simple idle test. 632 */ 633 static __inline__ int mga_is_idle( drm_mga_private_t *dev_priv ) 634 { 635 u32 status = MGA_READ( MGA_STATUS ) & MGA_ENGINE_IDLE_MASK; 636 return ( status == MGA_ENDPRDMASTS ); 637 } 638 639 #endif
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