Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/dev/drm/mga_drv.h
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1 /* mga_drv.h -- Private header for the Matrox G200/G400 driver -*- linux-c -*- 2 * Created: Mon Dec 13 01:50:01 1999 by jhartmann@precisioninsight.com */ 3 /*- 4 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. 5 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 6 * All rights reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice (including the next 16 * paragraph) shall be included in all copies or substantial portions of the 17 * Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 22 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 25 * OTHER DEALINGS IN THE SOFTWARE. 26 * 27 * Authors: 28 * Gareth Hughes <gareth@valinux.com> 29 * 30 * $FreeBSD$ 31 */ 32 33 #ifndef __MGA_DRV_H__ 34 #define __MGA_DRV_H__ 35 36 typedef struct drm_mga_primary_buffer { 37 u8 *start; 38 u8 *end; 39 int size; 40 41 u32 tail; 42 int space; 43 volatile long wrapped; 44 45 volatile u32 *status; 46 47 u32 last_flush; 48 u32 last_wrap; 49 50 u32 high_mark; 51 } drm_mga_primary_buffer_t; 52 53 typedef struct drm_mga_freelist { 54 struct drm_mga_freelist *next; 55 struct drm_mga_freelist *prev; 56 drm_mga_age_t age; 57 drm_buf_t *buf; 58 } drm_mga_freelist_t; 59 60 typedef struct { 61 drm_mga_freelist_t *list_entry; 62 int discard; 63 int dispatched; 64 } drm_mga_buf_priv_t; 65 66 typedef struct drm_mga_private { 67 drm_mga_primary_buffer_t prim; 68 drm_mga_sarea_t *sarea_priv; 69 70 drm_mga_freelist_t *head; 71 drm_mga_freelist_t *tail; 72 73 unsigned int warp_pipe; 74 unsigned long warp_pipe_phys[MGA_MAX_WARP_PIPES]; 75 76 int chipset; 77 int usec_timeout; 78 79 u32 clear_cmd; 80 u32 maccess; 81 82 unsigned int fb_cpp; 83 unsigned int front_offset; 84 unsigned int front_pitch; 85 unsigned int back_offset; 86 unsigned int back_pitch; 87 88 unsigned int depth_cpp; 89 unsigned int depth_offset; 90 unsigned int depth_pitch; 91 92 unsigned int texture_offset; 93 unsigned int texture_size; 94 95 drm_local_map_t *sarea; 96 drm_local_map_t *mmio; 97 drm_local_map_t *status; 98 drm_local_map_t *warp; 99 drm_local_map_t *primary; 100 drm_local_map_t *buffers; 101 drm_local_map_t *agp_textures; 102 } drm_mga_private_t; 103 104 /* mga_dma.c */ 105 extern int mga_dma_init( DRM_IOCTL_ARGS ); 106 extern int mga_dma_flush( DRM_IOCTL_ARGS ); 107 extern int mga_dma_reset( DRM_IOCTL_ARGS ); 108 extern int mga_dma_buffers( DRM_IOCTL_ARGS ); 109 110 extern int mga_do_wait_for_idle( drm_mga_private_t *dev_priv ); 111 extern int mga_do_dma_idle( drm_mga_private_t *dev_priv ); 112 extern int mga_do_dma_reset( drm_mga_private_t *dev_priv ); 113 extern int mga_do_engine_reset( drm_mga_private_t *dev_priv ); 114 extern int mga_do_cleanup_dma( drm_device_t *dev ); 115 116 extern void mga_do_dma_flush( drm_mga_private_t *dev_priv ); 117 extern void mga_do_dma_wrap_start( drm_mga_private_t *dev_priv ); 118 extern void mga_do_dma_wrap_end( drm_mga_private_t *dev_priv ); 119 120 extern int mga_freelist_put( drm_device_t *dev, drm_buf_t *buf ); 121 122 /* mga_state.c */ 123 extern int mga_dma_clear( DRM_IOCTL_ARGS ); 124 extern int mga_dma_swap( DRM_IOCTL_ARGS ); 125 extern int mga_dma_vertex( DRM_IOCTL_ARGS ); 126 extern int mga_dma_indices( DRM_IOCTL_ARGS ); 127 extern int mga_dma_iload( DRM_IOCTL_ARGS ); 128 extern int mga_dma_blit( DRM_IOCTL_ARGS ); 129 extern int mga_getparam( DRM_IOCTL_ARGS ); 130 131 /* mga_warp.c */ 132 extern int mga_warp_install_microcode( drm_mga_private_t *dev_priv ); 133 extern int mga_warp_init( drm_mga_private_t *dev_priv ); 134 135 #define mga_flush_write_combine() DRM_WRITEMEMORYBARRIER() 136 137 #if defined(__linux__) && defined(__alpha__) 138 #define MGA_BASE( reg ) ((unsigned long)(dev_priv->mmio->handle)) 139 #define MGA_ADDR( reg ) (MGA_BASE(reg) + reg) 140 141 #define MGA_DEREF( reg ) *(volatile u32 *)MGA_ADDR( reg ) 142 #define MGA_DEREF8( reg ) *(volatile u8 *)MGA_ADDR( reg ) 143 144 #define MGA_READ( reg ) (_MGA_READ((u32 *)MGA_ADDR(reg))) 145 #define MGA_READ8( reg ) (_MGA_READ((u8 *)MGA_ADDR(reg))) 146 #define MGA_WRITE( reg, val ) do { DRM_WRITEMEMORYBARRIER(); MGA_DEREF( reg ) = val; } while (0) 147 #define MGA_WRITE8( reg, val ) do { DRM_WRITEMEMORYBARRIER(); MGA_DEREF8( reg ) = val; } while (0) 148 149 static inline u32 _MGA_READ(u32 *addr) 150 { 151 DRM_MEMORYBARRIER(); 152 return *(volatile u32 *)addr; 153 } 154 #else 155 #define MGA_READ8( reg ) DRM_READ8(dev_priv->mmio, (reg)) 156 #define MGA_READ( reg ) DRM_READ32(dev_priv->mmio, (reg)) 157 #define MGA_WRITE8( reg, val ) DRM_WRITE8(dev_priv->mmio, (reg), (val)) 158 #define MGA_WRITE( reg, val ) DRM_WRITE32(dev_priv->mmio, (reg), (val)) 159 #endif 160 161 #define DWGREG0 0x1c00 162 #define DWGREG0_END 0x1dff 163 #define DWGREG1 0x2c00 164 #define DWGREG1_END 0x2dff 165 166 #define ISREG0(r) (r >= DWGREG0 && r <= DWGREG0_END) 167 #define DMAREG0(r) (u8)((r - DWGREG0) >> 2) 168 #define DMAREG1(r) (u8)(((r - DWGREG1) >> 2) | 0x80) 169 #define DMAREG(r) (ISREG0(r) ? DMAREG0(r) : DMAREG1(r)) 170 171 172 173 /* ================================================================ 174 * Helper macross... 175 */ 176 177 #define MGA_EMIT_STATE( dev_priv, dirty ) \ 178 do { \ 179 if ( (dirty) & ~MGA_UPLOAD_CLIPRECTS ) { \ 180 if ( dev_priv->chipset == MGA_CARD_TYPE_G400 ) { \ 181 mga_g400_emit_state( dev_priv ); \ 182 } else { \ 183 mga_g200_emit_state( dev_priv ); \ 184 } \ 185 } \ 186 } while (0) 187 188 #define WRAP_TEST_WITH_RETURN( dev_priv ) \ 189 do { \ 190 if ( test_bit( 0, &dev_priv->prim.wrapped ) ) { \ 191 if ( mga_is_idle( dev_priv ) ) { \ 192 mga_do_dma_wrap_end( dev_priv ); \ 193 } else if ( dev_priv->prim.space < \ 194 dev_priv->prim.high_mark ) { \ 195 if ( MGA_DMA_DEBUG ) \ 196 DRM_INFO( "%s: wrap...\n", __FUNCTION__ ); \ 197 return DRM_ERR(EBUSY); \ 198 } \ 199 } \ 200 } while (0) 201 202 #define WRAP_WAIT_WITH_RETURN( dev_priv ) \ 203 do { \ 204 if ( test_bit( 0, &dev_priv->prim.wrapped ) ) { \ 205 if ( mga_do_wait_for_idle( dev_priv ) < 0 ) { \ 206 if ( MGA_DMA_DEBUG ) \ 207 DRM_INFO( "%s: wrap...\n", __FUNCTION__ ); \ 208 return DRM_ERR(EBUSY); \ 209 } \ 210 mga_do_dma_wrap_end( dev_priv ); \ 211 } \ 212 } while (0) 213 214 215 /* ================================================================ 216 * Primary DMA command stream 217 */ 218 219 #define MGA_VERBOSE 0 220 221 #define DMA_LOCALS unsigned int write; volatile u8 *prim; 222 223 #define DMA_BLOCK_SIZE (5 * sizeof(u32)) 224 225 #define BEGIN_DMA( n ) \ 226 do { \ 227 if ( MGA_VERBOSE ) { \ 228 DRM_INFO( "BEGIN_DMA( %d ) in %s\n", \ 229 (n), __FUNCTION__ ); \ 230 DRM_INFO( " space=0x%x req=0x%Zx\n", \ 231 dev_priv->prim.space, (n) * DMA_BLOCK_SIZE ); \ 232 } \ 233 prim = dev_priv->prim.start; \ 234 write = dev_priv->prim.tail; \ 235 } while (0) 236 237 #define BEGIN_DMA_WRAP() \ 238 do { \ 239 if ( MGA_VERBOSE ) { \ 240 DRM_INFO( "BEGIN_DMA() in %s\n", __FUNCTION__ ); \ 241 DRM_INFO( " space=0x%x\n", dev_priv->prim.space ); \ 242 } \ 243 prim = dev_priv->prim.start; \ 244 write = dev_priv->prim.tail; \ 245 } while (0) 246 247 #define ADVANCE_DMA() \ 248 do { \ 249 dev_priv->prim.tail = write; \ 250 if ( MGA_VERBOSE ) { \ 251 DRM_INFO( "ADVANCE_DMA() tail=0x%05x sp=0x%x\n", \ 252 write, dev_priv->prim.space ); \ 253 } \ 254 } while (0) 255 256 #define FLUSH_DMA() \ 257 do { \ 258 if ( 0 ) { \ 259 DRM_INFO( "%s:\n", __FUNCTION__ ); \ 260 DRM_INFO( " tail=0x%06x head=0x%06lx\n", \ 261 dev_priv->prim.tail, \ 262 MGA_READ( MGA_PRIMADDRESS ) - \ 263 dev_priv->primary->offset ); \ 264 } \ 265 if ( !test_bit( 0, &dev_priv->prim.wrapped ) ) { \ 266 if ( dev_priv->prim.space < \ 267 dev_priv->prim.high_mark ) { \ 268 mga_do_dma_wrap_start( dev_priv ); \ 269 } else { \ 270 mga_do_dma_flush( dev_priv ); \ 271 } \ 272 } \ 273 } while (0) 274 275 /* Never use this, always use DMA_BLOCK(...) for primary DMA output. 276 */ 277 #define DMA_WRITE( offset, val ) \ 278 do { \ 279 if ( MGA_VERBOSE ) { \ 280 DRM_INFO( " DMA_WRITE( 0x%08x ) at 0x%04Zx\n", \ 281 (u32)(val), write + (offset) * sizeof(u32) ); \ 282 } \ 283 *(volatile u32 *)(prim + write + (offset) * sizeof(u32)) = val; \ 284 } while (0) 285 286 #define DMA_BLOCK( reg0, val0, reg1, val1, reg2, val2, reg3, val3 ) \ 287 do { \ 288 DMA_WRITE( 0, ((DMAREG( reg0 ) << 0) | \ 289 (DMAREG( reg1 ) << 8) | \ 290 (DMAREG( reg2 ) << 16) | \ 291 (DMAREG( reg3 ) << 24)) ); \ 292 DMA_WRITE( 1, val0 ); \ 293 DMA_WRITE( 2, val1 ); \ 294 DMA_WRITE( 3, val2 ); \ 295 DMA_WRITE( 4, val3 ); \ 296 write += DMA_BLOCK_SIZE; \ 297 } while (0) 298 299 300 /* Buffer aging via primary DMA stream head pointer. 301 */ 302 303 #define SET_AGE( age, h, w ) \ 304 do { \ 305 (age)->head = h; \ 306 (age)->wrap = w; \ 307 } while (0) 308 309 #define TEST_AGE( age, h, w ) ( (age)->wrap < w || \ 310 ( (age)->wrap == w && \ 311 (age)->head < h ) ) 312 313 #define AGE_BUFFER( buf_priv ) \ 314 do { \ 315 drm_mga_freelist_t *entry = (buf_priv)->list_entry; \ 316 if ( (buf_priv)->dispatched ) { \ 317 entry->age.head = (dev_priv->prim.tail + \ 318 dev_priv->primary->offset); \ 319 entry->age.wrap = dev_priv->sarea_priv->last_wrap; \ 320 } else { \ 321 entry->age.head = 0; \ 322 entry->age.wrap = 0; \ 323 } \ 324 } while (0) 325 326 327 #define MGA_ENGINE_IDLE_MASK (MGA_SOFTRAPEN | \ 328 MGA_DWGENGSTS | \ 329 MGA_ENDPRDMASTS) 330 #define MGA_DMA_IDLE_MASK (MGA_SOFTRAPEN | \ 331 MGA_ENDPRDMASTS) 332 333 #define MGA_DMA_DEBUG 0 334 335 336 337 /* A reduced set of the mga registers. 338 */ 339 #define MGA_CRTC_INDEX 0x1fd4 340 #define MGA_CRTC_DATA 0x1fd5 341 342 /* CRTC11 */ 343 #define MGA_VINTCLR (1 << 4) 344 #define MGA_VINTEN (1 << 5) 345 346 #define MGA_ALPHACTRL 0x2c7c 347 #define MGA_AR0 0x1c60 348 #define MGA_AR1 0x1c64 349 #define MGA_AR2 0x1c68 350 #define MGA_AR3 0x1c6c 351 #define MGA_AR4 0x1c70 352 #define MGA_AR5 0x1c74 353 #define MGA_AR6 0x1c78 354 355 #define MGA_CXBNDRY 0x1c80 356 #define MGA_CXLEFT 0x1ca0 357 #define MGA_CXRIGHT 0x1ca4 358 359 #define MGA_DMAPAD 0x1c54 360 #define MGA_DSTORG 0x2cb8 361 #define MGA_DWGCTL 0x1c00 362 # define MGA_OPCOD_MASK (15 << 0) 363 # define MGA_OPCOD_TRAP (4 << 0) 364 # define MGA_OPCOD_TEXTURE_TRAP (6 << 0) 365 # define MGA_OPCOD_BITBLT (8 << 0) 366 # define MGA_OPCOD_ILOAD (9 << 0) 367 # define MGA_ATYPE_MASK (7 << 4) 368 # define MGA_ATYPE_RPL (0 << 4) 369 # define MGA_ATYPE_RSTR (1 << 4) 370 # define MGA_ATYPE_ZI (3 << 4) 371 # define MGA_ATYPE_BLK (4 << 4) 372 # define MGA_ATYPE_I (7 << 4) 373 # define MGA_LINEAR (1 << 7) 374 # define MGA_ZMODE_MASK (7 << 8) 375 # define MGA_ZMODE_NOZCMP (0 << 8) 376 # define MGA_ZMODE_ZE (2 << 8) 377 # define MGA_ZMODE_ZNE (3 << 8) 378 # define MGA_ZMODE_ZLT (4 << 8) 379 # define MGA_ZMODE_ZLTE (5 << 8) 380 # define MGA_ZMODE_ZGT (6 << 8) 381 # define MGA_ZMODE_ZGTE (7 << 8) 382 # define MGA_SOLID (1 << 11) 383 # define MGA_ARZERO (1 << 12) 384 # define MGA_SGNZERO (1 << 13) 385 # define MGA_SHIFTZERO (1 << 14) 386 # define MGA_BOP_MASK (15 << 16) 387 # define MGA_BOP_ZERO (0 << 16) 388 # define MGA_BOP_DST (10 << 16) 389 # define MGA_BOP_SRC (12 << 16) 390 # define MGA_BOP_ONE (15 << 16) 391 # define MGA_TRANS_SHIFT 20 392 # define MGA_TRANS_MASK (15 << 20) 393 # define MGA_BLTMOD_MASK (15 << 25) 394 # define MGA_BLTMOD_BMONOLEF (0 << 25) 395 # define MGA_BLTMOD_BMONOWF (4 << 25) 396 # define MGA_BLTMOD_PLAN (1 << 25) 397 # define MGA_BLTMOD_BFCOL (2 << 25) 398 # define MGA_BLTMOD_BU32BGR (3 << 25) 399 # define MGA_BLTMOD_BU32RGB (7 << 25) 400 # define MGA_BLTMOD_BU24BGR (11 << 25) 401 # define MGA_BLTMOD_BU24RGB (15 << 25) 402 # define MGA_PATTERN (1 << 29) 403 # define MGA_TRANSC (1 << 30) 404 # define MGA_CLIPDIS (1 << 31) 405 #define MGA_DWGSYNC 0x2c4c 406 407 #define MGA_FCOL 0x1c24 408 #define MGA_FIFOSTATUS 0x1e10 409 #define MGA_FOGCOL 0x1cf4 410 #define MGA_FXBNDRY 0x1c84 411 #define MGA_FXLEFT 0x1ca8 412 #define MGA_FXRIGHT 0x1cac 413 414 #define MGA_ICLEAR 0x1e18 415 # define MGA_SOFTRAPICLR (1 << 0) 416 # define MGA_VLINEICLR (1 << 5) 417 #define MGA_IEN 0x1e1c 418 # define MGA_SOFTRAPIEN (1 << 0) 419 # define MGA_VLINEIEN (1 << 5) 420 421 #define MGA_LEN 0x1c5c 422 423 #define MGA_MACCESS 0x1c04 424 425 #define MGA_PITCH 0x1c8c 426 #define MGA_PLNWT 0x1c1c 427 #define MGA_PRIMADDRESS 0x1e58 428 # define MGA_DMA_GENERAL (0 << 0) 429 # define MGA_DMA_BLIT (1 << 0) 430 # define MGA_DMA_VECTOR (2 << 0) 431 # define MGA_DMA_VERTEX (3 << 0) 432 #define MGA_PRIMEND 0x1e5c 433 # define MGA_PRIMNOSTART (1 << 0) 434 # define MGA_PAGPXFER (1 << 1) 435 #define MGA_PRIMPTR 0x1e50 436 # define MGA_PRIMPTREN0 (1 << 0) 437 # define MGA_PRIMPTREN1 (1 << 1) 438 439 #define MGA_RST 0x1e40 440 # define MGA_SOFTRESET (1 << 0) 441 # define MGA_SOFTEXTRST (1 << 1) 442 443 #define MGA_SECADDRESS 0x2c40 444 #define MGA_SECEND 0x2c44 445 #define MGA_SETUPADDRESS 0x2cd0 446 #define MGA_SETUPEND 0x2cd4 447 #define MGA_SGN 0x1c58 448 #define MGA_SOFTRAP 0x2c48 449 #define MGA_SRCORG 0x2cb4 450 # define MGA_SRMMAP_MASK (1 << 0) 451 # define MGA_SRCMAP_FB (0 << 0) 452 # define MGA_SRCMAP_SYSMEM (1 << 0) 453 # define MGA_SRCACC_MASK (1 << 1) 454 # define MGA_SRCACC_PCI (0 << 1) 455 # define MGA_SRCACC_AGP (1 << 1) 456 #define MGA_STATUS 0x1e14 457 # define MGA_SOFTRAPEN (1 << 0) 458 # define MGA_VSYNCPEN (1 << 4) 459 # define MGA_VLINEPEN (1 << 5) 460 # define MGA_DWGENGSTS (1 << 16) 461 # define MGA_ENDPRDMASTS (1 << 17) 462 #define MGA_STENCIL 0x2cc8 463 #define MGA_STENCILCTL 0x2ccc 464 465 #define MGA_TDUALSTAGE0 0x2cf8 466 #define MGA_TDUALSTAGE1 0x2cfc 467 #define MGA_TEXBORDERCOL 0x2c5c 468 #define MGA_TEXCTL 0x2c30 469 #define MGA_TEXCTL2 0x2c3c 470 # define MGA_DUALTEX (1 << 7) 471 # define MGA_G400_TC2_MAGIC (1 << 15) 472 # define MGA_MAP1_ENABLE (1 << 31) 473 #define MGA_TEXFILTER 0x2c58 474 #define MGA_TEXHEIGHT 0x2c2c 475 #define MGA_TEXORG 0x2c24 476 # define MGA_TEXORGMAP_MASK (1 << 0) 477 # define MGA_TEXORGMAP_FB (0 << 0) 478 # define MGA_TEXORGMAP_SYSMEM (1 << 0) 479 # define MGA_TEXORGACC_MASK (1 << 1) 480 # define MGA_TEXORGACC_PCI (0 << 1) 481 # define MGA_TEXORGACC_AGP (1 << 1) 482 #define MGA_TEXORG1 0x2ca4 483 #define MGA_TEXORG2 0x2ca8 484 #define MGA_TEXORG3 0x2cac 485 #define MGA_TEXORG4 0x2cb0 486 #define MGA_TEXTRANS 0x2c34 487 #define MGA_TEXTRANSHIGH 0x2c38 488 #define MGA_TEXWIDTH 0x2c28 489 490 #define MGA_WACCEPTSEQ 0x1dd4 491 #define MGA_WCODEADDR 0x1e6c 492 #define MGA_WFLAG 0x1dc4 493 #define MGA_WFLAG1 0x1de0 494 #define MGA_WFLAGNB 0x1e64 495 #define MGA_WFLAGNB1 0x1e08 496 #define MGA_WGETMSB 0x1dc8 497 #define MGA_WIADDR 0x1dc0 498 #define MGA_WIADDR2 0x1dd8 499 # define MGA_WMODE_SUSPEND (0 << 0) 500 # define MGA_WMODE_RESUME (1 << 0) 501 # define MGA_WMODE_JUMP (2 << 0) 502 # define MGA_WMODE_START (3 << 0) 503 # define MGA_WAGP_ENABLE (1 << 2) 504 #define MGA_WMISC 0x1e70 505 # define MGA_WUCODECACHE_ENABLE (1 << 0) 506 # define MGA_WMASTER_ENABLE (1 << 1) 507 # define MGA_WCACHEFLUSH_ENABLE (1 << 3) 508 #define MGA_WVRTXSZ 0x1dcc 509 510 #define MGA_YBOT 0x1c9c 511 #define MGA_YDST 0x1c90 512 #define MGA_YDSTLEN 0x1c88 513 #define MGA_YDSTORG 0x1c94 514 #define MGA_YTOP 0x1c98 515 516 #define MGA_ZORG 0x1c0c 517 518 /* This finishes the current batch of commands 519 */ 520 #define MGA_EXEC 0x0100 521 522 /* Warp registers 523 */ 524 #define MGA_WR0 0x2d00 525 #define MGA_WR1 0x2d04 526 #define MGA_WR2 0x2d08 527 #define MGA_WR3 0x2d0c 528 #define MGA_WR4 0x2d10 529 #define MGA_WR5 0x2d14 530 #define MGA_WR6 0x2d18 531 #define MGA_WR7 0x2d1c 532 #define MGA_WR8 0x2d20 533 #define MGA_WR9 0x2d24 534 #define MGA_WR10 0x2d28 535 #define MGA_WR11 0x2d2c 536 #define MGA_WR12 0x2d30 537 #define MGA_WR13 0x2d34 538 #define MGA_WR14 0x2d38 539 #define MGA_WR15 0x2d3c 540 #define MGA_WR16 0x2d40 541 #define MGA_WR17 0x2d44 542 #define MGA_WR18 0x2d48 543 #define MGA_WR19 0x2d4c 544 #define MGA_WR20 0x2d50 545 #define MGA_WR21 0x2d54 546 #define MGA_WR22 0x2d58 547 #define MGA_WR23 0x2d5c 548 #define MGA_WR24 0x2d60 549 #define MGA_WR25 0x2d64 550 #define MGA_WR26 0x2d68 551 #define MGA_WR27 0x2d6c 552 #define MGA_WR28 0x2d70 553 #define MGA_WR29 0x2d74 554 #define MGA_WR30 0x2d78 555 #define MGA_WR31 0x2d7c 556 #define MGA_WR32 0x2d80 557 #define MGA_WR33 0x2d84 558 #define MGA_WR34 0x2d88 559 #define MGA_WR35 0x2d8c 560 #define MGA_WR36 0x2d90 561 #define MGA_WR37 0x2d94 562 #define MGA_WR38 0x2d98 563 #define MGA_WR39 0x2d9c 564 #define MGA_WR40 0x2da0 565 #define MGA_WR41 0x2da4 566 #define MGA_WR42 0x2da8 567 #define MGA_WR43 0x2dac 568 #define MGA_WR44 0x2db0 569 #define MGA_WR45 0x2db4 570 #define MGA_WR46 0x2db8 571 #define MGA_WR47 0x2dbc 572 #define MGA_WR48 0x2dc0 573 #define MGA_WR49 0x2dc4 574 #define MGA_WR50 0x2dc8 575 #define MGA_WR51 0x2dcc 576 #define MGA_WR52 0x2dd0 577 #define MGA_WR53 0x2dd4 578 #define MGA_WR54 0x2dd8 579 #define MGA_WR55 0x2ddc 580 #define MGA_WR56 0x2de0 581 #define MGA_WR57 0x2de4 582 #define MGA_WR58 0x2de8 583 #define MGA_WR59 0x2dec 584 #define MGA_WR60 0x2df0 585 #define MGA_WR61 0x2df4 586 #define MGA_WR62 0x2df8 587 #define MGA_WR63 0x2dfc 588 # define MGA_G400_WR_MAGIC (1 << 6) 589 # define MGA_G400_WR56_MAGIC 0x46480000 /* 12800.0f */ 590 591 592 #define MGA_ILOAD_ALIGN 64 593 #define MGA_ILOAD_MASK (MGA_ILOAD_ALIGN - 1) 594 595 #define MGA_DWGCTL_FLUSH (MGA_OPCOD_TEXTURE_TRAP | \ 596 MGA_ATYPE_I | \ 597 MGA_ZMODE_NOZCMP | \ 598 MGA_ARZERO | \ 599 MGA_SGNZERO | \ 600 MGA_BOP_SRC | \ 601 (15 << MGA_TRANS_SHIFT)) 602 603 #define MGA_DWGCTL_CLEAR (MGA_OPCOD_TRAP | \ 604 MGA_ZMODE_NOZCMP | \ 605 MGA_SOLID | \ 606 MGA_ARZERO | \ 607 MGA_SGNZERO | \ 608 MGA_SHIFTZERO | \ 609 MGA_BOP_SRC | \ 610 (0 << MGA_TRANS_SHIFT) | \ 611 MGA_BLTMOD_BMONOLEF | \ 612 MGA_TRANSC | \ 613 MGA_CLIPDIS) 614 615 #define MGA_DWGCTL_COPY (MGA_OPCOD_BITBLT | \ 616 MGA_ATYPE_RPL | \ 617 MGA_SGNZERO | \ 618 MGA_SHIFTZERO | \ 619 MGA_BOP_SRC | \ 620 (0 << MGA_TRANS_SHIFT) | \ 621 MGA_BLTMOD_BFCOL | \ 622 MGA_CLIPDIS) 623 624 /* Simple idle test. 625 */ 626 static __inline__ int mga_is_idle( drm_mga_private_t *dev_priv ) 627 { 628 u32 status = MGA_READ( MGA_STATUS ) & MGA_ENGINE_IDLE_MASK; 629 return ( status == MGA_ENDPRDMASTS ); 630 } 631 632 #endif
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