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sys/dev/drm/mga_drv.h
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1 /* mga_drv.h -- Private header for the Matrox G200/G400 driver -*- linux-c -*- 2 * Created: Mon Dec 13 01:50:01 1999 by jhartmann@precisioninsight.com 3 * 4 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. 5 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 6 * All rights reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice (including the next 16 * paragraph) shall be included in all copies or substantial portions of the 17 * Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 22 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 25 * OTHER DEALINGS IN THE SOFTWARE. 26 * 27 * Authors: 28 * Gareth Hughes <gareth@valinux.com> 29 */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD: releng/6.4/sys/dev/drm/mga_drv.h 158686 2006-05-17 07:40:12Z anholt $"); 33 34 #ifndef __MGA_DRV_H__ 35 #define __MGA_DRV_H__ 36 37 /* General customization: 38 */ 39 40 #define DRIVER_AUTHOR "Gareth Hughes, VA Linux Systems Inc." 41 42 #define DRIVER_NAME "mga" 43 #define DRIVER_DESC "Matrox G200/G400" 44 #define DRIVER_DATE "20060319" 45 46 #define DRIVER_MAJOR 3 47 #define DRIVER_MINOR 2 48 #define DRIVER_PATCHLEVEL 2 49 50 typedef struct drm_mga_primary_buffer { 51 u8 *start; 52 u8 *end; 53 int size; 54 55 u32 tail; 56 int space; 57 volatile long wrapped; 58 59 volatile u32 *status; 60 61 u32 last_flush; 62 u32 last_wrap; 63 64 u32 high_mark; 65 } drm_mga_primary_buffer_t; 66 67 typedef struct drm_mga_freelist { 68 struct drm_mga_freelist *next; 69 struct drm_mga_freelist *prev; 70 drm_mga_age_t age; 71 drm_buf_t *buf; 72 } drm_mga_freelist_t; 73 74 typedef struct { 75 drm_mga_freelist_t *list_entry; 76 int discard; 77 int dispatched; 78 } drm_mga_buf_priv_t; 79 80 typedef struct drm_mga_private { 81 drm_mga_primary_buffer_t prim; 82 drm_mga_sarea_t *sarea_priv; 83 84 drm_mga_freelist_t *head; 85 drm_mga_freelist_t *tail; 86 87 unsigned int warp_pipe; 88 unsigned long warp_pipe_phys[MGA_MAX_WARP_PIPES]; 89 90 int chipset; 91 int usec_timeout; 92 93 /** 94 * If set, the new DMA initialization sequence was used. This is 95 * primarilly used to select how the driver should uninitialized its 96 * internal DMA structures. 97 */ 98 int used_new_dma_init; 99 100 /** 101 * If AGP memory is used for DMA buffers, this will be the value 102 * \c MGA_PAGPXFER. Otherwise, it will be zero (for a PCI transfer). 103 */ 104 u32 dma_access; 105 106 /** 107 * If AGP memory is used for DMA buffers, this will be the value 108 * \c MGA_WAGP_ENABLE. Otherwise, it will be zero (for a PCI 109 * transfer). 110 */ 111 u32 wagp_enable; 112 113 /** 114 * \name MMIO region parameters. 115 * 116 * \sa drm_mga_private_t::mmio 117 */ 118 /*@{*/ 119 u32 mmio_base; /**< Bus address of base of MMIO. */ 120 u32 mmio_size; /**< Size of the MMIO region. */ 121 /*@}*/ 122 123 u32 clear_cmd; 124 u32 maccess; 125 126 wait_queue_head_t fence_queue; 127 atomic_t last_fence_retired; 128 u32 next_fence_to_post; 129 130 unsigned int fb_cpp; 131 unsigned int front_offset; 132 unsigned int front_pitch; 133 unsigned int back_offset; 134 unsigned int back_pitch; 135 136 unsigned int depth_cpp; 137 unsigned int depth_offset; 138 unsigned int depth_pitch; 139 140 unsigned int texture_offset; 141 unsigned int texture_size; 142 143 drm_local_map_t *sarea; 144 drm_local_map_t *mmio; 145 drm_local_map_t *status; 146 drm_local_map_t *warp; 147 drm_local_map_t *primary; 148 drm_local_map_t *agp_textures; 149 150 unsigned long agp_handle; 151 unsigned int agp_size; 152 } drm_mga_private_t; 153 154 extern drm_ioctl_desc_t mga_ioctls[]; 155 extern int mga_max_ioctl; 156 157 /* mga_dma.c */ 158 extern int mga_dma_bootstrap(DRM_IOCTL_ARGS); 159 extern int mga_dma_init(DRM_IOCTL_ARGS); 160 extern int mga_dma_flush(DRM_IOCTL_ARGS); 161 extern int mga_dma_reset(DRM_IOCTL_ARGS); 162 extern int mga_dma_buffers(DRM_IOCTL_ARGS); 163 extern int mga_driver_load(drm_device_t *dev, unsigned long flags); 164 extern int mga_driver_unload(drm_device_t * dev); 165 extern void mga_driver_lastclose(drm_device_t * dev); 166 extern int mga_driver_dma_quiescent(drm_device_t * dev); 167 168 extern int mga_do_wait_for_idle(drm_mga_private_t * dev_priv); 169 170 extern void mga_do_dma_flush(drm_mga_private_t * dev_priv); 171 extern void mga_do_dma_wrap_start(drm_mga_private_t * dev_priv); 172 extern void mga_do_dma_wrap_end(drm_mga_private_t * dev_priv); 173 174 extern int mga_freelist_put(drm_device_t * dev, drm_buf_t * buf); 175 176 /* mga_warp.c */ 177 extern unsigned int mga_warp_microcode_size(const drm_mga_private_t * dev_priv); 178 extern int mga_warp_install_microcode(drm_mga_private_t * dev_priv); 179 extern int mga_warp_init(drm_mga_private_t * dev_priv); 180 181 /* mga_irq.c */ 182 extern int mga_driver_fence_wait(drm_device_t * dev, unsigned int *sequence); 183 extern int mga_driver_vblank_wait(drm_device_t * dev, unsigned int *sequence); 184 extern irqreturn_t mga_driver_irq_handler(DRM_IRQ_ARGS); 185 extern void mga_driver_irq_preinstall(drm_device_t * dev); 186 extern void mga_driver_irq_postinstall(drm_device_t * dev); 187 extern void mga_driver_irq_uninstall(drm_device_t * dev); 188 extern long mga_compat_ioctl(struct file *filp, unsigned int cmd, 189 unsigned long arg); 190 191 #define mga_flush_write_combine() DRM_WRITEMEMORYBARRIER() 192 193 #if defined(__linux__) && defined(__alpha__) 194 #define MGA_BASE( reg ) ((unsigned long)(dev_priv->mmio->handle)) 195 #define MGA_ADDR( reg ) (MGA_BASE(reg) + reg) 196 197 #define MGA_DEREF( reg ) *(volatile u32 *)MGA_ADDR( reg ) 198 #define MGA_DEREF8( reg ) *(volatile u8 *)MGA_ADDR( reg ) 199 200 #define MGA_READ( reg ) (_MGA_READ((u32 *)MGA_ADDR(reg))) 201 #define MGA_READ8( reg ) (_MGA_READ((u8 *)MGA_ADDR(reg))) 202 #define MGA_WRITE( reg, val ) do { DRM_WRITEMEMORYBARRIER(); MGA_DEREF( reg ) = val; } while (0) 203 #define MGA_WRITE8( reg, val ) do { DRM_WRITEMEMORYBARRIER(); MGA_DEREF8( reg ) = val; } while (0) 204 205 static inline u32 _MGA_READ(u32 * addr) 206 { 207 DRM_MEMORYBARRIER(); 208 return *(volatile u32 *)addr; 209 } 210 #else 211 #define MGA_READ8( reg ) DRM_READ8(dev_priv->mmio, (reg)) 212 #define MGA_READ( reg ) DRM_READ32(dev_priv->mmio, (reg)) 213 #define MGA_WRITE8( reg, val ) DRM_WRITE8(dev_priv->mmio, (reg), (val)) 214 #define MGA_WRITE( reg, val ) DRM_WRITE32(dev_priv->mmio, (reg), (val)) 215 #endif 216 217 #define DWGREG0 0x1c00 218 #define DWGREG0_END 0x1dff 219 #define DWGREG1 0x2c00 220 #define DWGREG1_END 0x2dff 221 222 #define ISREG0(r) (r >= DWGREG0 && r <= DWGREG0_END) 223 #define DMAREG0(r) (u8)((r - DWGREG0) >> 2) 224 #define DMAREG1(r) (u8)(((r - DWGREG1) >> 2) | 0x80) 225 #define DMAREG(r) (ISREG0(r) ? DMAREG0(r) : DMAREG1(r)) 226 227 /* ================================================================ 228 * Helper macross... 229 */ 230 231 #define MGA_EMIT_STATE( dev_priv, dirty ) \ 232 do { \ 233 if ( (dirty) & ~MGA_UPLOAD_CLIPRECTS ) { \ 234 if ( dev_priv->chipset >= MGA_CARD_TYPE_G400 ) { \ 235 mga_g400_emit_state( dev_priv ); \ 236 } else { \ 237 mga_g200_emit_state( dev_priv ); \ 238 } \ 239 } \ 240 } while (0) 241 242 #define WRAP_TEST_WITH_RETURN( dev_priv ) \ 243 do { \ 244 if ( test_bit( 0, &dev_priv->prim.wrapped ) ) { \ 245 if ( mga_is_idle( dev_priv ) ) { \ 246 mga_do_dma_wrap_end( dev_priv ); \ 247 } else if ( dev_priv->prim.space < \ 248 dev_priv->prim.high_mark ) { \ 249 if ( MGA_DMA_DEBUG ) \ 250 DRM_INFO( "%s: wrap...\n", __FUNCTION__ ); \ 251 return DRM_ERR(EBUSY); \ 252 } \ 253 } \ 254 } while (0) 255 256 #define WRAP_WAIT_WITH_RETURN( dev_priv ) \ 257 do { \ 258 if ( test_bit( 0, &dev_priv->prim.wrapped ) ) { \ 259 if ( mga_do_wait_for_idle( dev_priv ) < 0 ) { \ 260 if ( MGA_DMA_DEBUG ) \ 261 DRM_INFO( "%s: wrap...\n", __FUNCTION__ ); \ 262 return DRM_ERR(EBUSY); \ 263 } \ 264 mga_do_dma_wrap_end( dev_priv ); \ 265 } \ 266 } while (0) 267 268 /* ================================================================ 269 * Primary DMA command stream 270 */ 271 272 #define MGA_VERBOSE 0 273 274 #define DMA_LOCALS unsigned int write; volatile u8 *prim; 275 276 #define DMA_BLOCK_SIZE (5 * sizeof(u32)) 277 278 #define BEGIN_DMA( n ) \ 279 do { \ 280 if ( MGA_VERBOSE ) { \ 281 DRM_INFO( "BEGIN_DMA( %d ) in %s\n", \ 282 (n), __FUNCTION__ ); \ 283 DRM_INFO( " space=0x%x req=0x%Zx\n", \ 284 dev_priv->prim.space, (n) * DMA_BLOCK_SIZE ); \ 285 } \ 286 prim = dev_priv->prim.start; \ 287 write = dev_priv->prim.tail; \ 288 } while (0) 289 290 #define BEGIN_DMA_WRAP() \ 291 do { \ 292 if ( MGA_VERBOSE ) { \ 293 DRM_INFO( "BEGIN_DMA() in %s\n", __FUNCTION__ ); \ 294 DRM_INFO( " space=0x%x\n", dev_priv->prim.space ); \ 295 } \ 296 prim = dev_priv->prim.start; \ 297 write = dev_priv->prim.tail; \ 298 } while (0) 299 300 #define ADVANCE_DMA() \ 301 do { \ 302 dev_priv->prim.tail = write; \ 303 if ( MGA_VERBOSE ) { \ 304 DRM_INFO( "ADVANCE_DMA() tail=0x%05x sp=0x%x\n", \ 305 write, dev_priv->prim.space ); \ 306 } \ 307 } while (0) 308 309 #define FLUSH_DMA() \ 310 do { \ 311 if ( 0 ) { \ 312 DRM_INFO( "%s:\n", __FUNCTION__ ); \ 313 DRM_INFO( " tail=0x%06x head=0x%06lx\n", \ 314 dev_priv->prim.tail, \ 315 MGA_READ( MGA_PRIMADDRESS ) - \ 316 dev_priv->primary->offset ); \ 317 } \ 318 if ( !test_bit( 0, &dev_priv->prim.wrapped ) ) { \ 319 if ( dev_priv->prim.space < \ 320 dev_priv->prim.high_mark ) { \ 321 mga_do_dma_wrap_start( dev_priv ); \ 322 } else { \ 323 mga_do_dma_flush( dev_priv ); \ 324 } \ 325 } \ 326 } while (0) 327 328 /* Never use this, always use DMA_BLOCK(...) for primary DMA output. 329 */ 330 #define DMA_WRITE( offset, val ) \ 331 do { \ 332 if ( MGA_VERBOSE ) { \ 333 DRM_INFO( " DMA_WRITE( 0x%08x ) at 0x%04Zx\n", \ 334 (u32)(val), write + (offset) * sizeof(u32) ); \ 335 } \ 336 *(volatile u32 *)(prim + write + (offset) * sizeof(u32)) = val; \ 337 } while (0) 338 339 #define DMA_BLOCK( reg0, val0, reg1, val1, reg2, val2, reg3, val3 ) \ 340 do { \ 341 DMA_WRITE( 0, ((DMAREG( reg0 ) << 0) | \ 342 (DMAREG( reg1 ) << 8) | \ 343 (DMAREG( reg2 ) << 16) | \ 344 (DMAREG( reg3 ) << 24)) ); \ 345 DMA_WRITE( 1, val0 ); \ 346 DMA_WRITE( 2, val1 ); \ 347 DMA_WRITE( 3, val2 ); \ 348 DMA_WRITE( 4, val3 ); \ 349 write += DMA_BLOCK_SIZE; \ 350 } while (0) 351 352 /* Buffer aging via primary DMA stream head pointer. 353 */ 354 355 #define SET_AGE( age, h, w ) \ 356 do { \ 357 (age)->head = h; \ 358 (age)->wrap = w; \ 359 } while (0) 360 361 #define TEST_AGE( age, h, w ) ( (age)->wrap < w || \ 362 ( (age)->wrap == w && \ 363 (age)->head < h ) ) 364 365 #define AGE_BUFFER( buf_priv ) \ 366 do { \ 367 drm_mga_freelist_t *entry = (buf_priv)->list_entry; \ 368 if ( (buf_priv)->dispatched ) { \ 369 entry->age.head = (dev_priv->prim.tail + \ 370 dev_priv->primary->offset); \ 371 entry->age.wrap = dev_priv->sarea_priv->last_wrap; \ 372 } else { \ 373 entry->age.head = 0; \ 374 entry->age.wrap = 0; \ 375 } \ 376 } while (0) 377 378 #define MGA_ENGINE_IDLE_MASK (MGA_SOFTRAPEN | \ 379 MGA_DWGENGSTS | \ 380 MGA_ENDPRDMASTS) 381 #define MGA_DMA_IDLE_MASK (MGA_SOFTRAPEN | \ 382 MGA_ENDPRDMASTS) 383 384 #define MGA_DMA_DEBUG 0 385 386 /* A reduced set of the mga registers. 387 */ 388 #define MGA_CRTC_INDEX 0x1fd4 389 #define MGA_CRTC_DATA 0x1fd5 390 391 /* CRTC11 */ 392 #define MGA_VINTCLR (1 << 4) 393 #define MGA_VINTEN (1 << 5) 394 395 #define MGA_ALPHACTRL 0x2c7c 396 #define MGA_AR0 0x1c60 397 #define MGA_AR1 0x1c64 398 #define MGA_AR2 0x1c68 399 #define MGA_AR3 0x1c6c 400 #define MGA_AR4 0x1c70 401 #define MGA_AR5 0x1c74 402 #define MGA_AR6 0x1c78 403 404 #define MGA_CXBNDRY 0x1c80 405 #define MGA_CXLEFT 0x1ca0 406 #define MGA_CXRIGHT 0x1ca4 407 408 #define MGA_DMAPAD 0x1c54 409 #define MGA_DSTORG 0x2cb8 410 #define MGA_DWGCTL 0x1c00 411 # define MGA_OPCOD_MASK (15 << 0) 412 # define MGA_OPCOD_TRAP (4 << 0) 413 # define MGA_OPCOD_TEXTURE_TRAP (6 << 0) 414 # define MGA_OPCOD_BITBLT (8 << 0) 415 # define MGA_OPCOD_ILOAD (9 << 0) 416 # define MGA_ATYPE_MASK (7 << 4) 417 # define MGA_ATYPE_RPL (0 << 4) 418 # define MGA_ATYPE_RSTR (1 << 4) 419 # define MGA_ATYPE_ZI (3 << 4) 420 # define MGA_ATYPE_BLK (4 << 4) 421 # define MGA_ATYPE_I (7 << 4) 422 # define MGA_LINEAR (1 << 7) 423 # define MGA_ZMODE_MASK (7 << 8) 424 # define MGA_ZMODE_NOZCMP (0 << 8) 425 # define MGA_ZMODE_ZE (2 << 8) 426 # define MGA_ZMODE_ZNE (3 << 8) 427 # define MGA_ZMODE_ZLT (4 << 8) 428 # define MGA_ZMODE_ZLTE (5 << 8) 429 # define MGA_ZMODE_ZGT (6 << 8) 430 # define MGA_ZMODE_ZGTE (7 << 8) 431 # define MGA_SOLID (1 << 11) 432 # define MGA_ARZERO (1 << 12) 433 # define MGA_SGNZERO (1 << 13) 434 # define MGA_SHIFTZERO (1 << 14) 435 # define MGA_BOP_MASK (15 << 16) 436 # define MGA_BOP_ZERO (0 << 16) 437 # define MGA_BOP_DST (10 << 16) 438 # define MGA_BOP_SRC (12 << 16) 439 # define MGA_BOP_ONE (15 << 16) 440 # define MGA_TRANS_SHIFT 20 441 # define MGA_TRANS_MASK (15 << 20) 442 # define MGA_BLTMOD_MASK (15 << 25) 443 # define MGA_BLTMOD_BMONOLEF (0 << 25) 444 # define MGA_BLTMOD_BMONOWF (4 << 25) 445 # define MGA_BLTMOD_PLAN (1 << 25) 446 # define MGA_BLTMOD_BFCOL (2 << 25) 447 # define MGA_BLTMOD_BU32BGR (3 << 25) 448 # define MGA_BLTMOD_BU32RGB (7 << 25) 449 # define MGA_BLTMOD_BU24BGR (11 << 25) 450 # define MGA_BLTMOD_BU24RGB (15 << 25) 451 # define MGA_PATTERN (1 << 29) 452 # define MGA_TRANSC (1 << 30) 453 # define MGA_CLIPDIS (1 << 31) 454 #define MGA_DWGSYNC 0x2c4c 455 456 #define MGA_FCOL 0x1c24 457 #define MGA_FIFOSTATUS 0x1e10 458 #define MGA_FOGCOL 0x1cf4 459 #define MGA_FXBNDRY 0x1c84 460 #define MGA_FXLEFT 0x1ca8 461 #define MGA_FXRIGHT 0x1cac 462 463 #define MGA_ICLEAR 0x1e18 464 # define MGA_SOFTRAPICLR (1 << 0) 465 # define MGA_VLINEICLR (1 << 5) 466 #define MGA_IEN 0x1e1c 467 # define MGA_SOFTRAPIEN (1 << 0) 468 # define MGA_VLINEIEN (1 << 5) 469 470 #define MGA_LEN 0x1c5c 471 472 #define MGA_MACCESS 0x1c04 473 474 #define MGA_PITCH 0x1c8c 475 #define MGA_PLNWT 0x1c1c 476 #define MGA_PRIMADDRESS 0x1e58 477 # define MGA_DMA_GENERAL (0 << 0) 478 # define MGA_DMA_BLIT (1 << 0) 479 # define MGA_DMA_VECTOR (2 << 0) 480 # define MGA_DMA_VERTEX (3 << 0) 481 #define MGA_PRIMEND 0x1e5c 482 # define MGA_PRIMNOSTART (1 << 0) 483 # define MGA_PAGPXFER (1 << 1) 484 #define MGA_PRIMPTR 0x1e50 485 # define MGA_PRIMPTREN0 (1 << 0) 486 # define MGA_PRIMPTREN1 (1 << 1) 487 488 #define MGA_RST 0x1e40 489 # define MGA_SOFTRESET (1 << 0) 490 # define MGA_SOFTEXTRST (1 << 1) 491 492 #define MGA_SECADDRESS 0x2c40 493 #define MGA_SECEND 0x2c44 494 #define MGA_SETUPADDRESS 0x2cd0 495 #define MGA_SETUPEND 0x2cd4 496 #define MGA_SGN 0x1c58 497 #define MGA_SOFTRAP 0x2c48 498 #define MGA_SRCORG 0x2cb4 499 # define MGA_SRMMAP_MASK (1 << 0) 500 # define MGA_SRCMAP_FB (0 << 0) 501 # define MGA_SRCMAP_SYSMEM (1 << 0) 502 # define MGA_SRCACC_MASK (1 << 1) 503 # define MGA_SRCACC_PCI (0 << 1) 504 # define MGA_SRCACC_AGP (1 << 1) 505 #define MGA_STATUS 0x1e14 506 # define MGA_SOFTRAPEN (1 << 0) 507 # define MGA_VSYNCPEN (1 << 4) 508 # define MGA_VLINEPEN (1 << 5) 509 # define MGA_DWGENGSTS (1 << 16) 510 # define MGA_ENDPRDMASTS (1 << 17) 511 #define MGA_STENCIL 0x2cc8 512 #define MGA_STENCILCTL 0x2ccc 513 514 #define MGA_TDUALSTAGE0 0x2cf8 515 #define MGA_TDUALSTAGE1 0x2cfc 516 #define MGA_TEXBORDERCOL 0x2c5c 517 #define MGA_TEXCTL 0x2c30 518 #define MGA_TEXCTL2 0x2c3c 519 # define MGA_DUALTEX (1 << 7) 520 # define MGA_G400_TC2_MAGIC (1 << 15) 521 # define MGA_MAP1_ENABLE (1 << 31) 522 #define MGA_TEXFILTER 0x2c58 523 #define MGA_TEXHEIGHT 0x2c2c 524 #define MGA_TEXORG 0x2c24 525 # define MGA_TEXORGMAP_MASK (1 << 0) 526 # define MGA_TEXORGMAP_FB (0 << 0) 527 # define MGA_TEXORGMAP_SYSMEM (1 << 0) 528 # define MGA_TEXORGACC_MASK (1 << 1) 529 # define MGA_TEXORGACC_PCI (0 << 1) 530 # define MGA_TEXORGACC_AGP (1 << 1) 531 #define MGA_TEXORG1 0x2ca4 532 #define MGA_TEXORG2 0x2ca8 533 #define MGA_TEXORG3 0x2cac 534 #define MGA_TEXORG4 0x2cb0 535 #define MGA_TEXTRANS 0x2c34 536 #define MGA_TEXTRANSHIGH 0x2c38 537 #define MGA_TEXWIDTH 0x2c28 538 539 #define MGA_WACCEPTSEQ 0x1dd4 540 #define MGA_WCODEADDR 0x1e6c 541 #define MGA_WFLAG 0x1dc4 542 #define MGA_WFLAG1 0x1de0 543 #define MGA_WFLAGNB 0x1e64 544 #define MGA_WFLAGNB1 0x1e08 545 #define MGA_WGETMSB 0x1dc8 546 #define MGA_WIADDR 0x1dc0 547 #define MGA_WIADDR2 0x1dd8 548 # define MGA_WMODE_SUSPEND (0 << 0) 549 # define MGA_WMODE_RESUME (1 << 0) 550 # define MGA_WMODE_JUMP (2 << 0) 551 # define MGA_WMODE_START (3 << 0) 552 # define MGA_WAGP_ENABLE (1 << 2) 553 #define MGA_WMISC 0x1e70 554 # define MGA_WUCODECACHE_ENABLE (1 << 0) 555 # define MGA_WMASTER_ENABLE (1 << 1) 556 # define MGA_WCACHEFLUSH_ENABLE (1 << 3) 557 #define MGA_WVRTXSZ 0x1dcc 558 559 #define MGA_YBOT 0x1c9c 560 #define MGA_YDST 0x1c90 561 #define MGA_YDSTLEN 0x1c88 562 #define MGA_YDSTORG 0x1c94 563 #define MGA_YTOP 0x1c98 564 565 #define MGA_ZORG 0x1c0c 566 567 /* This finishes the current batch of commands 568 */ 569 #define MGA_EXEC 0x0100 570 571 /* AGP PLL encoding (for G200 only). 572 */ 573 #define MGA_AGP_PLL 0x1e4c 574 # define MGA_AGP2XPLL_DISABLE (0 << 0) 575 # define MGA_AGP2XPLL_ENABLE (1 << 0) 576 577 /* Warp registers 578 */ 579 #define MGA_WR0 0x2d00 580 #define MGA_WR1 0x2d04 581 #define MGA_WR2 0x2d08 582 #define MGA_WR3 0x2d0c 583 #define MGA_WR4 0x2d10 584 #define MGA_WR5 0x2d14 585 #define MGA_WR6 0x2d18 586 #define MGA_WR7 0x2d1c 587 #define MGA_WR8 0x2d20 588 #define MGA_WR9 0x2d24 589 #define MGA_WR10 0x2d28 590 #define MGA_WR11 0x2d2c 591 #define MGA_WR12 0x2d30 592 #define MGA_WR13 0x2d34 593 #define MGA_WR14 0x2d38 594 #define MGA_WR15 0x2d3c 595 #define MGA_WR16 0x2d40 596 #define MGA_WR17 0x2d44 597 #define MGA_WR18 0x2d48 598 #define MGA_WR19 0x2d4c 599 #define MGA_WR20 0x2d50 600 #define MGA_WR21 0x2d54 601 #define MGA_WR22 0x2d58 602 #define MGA_WR23 0x2d5c 603 #define MGA_WR24 0x2d60 604 #define MGA_WR25 0x2d64 605 #define MGA_WR26 0x2d68 606 #define MGA_WR27 0x2d6c 607 #define MGA_WR28 0x2d70 608 #define MGA_WR29 0x2d74 609 #define MGA_WR30 0x2d78 610 #define MGA_WR31 0x2d7c 611 #define MGA_WR32 0x2d80 612 #define MGA_WR33 0x2d84 613 #define MGA_WR34 0x2d88 614 #define MGA_WR35 0x2d8c 615 #define MGA_WR36 0x2d90 616 #define MGA_WR37 0x2d94 617 #define MGA_WR38 0x2d98 618 #define MGA_WR39 0x2d9c 619 #define MGA_WR40 0x2da0 620 #define MGA_WR41 0x2da4 621 #define MGA_WR42 0x2da8 622 #define MGA_WR43 0x2dac 623 #define MGA_WR44 0x2db0 624 #define MGA_WR45 0x2db4 625 #define MGA_WR46 0x2db8 626 #define MGA_WR47 0x2dbc 627 #define MGA_WR48 0x2dc0 628 #define MGA_WR49 0x2dc4 629 #define MGA_WR50 0x2dc8 630 #define MGA_WR51 0x2dcc 631 #define MGA_WR52 0x2dd0 632 #define MGA_WR53 0x2dd4 633 #define MGA_WR54 0x2dd8 634 #define MGA_WR55 0x2ddc 635 #define MGA_WR56 0x2de0 636 #define MGA_WR57 0x2de4 637 #define MGA_WR58 0x2de8 638 #define MGA_WR59 0x2dec 639 #define MGA_WR60 0x2df0 640 #define MGA_WR61 0x2df4 641 #define MGA_WR62 0x2df8 642 #define MGA_WR63 0x2dfc 643 # define MGA_G400_WR_MAGIC (1 << 6) 644 # define MGA_G400_WR56_MAGIC 0x46480000 /* 12800.0f */ 645 646 #define MGA_ILOAD_ALIGN 64 647 #define MGA_ILOAD_MASK (MGA_ILOAD_ALIGN - 1) 648 649 #define MGA_DWGCTL_FLUSH (MGA_OPCOD_TEXTURE_TRAP | \ 650 MGA_ATYPE_I | \ 651 MGA_ZMODE_NOZCMP | \ 652 MGA_ARZERO | \ 653 MGA_SGNZERO | \ 654 MGA_BOP_SRC | \ 655 (15 << MGA_TRANS_SHIFT)) 656 657 #define MGA_DWGCTL_CLEAR (MGA_OPCOD_TRAP | \ 658 MGA_ZMODE_NOZCMP | \ 659 MGA_SOLID | \ 660 MGA_ARZERO | \ 661 MGA_SGNZERO | \ 662 MGA_SHIFTZERO | \ 663 MGA_BOP_SRC | \ 664 (0 << MGA_TRANS_SHIFT) | \ 665 MGA_BLTMOD_BMONOLEF | \ 666 MGA_TRANSC | \ 667 MGA_CLIPDIS) 668 669 #define MGA_DWGCTL_COPY (MGA_OPCOD_BITBLT | \ 670 MGA_ATYPE_RPL | \ 671 MGA_SGNZERO | \ 672 MGA_SHIFTZERO | \ 673 MGA_BOP_SRC | \ 674 (0 << MGA_TRANS_SHIFT) | \ 675 MGA_BLTMOD_BFCOL | \ 676 MGA_CLIPDIS) 677 678 /* Simple idle test. 679 */ 680 static __inline__ int mga_is_idle(drm_mga_private_t * dev_priv) 681 { 682 u32 status = MGA_READ(MGA_STATUS) & MGA_ENGINE_IDLE_MASK; 683 return (status == MGA_ENDPRDMASTS); 684 } 685 686 #endif
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