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sys/dev/drm/r128_cce.c
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1 /* r128_cce.c -- ATI Rage 128 driver -*- linux-c -*- 2 * Created: Wed Apr 5 19:24:19 2000 by kevin@precisioninsight.com 3 * 4 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. 5 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 6 * All Rights Reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice (including the next 16 * paragraph) shall be included in all copies or substantial portions of the 17 * Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 22 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 25 * DEALINGS IN THE SOFTWARE. 26 * 27 * Authors: 28 * Gareth Hughes <gareth@valinux.com> 29 * 30 * $FreeBSD: releng/5.0/sys/dev/drm/r128_cce.c 97683 2002-05-31 23:19:50Z anholt $ 31 */ 32 33 #define __NO_VERSION__ 34 #include "dev/drm/r128.h" 35 #include "dev/drm/drmP.h" 36 #include "dev/drm/r128_drm.h" 37 #include "dev/drm/r128_drv.h" 38 39 #ifdef __linux__ 40 #include <linux/interrupt.h> /* For task queue support */ 41 #include <linux/delay.h> 42 #endif /* __linux__ */ 43 44 #define R128_FIFO_DEBUG 0 45 46 int r128_do_wait_for_idle( drm_r128_private_t *dev_priv ); 47 48 /* CCE microcode (from ATI) */ 49 static u32 r128_cce_microcode[] = { 50 0, 276838400, 0, 268449792, 2, 142, 2, 145, 0, 1076765731, 0, 51 1617039951, 0, 774592877, 0, 1987540286, 0, 2307490946U, 0, 52 599558925, 0, 589505315, 0, 596487092, 0, 589505315, 1, 53 11544576, 1, 206848, 1, 311296, 1, 198656, 2, 912273422, 11, 54 262144, 0, 0, 1, 33559837, 1, 7438, 1, 14809, 1, 6615, 12, 28, 55 1, 6614, 12, 28, 2, 23, 11, 18874368, 0, 16790922, 1, 409600, 9, 56 30, 1, 147854772, 16, 420483072, 3, 8192, 0, 10240, 1, 198656, 57 1, 15630, 1, 51200, 10, 34858, 9, 42, 1, 33559823, 2, 10276, 1, 58 15717, 1, 15718, 2, 43, 1, 15936948, 1, 570480831, 1, 14715071, 59 12, 322123831, 1, 33953125, 12, 55, 1, 33559908, 1, 15718, 2, 60 46, 4, 2099258, 1, 526336, 1, 442623, 4, 4194365, 1, 509952, 1, 61 459007, 3, 0, 12, 92, 2, 46, 12, 176, 1, 15734, 1, 206848, 1, 62 18432, 1, 133120, 1, 100670734, 1, 149504, 1, 165888, 1, 63 15975928, 1, 1048576, 6, 3145806, 1, 15715, 16, 2150645232U, 2, 64 268449859, 2, 10307, 12, 176, 1, 15734, 1, 15735, 1, 15630, 1, 65 15631, 1, 5253120, 6, 3145810, 16, 2150645232U, 1, 15864, 2, 82, 66 1, 343310, 1, 1064207, 2, 3145813, 1, 15728, 1, 7817, 1, 15729, 67 3, 15730, 12, 92, 2, 98, 1, 16168, 1, 16167, 1, 16002, 1, 16008, 68 1, 15974, 1, 15975, 1, 15990, 1, 15976, 1, 15977, 1, 15980, 0, 69 15981, 1, 10240, 1, 5253120, 1, 15720, 1, 198656, 6, 110, 1, 70 180224, 1, 103824738, 2, 112, 2, 3145839, 0, 536885440, 1, 71 114880, 14, 125, 12, 206975, 1, 33559995, 12, 198784, 0, 72 33570236, 1, 15803, 0, 15804, 3, 294912, 1, 294912, 3, 442370, 73 1, 11544576, 0, 811612160, 1, 12593152, 1, 11536384, 1, 74 14024704, 7, 310382726, 0, 10240, 1, 14796, 1, 14797, 1, 14793, 75 1, 14794, 0, 14795, 1, 268679168, 1, 9437184, 1, 268449792, 1, 76 198656, 1, 9452827, 1, 1075854602, 1, 1075854603, 1, 557056, 1, 77 114880, 14, 159, 12, 198784, 1, 1109409213, 12, 198783, 1, 78 1107312059, 12, 198784, 1, 1109409212, 2, 162, 1, 1075854781, 1, 79 1073757627, 1, 1075854780, 1, 540672, 1, 10485760, 6, 3145894, 80 16, 274741248, 9, 168, 3, 4194304, 3, 4209949, 0, 0, 0, 256, 14, 81 174, 1, 114857, 1, 33560007, 12, 176, 0, 10240, 1, 114858, 1, 82 33560018, 1, 114857, 3, 33560007, 1, 16008, 1, 114874, 1, 83 33560360, 1, 114875, 1, 33560154, 0, 15963, 0, 256, 0, 4096, 1, 84 409611, 9, 188, 0, 10240, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 85 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 86 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 87 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 88 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 89 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 90 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 91 }; 92 93 94 int R128_READ_PLL(drm_device_t *dev, int addr) 95 { 96 drm_r128_private_t *dev_priv = dev->dev_private; 97 98 R128_WRITE8(R128_CLOCK_CNTL_INDEX, addr & 0x1f); 99 return R128_READ(R128_CLOCK_CNTL_DATA); 100 } 101 102 #if R128_FIFO_DEBUG 103 static void r128_status( drm_r128_private_t *dev_priv ) 104 { 105 printk( "GUI_STAT = 0x%08x\n", 106 (unsigned int)R128_READ( R128_GUI_STAT ) ); 107 printk( "PM4_STAT = 0x%08x\n", 108 (unsigned int)R128_READ( R128_PM4_STAT ) ); 109 printk( "PM4_BUFFER_DL_WPTR = 0x%08x\n", 110 (unsigned int)R128_READ( R128_PM4_BUFFER_DL_WPTR ) ); 111 printk( "PM4_BUFFER_DL_RPTR = 0x%08x\n", 112 (unsigned int)R128_READ( R128_PM4_BUFFER_DL_RPTR ) ); 113 printk( "PM4_MICRO_CNTL = 0x%08x\n", 114 (unsigned int)R128_READ( R128_PM4_MICRO_CNTL ) ); 115 printk( "PM4_BUFFER_CNTL = 0x%08x\n", 116 (unsigned int)R128_READ( R128_PM4_BUFFER_CNTL ) ); 117 } 118 #endif 119 120 121 /* ================================================================ 122 * Engine, FIFO control 123 */ 124 125 static int r128_do_pixcache_flush( drm_r128_private_t *dev_priv ) 126 { 127 u32 tmp; 128 int i; 129 130 tmp = R128_READ( R128_PC_NGUI_CTLSTAT ) | R128_PC_FLUSH_ALL; 131 R128_WRITE( R128_PC_NGUI_CTLSTAT, tmp ); 132 133 for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { 134 if ( !(R128_READ( R128_PC_NGUI_CTLSTAT ) & R128_PC_BUSY) ) { 135 return 0; 136 } 137 DRM_OS_DELAY( 1 ); 138 } 139 140 #if R128_FIFO_DEBUG 141 DRM_ERROR( "%s failed!\n", __func__ ); 142 #endif 143 return DRM_OS_ERR(EBUSY); 144 } 145 146 static int r128_do_wait_for_fifo( drm_r128_private_t *dev_priv, int entries ) 147 { 148 int i; 149 150 for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { 151 int slots = R128_READ( R128_GUI_STAT ) & R128_GUI_FIFOCNT_MASK; 152 if ( slots >= entries ) return 0; 153 DRM_OS_DELAY( 1 ); 154 } 155 156 #if R128_FIFO_DEBUG 157 DRM_ERROR( "%s failed!\n", __func__ ); 158 #endif 159 return DRM_OS_ERR(EBUSY); 160 } 161 162 int r128_do_wait_for_idle( drm_r128_private_t *dev_priv ) 163 { 164 int i, ret; 165 166 ret = r128_do_wait_for_fifo( dev_priv, 64 ); 167 if ( ret ) return ret; 168 169 for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { 170 if ( !(R128_READ( R128_GUI_STAT ) & R128_GUI_ACTIVE) ) { 171 r128_do_pixcache_flush( dev_priv ); 172 return 0; 173 } 174 DRM_OS_DELAY( 1 ); 175 } 176 177 #if R128_FIFO_DEBUG 178 DRM_ERROR( "%s failed!\n", __func__ ); 179 #endif 180 return DRM_OS_ERR(EBUSY); 181 } 182 183 184 /* ================================================================ 185 * CCE control, initialization 186 */ 187 188 /* Load the microcode for the CCE */ 189 static void r128_cce_load_microcode( drm_r128_private_t *dev_priv ) 190 { 191 int i; 192 193 DRM_DEBUG( "%s\n", __func__ ); 194 195 r128_do_wait_for_idle( dev_priv ); 196 197 R128_WRITE( R128_PM4_MICROCODE_ADDR, 0 ); 198 for ( i = 0 ; i < 256 ; i++ ) { 199 R128_WRITE( R128_PM4_MICROCODE_DATAH, 200 r128_cce_microcode[i * 2] ); 201 R128_WRITE( R128_PM4_MICROCODE_DATAL, 202 r128_cce_microcode[i * 2 + 1] ); 203 } 204 } 205 206 /* Flush any pending commands to the CCE. This should only be used just 207 * prior to a wait for idle, as it informs the engine that the command 208 * stream is ending. 209 */ 210 static void r128_do_cce_flush( drm_r128_private_t *dev_priv ) 211 { 212 u32 tmp; 213 214 tmp = R128_READ( R128_PM4_BUFFER_DL_WPTR ) | R128_PM4_BUFFER_DL_DONE; 215 R128_WRITE( R128_PM4_BUFFER_DL_WPTR, tmp ); 216 } 217 218 /* Wait for the CCE to go idle. 219 */ 220 int r128_do_cce_idle( drm_r128_private_t *dev_priv ) 221 { 222 int i; 223 224 for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { 225 if ( GET_RING_HEAD( &dev_priv->ring ) == dev_priv->ring.tail ) { 226 int pm4stat = R128_READ( R128_PM4_STAT ); 227 if ( ( (pm4stat & R128_PM4_FIFOCNT_MASK) >= 228 dev_priv->cce_fifo_size ) && 229 !(pm4stat & (R128_PM4_BUSY | 230 R128_PM4_GUI_ACTIVE)) ) { 231 return r128_do_pixcache_flush( dev_priv ); 232 } 233 } 234 DRM_OS_DELAY( 1 ); 235 } 236 237 #if R128_FIFO_DEBUG 238 DRM_ERROR( "failed!\n" ); 239 r128_status( dev_priv ); 240 #endif 241 return DRM_OS_ERR(EBUSY); 242 } 243 244 /* Start the Concurrent Command Engine. 245 */ 246 static void r128_do_cce_start( drm_r128_private_t *dev_priv ) 247 { 248 r128_do_wait_for_idle( dev_priv ); 249 250 R128_WRITE( R128_PM4_BUFFER_CNTL, 251 dev_priv->cce_mode | dev_priv->ring.size_l2qw ); 252 R128_READ( R128_PM4_BUFFER_ADDR ); /* as per the sample code */ 253 R128_WRITE( R128_PM4_MICRO_CNTL, R128_PM4_MICRO_FREERUN ); 254 255 dev_priv->cce_running = 1; 256 } 257 258 /* Reset the Concurrent Command Engine. This will not flush any pending 259 * commands, so you must wait for the CCE command stream to complete 260 * before calling this routine. 261 */ 262 static void r128_do_cce_reset( drm_r128_private_t *dev_priv ) 263 { 264 R128_WRITE( R128_PM4_BUFFER_DL_WPTR, 0 ); 265 R128_WRITE( R128_PM4_BUFFER_DL_RPTR, 0 ); 266 SET_RING_HEAD( &dev_priv->ring, 0 ); 267 dev_priv->ring.tail = 0; 268 } 269 270 /* Stop the Concurrent Command Engine. This will not flush any pending 271 * commands, so you must flush the command stream and wait for the CCE 272 * to go idle before calling this routine. 273 */ 274 static void r128_do_cce_stop( drm_r128_private_t *dev_priv ) 275 { 276 R128_WRITE( R128_PM4_MICRO_CNTL, 0 ); 277 R128_WRITE( R128_PM4_BUFFER_CNTL, R128_PM4_NONPM4 ); 278 279 dev_priv->cce_running = 0; 280 } 281 282 /* Reset the engine. This will stop the CCE if it is running. 283 */ 284 static int r128_do_engine_reset( drm_device_t *dev ) 285 { 286 drm_r128_private_t *dev_priv = dev->dev_private; 287 u32 clock_cntl_index, mclk_cntl, gen_reset_cntl; 288 289 r128_do_pixcache_flush( dev_priv ); 290 291 clock_cntl_index = R128_READ( R128_CLOCK_CNTL_INDEX ); 292 mclk_cntl = R128_READ_PLL( dev, R128_MCLK_CNTL ); 293 294 R128_WRITE_PLL( R128_MCLK_CNTL, 295 mclk_cntl | R128_FORCE_GCP | R128_FORCE_PIPE3D_CP ); 296 297 gen_reset_cntl = R128_READ( R128_GEN_RESET_CNTL ); 298 299 /* Taken from the sample code - do not change */ 300 R128_WRITE( R128_GEN_RESET_CNTL, 301 gen_reset_cntl | R128_SOFT_RESET_GUI ); 302 R128_READ( R128_GEN_RESET_CNTL ); 303 R128_WRITE( R128_GEN_RESET_CNTL, 304 gen_reset_cntl & ~R128_SOFT_RESET_GUI ); 305 R128_READ( R128_GEN_RESET_CNTL ); 306 307 R128_WRITE_PLL( R128_MCLK_CNTL, mclk_cntl ); 308 R128_WRITE( R128_CLOCK_CNTL_INDEX, clock_cntl_index ); 309 R128_WRITE( R128_GEN_RESET_CNTL, gen_reset_cntl ); 310 311 /* Reset the CCE ring */ 312 r128_do_cce_reset( dev_priv ); 313 314 /* The CCE is no longer running after an engine reset */ 315 dev_priv->cce_running = 0; 316 317 /* Reset any pending vertex, indirect buffers */ 318 r128_freelist_reset( dev ); 319 320 return 0; 321 } 322 323 static void r128_cce_init_ring_buffer( drm_device_t *dev, 324 drm_r128_private_t *dev_priv ) 325 { 326 u32 ring_start; 327 u32 tmp; 328 329 DRM_DEBUG( "%s\n", __func__ ); 330 331 /* The manual (p. 2) says this address is in "VM space". This 332 * means it's an offset from the start of AGP space. 333 */ 334 #if __REALLY_HAVE_AGP 335 if ( !dev_priv->is_pci ) 336 ring_start = dev_priv->cce_ring->offset - dev->agp->base; 337 else 338 #endif 339 ring_start = dev_priv->cce_ring->offset - dev->sg->handle; 340 341 R128_WRITE( R128_PM4_BUFFER_OFFSET, ring_start | R128_AGP_OFFSET ); 342 343 R128_WRITE( R128_PM4_BUFFER_DL_WPTR, 0 ); 344 R128_WRITE( R128_PM4_BUFFER_DL_RPTR, 0 ); 345 346 /* DL_RPTR_ADDR is a physical address in AGP space. */ 347 SET_RING_HEAD( &dev_priv->ring, 0 ); 348 349 #if __REALLY_HAVE_SG 350 if ( !dev_priv->is_pci ) { 351 #endif 352 R128_WRITE( R128_PM4_BUFFER_DL_RPTR_ADDR, 353 dev_priv->ring_rptr->offset ); 354 #if __REALLY_HAVE_SG 355 } else { 356 drm_sg_mem_t *entry = dev->sg; 357 unsigned long tmp_ofs, page_ofs; 358 359 tmp_ofs = dev_priv->ring_rptr->offset - dev->sg->handle; 360 page_ofs = tmp_ofs >> PAGE_SHIFT; 361 362 R128_WRITE( R128_PM4_BUFFER_DL_RPTR_ADDR, 363 entry->busaddr[page_ofs]); 364 DRM_DEBUG( "ring rptr: offset=0x%08x handle=0x%08lx\n", 365 entry->busaddr[page_ofs], 366 entry->handle + tmp_ofs ); 367 } 368 #endif 369 370 /* Set watermark control */ 371 R128_WRITE( R128_PM4_BUFFER_WM_CNTL, 372 ((R128_WATERMARK_L/4) << R128_WMA_SHIFT) 373 | ((R128_WATERMARK_M/4) << R128_WMB_SHIFT) 374 | ((R128_WATERMARK_N/4) << R128_WMC_SHIFT) 375 | ((R128_WATERMARK_K/64) << R128_WB_WM_SHIFT) ); 376 377 /* Force read. Why? Because it's in the examples... */ 378 R128_READ( R128_PM4_BUFFER_ADDR ); 379 380 /* Turn on bus mastering */ 381 tmp = R128_READ( R128_BUS_CNTL ) & ~R128_BUS_MASTER_DIS; 382 R128_WRITE( R128_BUS_CNTL, tmp ); 383 } 384 385 static int r128_do_init_cce( drm_device_t *dev, drm_r128_init_t *init ) 386 { 387 drm_r128_private_t *dev_priv; 388 #ifdef __linux__ 389 struct list_head *list; 390 #endif /* __linux__ */ 391 #ifdef __FreeBSD__ 392 drm_map_list_entry_t *listentry; 393 #endif /* __FreeBSD__ */ 394 395 DRM_DEBUG( "%s\n", __func__ ); 396 397 dev_priv = DRM(alloc)( sizeof(drm_r128_private_t), DRM_MEM_DRIVER ); 398 if ( dev_priv == NULL ) 399 return DRM_OS_ERR(ENOMEM); 400 401 memset( dev_priv, 0, sizeof(drm_r128_private_t) ); 402 403 dev_priv->is_pci = init->is_pci; 404 405 if ( dev_priv->is_pci && !dev->sg ) { 406 DRM_ERROR( "PCI GART memory not allocated!\n" ); 407 dev->dev_private = (void *)dev_priv; 408 r128_do_cleanup_cce( dev ); 409 return DRM_OS_ERR(EINVAL); 410 } 411 412 dev_priv->usec_timeout = init->usec_timeout; 413 if ( dev_priv->usec_timeout < 1 || 414 dev_priv->usec_timeout > R128_MAX_USEC_TIMEOUT ) { 415 DRM_DEBUG( "TIMEOUT problem!\n" ); 416 dev->dev_private = (void *)dev_priv; 417 r128_do_cleanup_cce( dev ); 418 return DRM_OS_ERR(EINVAL); 419 } 420 421 dev_priv->cce_mode = init->cce_mode; 422 423 /* GH: Simple idle check. 424 */ 425 atomic_set( &dev_priv->idle_count, 0 ); 426 427 /* We don't support anything other than bus-mastering ring mode, 428 * but the ring can be in either AGP or PCI space for the ring 429 * read pointer. 430 */ 431 if ( ( init->cce_mode != R128_PM4_192BM ) && 432 ( init->cce_mode != R128_PM4_128BM_64INDBM ) && 433 ( init->cce_mode != R128_PM4_64BM_128INDBM ) && 434 ( init->cce_mode != R128_PM4_64BM_64VCBM_64INDBM ) ) { 435 DRM_DEBUG( "Bad cce_mode!\n" ); 436 dev->dev_private = (void *)dev_priv; 437 r128_do_cleanup_cce( dev ); 438 return DRM_OS_ERR(EINVAL); 439 } 440 441 switch ( init->cce_mode ) { 442 case R128_PM4_NONPM4: 443 dev_priv->cce_fifo_size = 0; 444 break; 445 case R128_PM4_192PIO: 446 case R128_PM4_192BM: 447 dev_priv->cce_fifo_size = 192; 448 break; 449 case R128_PM4_128PIO_64INDBM: 450 case R128_PM4_128BM_64INDBM: 451 dev_priv->cce_fifo_size = 128; 452 break; 453 case R128_PM4_64PIO_128INDBM: 454 case R128_PM4_64BM_128INDBM: 455 case R128_PM4_64PIO_64VCBM_64INDBM: 456 case R128_PM4_64BM_64VCBM_64INDBM: 457 case R128_PM4_64PIO_64VCPIO_64INDPIO: 458 dev_priv->cce_fifo_size = 64; 459 break; 460 } 461 462 switch ( init->fb_bpp ) { 463 case 16: 464 dev_priv->color_fmt = R128_DATATYPE_RGB565; 465 break; 466 case 32: 467 default: 468 dev_priv->color_fmt = R128_DATATYPE_ARGB8888; 469 break; 470 } 471 dev_priv->front_offset = init->front_offset; 472 dev_priv->front_pitch = init->front_pitch; 473 dev_priv->back_offset = init->back_offset; 474 dev_priv->back_pitch = init->back_pitch; 475 476 switch ( init->depth_bpp ) { 477 case 16: 478 dev_priv->depth_fmt = R128_DATATYPE_RGB565; 479 break; 480 case 24: 481 case 32: 482 default: 483 dev_priv->depth_fmt = R128_DATATYPE_ARGB8888; 484 break; 485 } 486 dev_priv->depth_offset = init->depth_offset; 487 dev_priv->depth_pitch = init->depth_pitch; 488 dev_priv->span_offset = init->span_offset; 489 490 dev_priv->front_pitch_offset_c = (((dev_priv->front_pitch/8) << 21) | 491 (dev_priv->front_offset >> 5)); 492 dev_priv->back_pitch_offset_c = (((dev_priv->back_pitch/8) << 21) | 493 (dev_priv->back_offset >> 5)); 494 dev_priv->depth_pitch_offset_c = (((dev_priv->depth_pitch/8) << 21) | 495 (dev_priv->depth_offset >> 5) | 496 R128_DST_TILE); 497 dev_priv->span_pitch_offset_c = (((dev_priv->depth_pitch/8) << 21) | 498 (dev_priv->span_offset >> 5)); 499 500 #ifdef __linux__ 501 list_for_each(list, &dev->maplist->head) { 502 drm_map_list_t *r_list = (drm_map_list_t *)list; 503 if( r_list->map && 504 r_list->map->type == _DRM_SHM && 505 r_list->map->flags & _DRM_CONTAINS_LOCK ) { 506 dev_priv->sarea = r_list->map; 507 break; 508 } 509 } 510 #endif /* __linux__ */ 511 #ifdef __FreeBSD__ 512 TAILQ_FOREACH(listentry, dev->maplist, link) { 513 drm_map_t *map = listentry->map; 514 if (map->type == _DRM_SHM && 515 map->flags & _DRM_CONTAINS_LOCK) { 516 dev_priv->sarea = map; 517 break; 518 } 519 } 520 #endif /* __FreeBSD__ */ 521 522 if(!dev_priv->sarea) { 523 DRM_ERROR("could not find sarea!\n"); 524 dev->dev_private = (void *)dev_priv; 525 r128_do_cleanup_cce( dev ); 526 return DRM_OS_ERR(EINVAL); 527 } 528 529 DRM_FIND_MAP( dev_priv->fb, init->fb_offset ); 530 if(!dev_priv->fb) { 531 DRM_ERROR("could not find framebuffer!\n"); 532 dev->dev_private = (void *)dev_priv; 533 r128_do_cleanup_cce( dev ); 534 return DRM_OS_ERR(EINVAL); 535 } 536 DRM_FIND_MAP( dev_priv->mmio, init->mmio_offset ); 537 if(!dev_priv->mmio) { 538 DRM_ERROR("could not find mmio region!\n"); 539 dev->dev_private = (void *)dev_priv; 540 r128_do_cleanup_cce( dev ); 541 return DRM_OS_ERR(EINVAL); 542 } 543 DRM_FIND_MAP( dev_priv->cce_ring, init->ring_offset ); 544 if(!dev_priv->cce_ring) { 545 DRM_ERROR("could not find cce ring region!\n"); 546 dev->dev_private = (void *)dev_priv; 547 r128_do_cleanup_cce( dev ); 548 return DRM_OS_ERR(EINVAL); 549 } 550 DRM_FIND_MAP( dev_priv->ring_rptr, init->ring_rptr_offset ); 551 if(!dev_priv->ring_rptr) { 552 DRM_ERROR("could not find ring read pointer!\n"); 553 dev->dev_private = (void *)dev_priv; 554 r128_do_cleanup_cce( dev ); 555 return DRM_OS_ERR(EINVAL); 556 } 557 DRM_FIND_MAP( dev_priv->buffers, init->buffers_offset ); 558 if(!dev_priv->buffers) { 559 DRM_ERROR("could not find dma buffer region!\n"); 560 dev->dev_private = (void *)dev_priv; 561 r128_do_cleanup_cce( dev ); 562 return DRM_OS_ERR(EINVAL); 563 } 564 565 if ( !dev_priv->is_pci ) { 566 DRM_FIND_MAP( dev_priv->agp_textures, 567 init->agp_textures_offset ); 568 if(!dev_priv->agp_textures) { 569 DRM_ERROR("could not find agp texture region!\n"); 570 dev->dev_private = (void *)dev_priv; 571 r128_do_cleanup_cce( dev ); 572 return DRM_OS_ERR(EINVAL); 573 } 574 } 575 576 dev_priv->sarea_priv = 577 (drm_r128_sarea_t *)((u8 *)dev_priv->sarea->handle + 578 init->sarea_priv_offset); 579 580 if ( !dev_priv->is_pci ) { 581 DRM_IOREMAP( dev_priv->cce_ring ); 582 DRM_IOREMAP( dev_priv->ring_rptr ); 583 DRM_IOREMAP( dev_priv->buffers ); 584 if(!dev_priv->cce_ring->handle || 585 !dev_priv->ring_rptr->handle || 586 !dev_priv->buffers->handle) { 587 DRM_ERROR("Could not ioremap agp regions!\n"); 588 dev->dev_private = (void *)dev_priv; 589 r128_do_cleanup_cce( dev ); 590 return DRM_OS_ERR(ENOMEM); 591 } 592 } else { 593 dev_priv->cce_ring->handle = 594 (void *)dev_priv->cce_ring->offset; 595 dev_priv->ring_rptr->handle = 596 (void *)dev_priv->ring_rptr->offset; 597 dev_priv->buffers->handle = (void *)dev_priv->buffers->offset; 598 } 599 600 #if __REALLY_HAVE_AGP 601 if ( !dev_priv->is_pci ) 602 dev_priv->cce_buffers_offset = dev->agp->base; 603 else 604 #endif 605 dev_priv->cce_buffers_offset = dev->sg->handle; 606 607 dev_priv->ring.head = ((__volatile__ u32 *) 608 dev_priv->ring_rptr->handle); 609 610 dev_priv->ring.start = (u32 *)dev_priv->cce_ring->handle; 611 dev_priv->ring.end = ((u32 *)dev_priv->cce_ring->handle 612 + init->ring_size / sizeof(u32)); 613 dev_priv->ring.size = init->ring_size; 614 dev_priv->ring.size_l2qw = DRM(order)( init->ring_size / 8 ); 615 616 dev_priv->ring.tail_mask = 617 (dev_priv->ring.size / sizeof(u32)) - 1; 618 619 dev_priv->ring.high_mark = 128; 620 621 dev_priv->sarea_priv->last_frame = 0; 622 R128_WRITE( R128_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame ); 623 624 dev_priv->sarea_priv->last_dispatch = 0; 625 R128_WRITE( R128_LAST_DISPATCH_REG, 626 dev_priv->sarea_priv->last_dispatch ); 627 628 #if __REALLY_HAVE_SG 629 if ( dev_priv->is_pci ) { 630 if (!DRM(ati_pcigart_init)( dev, &dev_priv->phys_pci_gart, 631 &dev_priv->bus_pci_gart) ) { 632 DRM_ERROR( "failed to init PCI GART!\n" ); 633 dev->dev_private = (void *)dev_priv; 634 r128_do_cleanup_cce( dev ); 635 return DRM_OS_ERR(ENOMEM); 636 } 637 R128_WRITE( R128_PCI_GART_PAGE, dev_priv->bus_pci_gart ); 638 } 639 #endif 640 641 r128_cce_init_ring_buffer( dev, dev_priv ); 642 r128_cce_load_microcode( dev_priv ); 643 644 dev->dev_private = (void *)dev_priv; 645 646 r128_do_engine_reset( dev ); 647 648 return 0; 649 } 650 651 int r128_do_cleanup_cce( drm_device_t *dev ) 652 { 653 if ( dev->dev_private ) { 654 drm_r128_private_t *dev_priv = dev->dev_private; 655 656 #if __REALLY_HAVE_SG 657 if ( !dev_priv->is_pci ) { 658 #endif 659 DRM_IOREMAPFREE( dev_priv->cce_ring ); 660 DRM_IOREMAPFREE( dev_priv->ring_rptr ); 661 DRM_IOREMAPFREE( dev_priv->buffers ); 662 #if __REALLY_HAVE_SG 663 } else { 664 if (!DRM(ati_pcigart_cleanup)( dev, 665 dev_priv->phys_pci_gart, 666 dev_priv->bus_pci_gart )) 667 DRM_ERROR( "failed to cleanup PCI GART!\n" ); 668 } 669 #endif 670 671 DRM(free)( dev->dev_private, sizeof(drm_r128_private_t), 672 DRM_MEM_DRIVER ); 673 dev->dev_private = NULL; 674 } 675 676 return 0; 677 } 678 679 int r128_cce_init( DRM_OS_IOCTL ) 680 { 681 DRM_OS_DEVICE; 682 drm_r128_init_t init; 683 684 DRM_DEBUG( "%s\n", __func__ ); 685 686 DRM_OS_KRNFROMUSR( init, (drm_r128_init_t *)data, sizeof(init) ); 687 688 switch ( init.func ) { 689 case R128_INIT_CCE: 690 return r128_do_init_cce( dev, &init ); 691 case R128_CLEANUP_CCE: 692 return r128_do_cleanup_cce( dev ); 693 } 694 695 return DRM_OS_ERR(EINVAL); 696 } 697 698 int r128_cce_start( DRM_OS_IOCTL ) 699 { 700 DRM_OS_DEVICE; 701 drm_r128_private_t *dev_priv = dev->dev_private; 702 DRM_DEBUG( "%s\n", __func__ ); 703 704 LOCK_TEST_WITH_RETURN( dev ); 705 706 if ( dev_priv->cce_running || dev_priv->cce_mode == R128_PM4_NONPM4 ) { 707 DRM_DEBUG( "%s while CCE running\n", __func__ ); 708 return 0; 709 } 710 711 r128_do_cce_start( dev_priv ); 712 713 return 0; 714 } 715 716 /* Stop the CCE. The engine must have been idled before calling this 717 * routine. 718 */ 719 int r128_cce_stop( DRM_OS_IOCTL ) 720 { 721 DRM_OS_DEVICE; 722 drm_r128_private_t *dev_priv = dev->dev_private; 723 drm_r128_cce_stop_t stop; 724 int ret; 725 DRM_DEBUG( "%s\n", __func__ ); 726 727 LOCK_TEST_WITH_RETURN( dev ); 728 729 DRM_OS_KRNFROMUSR(stop, (drm_r128_cce_stop_t *)data, sizeof(stop) ); 730 731 /* Flush any pending CCE commands. This ensures any outstanding 732 * commands are exectuted by the engine before we turn it off. 733 */ 734 if ( stop.flush ) { 735 r128_do_cce_flush( dev_priv ); 736 } 737 738 /* If we fail to make the engine go idle, we return an error 739 * code so that the DRM ioctl wrapper can try again. 740 */ 741 if ( stop.idle ) { 742 ret = r128_do_cce_idle( dev_priv ); 743 #ifdef __linux__ 744 if ( ret < 0 ) return ret; 745 #endif /* __linux__ */ 746 #ifdef __FreeBSD__ 747 if ( ret ) return ret; 748 #endif /* __FreeBSD__ */ 749 } 750 751 /* Finally, we can turn off the CCE. If the engine isn't idle, 752 * we will get some dropped triangles as they won't be fully 753 * rendered before the CCE is shut down. 754 */ 755 r128_do_cce_stop( dev_priv ); 756 757 /* Reset the engine */ 758 r128_do_engine_reset( dev ); 759 760 return 0; 761 } 762 763 /* Just reset the CCE ring. Called as part of an X Server engine reset. 764 */ 765 int r128_cce_reset( DRM_OS_IOCTL ) 766 { 767 DRM_OS_DEVICE; 768 drm_r128_private_t *dev_priv = dev->dev_private; 769 DRM_DEBUG( "%s\n", __func__ ); 770 771 LOCK_TEST_WITH_RETURN( dev ); 772 773 if ( !dev_priv ) { 774 DRM_DEBUG( "%s called before init done\n", __func__ ); 775 return DRM_OS_ERR(EINVAL); 776 } 777 778 r128_do_cce_reset( dev_priv ); 779 780 /* The CCE is no longer running after an engine reset */ 781 dev_priv->cce_running = 0; 782 783 return 0; 784 } 785 786 int r128_cce_idle( DRM_OS_IOCTL ) 787 { 788 DRM_OS_DEVICE; 789 drm_r128_private_t *dev_priv = dev->dev_private; 790 DRM_DEBUG( "%s\n", __func__ ); 791 792 LOCK_TEST_WITH_RETURN( dev ); 793 794 if ( dev_priv->cce_running ) { 795 r128_do_cce_flush( dev_priv ); 796 } 797 798 return r128_do_cce_idle( dev_priv ); 799 } 800 801 int r128_engine_reset( DRM_OS_IOCTL ) 802 { 803 DRM_OS_DEVICE; 804 DRM_DEBUG( "%s\n", __func__ ); 805 806 LOCK_TEST_WITH_RETURN( dev ); 807 808 return r128_do_engine_reset( dev ); 809 } 810 811 812 /* ================================================================ 813 * Fullscreen mode 814 */ 815 816 static int r128_do_init_pageflip( drm_device_t *dev ) 817 { 818 drm_r128_private_t *dev_priv = dev->dev_private; 819 DRM_DEBUG( "%s\n", __func__ ); 820 821 dev_priv->crtc_offset = R128_READ( R128_CRTC_OFFSET ); 822 dev_priv->crtc_offset_cntl = R128_READ( R128_CRTC_OFFSET_CNTL ); 823 824 R128_WRITE( R128_CRTC_OFFSET, dev_priv->front_offset ); 825 R128_WRITE( R128_CRTC_OFFSET_CNTL, 826 dev_priv->crtc_offset_cntl | R128_CRTC_OFFSET_FLIP_CNTL ); 827 828 dev_priv->page_flipping = 1; 829 dev_priv->current_page = 0; 830 831 return 0; 832 } 833 834 int r128_do_cleanup_pageflip( drm_device_t *dev ) 835 { 836 drm_r128_private_t *dev_priv = dev->dev_private; 837 DRM_DEBUG( "%s\n", __func__ ); 838 839 R128_WRITE( R128_CRTC_OFFSET, dev_priv->crtc_offset ); 840 R128_WRITE( R128_CRTC_OFFSET_CNTL, dev_priv->crtc_offset_cntl ); 841 842 dev_priv->page_flipping = 0; 843 dev_priv->current_page = 0; 844 845 return 0; 846 } 847 848 int r128_fullscreen( DRM_OS_IOCTL ) 849 { 850 DRM_OS_DEVICE; 851 drm_r128_fullscreen_t fs; 852 853 LOCK_TEST_WITH_RETURN( dev ); 854 855 DRM_OS_KRNFROMUSR( fs, (drm_r128_fullscreen_t *)data, sizeof(fs) ); 856 857 switch ( fs.func ) { 858 case R128_INIT_FULLSCREEN: 859 return r128_do_init_pageflip( dev ); 860 case R128_CLEANUP_FULLSCREEN: 861 return r128_do_cleanup_pageflip( dev ); 862 } 863 864 return DRM_OS_ERR(EINVAL); 865 } 866 867 868 /* ================================================================ 869 * Freelist management 870 */ 871 #define R128_BUFFER_USED 0xffffffff 872 #define R128_BUFFER_FREE 0 873 874 #if 0 875 static int r128_freelist_init( drm_device_t *dev ) 876 { 877 drm_device_dma_t *dma = dev->dma; 878 drm_r128_private_t *dev_priv = dev->dev_private; 879 drm_buf_t *buf; 880 drm_r128_buf_priv_t *buf_priv; 881 drm_r128_freelist_t *entry; 882 int i; 883 884 dev_priv->head = DRM(alloc)( sizeof(drm_r128_freelist_t), 885 DRM_MEM_DRIVER ); 886 if ( dev_priv->head == NULL ) 887 return DRM_OS_ERR(ENOMEM); 888 889 memset( dev_priv->head, 0, sizeof(drm_r128_freelist_t) ); 890 dev_priv->head->age = R128_BUFFER_USED; 891 892 for ( i = 0 ; i < dma->buf_count ; i++ ) { 893 buf = dma->buflist[i]; 894 buf_priv = buf->dev_private; 895 896 entry = DRM(alloc)( sizeof(drm_r128_freelist_t), 897 DRM_MEM_DRIVER ); 898 if ( !entry ) return DRM_OS_ERR(ENOMEM); 899 900 entry->age = R128_BUFFER_FREE; 901 entry->buf = buf; 902 entry->prev = dev_priv->head; 903 entry->next = dev_priv->head->next; 904 if ( !entry->next ) 905 dev_priv->tail = entry; 906 907 buf_priv->discard = 0; 908 buf_priv->dispatched = 0; 909 buf_priv->list_entry = entry; 910 911 dev_priv->head->next = entry; 912 913 if ( dev_priv->head->next ) 914 dev_priv->head->next->prev = entry; 915 } 916 917 return 0; 918 919 } 920 #endif 921 922 drm_buf_t *r128_freelist_get( drm_device_t *dev ) 923 { 924 drm_device_dma_t *dma = dev->dma; 925 drm_r128_private_t *dev_priv = dev->dev_private; 926 drm_r128_buf_priv_t *buf_priv; 927 drm_buf_t *buf; 928 int i, t; 929 930 /* FIXME: Optimize -- use freelist code */ 931 932 for ( i = 0 ; i < dma->buf_count ; i++ ) { 933 buf = dma->buflist[i]; 934 buf_priv = buf->dev_private; 935 if ( buf->pid == 0 ) 936 return buf; 937 } 938 939 for ( t = 0 ; t < dev_priv->usec_timeout ; t++ ) { 940 u32 done_age = R128_READ( R128_LAST_DISPATCH_REG ); 941 942 for ( i = 0 ; i < dma->buf_count ; i++ ) { 943 buf = dma->buflist[i]; 944 buf_priv = buf->dev_private; 945 if ( buf->pending && buf_priv->age <= done_age ) { 946 /* The buffer has been processed, so it 947 * can now be used. 948 */ 949 buf->pending = 0; 950 return buf; 951 } 952 } 953 DRM_OS_DELAY( 1 ); 954 } 955 956 DRM_ERROR( "returning NULL!\n" ); 957 return NULL; 958 } 959 960 void r128_freelist_reset( drm_device_t *dev ) 961 { 962 drm_device_dma_t *dma = dev->dma; 963 int i; 964 965 for ( i = 0 ; i < dma->buf_count ; i++ ) { 966 drm_buf_t *buf = dma->buflist[i]; 967 drm_r128_buf_priv_t *buf_priv = buf->dev_private; 968 buf_priv->age = 0; 969 } 970 } 971 972 973 /* ================================================================ 974 * CCE command submission 975 */ 976 977 int r128_wait_ring( drm_r128_private_t *dev_priv, int n ) 978 { 979 drm_r128_ring_buffer_t *ring = &dev_priv->ring; 980 int i; 981 982 for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { 983 r128_update_ring_snapshot( ring ); 984 if ( ring->space >= n ) 985 return 0; 986 DRM_OS_DELAY( 1 ); 987 } 988 989 /* FIXME: This is being ignored... */ 990 DRM_ERROR( "failed!\n" ); 991 return DRM_OS_ERR(EBUSY); 992 } 993 994 static int r128_cce_get_buffers( drm_device_t *dev, drm_dma_t *d) 995 { 996 int i; 997 drm_buf_t *buf; 998 999 for ( i = d->granted_count ; i < d->request_count ; i++ ) { 1000 buf = r128_freelist_get( dev ); 1001 if ( !buf ) return DRM_OS_ERR(EAGAIN); 1002 1003 buf->pid = DRM_OS_CURRENTPID; 1004 1005 if ( DRM_OS_COPYTOUSR( &d->request_indices[i], &buf->idx, 1006 sizeof(buf->idx) ) ) 1007 return DRM_OS_ERR(EFAULT); 1008 if ( DRM_OS_COPYTOUSR( &d->request_sizes[i], &buf->total, 1009 sizeof(buf->total) ) ) 1010 return DRM_OS_ERR(EFAULT); 1011 d->granted_count++; 1012 } 1013 return 0; 1014 } 1015 1016 int r128_cce_buffers( DRM_OS_IOCTL ) 1017 { 1018 DRM_OS_DEVICE; 1019 drm_device_dma_t *dma = dev->dma; 1020 int ret = 0; 1021 drm_dma_t d; 1022 1023 LOCK_TEST_WITH_RETURN( dev ); 1024 1025 DRM_OS_KRNFROMUSR( d, (drm_dma_t *) data, sizeof(d) ); 1026 1027 /* Please don't send us buffers. 1028 */ 1029 if ( d.send_count != 0 ) { 1030 DRM_ERROR( "Process %d trying to send %d buffers via drmDMA\n", 1031 DRM_OS_CURRENTPID, d.send_count ); 1032 return DRM_OS_ERR(EINVAL); 1033 } 1034 1035 /* We'll send you buffers. 1036 */ 1037 if ( d.request_count < 0 || d.request_count > dma->buf_count ) { 1038 DRM_ERROR( "Process %d trying to get %d buffers (of %d max)\n", 1039 DRM_OS_CURRENTPID, d.request_count, dma->buf_count ); 1040 return DRM_OS_ERR(EINVAL); 1041 } 1042 1043 d.granted_count = 0; 1044 1045 if ( d.request_count ) { 1046 ret = r128_cce_get_buffers( dev, &d ); 1047 } 1048 1049 DRM_OS_KRNTOUSR((drm_dma_t *) data, d, sizeof(d) ); 1050 1051 return ret; 1052 }
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