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sys/dev/drm/r128_cce.c
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1 /* r128_cce.c -- ATI Rage 128 driver -*- linux-c -*- 2 * Created: Wed Apr 5 19:24:19 2000 by kevin@precisioninsight.com 3 */ 4 /*- 5 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. 6 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 7 * All Rights Reserved. 8 * 9 * Permission is hereby granted, free of charge, to any person obtaining a 10 * copy of this software and associated documentation files (the "Software"), 11 * to deal in the Software without restriction, including without limitation 12 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 13 * and/or sell copies of the Software, and to permit persons to whom the 14 * Software is furnished to do so, subject to the following conditions: 15 * 16 * The above copyright notice and this permission notice (including the next 17 * paragraph) shall be included in all copies or substantial portions of the 18 * Software. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 23 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 24 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 25 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 26 * DEALINGS IN THE SOFTWARE. 27 * 28 * Authors: 29 * Gareth Hughes <gareth@valinux.com> 30 */ 31 32 #include <sys/cdefs.h> 33 __FBSDID("$FreeBSD: releng/6.4/sys/dev/drm/r128_cce.c 153401 2005-12-14 00:52:59Z anholt $"); 34 35 #include "dev/drm/drmP.h" 36 #include "dev/drm/drm.h" 37 #include "dev/drm/r128_drm.h" 38 #include "dev/drm/r128_drv.h" 39 40 #define R128_FIFO_DEBUG 0 41 42 /* CCE microcode (from ATI) */ 43 static u32 r128_cce_microcode[] = { 44 0, 276838400, 0, 268449792, 2, 142, 2, 145, 0, 1076765731, 0, 45 1617039951, 0, 774592877, 0, 1987540286, 0, 2307490946U, 0, 46 599558925, 0, 589505315, 0, 596487092, 0, 589505315, 1, 47 11544576, 1, 206848, 1, 311296, 1, 198656, 2, 912273422, 11, 48 262144, 0, 0, 1, 33559837, 1, 7438, 1, 14809, 1, 6615, 12, 28, 49 1, 6614, 12, 28, 2, 23, 11, 18874368, 0, 16790922, 1, 409600, 9, 50 30, 1, 147854772, 16, 420483072, 3, 8192, 0, 10240, 1, 198656, 51 1, 15630, 1, 51200, 10, 34858, 9, 42, 1, 33559823, 2, 10276, 1, 52 15717, 1, 15718, 2, 43, 1, 15936948, 1, 570480831, 1, 14715071, 53 12, 322123831, 1, 33953125, 12, 55, 1, 33559908, 1, 15718, 2, 54 46, 4, 2099258, 1, 526336, 1, 442623, 4, 4194365, 1, 509952, 1, 55 459007, 3, 0, 12, 92, 2, 46, 12, 176, 1, 15734, 1, 206848, 1, 56 18432, 1, 133120, 1, 100670734, 1, 149504, 1, 165888, 1, 57 15975928, 1, 1048576, 6, 3145806, 1, 15715, 16, 2150645232U, 2, 58 268449859, 2, 10307, 12, 176, 1, 15734, 1, 15735, 1, 15630, 1, 59 15631, 1, 5253120, 6, 3145810, 16, 2150645232U, 1, 15864, 2, 82, 60 1, 343310, 1, 1064207, 2, 3145813, 1, 15728, 1, 7817, 1, 15729, 61 3, 15730, 12, 92, 2, 98, 1, 16168, 1, 16167, 1, 16002, 1, 16008, 62 1, 15974, 1, 15975, 1, 15990, 1, 15976, 1, 15977, 1, 15980, 0, 63 15981, 1, 10240, 1, 5253120, 1, 15720, 1, 198656, 6, 110, 1, 64 180224, 1, 103824738, 2, 112, 2, 3145839, 0, 536885440, 1, 65 114880, 14, 125, 12, 206975, 1, 33559995, 12, 198784, 0, 66 33570236, 1, 15803, 0, 15804, 3, 294912, 1, 294912, 3, 442370, 67 1, 11544576, 0, 811612160, 1, 12593152, 1, 11536384, 1, 68 14024704, 7, 310382726, 0, 10240, 1, 14796, 1, 14797, 1, 14793, 69 1, 14794, 0, 14795, 1, 268679168, 1, 9437184, 1, 268449792, 1, 70 198656, 1, 9452827, 1, 1075854602, 1, 1075854603, 1, 557056, 1, 71 114880, 14, 159, 12, 198784, 1, 1109409213, 12, 198783, 1, 72 1107312059, 12, 198784, 1, 1109409212, 2, 162, 1, 1075854781, 1, 73 1073757627, 1, 1075854780, 1, 540672, 1, 10485760, 6, 3145894, 74 16, 274741248, 9, 168, 3, 4194304, 3, 4209949, 0, 0, 0, 256, 14, 75 174, 1, 114857, 1, 33560007, 12, 176, 0, 10240, 1, 114858, 1, 76 33560018, 1, 114857, 3, 33560007, 1, 16008, 1, 114874, 1, 77 33560360, 1, 114875, 1, 33560154, 0, 15963, 0, 256, 0, 4096, 1, 78 409611, 9, 188, 0, 10240, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 79 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 80 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 81 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 82 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 83 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 84 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 85 }; 86 87 static int R128_READ_PLL(drm_device_t * dev, int addr) 88 { 89 drm_r128_private_t *dev_priv = dev->dev_private; 90 91 R128_WRITE8(R128_CLOCK_CNTL_INDEX, addr & 0x1f); 92 return R128_READ(R128_CLOCK_CNTL_DATA); 93 } 94 95 #if R128_FIFO_DEBUG 96 static void r128_status(drm_r128_private_t * dev_priv) 97 { 98 printk("GUI_STAT = 0x%08x\n", 99 (unsigned int)R128_READ(R128_GUI_STAT)); 100 printk("PM4_STAT = 0x%08x\n", 101 (unsigned int)R128_READ(R128_PM4_STAT)); 102 printk("PM4_BUFFER_DL_WPTR = 0x%08x\n", 103 (unsigned int)R128_READ(R128_PM4_BUFFER_DL_WPTR)); 104 printk("PM4_BUFFER_DL_RPTR = 0x%08x\n", 105 (unsigned int)R128_READ(R128_PM4_BUFFER_DL_RPTR)); 106 printk("PM4_MICRO_CNTL = 0x%08x\n", 107 (unsigned int)R128_READ(R128_PM4_MICRO_CNTL)); 108 printk("PM4_BUFFER_CNTL = 0x%08x\n", 109 (unsigned int)R128_READ(R128_PM4_BUFFER_CNTL)); 110 } 111 #endif 112 113 /* ================================================================ 114 * Engine, FIFO control 115 */ 116 117 static int r128_do_pixcache_flush(drm_r128_private_t * dev_priv) 118 { 119 u32 tmp; 120 int i; 121 122 tmp = R128_READ(R128_PC_NGUI_CTLSTAT) | R128_PC_FLUSH_ALL; 123 R128_WRITE(R128_PC_NGUI_CTLSTAT, tmp); 124 125 for (i = 0; i < dev_priv->usec_timeout; i++) { 126 if (!(R128_READ(R128_PC_NGUI_CTLSTAT) & R128_PC_BUSY)) { 127 return 0; 128 } 129 DRM_UDELAY(1); 130 } 131 132 #if R128_FIFO_DEBUG 133 DRM_ERROR("failed!\n"); 134 #endif 135 return DRM_ERR(EBUSY); 136 } 137 138 static int r128_do_wait_for_fifo(drm_r128_private_t * dev_priv, int entries) 139 { 140 int i; 141 142 for (i = 0; i < dev_priv->usec_timeout; i++) { 143 int slots = R128_READ(R128_GUI_STAT) & R128_GUI_FIFOCNT_MASK; 144 if (slots >= entries) 145 return 0; 146 DRM_UDELAY(1); 147 } 148 149 #if R128_FIFO_DEBUG 150 DRM_ERROR("failed!\n"); 151 #endif 152 return DRM_ERR(EBUSY); 153 } 154 155 static int r128_do_wait_for_idle(drm_r128_private_t * dev_priv) 156 { 157 int i, ret; 158 159 ret = r128_do_wait_for_fifo(dev_priv, 64); 160 if (ret) 161 return ret; 162 163 for (i = 0; i < dev_priv->usec_timeout; i++) { 164 if (!(R128_READ(R128_GUI_STAT) & R128_GUI_ACTIVE)) { 165 r128_do_pixcache_flush(dev_priv); 166 return 0; 167 } 168 DRM_UDELAY(1); 169 } 170 171 #if R128_FIFO_DEBUG 172 DRM_ERROR("failed!\n"); 173 #endif 174 return DRM_ERR(EBUSY); 175 } 176 177 /* ================================================================ 178 * CCE control, initialization 179 */ 180 181 /* Load the microcode for the CCE */ 182 static void r128_cce_load_microcode(drm_r128_private_t * dev_priv) 183 { 184 int i; 185 186 DRM_DEBUG("\n"); 187 188 r128_do_wait_for_idle(dev_priv); 189 190 R128_WRITE(R128_PM4_MICROCODE_ADDR, 0); 191 for (i = 0; i < 256; i++) { 192 R128_WRITE(R128_PM4_MICROCODE_DATAH, r128_cce_microcode[i * 2]); 193 R128_WRITE(R128_PM4_MICROCODE_DATAL, 194 r128_cce_microcode[i * 2 + 1]); 195 } 196 } 197 198 /* Flush any pending commands to the CCE. This should only be used just 199 * prior to a wait for idle, as it informs the engine that the command 200 * stream is ending. 201 */ 202 static void r128_do_cce_flush(drm_r128_private_t * dev_priv) 203 { 204 u32 tmp; 205 206 tmp = R128_READ(R128_PM4_BUFFER_DL_WPTR) | R128_PM4_BUFFER_DL_DONE; 207 R128_WRITE(R128_PM4_BUFFER_DL_WPTR, tmp); 208 } 209 210 /* Wait for the CCE to go idle. 211 */ 212 int r128_do_cce_idle(drm_r128_private_t * dev_priv) 213 { 214 int i; 215 216 for (i = 0; i < dev_priv->usec_timeout; i++) { 217 if (GET_RING_HEAD(dev_priv) == dev_priv->ring.tail) { 218 int pm4stat = R128_READ(R128_PM4_STAT); 219 if (((pm4stat & R128_PM4_FIFOCNT_MASK) >= 220 dev_priv->cce_fifo_size) && 221 !(pm4stat & (R128_PM4_BUSY | 222 R128_PM4_GUI_ACTIVE))) { 223 return r128_do_pixcache_flush(dev_priv); 224 } 225 } 226 DRM_UDELAY(1); 227 } 228 229 #if R128_FIFO_DEBUG 230 DRM_ERROR("failed!\n"); 231 r128_status(dev_priv); 232 #endif 233 return DRM_ERR(EBUSY); 234 } 235 236 /* Start the Concurrent Command Engine. 237 */ 238 static void r128_do_cce_start(drm_r128_private_t * dev_priv) 239 { 240 r128_do_wait_for_idle(dev_priv); 241 242 R128_WRITE(R128_PM4_BUFFER_CNTL, 243 dev_priv->cce_mode | dev_priv->ring.size_l2qw 244 | R128_PM4_BUFFER_CNTL_NOUPDATE); 245 R128_READ(R128_PM4_BUFFER_ADDR); /* as per the sample code */ 246 R128_WRITE(R128_PM4_MICRO_CNTL, R128_PM4_MICRO_FREERUN); 247 248 dev_priv->cce_running = 1; 249 } 250 251 /* Reset the Concurrent Command Engine. This will not flush any pending 252 * commands, so you must wait for the CCE command stream to complete 253 * before calling this routine. 254 */ 255 static void r128_do_cce_reset(drm_r128_private_t * dev_priv) 256 { 257 R128_WRITE(R128_PM4_BUFFER_DL_WPTR, 0); 258 R128_WRITE(R128_PM4_BUFFER_DL_RPTR, 0); 259 dev_priv->ring.tail = 0; 260 } 261 262 /* Stop the Concurrent Command Engine. This will not flush any pending 263 * commands, so you must flush the command stream and wait for the CCE 264 * to go idle before calling this routine. 265 */ 266 static void r128_do_cce_stop(drm_r128_private_t * dev_priv) 267 { 268 R128_WRITE(R128_PM4_MICRO_CNTL, 0); 269 R128_WRITE(R128_PM4_BUFFER_CNTL, 270 R128_PM4_NONPM4 | R128_PM4_BUFFER_CNTL_NOUPDATE); 271 272 dev_priv->cce_running = 0; 273 } 274 275 /* Reset the engine. This will stop the CCE if it is running. 276 */ 277 static int r128_do_engine_reset(drm_device_t * dev) 278 { 279 drm_r128_private_t *dev_priv = dev->dev_private; 280 u32 clock_cntl_index, mclk_cntl, gen_reset_cntl; 281 282 r128_do_pixcache_flush(dev_priv); 283 284 clock_cntl_index = R128_READ(R128_CLOCK_CNTL_INDEX); 285 mclk_cntl = R128_READ_PLL(dev, R128_MCLK_CNTL); 286 287 R128_WRITE_PLL(R128_MCLK_CNTL, 288 mclk_cntl | R128_FORCE_GCP | R128_FORCE_PIPE3D_CP); 289 290 gen_reset_cntl = R128_READ(R128_GEN_RESET_CNTL); 291 292 /* Taken from the sample code - do not change */ 293 R128_WRITE(R128_GEN_RESET_CNTL, gen_reset_cntl | R128_SOFT_RESET_GUI); 294 R128_READ(R128_GEN_RESET_CNTL); 295 R128_WRITE(R128_GEN_RESET_CNTL, gen_reset_cntl & ~R128_SOFT_RESET_GUI); 296 R128_READ(R128_GEN_RESET_CNTL); 297 298 R128_WRITE_PLL(R128_MCLK_CNTL, mclk_cntl); 299 R128_WRITE(R128_CLOCK_CNTL_INDEX, clock_cntl_index); 300 R128_WRITE(R128_GEN_RESET_CNTL, gen_reset_cntl); 301 302 /* Reset the CCE ring */ 303 r128_do_cce_reset(dev_priv); 304 305 /* The CCE is no longer running after an engine reset */ 306 dev_priv->cce_running = 0; 307 308 /* Reset any pending vertex, indirect buffers */ 309 r128_freelist_reset(dev); 310 311 return 0; 312 } 313 314 static void r128_cce_init_ring_buffer(drm_device_t * dev, 315 drm_r128_private_t * dev_priv) 316 { 317 u32 ring_start; 318 u32 tmp; 319 320 DRM_DEBUG("\n"); 321 322 /* The manual (p. 2) says this address is in "VM space". This 323 * means it's an offset from the start of AGP space. 324 */ 325 #if __OS_HAS_AGP 326 if (!dev_priv->is_pci) 327 ring_start = dev_priv->cce_ring->offset - dev->agp->base; 328 else 329 #endif 330 ring_start = dev_priv->cce_ring->offset - 331 (unsigned long)dev->sg->virtual; 332 333 R128_WRITE(R128_PM4_BUFFER_OFFSET, ring_start | R128_AGP_OFFSET); 334 335 R128_WRITE(R128_PM4_BUFFER_DL_WPTR, 0); 336 R128_WRITE(R128_PM4_BUFFER_DL_RPTR, 0); 337 338 /* Set watermark control */ 339 R128_WRITE(R128_PM4_BUFFER_WM_CNTL, 340 ((R128_WATERMARK_L / 4) << R128_WMA_SHIFT) 341 | ((R128_WATERMARK_M / 4) << R128_WMB_SHIFT) 342 | ((R128_WATERMARK_N / 4) << R128_WMC_SHIFT) 343 | ((R128_WATERMARK_K / 64) << R128_WB_WM_SHIFT)); 344 345 /* Force read. Why? Because it's in the examples... */ 346 R128_READ(R128_PM4_BUFFER_ADDR); 347 348 /* Turn on bus mastering */ 349 tmp = R128_READ(R128_BUS_CNTL) & ~R128_BUS_MASTER_DIS; 350 R128_WRITE(R128_BUS_CNTL, tmp); 351 } 352 353 static int r128_do_init_cce(drm_device_t * dev, drm_r128_init_t * init) 354 { 355 drm_r128_private_t *dev_priv; 356 357 DRM_DEBUG("\n"); 358 359 dev_priv = drm_alloc(sizeof(drm_r128_private_t), DRM_MEM_DRIVER); 360 if (dev_priv == NULL) 361 return DRM_ERR(ENOMEM); 362 363 memset(dev_priv, 0, sizeof(drm_r128_private_t)); 364 365 dev_priv->is_pci = init->is_pci; 366 367 if (dev_priv->is_pci && !dev->sg) { 368 DRM_ERROR("PCI GART memory not allocated!\n"); 369 dev->dev_private = (void *)dev_priv; 370 r128_do_cleanup_cce(dev); 371 return DRM_ERR(EINVAL); 372 } 373 374 dev_priv->usec_timeout = init->usec_timeout; 375 if (dev_priv->usec_timeout < 1 || 376 dev_priv->usec_timeout > R128_MAX_USEC_TIMEOUT) { 377 DRM_DEBUG("TIMEOUT problem!\n"); 378 dev->dev_private = (void *)dev_priv; 379 r128_do_cleanup_cce(dev); 380 return DRM_ERR(EINVAL); 381 } 382 383 dev_priv->cce_mode = init->cce_mode; 384 385 /* GH: Simple idle check. 386 */ 387 atomic_set(&dev_priv->idle_count, 0); 388 389 /* We don't support anything other than bus-mastering ring mode, 390 * but the ring can be in either AGP or PCI space for the ring 391 * read pointer. 392 */ 393 if ((init->cce_mode != R128_PM4_192BM) && 394 (init->cce_mode != R128_PM4_128BM_64INDBM) && 395 (init->cce_mode != R128_PM4_64BM_128INDBM) && 396 (init->cce_mode != R128_PM4_64BM_64VCBM_64INDBM)) { 397 DRM_DEBUG("Bad cce_mode!\n"); 398 dev->dev_private = (void *)dev_priv; 399 r128_do_cleanup_cce(dev); 400 return DRM_ERR(EINVAL); 401 } 402 403 switch (init->cce_mode) { 404 case R128_PM4_NONPM4: 405 dev_priv->cce_fifo_size = 0; 406 break; 407 case R128_PM4_192PIO: 408 case R128_PM4_192BM: 409 dev_priv->cce_fifo_size = 192; 410 break; 411 case R128_PM4_128PIO_64INDBM: 412 case R128_PM4_128BM_64INDBM: 413 dev_priv->cce_fifo_size = 128; 414 break; 415 case R128_PM4_64PIO_128INDBM: 416 case R128_PM4_64BM_128INDBM: 417 case R128_PM4_64PIO_64VCBM_64INDBM: 418 case R128_PM4_64BM_64VCBM_64INDBM: 419 case R128_PM4_64PIO_64VCPIO_64INDPIO: 420 dev_priv->cce_fifo_size = 64; 421 break; 422 } 423 424 switch (init->fb_bpp) { 425 case 16: 426 dev_priv->color_fmt = R128_DATATYPE_RGB565; 427 break; 428 case 32: 429 default: 430 dev_priv->color_fmt = R128_DATATYPE_ARGB8888; 431 break; 432 } 433 dev_priv->front_offset = init->front_offset; 434 dev_priv->front_pitch = init->front_pitch; 435 dev_priv->back_offset = init->back_offset; 436 dev_priv->back_pitch = init->back_pitch; 437 438 switch (init->depth_bpp) { 439 case 16: 440 dev_priv->depth_fmt = R128_DATATYPE_RGB565; 441 break; 442 case 24: 443 case 32: 444 default: 445 dev_priv->depth_fmt = R128_DATATYPE_ARGB8888; 446 break; 447 } 448 dev_priv->depth_offset = init->depth_offset; 449 dev_priv->depth_pitch = init->depth_pitch; 450 dev_priv->span_offset = init->span_offset; 451 452 dev_priv->front_pitch_offset_c = (((dev_priv->front_pitch / 8) << 21) | 453 (dev_priv->front_offset >> 5)); 454 dev_priv->back_pitch_offset_c = (((dev_priv->back_pitch / 8) << 21) | 455 (dev_priv->back_offset >> 5)); 456 dev_priv->depth_pitch_offset_c = (((dev_priv->depth_pitch / 8) << 21) | 457 (dev_priv->depth_offset >> 5) | 458 R128_DST_TILE); 459 dev_priv->span_pitch_offset_c = (((dev_priv->depth_pitch / 8) << 21) | 460 (dev_priv->span_offset >> 5)); 461 462 DRM_GETSAREA(); 463 464 if (!dev_priv->sarea) { 465 DRM_ERROR("could not find sarea!\n"); 466 dev->dev_private = (void *)dev_priv; 467 r128_do_cleanup_cce(dev); 468 return DRM_ERR(EINVAL); 469 } 470 471 dev_priv->mmio = drm_core_findmap(dev, init->mmio_offset); 472 if (!dev_priv->mmio) { 473 DRM_ERROR("could not find mmio region!\n"); 474 dev->dev_private = (void *)dev_priv; 475 r128_do_cleanup_cce(dev); 476 return DRM_ERR(EINVAL); 477 } 478 dev_priv->cce_ring = drm_core_findmap(dev, init->ring_offset); 479 if (!dev_priv->cce_ring) { 480 DRM_ERROR("could not find cce ring region!\n"); 481 dev->dev_private = (void *)dev_priv; 482 r128_do_cleanup_cce(dev); 483 return DRM_ERR(EINVAL); 484 } 485 dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset); 486 if (!dev_priv->ring_rptr) { 487 DRM_ERROR("could not find ring read pointer!\n"); 488 dev->dev_private = (void *)dev_priv; 489 r128_do_cleanup_cce(dev); 490 return DRM_ERR(EINVAL); 491 } 492 dev->agp_buffer_token = init->buffers_offset; 493 dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset); 494 if (!dev->agp_buffer_map) { 495 DRM_ERROR("could not find dma buffer region!\n"); 496 dev->dev_private = (void *)dev_priv; 497 r128_do_cleanup_cce(dev); 498 return DRM_ERR(EINVAL); 499 } 500 501 if (!dev_priv->is_pci) { 502 dev_priv->agp_textures = 503 drm_core_findmap(dev, init->agp_textures_offset); 504 if (!dev_priv->agp_textures) { 505 DRM_ERROR("could not find agp texture region!\n"); 506 dev->dev_private = (void *)dev_priv; 507 r128_do_cleanup_cce(dev); 508 return DRM_ERR(EINVAL); 509 } 510 } 511 512 dev_priv->sarea_priv = 513 (drm_r128_sarea_t *) ((u8 *) dev_priv->sarea->handle + 514 init->sarea_priv_offset); 515 516 #if __OS_HAS_AGP 517 if (!dev_priv->is_pci) { 518 drm_core_ioremap(dev_priv->cce_ring, dev); 519 drm_core_ioremap(dev_priv->ring_rptr, dev); 520 drm_core_ioremap(dev->agp_buffer_map, dev); 521 if (!dev_priv->cce_ring->handle || 522 !dev_priv->ring_rptr->handle || 523 !dev->agp_buffer_map->handle) { 524 DRM_ERROR("Could not ioremap agp regions!\n"); 525 dev->dev_private = (void *)dev_priv; 526 r128_do_cleanup_cce(dev); 527 return DRM_ERR(ENOMEM); 528 } 529 } else 530 #endif 531 { 532 dev_priv->cce_ring->handle = (void *)dev_priv->cce_ring->offset; 533 dev_priv->ring_rptr->handle = 534 (void *)dev_priv->ring_rptr->offset; 535 dev->agp_buffer_map->handle = 536 (void *)dev->agp_buffer_map->offset; 537 } 538 539 #if __OS_HAS_AGP 540 if (!dev_priv->is_pci) 541 dev_priv->cce_buffers_offset = dev->agp->base; 542 else 543 #endif 544 dev_priv->cce_buffers_offset = (unsigned long)dev->sg->virtual; 545 546 dev_priv->ring.start = (u32 *) dev_priv->cce_ring->handle; 547 dev_priv->ring.end = ((u32 *) dev_priv->cce_ring->handle 548 + init->ring_size / sizeof(u32)); 549 dev_priv->ring.size = init->ring_size; 550 dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8); 551 552 dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1; 553 554 dev_priv->ring.high_mark = 128; 555 556 dev_priv->sarea_priv->last_frame = 0; 557 R128_WRITE(R128_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame); 558 559 dev_priv->sarea_priv->last_dispatch = 0; 560 R128_WRITE(R128_LAST_DISPATCH_REG, dev_priv->sarea_priv->last_dispatch); 561 562 #if __OS_HAS_AGP 563 if (dev_priv->is_pci) { 564 #endif 565 dev_priv->gart_info.gart_table_location = DRM_ATI_GART_MAIN; 566 dev_priv->gart_info.addr = NULL; 567 dev_priv->gart_info.bus_addr = 0; 568 dev_priv->gart_info.is_pcie = 0; 569 if (!drm_ati_pcigart_init(dev, &dev_priv->gart_info)) { 570 DRM_ERROR("failed to init PCI GART!\n"); 571 dev->dev_private = (void *)dev_priv; 572 r128_do_cleanup_cce(dev); 573 return DRM_ERR(ENOMEM); 574 } 575 R128_WRITE(R128_PCI_GART_PAGE, dev_priv->gart_info.bus_addr); 576 #if __OS_HAS_AGP 577 } 578 #endif 579 580 r128_cce_init_ring_buffer(dev, dev_priv); 581 r128_cce_load_microcode(dev_priv); 582 583 dev->dev_private = (void *)dev_priv; 584 585 r128_do_engine_reset(dev); 586 587 return 0; 588 } 589 590 int r128_do_cleanup_cce(drm_device_t * dev) 591 { 592 593 /* Make sure interrupts are disabled here because the uninstall ioctl 594 * may not have been called from userspace and after dev_private 595 * is freed, it's too late. 596 */ 597 if (dev->irq_enabled) 598 drm_irq_uninstall(dev); 599 600 if (dev->dev_private) { 601 drm_r128_private_t *dev_priv = dev->dev_private; 602 603 #if __OS_HAS_AGP 604 if (!dev_priv->is_pci) { 605 if (dev_priv->cce_ring != NULL) 606 drm_core_ioremapfree(dev_priv->cce_ring, dev); 607 if (dev_priv->ring_rptr != NULL) 608 drm_core_ioremapfree(dev_priv->ring_rptr, dev); 609 if (dev->agp_buffer_map != NULL) { 610 drm_core_ioremapfree(dev->agp_buffer_map, dev); 611 dev->agp_buffer_map = NULL; 612 } 613 } else 614 #endif 615 { 616 if (dev_priv->gart_info.bus_addr) 617 if (!drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info)) 618 DRM_ERROR("failed to cleanup PCI GART!\n"); 619 } 620 621 drm_free(dev->dev_private, sizeof(drm_r128_private_t), 622 DRM_MEM_DRIVER); 623 dev->dev_private = NULL; 624 } 625 626 return 0; 627 } 628 629 int r128_cce_init(DRM_IOCTL_ARGS) 630 { 631 DRM_DEVICE; 632 drm_r128_init_t init; 633 634 DRM_DEBUG("\n"); 635 636 LOCK_TEST_WITH_RETURN(dev, filp); 637 638 DRM_COPY_FROM_USER_IOCTL(init, (drm_r128_init_t __user *) data, 639 sizeof(init)); 640 641 switch (init.func) { 642 case R128_INIT_CCE: 643 return r128_do_init_cce(dev, &init); 644 case R128_CLEANUP_CCE: 645 return r128_do_cleanup_cce(dev); 646 } 647 648 return DRM_ERR(EINVAL); 649 } 650 651 int r128_cce_start(DRM_IOCTL_ARGS) 652 { 653 DRM_DEVICE; 654 drm_r128_private_t *dev_priv = dev->dev_private; 655 DRM_DEBUG("\n"); 656 657 LOCK_TEST_WITH_RETURN(dev, filp); 658 659 if (dev_priv->cce_running || dev_priv->cce_mode == R128_PM4_NONPM4) { 660 DRM_DEBUG("%s while CCE running\n", __FUNCTION__); 661 return 0; 662 } 663 664 r128_do_cce_start(dev_priv); 665 666 return 0; 667 } 668 669 /* Stop the CCE. The engine must have been idled before calling this 670 * routine. 671 */ 672 int r128_cce_stop(DRM_IOCTL_ARGS) 673 { 674 DRM_DEVICE; 675 drm_r128_private_t *dev_priv = dev->dev_private; 676 drm_r128_cce_stop_t stop; 677 int ret; 678 DRM_DEBUG("\n"); 679 680 LOCK_TEST_WITH_RETURN(dev, filp); 681 682 DRM_COPY_FROM_USER_IOCTL(stop, (drm_r128_cce_stop_t __user *) data, 683 sizeof(stop)); 684 685 /* Flush any pending CCE commands. This ensures any outstanding 686 * commands are exectuted by the engine before we turn it off. 687 */ 688 if (stop.flush) { 689 r128_do_cce_flush(dev_priv); 690 } 691 692 /* If we fail to make the engine go idle, we return an error 693 * code so that the DRM ioctl wrapper can try again. 694 */ 695 if (stop.idle) { 696 ret = r128_do_cce_idle(dev_priv); 697 if (ret) 698 return ret; 699 } 700 701 /* Finally, we can turn off the CCE. If the engine isn't idle, 702 * we will get some dropped triangles as they won't be fully 703 * rendered before the CCE is shut down. 704 */ 705 r128_do_cce_stop(dev_priv); 706 707 /* Reset the engine */ 708 r128_do_engine_reset(dev); 709 710 return 0; 711 } 712 713 /* Just reset the CCE ring. Called as part of an X Server engine reset. 714 */ 715 int r128_cce_reset(DRM_IOCTL_ARGS) 716 { 717 DRM_DEVICE; 718 drm_r128_private_t *dev_priv = dev->dev_private; 719 DRM_DEBUG("\n"); 720 721 LOCK_TEST_WITH_RETURN(dev, filp); 722 723 if (!dev_priv) { 724 DRM_DEBUG("%s called before init done\n", __FUNCTION__); 725 return DRM_ERR(EINVAL); 726 } 727 728 r128_do_cce_reset(dev_priv); 729 730 /* The CCE is no longer running after an engine reset */ 731 dev_priv->cce_running = 0; 732 733 return 0; 734 } 735 736 int r128_cce_idle(DRM_IOCTL_ARGS) 737 { 738 DRM_DEVICE; 739 drm_r128_private_t *dev_priv = dev->dev_private; 740 DRM_DEBUG("\n"); 741 742 LOCK_TEST_WITH_RETURN(dev, filp); 743 744 if (dev_priv->cce_running) { 745 r128_do_cce_flush(dev_priv); 746 } 747 748 return r128_do_cce_idle(dev_priv); 749 } 750 751 int r128_engine_reset(DRM_IOCTL_ARGS) 752 { 753 DRM_DEVICE; 754 DRM_DEBUG("\n"); 755 756 LOCK_TEST_WITH_RETURN(dev, filp); 757 758 return r128_do_engine_reset(dev); 759 } 760 761 int r128_fullscreen(DRM_IOCTL_ARGS) 762 { 763 return DRM_ERR(EINVAL); 764 } 765 766 /* ================================================================ 767 * Freelist management 768 */ 769 #define R128_BUFFER_USED 0xffffffff 770 #define R128_BUFFER_FREE 0 771 772 #if 0 773 static int r128_freelist_init(drm_device_t * dev) 774 { 775 drm_device_dma_t *dma = dev->dma; 776 drm_r128_private_t *dev_priv = dev->dev_private; 777 drm_buf_t *buf; 778 drm_r128_buf_priv_t *buf_priv; 779 drm_r128_freelist_t *entry; 780 int i; 781 782 dev_priv->head = drm_alloc(sizeof(drm_r128_freelist_t), DRM_MEM_DRIVER); 783 if (dev_priv->head == NULL) 784 return DRM_ERR(ENOMEM); 785 786 memset(dev_priv->head, 0, sizeof(drm_r128_freelist_t)); 787 dev_priv->head->age = R128_BUFFER_USED; 788 789 for (i = 0; i < dma->buf_count; i++) { 790 buf = dma->buflist[i]; 791 buf_priv = buf->dev_private; 792 793 entry = drm_alloc(sizeof(drm_r128_freelist_t), DRM_MEM_DRIVER); 794 if (!entry) 795 return DRM_ERR(ENOMEM); 796 797 entry->age = R128_BUFFER_FREE; 798 entry->buf = buf; 799 entry->prev = dev_priv->head; 800 entry->next = dev_priv->head->next; 801 if (!entry->next) 802 dev_priv->tail = entry; 803 804 buf_priv->discard = 0; 805 buf_priv->dispatched = 0; 806 buf_priv->list_entry = entry; 807 808 dev_priv->head->next = entry; 809 810 if (dev_priv->head->next) 811 dev_priv->head->next->prev = entry; 812 } 813 814 return 0; 815 816 } 817 #endif 818 819 static drm_buf_t *r128_freelist_get(drm_device_t * dev) 820 { 821 drm_device_dma_t *dma = dev->dma; 822 drm_r128_private_t *dev_priv = dev->dev_private; 823 drm_r128_buf_priv_t *buf_priv; 824 drm_buf_t *buf; 825 int i, t; 826 827 /* FIXME: Optimize -- use freelist code */ 828 829 for (i = 0; i < dma->buf_count; i++) { 830 buf = dma->buflist[i]; 831 buf_priv = buf->dev_private; 832 if (buf->filp == 0) 833 return buf; 834 } 835 836 for (t = 0; t < dev_priv->usec_timeout; t++) { 837 u32 done_age = R128_READ(R128_LAST_DISPATCH_REG); 838 839 for (i = 0; i < dma->buf_count; i++) { 840 buf = dma->buflist[i]; 841 buf_priv = buf->dev_private; 842 if (buf->pending && buf_priv->age <= done_age) { 843 /* The buffer has been processed, so it 844 * can now be used. 845 */ 846 buf->pending = 0; 847 return buf; 848 } 849 } 850 DRM_UDELAY(1); 851 } 852 853 DRM_DEBUG("returning NULL!\n"); 854 return NULL; 855 } 856 857 void r128_freelist_reset(drm_device_t * dev) 858 { 859 drm_device_dma_t *dma = dev->dma; 860 int i; 861 862 for (i = 0; i < dma->buf_count; i++) { 863 drm_buf_t *buf = dma->buflist[i]; 864 drm_r128_buf_priv_t *buf_priv = buf->dev_private; 865 buf_priv->age = 0; 866 } 867 } 868 869 /* ================================================================ 870 * CCE command submission 871 */ 872 873 int r128_wait_ring(drm_r128_private_t * dev_priv, int n) 874 { 875 drm_r128_ring_buffer_t *ring = &dev_priv->ring; 876 int i; 877 878 for (i = 0; i < dev_priv->usec_timeout; i++) { 879 r128_update_ring_snapshot(dev_priv); 880 if (ring->space >= n) 881 return 0; 882 DRM_UDELAY(1); 883 } 884 885 /* FIXME: This is being ignored... */ 886 DRM_ERROR("failed!\n"); 887 return DRM_ERR(EBUSY); 888 } 889 890 static int r128_cce_get_buffers(DRMFILE filp, drm_device_t * dev, drm_dma_t * d) 891 { 892 int i; 893 drm_buf_t *buf; 894 895 for (i = d->granted_count; i < d->request_count; i++) { 896 buf = r128_freelist_get(dev); 897 if (!buf) 898 return DRM_ERR(EAGAIN); 899 900 buf->filp = filp; 901 902 if (DRM_COPY_TO_USER(&d->request_indices[i], &buf->idx, 903 sizeof(buf->idx))) 904 return DRM_ERR(EFAULT); 905 if (DRM_COPY_TO_USER(&d->request_sizes[i], &buf->total, 906 sizeof(buf->total))) 907 return DRM_ERR(EFAULT); 908 909 d->granted_count++; 910 } 911 return 0; 912 } 913 914 int r128_cce_buffers(DRM_IOCTL_ARGS) 915 { 916 DRM_DEVICE; 917 drm_device_dma_t *dma = dev->dma; 918 int ret = 0; 919 drm_dma_t __user *argp = (void __user *)data; 920 drm_dma_t d; 921 922 LOCK_TEST_WITH_RETURN(dev, filp); 923 924 DRM_COPY_FROM_USER_IOCTL(d, argp, sizeof(d)); 925 926 /* Please don't send us buffers. 927 */ 928 if (d.send_count != 0) { 929 DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n", 930 DRM_CURRENTPID, d.send_count); 931 return DRM_ERR(EINVAL); 932 } 933 934 /* We'll send you buffers. 935 */ 936 if (d.request_count < 0 || d.request_count > dma->buf_count) { 937 DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n", 938 DRM_CURRENTPID, d.request_count, dma->buf_count); 939 return DRM_ERR(EINVAL); 940 } 941 942 d.granted_count = 0; 943 944 if (d.request_count) { 945 ret = r128_cce_get_buffers(filp, dev, &d); 946 } 947 948 DRM_COPY_TO_USER_IOCTL(argp, d, sizeof(d)); 949 950 return ret; 951 }
Cache object: d7ed0a76a74440ce6e21fd6fd5e46272
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