Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/dev/drm/r128_drv.h
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1 /* r128_drv.h -- Private header for r128 driver -*- linux-c -*- 2 * Created: Mon Dec 13 09:51:11 1999 by faith@precisioninsight.com */ 3 /*- 4 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. 5 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 6 * All rights reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice (including the next 16 * paragraph) shall be included in all copies or substantial portions of the 17 * Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 22 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 25 * DEALINGS IN THE SOFTWARE. 26 * 27 * Authors: 28 * Rickard E. (Rik) Faith <faith@valinux.com> 29 * Kevin E. Martin <martin@valinux.com> 30 * Gareth Hughes <gareth@valinux.com> 31 * Michel Dänzer <daenzerm@student.ethz.ch> 32 * 33 * $FreeBSD$ 34 */ 35 36 #ifndef __R128_DRV_H__ 37 #define __R128_DRV_H__ 38 39 #define GET_RING_HEAD(dev_priv) R128_READ( R128_PM4_BUFFER_DL_RPTR ) 40 41 typedef struct drm_r128_freelist { 42 unsigned int age; 43 drm_buf_t *buf; 44 struct drm_r128_freelist *next; 45 struct drm_r128_freelist *prev; 46 } drm_r128_freelist_t; 47 48 typedef struct drm_r128_ring_buffer { 49 u32 *start; 50 u32 *end; 51 int size; 52 int size_l2qw; 53 54 u32 tail; 55 u32 tail_mask; 56 int space; 57 58 int high_mark; 59 } drm_r128_ring_buffer_t; 60 61 typedef struct drm_r128_private { 62 drm_r128_ring_buffer_t ring; 63 drm_r128_sarea_t *sarea_priv; 64 65 int cce_mode; 66 int cce_fifo_size; 67 int cce_running; 68 69 drm_r128_freelist_t *head; 70 drm_r128_freelist_t *tail; 71 72 int usec_timeout; 73 int is_pci; 74 unsigned long phys_pci_gart; 75 dma_addr_t bus_pci_gart; 76 unsigned long cce_buffers_offset; 77 78 atomic_t idle_count; 79 80 int page_flipping; 81 int current_page; 82 u32 crtc_offset; 83 u32 crtc_offset_cntl; 84 85 u32 color_fmt; 86 unsigned int front_offset; 87 unsigned int front_pitch; 88 unsigned int back_offset; 89 unsigned int back_pitch; 90 91 u32 depth_fmt; 92 unsigned int depth_offset; 93 unsigned int depth_pitch; 94 unsigned int span_offset; 95 96 u32 front_pitch_offset_c; 97 u32 back_pitch_offset_c; 98 u32 depth_pitch_offset_c; 99 u32 span_pitch_offset_c; 100 101 drm_local_map_t *sarea; 102 drm_local_map_t *mmio; 103 drm_local_map_t *cce_ring; 104 drm_local_map_t *ring_rptr; 105 drm_local_map_t *buffers; 106 drm_local_map_t *agp_textures; 107 } drm_r128_private_t; 108 109 typedef struct drm_r128_buf_priv { 110 u32 age; 111 int prim; 112 int discard; 113 int dispatched; 114 drm_r128_freelist_t *list_entry; 115 } drm_r128_buf_priv_t; 116 117 /* r128_cce.c */ 118 extern int r128_cce_init( DRM_IOCTL_ARGS ); 119 extern int r128_cce_start( DRM_IOCTL_ARGS ); 120 extern int r128_cce_stop( DRM_IOCTL_ARGS ); 121 extern int r128_cce_reset( DRM_IOCTL_ARGS ); 122 extern int r128_cce_idle( DRM_IOCTL_ARGS ); 123 extern int r128_engine_reset( DRM_IOCTL_ARGS ); 124 extern int r128_fullscreen( DRM_IOCTL_ARGS ); 125 extern int r128_cce_buffers( DRM_IOCTL_ARGS ); 126 extern int r128_getparam( DRM_IOCTL_ARGS ); 127 128 extern void r128_freelist_reset( drm_device_t *dev ); 129 extern drm_buf_t *r128_freelist_get( drm_device_t *dev ); 130 131 extern int r128_wait_ring( drm_r128_private_t *dev_priv, int n ); 132 133 extern int r128_do_cce_idle( drm_r128_private_t *dev_priv ); 134 extern int r128_do_cleanup_cce( drm_device_t *dev ); 135 extern int r128_do_cleanup_pageflip( drm_device_t *dev ); 136 137 /* r128_state.c */ 138 extern int r128_cce_clear( DRM_IOCTL_ARGS ); 139 extern int r128_cce_swap( DRM_IOCTL_ARGS ); 140 extern int r128_cce_flip( DRM_IOCTL_ARGS ); 141 extern int r128_cce_vertex( DRM_IOCTL_ARGS ); 142 extern int r128_cce_indices( DRM_IOCTL_ARGS ); 143 extern int r128_cce_blit( DRM_IOCTL_ARGS ); 144 extern int r128_cce_depth( DRM_IOCTL_ARGS ); 145 extern int r128_cce_stipple( DRM_IOCTL_ARGS ); 146 extern int r128_cce_indirect( DRM_IOCTL_ARGS ); 147 148 149 /* Register definitions, register access macros and drmAddMap constants 150 * for Rage 128 kernel driver. 151 */ 152 153 #define R128_AUX_SC_CNTL 0x1660 154 # define R128_AUX1_SC_EN (1 << 0) 155 # define R128_AUX1_SC_MODE_OR (0 << 1) 156 # define R128_AUX1_SC_MODE_NAND (1 << 1) 157 # define R128_AUX2_SC_EN (1 << 2) 158 # define R128_AUX2_SC_MODE_OR (0 << 3) 159 # define R128_AUX2_SC_MODE_NAND (1 << 3) 160 # define R128_AUX3_SC_EN (1 << 4) 161 # define R128_AUX3_SC_MODE_OR (0 << 5) 162 # define R128_AUX3_SC_MODE_NAND (1 << 5) 163 #define R128_AUX1_SC_LEFT 0x1664 164 #define R128_AUX1_SC_RIGHT 0x1668 165 #define R128_AUX1_SC_TOP 0x166c 166 #define R128_AUX1_SC_BOTTOM 0x1670 167 #define R128_AUX2_SC_LEFT 0x1674 168 #define R128_AUX2_SC_RIGHT 0x1678 169 #define R128_AUX2_SC_TOP 0x167c 170 #define R128_AUX2_SC_BOTTOM 0x1680 171 #define R128_AUX3_SC_LEFT 0x1684 172 #define R128_AUX3_SC_RIGHT 0x1688 173 #define R128_AUX3_SC_TOP 0x168c 174 #define R128_AUX3_SC_BOTTOM 0x1690 175 176 #define R128_BRUSH_DATA0 0x1480 177 #define R128_BUS_CNTL 0x0030 178 # define R128_BUS_MASTER_DIS (1 << 6) 179 180 #define R128_CLOCK_CNTL_INDEX 0x0008 181 #define R128_CLOCK_CNTL_DATA 0x000c 182 # define R128_PLL_WR_EN (1 << 7) 183 #define R128_CONSTANT_COLOR_C 0x1d34 184 #define R128_CRTC_OFFSET 0x0224 185 #define R128_CRTC_OFFSET_CNTL 0x0228 186 # define R128_CRTC_OFFSET_FLIP_CNTL (1 << 16) 187 188 #define R128_DP_GUI_MASTER_CNTL 0x146c 189 # define R128_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0) 190 # define R128_GMC_DST_PITCH_OFFSET_CNTL (1 << 1) 191 # define R128_GMC_BRUSH_SOLID_COLOR (13 << 4) 192 # define R128_GMC_BRUSH_NONE (15 << 4) 193 # define R128_GMC_DST_16BPP (4 << 8) 194 # define R128_GMC_DST_24BPP (5 << 8) 195 # define R128_GMC_DST_32BPP (6 << 8) 196 # define R128_GMC_DST_DATATYPE_SHIFT 8 197 # define R128_GMC_SRC_DATATYPE_COLOR (3 << 12) 198 # define R128_DP_SRC_SOURCE_MEMORY (2 << 24) 199 # define R128_DP_SRC_SOURCE_HOST_DATA (3 << 24) 200 # define R128_GMC_CLR_CMP_CNTL_DIS (1 << 28) 201 # define R128_GMC_AUX_CLIP_DIS (1 << 29) 202 # define R128_GMC_WR_MSK_DIS (1 << 30) 203 # define R128_ROP3_S 0x00cc0000 204 # define R128_ROP3_P 0x00f00000 205 #define R128_DP_WRITE_MASK 0x16cc 206 #define R128_DST_PITCH_OFFSET_C 0x1c80 207 # define R128_DST_TILE (1 << 31) 208 209 #define R128_GEN_INT_CNTL 0x0040 210 # define R128_CRTC_VBLANK_INT_EN (1 << 0) 211 #define R128_GEN_INT_STATUS 0x0044 212 # define R128_CRTC_VBLANK_INT (1 << 0) 213 # define R128_CRTC_VBLANK_INT_AK (1 << 0) 214 #define R128_GEN_RESET_CNTL 0x00f0 215 # define R128_SOFT_RESET_GUI (1 << 0) 216 217 #define R128_GUI_SCRATCH_REG0 0x15e0 218 #define R128_GUI_SCRATCH_REG1 0x15e4 219 #define R128_GUI_SCRATCH_REG2 0x15e8 220 #define R128_GUI_SCRATCH_REG3 0x15ec 221 #define R128_GUI_SCRATCH_REG4 0x15f0 222 #define R128_GUI_SCRATCH_REG5 0x15f4 223 224 #define R128_GUI_STAT 0x1740 225 # define R128_GUI_FIFOCNT_MASK 0x0fff 226 # define R128_GUI_ACTIVE (1 << 31) 227 228 #define R128_MCLK_CNTL 0x000f 229 # define R128_FORCE_GCP (1 << 16) 230 # define R128_FORCE_PIPE3D_CP (1 << 17) 231 # define R128_FORCE_RCP (1 << 18) 232 233 #define R128_PC_GUI_CTLSTAT 0x1748 234 #define R128_PC_NGUI_CTLSTAT 0x0184 235 # define R128_PC_FLUSH_GUI (3 << 0) 236 # define R128_PC_RI_GUI (1 << 2) 237 # define R128_PC_FLUSH_ALL 0x00ff 238 # define R128_PC_BUSY (1 << 31) 239 240 #define R128_PCI_GART_PAGE 0x017c 241 #define R128_PRIM_TEX_CNTL_C 0x1cb0 242 243 #define R128_SCALE_3D_CNTL 0x1a00 244 #define R128_SEC_TEX_CNTL_C 0x1d00 245 #define R128_SEC_TEXTURE_BORDER_COLOR_C 0x1d3c 246 #define R128_SETUP_CNTL 0x1bc4 247 #define R128_STEN_REF_MASK_C 0x1d40 248 249 #define R128_TEX_CNTL_C 0x1c9c 250 # define R128_TEX_CACHE_FLUSH (1 << 23) 251 252 #define R128_WAIT_UNTIL 0x1720 253 # define R128_EVENT_CRTC_OFFSET (1 << 0) 254 #define R128_WINDOW_XY_OFFSET 0x1bcc 255 256 257 /* CCE registers 258 */ 259 #define R128_PM4_BUFFER_OFFSET 0x0700 260 #define R128_PM4_BUFFER_CNTL 0x0704 261 # define R128_PM4_MASK (15 << 28) 262 # define R128_PM4_NONPM4 (0 << 28) 263 # define R128_PM4_192PIO (1 << 28) 264 # define R128_PM4_192BM (2 << 28) 265 # define R128_PM4_128PIO_64INDBM (3 << 28) 266 # define R128_PM4_128BM_64INDBM (4 << 28) 267 # define R128_PM4_64PIO_128INDBM (5 << 28) 268 # define R128_PM4_64BM_128INDBM (6 << 28) 269 # define R128_PM4_64PIO_64VCBM_64INDBM (7 << 28) 270 # define R128_PM4_64BM_64VCBM_64INDBM (8 << 28) 271 # define R128_PM4_64PIO_64VCPIO_64INDPIO (15 << 28) 272 # define R128_PM4_BUFFER_CNTL_NOUPDATE (1 << 27) 273 274 #define R128_PM4_BUFFER_WM_CNTL 0x0708 275 # define R128_WMA_SHIFT 0 276 # define R128_WMB_SHIFT 8 277 # define R128_WMC_SHIFT 16 278 # define R128_WB_WM_SHIFT 24 279 280 #define R128_PM4_BUFFER_DL_RPTR_ADDR 0x070c 281 #define R128_PM4_BUFFER_DL_RPTR 0x0710 282 #define R128_PM4_BUFFER_DL_WPTR 0x0714 283 # define R128_PM4_BUFFER_DL_DONE (1 << 31) 284 285 #define R128_PM4_VC_FPU_SETUP 0x071c 286 287 #define R128_PM4_IW_INDOFF 0x0738 288 #define R128_PM4_IW_INDSIZE 0x073c 289 290 #define R128_PM4_STAT 0x07b8 291 # define R128_PM4_FIFOCNT_MASK 0x0fff 292 # define R128_PM4_BUSY (1 << 16) 293 # define R128_PM4_GUI_ACTIVE (1 << 31) 294 295 #define R128_PM4_MICROCODE_ADDR 0x07d4 296 #define R128_PM4_MICROCODE_RADDR 0x07d8 297 #define R128_PM4_MICROCODE_DATAH 0x07dc 298 #define R128_PM4_MICROCODE_DATAL 0x07e0 299 300 #define R128_PM4_BUFFER_ADDR 0x07f0 301 #define R128_PM4_MICRO_CNTL 0x07fc 302 # define R128_PM4_MICRO_FREERUN (1 << 30) 303 304 #define R128_PM4_FIFO_DATA_EVEN 0x1000 305 #define R128_PM4_FIFO_DATA_ODD 0x1004 306 307 308 /* CCE command packets 309 */ 310 #define R128_CCE_PACKET0 0x00000000 311 #define R128_CCE_PACKET1 0x40000000 312 #define R128_CCE_PACKET2 0x80000000 313 #define R128_CCE_PACKET3 0xC0000000 314 # define R128_CNTL_HOSTDATA_BLT 0x00009400 315 # define R128_CNTL_PAINT_MULTI 0x00009A00 316 # define R128_CNTL_BITBLT_MULTI 0x00009B00 317 # define R128_3D_RNDR_GEN_INDX_PRIM 0x00002300 318 319 #define R128_CCE_PACKET_MASK 0xC0000000 320 #define R128_CCE_PACKET_COUNT_MASK 0x3fff0000 321 #define R128_CCE_PACKET0_REG_MASK 0x000007ff 322 #define R128_CCE_PACKET1_REG0_MASK 0x000007ff 323 #define R128_CCE_PACKET1_REG1_MASK 0x003ff800 324 325 #define R128_CCE_VC_CNTL_PRIM_TYPE_NONE 0x00000000 326 #define R128_CCE_VC_CNTL_PRIM_TYPE_POINT 0x00000001 327 #define R128_CCE_VC_CNTL_PRIM_TYPE_LINE 0x00000002 328 #define R128_CCE_VC_CNTL_PRIM_TYPE_POLY_LINE 0x00000003 329 #define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_LIST 0x00000004 330 #define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_FAN 0x00000005 331 #define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_STRIP 0x00000006 332 #define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_TYPE2 0x00000007 333 #define R128_CCE_VC_CNTL_PRIM_WALK_IND 0x00000010 334 #define R128_CCE_VC_CNTL_PRIM_WALK_LIST 0x00000020 335 #define R128_CCE_VC_CNTL_PRIM_WALK_RING 0x00000030 336 #define R128_CCE_VC_CNTL_NUM_SHIFT 16 337 338 #define R128_DATATYPE_VQ 0 339 #define R128_DATATYPE_CI4 1 340 #define R128_DATATYPE_CI8 2 341 #define R128_DATATYPE_ARGB1555 3 342 #define R128_DATATYPE_RGB565 4 343 #define R128_DATATYPE_RGB888 5 344 #define R128_DATATYPE_ARGB8888 6 345 #define R128_DATATYPE_RGB332 7 346 #define R128_DATATYPE_Y8 8 347 #define R128_DATATYPE_RGB8 9 348 #define R128_DATATYPE_CI16 10 349 #define R128_DATATYPE_YVYU422 11 350 #define R128_DATATYPE_VYUY422 12 351 #define R128_DATATYPE_AYUV444 14 352 #define R128_DATATYPE_ARGB4444 15 353 354 /* Constants */ 355 #define R128_AGP_OFFSET 0x02000000 356 357 #define R128_WATERMARK_L 16 358 #define R128_WATERMARK_M 8 359 #define R128_WATERMARK_N 8 360 #define R128_WATERMARK_K 128 361 362 #define R128_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 363 364 #define R128_LAST_FRAME_REG R128_GUI_SCRATCH_REG0 365 #define R128_LAST_DISPATCH_REG R128_GUI_SCRATCH_REG1 366 #define R128_MAX_VB_AGE 0x7fffffff 367 #define R128_MAX_VB_VERTS (0xffff) 368 369 #define R128_RING_HIGH_MARK 128 370 371 #define R128_PERFORMANCE_BOXES 0 372 373 #define R128_READ(reg) DRM_READ32( dev_priv->mmio, (reg) ) 374 #define R128_WRITE(reg,val) DRM_WRITE32( dev_priv->mmio, (reg), (val) ) 375 #define R128_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) ) 376 #define R128_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) ) 377 378 #define R128_WRITE_PLL(addr,val) \ 379 do { \ 380 R128_WRITE8(R128_CLOCK_CNTL_INDEX, \ 381 ((addr) & 0x1f) | R128_PLL_WR_EN); \ 382 R128_WRITE(R128_CLOCK_CNTL_DATA, (val)); \ 383 } while (0) 384 385 extern int R128_READ_PLL(drm_device_t *dev, int addr); 386 387 388 #define CCE_PACKET0( reg, n ) (R128_CCE_PACKET0 | \ 389 ((n) << 16) | ((reg) >> 2)) 390 #define CCE_PACKET1( reg0, reg1 ) (R128_CCE_PACKET1 | \ 391 (((reg1) >> 2) << 11) | ((reg0) >> 2)) 392 #define CCE_PACKET2() (R128_CCE_PACKET2) 393 #define CCE_PACKET3( pkt, n ) (R128_CCE_PACKET3 | \ 394 (pkt) | ((n) << 16)) 395 396 397 static __inline__ void 398 r128_update_ring_snapshot( drm_r128_private_t *dev_priv ) 399 { 400 drm_r128_ring_buffer_t *ring = &dev_priv->ring; 401 ring->space = (GET_RING_HEAD( dev_priv ) - ring->tail) * sizeof(u32); 402 if ( ring->space <= 0 ) 403 ring->space += ring->size; 404 } 405 406 /* ================================================================ 407 * Misc helper macros 408 */ 409 410 #define RING_SPACE_TEST_WITH_RETURN( dev_priv ) \ 411 do { \ 412 drm_r128_ring_buffer_t *ring = &dev_priv->ring; int i; \ 413 if ( ring->space < ring->high_mark ) { \ 414 for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { \ 415 r128_update_ring_snapshot( dev_priv ); \ 416 if ( ring->space >= ring->high_mark ) \ 417 goto __ring_space_done; \ 418 DRM_UDELAY(1); \ 419 } \ 420 DRM_ERROR( "ring space check failed!\n" ); \ 421 return DRM_ERR(EBUSY); \ 422 } \ 423 __ring_space_done: \ 424 ; \ 425 } while (0) 426 427 #define VB_AGE_TEST_WITH_RETURN( dev_priv ) \ 428 do { \ 429 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; \ 430 if ( sarea_priv->last_dispatch >= R128_MAX_VB_AGE ) { \ 431 int __ret = r128_do_cce_idle( dev_priv ); \ 432 if ( __ret ) return __ret; \ 433 sarea_priv->last_dispatch = 0; \ 434 r128_freelist_reset( dev ); \ 435 } \ 436 } while (0) 437 438 #define R128_WAIT_UNTIL_PAGE_FLIPPED() do { \ 439 OUT_RING( CCE_PACKET0( R128_WAIT_UNTIL, 0 ) ); \ 440 OUT_RING( R128_EVENT_CRTC_OFFSET ); \ 441 } while (0) 442 443 444 /* ================================================================ 445 * Ring control 446 */ 447 448 #define R128_VERBOSE 0 449 450 #define RING_LOCALS \ 451 int write, _nr; unsigned int tail_mask; volatile u32 *ring; 452 453 #define BEGIN_RING( n ) do { \ 454 if ( R128_VERBOSE ) { \ 455 DRM_INFO( "BEGIN_RING( %d ) in %s\n", \ 456 (n), __FUNCTION__ ); \ 457 } \ 458 if ( dev_priv->ring.space <= (n) * sizeof(u32) ) { \ 459 COMMIT_RING(); \ 460 r128_wait_ring( dev_priv, (n) * sizeof(u32) ); \ 461 } \ 462 _nr = n; dev_priv->ring.space -= (n) * sizeof(u32); \ 463 ring = dev_priv->ring.start; \ 464 write = dev_priv->ring.tail; \ 465 tail_mask = dev_priv->ring.tail_mask; \ 466 } while (0) 467 468 /* You can set this to zero if you want. If the card locks up, you'll 469 * need to keep this set. It works around a bug in early revs of the 470 * Rage 128 chipset, where the CCE would read 32 dwords past the end of 471 * the ring buffer before wrapping around. 472 */ 473 #define R128_BROKEN_CCE 1 474 475 #define ADVANCE_RING() do { \ 476 if ( R128_VERBOSE ) { \ 477 DRM_INFO( "ADVANCE_RING() wr=0x%06x tail=0x%06x\n", \ 478 write, dev_priv->ring.tail ); \ 479 } \ 480 if ( R128_BROKEN_CCE && write < 32 ) { \ 481 memcpy( dev_priv->ring.end, \ 482 dev_priv->ring.start, \ 483 write * sizeof(u32) ); \ 484 } \ 485 if (((dev_priv->ring.tail + _nr) & tail_mask) != write) { \ 486 DRM_ERROR( \ 487 "ADVANCE_RING(): mismatch: nr: %x write: %x line: %d\n", \ 488 ((dev_priv->ring.tail + _nr) & tail_mask), \ 489 write, __LINE__); \ 490 } else \ 491 dev_priv->ring.tail = write; \ 492 } while (0) 493 494 #define COMMIT_RING() do { \ 495 if ( R128_VERBOSE ) { \ 496 DRM_INFO( "COMMIT_RING() tail=0x%06x\n", \ 497 dev_priv->ring.tail ); \ 498 } \ 499 DRM_MEMORYBARRIER(); \ 500 R128_WRITE( R128_PM4_BUFFER_DL_WPTR, dev_priv->ring.tail ); \ 501 R128_READ( R128_PM4_BUFFER_DL_WPTR ); \ 502 } while (0) 503 504 #define OUT_RING( x ) do { \ 505 if ( R128_VERBOSE ) { \ 506 DRM_INFO( " OUT_RING( 0x%08x ) at 0x%x\n", \ 507 (unsigned int)(x), write ); \ 508 } \ 509 ring[write++] = cpu_to_le32( x ); \ 510 write &= tail_mask; \ 511 } while (0) 512 513 #endif /* __R128_DRV_H__ */
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