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sys/dev/drm/radeon_cp.c
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1 /*- 2 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. 3 * Copyright 2000 VA Linux Systems, Inc., Fremont, California. 4 * Copyright 2007 Advanced Micro Devices, Inc. 5 * All Rights Reserved. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the "Software"), 9 * to deal in the Software without restriction, including without limitation 10 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 11 * and/or sell copies of the Software, and to permit persons to whom the 12 * Software is furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice (including the next 15 * paragraph) shall be included in all copies or substantial portions of the 16 * Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 24 * DEALINGS IN THE SOFTWARE. 25 * 26 * Authors: 27 * Kevin E. Martin <martin@valinux.com> 28 * Gareth Hughes <gareth@valinux.com> 29 */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD: releng/9.0/sys/dev/drm/radeon_cp.c 207067 2010-04-22 18:44:23Z rnoland $"); 33 34 #include "dev/drm/drmP.h" 35 #include "dev/drm/drm.h" 36 #include "dev/drm/drm_sarea.h" 37 #include "dev/drm/radeon_drm.h" 38 #include "dev/drm/radeon_drv.h" 39 #include "dev/drm/r300_reg.h" 40 41 #include "dev/drm/radeon_microcode.h" 42 43 #define RADEON_FIFO_DEBUG 0 44 45 static int radeon_do_cleanup_cp(struct drm_device * dev); 46 static void radeon_do_cp_start(drm_radeon_private_t * dev_priv); 47 48 u32 radeon_read_ring_rptr(drm_radeon_private_t *dev_priv, u32 off) 49 { 50 u32 val; 51 52 if (dev_priv->flags & RADEON_IS_AGP) { 53 val = DRM_READ32(dev_priv->ring_rptr, off); 54 } else { 55 val = *(((volatile u32 *) 56 dev_priv->ring_rptr->virtual) + 57 (off / sizeof(u32))); 58 val = le32_to_cpu(val); 59 } 60 return val; 61 } 62 63 u32 radeon_get_ring_head(drm_radeon_private_t *dev_priv) 64 { 65 if (dev_priv->writeback_works) 66 return radeon_read_ring_rptr(dev_priv, 0); 67 else { 68 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) 69 return RADEON_READ(R600_CP_RB_RPTR); 70 else 71 return RADEON_READ(RADEON_CP_RB_RPTR); 72 } 73 } 74 75 void radeon_write_ring_rptr(drm_radeon_private_t *dev_priv, u32 off, u32 val) 76 { 77 if (dev_priv->flags & RADEON_IS_AGP) 78 DRM_WRITE32(dev_priv->ring_rptr, off, val); 79 else 80 *(((volatile u32 *) dev_priv->ring_rptr->virtual) + 81 (off / sizeof(u32))) = cpu_to_le32(val); 82 } 83 84 void radeon_set_ring_head(drm_radeon_private_t *dev_priv, u32 val) 85 { 86 radeon_write_ring_rptr(dev_priv, 0, val); 87 } 88 89 u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index) 90 { 91 if (dev_priv->writeback_works) { 92 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) 93 return radeon_read_ring_rptr(dev_priv, 94 R600_SCRATCHOFF(index)); 95 else 96 return radeon_read_ring_rptr(dev_priv, 97 RADEON_SCRATCHOFF(index)); 98 } else { 99 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) 100 return RADEON_READ(R600_SCRATCH_REG0 + 4*index); 101 else 102 return RADEON_READ(RADEON_SCRATCH_REG0 + 4*index); 103 } 104 } 105 106 u32 RADEON_READ_MM(drm_radeon_private_t *dev_priv, int addr) 107 { 108 u32 ret; 109 110 if (addr < 0x10000) 111 ret = DRM_READ32(dev_priv->mmio, addr); 112 else { 113 DRM_WRITE32(dev_priv->mmio, RADEON_MM_INDEX, addr); 114 ret = DRM_READ32(dev_priv->mmio, RADEON_MM_DATA); 115 } 116 117 return ret; 118 } 119 120 static u32 R500_READ_MCIND(drm_radeon_private_t *dev_priv, int addr) 121 { 122 u32 ret; 123 RADEON_WRITE(R520_MC_IND_INDEX, 0x7f0000 | (addr & 0xff)); 124 ret = RADEON_READ(R520_MC_IND_DATA); 125 RADEON_WRITE(R520_MC_IND_INDEX, 0); 126 return ret; 127 } 128 129 static u32 RS480_READ_MCIND(drm_radeon_private_t *dev_priv, int addr) 130 { 131 u32 ret; 132 RADEON_WRITE(RS480_NB_MC_INDEX, addr & 0xff); 133 ret = RADEON_READ(RS480_NB_MC_DATA); 134 RADEON_WRITE(RS480_NB_MC_INDEX, 0xff); 135 return ret; 136 } 137 138 static u32 RS690_READ_MCIND(drm_radeon_private_t *dev_priv, int addr) 139 { 140 u32 ret; 141 RADEON_WRITE(RS690_MC_INDEX, (addr & RS690_MC_INDEX_MASK)); 142 ret = RADEON_READ(RS690_MC_DATA); 143 RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_MASK); 144 return ret; 145 } 146 147 static u32 RS600_READ_MCIND(drm_radeon_private_t *dev_priv, int addr) 148 { 149 u32 ret; 150 RADEON_WRITE(RS600_MC_INDEX, ((addr & RS600_MC_ADDR_MASK) | 151 RS600_MC_IND_CITF_ARB0)); 152 ret = RADEON_READ(RS600_MC_DATA); 153 return ret; 154 } 155 156 static u32 IGP_READ_MCIND(drm_radeon_private_t *dev_priv, int addr) 157 { 158 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || 159 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) 160 return RS690_READ_MCIND(dev_priv, addr); 161 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) 162 return RS600_READ_MCIND(dev_priv, addr); 163 else 164 return RS480_READ_MCIND(dev_priv, addr); 165 } 166 167 u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv) 168 { 169 170 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) 171 return RADEON_READ(R700_MC_VM_FB_LOCATION); 172 else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) 173 return RADEON_READ(R600_MC_VM_FB_LOCATION); 174 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) 175 return R500_READ_MCIND(dev_priv, RV515_MC_FB_LOCATION); 176 else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || 177 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) 178 return RS690_READ_MCIND(dev_priv, RS690_MC_FB_LOCATION); 179 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) 180 return RS600_READ_MCIND(dev_priv, RS600_MC_FB_LOCATION); 181 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) 182 return R500_READ_MCIND(dev_priv, R520_MC_FB_LOCATION); 183 else 184 return RADEON_READ(RADEON_MC_FB_LOCATION); 185 } 186 187 static void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc) 188 { 189 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) 190 RADEON_WRITE(R700_MC_VM_FB_LOCATION, fb_loc); 191 else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) 192 RADEON_WRITE(R600_MC_VM_FB_LOCATION, fb_loc); 193 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) 194 R500_WRITE_MCIND(RV515_MC_FB_LOCATION, fb_loc); 195 else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || 196 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) 197 RS690_WRITE_MCIND(RS690_MC_FB_LOCATION, fb_loc); 198 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) 199 RS600_WRITE_MCIND(RS600_MC_FB_LOCATION, fb_loc); 200 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) 201 R500_WRITE_MCIND(R520_MC_FB_LOCATION, fb_loc); 202 else 203 RADEON_WRITE(RADEON_MC_FB_LOCATION, fb_loc); 204 } 205 206 void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc) 207 { 208 /*R6xx/R7xx: AGP_TOP and BOT are actually 18 bits each */ 209 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) { 210 RADEON_WRITE(R700_MC_VM_AGP_BOT, agp_loc & 0xffff); /* FIX ME */ 211 RADEON_WRITE(R700_MC_VM_AGP_TOP, (agp_loc >> 16) & 0xffff); 212 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) { 213 RADEON_WRITE(R600_MC_VM_AGP_BOT, agp_loc & 0xffff); /* FIX ME */ 214 RADEON_WRITE(R600_MC_VM_AGP_TOP, (agp_loc >> 16) & 0xffff); 215 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) 216 R500_WRITE_MCIND(RV515_MC_AGP_LOCATION, agp_loc); 217 else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || 218 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) 219 RS690_WRITE_MCIND(RS690_MC_AGP_LOCATION, agp_loc); 220 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) 221 RS600_WRITE_MCIND(RS600_MC_AGP_LOCATION, agp_loc); 222 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) 223 R500_WRITE_MCIND(R520_MC_AGP_LOCATION, agp_loc); 224 else 225 RADEON_WRITE(RADEON_MC_AGP_LOCATION, agp_loc); 226 } 227 228 void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base) 229 { 230 u32 agp_base_hi = upper_32_bits(agp_base); 231 u32 agp_base_lo = agp_base & 0xffffffff; 232 u32 r6xx_agp_base = (agp_base >> 22) & 0x3ffff; 233 234 /* R6xx/R7xx must be aligned to a 4MB boundry */ 235 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) 236 RADEON_WRITE(R700_MC_VM_AGP_BASE, r6xx_agp_base); 237 else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) 238 RADEON_WRITE(R600_MC_VM_AGP_BASE, r6xx_agp_base); 239 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) { 240 R500_WRITE_MCIND(RV515_MC_AGP_BASE, agp_base_lo); 241 R500_WRITE_MCIND(RV515_MC_AGP_BASE_2, agp_base_hi); 242 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || 243 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) { 244 RS690_WRITE_MCIND(RS690_MC_AGP_BASE, agp_base_lo); 245 RS690_WRITE_MCIND(RS690_MC_AGP_BASE_2, agp_base_hi); 246 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) { 247 RS600_WRITE_MCIND(RS600_AGP_BASE, agp_base_lo); 248 RS600_WRITE_MCIND(RS600_AGP_BASE_2, agp_base_hi); 249 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) { 250 R500_WRITE_MCIND(R520_MC_AGP_BASE, agp_base_lo); 251 R500_WRITE_MCIND(R520_MC_AGP_BASE_2, agp_base_hi); 252 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) || 253 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) { 254 RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo); 255 RADEON_WRITE(RS480_AGP_BASE_2, agp_base_hi); 256 } else { 257 RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo); 258 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R200) 259 RADEON_WRITE(RADEON_AGP_BASE_2, agp_base_hi); 260 } 261 } 262 263 void radeon_enable_bm(struct drm_radeon_private *dev_priv) 264 { 265 u32 tmp; 266 /* Turn on bus mastering */ 267 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || 268 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) { 269 /* rs600/rs690/rs740 */ 270 tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS; 271 RADEON_WRITE(RADEON_BUS_CNTL, tmp); 272 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV350) || 273 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) || 274 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) || 275 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) { 276 /* r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */ 277 tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS; 278 RADEON_WRITE(RADEON_BUS_CNTL, tmp); 279 } /* PCIE cards appears to not need this */ 280 } 281 282 static int RADEON_READ_PLL(struct drm_device * dev, int addr) 283 { 284 drm_radeon_private_t *dev_priv = dev->dev_private; 285 286 RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x1f); 287 return RADEON_READ(RADEON_CLOCK_CNTL_DATA); 288 } 289 290 static u32 RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr) 291 { 292 RADEON_WRITE8(RADEON_PCIE_INDEX, addr & 0xff); 293 return RADEON_READ(RADEON_PCIE_DATA); 294 } 295 296 #if RADEON_FIFO_DEBUG 297 static void radeon_status(drm_radeon_private_t * dev_priv) 298 { 299 printk("%s:\n", __func__); 300 printk("RBBM_STATUS = 0x%08x\n", 301 (unsigned int)RADEON_READ(RADEON_RBBM_STATUS)); 302 printk("CP_RB_RTPR = 0x%08x\n", 303 (unsigned int)RADEON_READ(RADEON_CP_RB_RPTR)); 304 printk("CP_RB_WTPR = 0x%08x\n", 305 (unsigned int)RADEON_READ(RADEON_CP_RB_WPTR)); 306 printk("AIC_CNTL = 0x%08x\n", 307 (unsigned int)RADEON_READ(RADEON_AIC_CNTL)); 308 printk("AIC_STAT = 0x%08x\n", 309 (unsigned int)RADEON_READ(RADEON_AIC_STAT)); 310 printk("AIC_PT_BASE = 0x%08x\n", 311 (unsigned int)RADEON_READ(RADEON_AIC_PT_BASE)); 312 printk("TLB_ADDR = 0x%08x\n", 313 (unsigned int)RADEON_READ(RADEON_AIC_TLB_ADDR)); 314 printk("TLB_DATA = 0x%08x\n", 315 (unsigned int)RADEON_READ(RADEON_AIC_TLB_DATA)); 316 } 317 #endif 318 319 /* ================================================================ 320 * Engine, FIFO control 321 */ 322 323 static int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv) 324 { 325 u32 tmp; 326 int i; 327 328 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; 329 330 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { 331 tmp = RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT); 332 tmp |= RADEON_RB3D_DC_FLUSH_ALL; 333 RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT, tmp); 334 335 for (i = 0; i < dev_priv->usec_timeout; i++) { 336 if (!(RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT) 337 & RADEON_RB3D_DC_BUSY)) { 338 return 0; 339 } 340 DRM_UDELAY(1); 341 } 342 } else { 343 /* don't flush or purge cache here or lockup */ 344 return 0; 345 } 346 347 #if RADEON_FIFO_DEBUG 348 DRM_ERROR("failed!\n"); 349 radeon_status(dev_priv); 350 #endif 351 return -EBUSY; 352 } 353 354 static int radeon_do_wait_for_fifo(drm_radeon_private_t * dev_priv, int entries) 355 { 356 int i; 357 358 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; 359 360 for (i = 0; i < dev_priv->usec_timeout; i++) { 361 int slots = (RADEON_READ(RADEON_RBBM_STATUS) 362 & RADEON_RBBM_FIFOCNT_MASK); 363 if (slots >= entries) 364 return 0; 365 DRM_UDELAY(1); 366 } 367 DRM_DEBUG("wait for fifo failed status : 0x%08X 0x%08X\n", 368 RADEON_READ(RADEON_RBBM_STATUS), 369 RADEON_READ(R300_VAP_CNTL_STATUS)); 370 371 #if RADEON_FIFO_DEBUG 372 DRM_ERROR("failed!\n"); 373 radeon_status(dev_priv); 374 #endif 375 return -EBUSY; 376 } 377 378 static int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv) 379 { 380 int i, ret; 381 382 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; 383 384 ret = radeon_do_wait_for_fifo(dev_priv, 64); 385 if (ret) 386 return ret; 387 388 for (i = 0; i < dev_priv->usec_timeout; i++) { 389 if (!(RADEON_READ(RADEON_RBBM_STATUS) 390 & RADEON_RBBM_ACTIVE)) { 391 radeon_do_pixcache_flush(dev_priv); 392 return 0; 393 } 394 DRM_UDELAY(1); 395 } 396 DRM_DEBUG("wait idle failed status : 0x%08X 0x%08X\n", 397 RADEON_READ(RADEON_RBBM_STATUS), 398 RADEON_READ(R300_VAP_CNTL_STATUS)); 399 400 #if RADEON_FIFO_DEBUG 401 DRM_ERROR("failed!\n"); 402 radeon_status(dev_priv); 403 #endif 404 return -EBUSY; 405 } 406 407 static void radeon_init_pipes(drm_radeon_private_t *dev_priv) 408 { 409 uint32_t gb_tile_config, gb_pipe_sel = 0; 410 411 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV530) { 412 uint32_t z_pipe_sel = RADEON_READ(RV530_GB_PIPE_SELECT2); 413 if ((z_pipe_sel & 3) == 3) 414 dev_priv->num_z_pipes = 2; 415 else 416 dev_priv->num_z_pipes = 1; 417 } else 418 dev_priv->num_z_pipes = 1; 419 420 /* RS4xx/RS6xx/R4xx/R5xx */ 421 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R420) { 422 gb_pipe_sel = RADEON_READ(R400_GB_PIPE_SELECT); 423 dev_priv->num_gb_pipes = ((gb_pipe_sel >> 12) & 0x3) + 1; 424 } else { 425 /* R3xx */ 426 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) || 427 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350)) { 428 dev_priv->num_gb_pipes = 2; 429 } else { 430 /* R3Vxx */ 431 dev_priv->num_gb_pipes = 1; 432 } 433 } 434 DRM_INFO("Num pipes: %d\n", dev_priv->num_gb_pipes); 435 436 gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16 /*| R300_SUBPIXEL_1_16*/); 437 438 switch (dev_priv->num_gb_pipes) { 439 case 2: gb_tile_config |= R300_PIPE_COUNT_R300; break; 440 case 3: gb_tile_config |= R300_PIPE_COUNT_R420_3P; break; 441 case 4: gb_tile_config |= R300_PIPE_COUNT_R420; break; 442 default: 443 case 1: gb_tile_config |= R300_PIPE_COUNT_RV350; break; 444 } 445 446 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV515) { 447 RADEON_WRITE_PLL(R500_DYN_SCLK_PWMEM_PIPE, (1 | ((gb_pipe_sel >> 8) & 0xf) << 4)); 448 RADEON_WRITE(R300_SU_REG_DEST, ((1 << dev_priv->num_gb_pipes) - 1)); 449 } 450 RADEON_WRITE(R300_GB_TILE_CONFIG, gb_tile_config); 451 radeon_do_wait_for_idle(dev_priv); 452 RADEON_WRITE(R300_DST_PIPE_CONFIG, RADEON_READ(R300_DST_PIPE_CONFIG) | R300_PIPE_AUTO_CONFIG); 453 RADEON_WRITE(R300_RB2D_DSTCACHE_MODE, (RADEON_READ(R300_RB2D_DSTCACHE_MODE) | 454 R300_DC_AUTOFLUSH_ENABLE | 455 R300_DC_DC_DISABLE_IGNORE_PE)); 456 457 458 } 459 460 /* ================================================================ 461 * CP control, initialization 462 */ 463 464 /* Load the microcode for the CP */ 465 static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv) 466 { 467 const u32 (*cp)[2]; 468 int i; 469 470 DRM_DEBUG("\n"); 471 472 switch (dev_priv->flags & RADEON_FAMILY_MASK) { 473 case CHIP_R100: 474 case CHIP_RV100: 475 case CHIP_RV200: 476 case CHIP_RS100: 477 case CHIP_RS200: 478 DRM_INFO("Loading R100 Microcode\n"); 479 cp = R100_cp_microcode; 480 break; 481 case CHIP_R200: 482 case CHIP_RV250: 483 case CHIP_RV280: 484 case CHIP_RS300: 485 DRM_INFO("Loading R200 Microcode\n"); 486 cp = R200_cp_microcode; 487 break; 488 case CHIP_R300: 489 case CHIP_R350: 490 case CHIP_RV350: 491 case CHIP_RV380: 492 case CHIP_RS400: 493 case CHIP_RS480: 494 DRM_INFO("Loading R300 Microcode\n"); 495 cp = R300_cp_microcode; 496 break; 497 case CHIP_R420: 498 case CHIP_R423: 499 case CHIP_RV410: 500 DRM_INFO("Loading R400 Microcode\n"); 501 cp = R420_cp_microcode; 502 break; 503 case CHIP_RS690: 504 case CHIP_RS740: 505 DRM_INFO("Loading RS690/RS740 Microcode\n"); 506 cp = RS690_cp_microcode; 507 break; 508 case CHIP_RS600: 509 DRM_INFO("Loading RS600 Microcode\n"); 510 cp = RS600_cp_microcode; 511 break; 512 case CHIP_RV515: 513 case CHIP_R520: 514 case CHIP_RV530: 515 case CHIP_R580: 516 case CHIP_RV560: 517 case CHIP_RV570: 518 DRM_INFO("Loading R500 Microcode\n"); 519 cp = R520_cp_microcode; 520 break; 521 default: 522 return; 523 } 524 525 radeon_do_wait_for_idle(dev_priv); 526 527 RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0); 528 529 for (i = 0; i != 256; i++) { 530 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, cp[i][1]); 531 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, cp[i][0]); 532 } 533 } 534 535 /* Flush any pending commands to the CP. This should only be used just 536 * prior to a wait for idle, as it informs the engine that the command 537 * stream is ending. 538 */ 539 static void radeon_do_cp_flush(drm_radeon_private_t * dev_priv) 540 { 541 DRM_DEBUG("\n"); 542 #if 0 543 u32 tmp; 544 545 tmp = RADEON_READ(RADEON_CP_RB_WPTR) | (1 << 31); 546 RADEON_WRITE(RADEON_CP_RB_WPTR, tmp); 547 #endif 548 } 549 550 /* Wait for the CP to go idle. 551 */ 552 int radeon_do_cp_idle(drm_radeon_private_t * dev_priv) 553 { 554 RING_LOCALS; 555 DRM_DEBUG("\n"); 556 557 BEGIN_RING(6); 558 559 RADEON_PURGE_CACHE(); 560 RADEON_PURGE_ZCACHE(); 561 RADEON_WAIT_UNTIL_IDLE(); 562 563 ADVANCE_RING(); 564 COMMIT_RING(); 565 566 return radeon_do_wait_for_idle(dev_priv); 567 } 568 569 /* Start the Command Processor. 570 */ 571 static void radeon_do_cp_start(drm_radeon_private_t * dev_priv) 572 { 573 RING_LOCALS; 574 DRM_DEBUG("\n"); 575 576 radeon_do_wait_for_idle(dev_priv); 577 578 RADEON_WRITE(RADEON_CP_CSQ_CNTL, dev_priv->cp_mode); 579 580 dev_priv->cp_running = 1; 581 582 BEGIN_RING(8); 583 /* isync can only be written through cp on r5xx write it here */ 584 OUT_RING(CP_PACKET0(RADEON_ISYNC_CNTL, 0)); 585 OUT_RING(RADEON_ISYNC_ANY2D_IDLE3D | 586 RADEON_ISYNC_ANY3D_IDLE2D | 587 RADEON_ISYNC_WAIT_IDLEGUI | 588 RADEON_ISYNC_CPSCRATCH_IDLEGUI); 589 RADEON_PURGE_CACHE(); 590 RADEON_PURGE_ZCACHE(); 591 RADEON_WAIT_UNTIL_IDLE(); 592 ADVANCE_RING(); 593 COMMIT_RING(); 594 595 dev_priv->track_flush |= RADEON_FLUSH_EMITED | RADEON_PURGE_EMITED; 596 } 597 598 /* Reset the Command Processor. This will not flush any pending 599 * commands, so you must wait for the CP command stream to complete 600 * before calling this routine. 601 */ 602 static void radeon_do_cp_reset(drm_radeon_private_t * dev_priv) 603 { 604 u32 cur_read_ptr; 605 DRM_DEBUG("\n"); 606 607 cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR); 608 RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr); 609 SET_RING_HEAD(dev_priv, cur_read_ptr); 610 dev_priv->ring.tail = cur_read_ptr; 611 } 612 613 /* Stop the Command Processor. This will not flush any pending 614 * commands, so you must flush the command stream and wait for the CP 615 * to go idle before calling this routine. 616 */ 617 static void radeon_do_cp_stop(drm_radeon_private_t * dev_priv) 618 { 619 DRM_DEBUG("\n"); 620 621 RADEON_WRITE(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS); 622 623 dev_priv->cp_running = 0; 624 } 625 626 /* Reset the engine. This will stop the CP if it is running. 627 */ 628 static int radeon_do_engine_reset(struct drm_device * dev) 629 { 630 drm_radeon_private_t *dev_priv = dev->dev_private; 631 u32 clock_cntl_index = 0, mclk_cntl = 0, rbbm_soft_reset; 632 DRM_DEBUG("\n"); 633 634 radeon_do_pixcache_flush(dev_priv); 635 636 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) { 637 /* may need something similar for newer chips */ 638 clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX); 639 mclk_cntl = RADEON_READ_PLL(dev, RADEON_MCLK_CNTL); 640 641 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, (mclk_cntl | 642 RADEON_FORCEON_MCLKA | 643 RADEON_FORCEON_MCLKB | 644 RADEON_FORCEON_YCLKA | 645 RADEON_FORCEON_YCLKB | 646 RADEON_FORCEON_MC | 647 RADEON_FORCEON_AIC)); 648 } 649 650 rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET); 651 652 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset | 653 RADEON_SOFT_RESET_CP | 654 RADEON_SOFT_RESET_HI | 655 RADEON_SOFT_RESET_SE | 656 RADEON_SOFT_RESET_RE | 657 RADEON_SOFT_RESET_PP | 658 RADEON_SOFT_RESET_E2 | 659 RADEON_SOFT_RESET_RB)); 660 RADEON_READ(RADEON_RBBM_SOFT_RESET); 661 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset & 662 ~(RADEON_SOFT_RESET_CP | 663 RADEON_SOFT_RESET_HI | 664 RADEON_SOFT_RESET_SE | 665 RADEON_SOFT_RESET_RE | 666 RADEON_SOFT_RESET_PP | 667 RADEON_SOFT_RESET_E2 | 668 RADEON_SOFT_RESET_RB))); 669 RADEON_READ(RADEON_RBBM_SOFT_RESET); 670 671 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) { 672 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, mclk_cntl); 673 RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index); 674 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset); 675 } 676 677 /* setup the raster pipes */ 678 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R300) 679 radeon_init_pipes(dev_priv); 680 681 /* Reset the CP ring */ 682 radeon_do_cp_reset(dev_priv); 683 684 /* The CP is no longer running after an engine reset */ 685 dev_priv->cp_running = 0; 686 687 /* Reset any pending vertex, indirect buffers */ 688 radeon_freelist_reset(dev); 689 690 return 0; 691 } 692 693 static void radeon_cp_init_ring_buffer(struct drm_device * dev, 694 drm_radeon_private_t *dev_priv, 695 struct drm_file *file_priv) 696 { 697 u32 ring_start, cur_read_ptr; 698 699 /* Initialize the memory controller. With new memory map, the fb location 700 * is not changed, it should have been properly initialized already. Part 701 * of the problem is that the code below is bogus, assuming the GART is 702 * always appended to the fb which is not necessarily the case 703 */ 704 if (!dev_priv->new_memmap) 705 radeon_write_fb_location(dev_priv, 706 ((dev_priv->gart_vm_start - 1) & 0xffff0000) 707 | (dev_priv->fb_location >> 16)); 708 709 #if __OS_HAS_AGP 710 if (dev_priv->flags & RADEON_IS_AGP) { 711 radeon_write_agp_base(dev_priv, dev->agp->base); 712 713 radeon_write_agp_location(dev_priv, 714 (((dev_priv->gart_vm_start - 1 + 715 dev_priv->gart_size) & 0xffff0000) | 716 (dev_priv->gart_vm_start >> 16))); 717 718 ring_start = (dev_priv->cp_ring->offset 719 - dev->agp->base 720 + dev_priv->gart_vm_start); 721 } else 722 #endif 723 ring_start = (dev_priv->cp_ring->offset - dev->sg->vaddr + 724 dev_priv->gart_vm_start); 725 726 RADEON_WRITE(RADEON_CP_RB_BASE, ring_start); 727 728 /* Set the write pointer delay */ 729 RADEON_WRITE(RADEON_CP_RB_WPTR_DELAY, 0); 730 731 /* Initialize the ring buffer's read and write pointers */ 732 cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR); 733 RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr); 734 SET_RING_HEAD(dev_priv, cur_read_ptr); 735 dev_priv->ring.tail = cur_read_ptr; 736 737 #if __OS_HAS_AGP 738 if (dev_priv->flags & RADEON_IS_AGP) { 739 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR, 740 dev_priv->ring_rptr->offset 741 - dev->agp->base + dev_priv->gart_vm_start); 742 } else 743 #endif 744 { 745 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR, 746 dev_priv->ring_rptr->offset - dev->sg->vaddr + 747 dev_priv->gart_vm_start); 748 } 749 750 /* Set ring buffer size */ 751 #ifdef __BIG_ENDIAN 752 RADEON_WRITE(RADEON_CP_RB_CNTL, 753 RADEON_BUF_SWAP_32BIT | 754 (dev_priv->ring.fetch_size_l2ow << 18) | 755 (dev_priv->ring.rptr_update_l2qw << 8) | 756 dev_priv->ring.size_l2qw); 757 #else 758 RADEON_WRITE(RADEON_CP_RB_CNTL, 759 (dev_priv->ring.fetch_size_l2ow << 18) | 760 (dev_priv->ring.rptr_update_l2qw << 8) | 761 dev_priv->ring.size_l2qw); 762 #endif 763 764 765 /* Initialize the scratch register pointer. This will cause 766 * the scratch register values to be written out to memory 767 * whenever they are updated. 768 * 769 * We simply put this behind the ring read pointer, this works 770 * with PCI GART as well as (whatever kind of) AGP GART 771 */ 772 RADEON_WRITE(RADEON_SCRATCH_ADDR, RADEON_READ(RADEON_CP_RB_RPTR_ADDR) 773 + RADEON_SCRATCH_REG_OFFSET); 774 775 RADEON_WRITE(RADEON_SCRATCH_UMSK, 0x7); 776 777 radeon_enable_bm(dev_priv); 778 779 radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(0), 0); 780 RADEON_WRITE(RADEON_LAST_FRAME_REG, 0); 781 782 radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1), 0); 783 RADEON_WRITE(RADEON_LAST_DISPATCH_REG, 0); 784 785 radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(2), 0); 786 RADEON_WRITE(RADEON_LAST_CLEAR_REG, 0); 787 788 /* reset sarea copies of these */ 789 if (dev_priv->sarea_priv) { 790 dev_priv->sarea_priv->last_frame = 0; 791 dev_priv->sarea_priv->last_dispatch = 0; 792 dev_priv->sarea_priv->last_clear = 0; 793 } 794 795 radeon_do_wait_for_idle(dev_priv); 796 797 /* Sync everything up */ 798 RADEON_WRITE(RADEON_ISYNC_CNTL, 799 (RADEON_ISYNC_ANY2D_IDLE3D | 800 RADEON_ISYNC_ANY3D_IDLE2D | 801 RADEON_ISYNC_WAIT_IDLEGUI | 802 RADEON_ISYNC_CPSCRATCH_IDLEGUI)); 803 804 } 805 806 static void radeon_test_writeback(drm_radeon_private_t * dev_priv) 807 { 808 u32 tmp; 809 810 /* Start with assuming that writeback doesn't work */ 811 dev_priv->writeback_works = 0; 812 813 /* Writeback doesn't seem to work everywhere, test it here and possibly 814 * enable it if it appears to work 815 */ 816 radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1), 0); 817 818 RADEON_WRITE(RADEON_SCRATCH_REG1, 0xdeadbeef); 819 820 for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) { 821 u32 val; 822 823 val = radeon_read_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1)); 824 if (val == 0xdeadbeef) 825 break; 826 DRM_UDELAY(1); 827 } 828 829 if (tmp < dev_priv->usec_timeout) { 830 dev_priv->writeback_works = 1; 831 DRM_INFO("writeback test succeeded in %d usecs\n", tmp); 832 } else { 833 dev_priv->writeback_works = 0; 834 DRM_INFO("writeback test failed\n"); 835 } 836 if (radeon_no_wb == 1) { 837 dev_priv->writeback_works = 0; 838 DRM_INFO("writeback forced off\n"); 839 } 840 841 if (!dev_priv->writeback_works) { 842 /* Disable writeback to avoid unnecessary bus master transfer */ 843 RADEON_WRITE(RADEON_CP_RB_CNTL, RADEON_READ(RADEON_CP_RB_CNTL) | 844 RADEON_RB_NO_UPDATE); 845 RADEON_WRITE(RADEON_SCRATCH_UMSK, 0); 846 } 847 } 848 849 /* Enable or disable IGP GART on the chip */ 850 static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on) 851 { 852 u32 temp; 853 854 if (on) { 855 DRM_DEBUG("programming igp gart %08X %08lX %08X\n", 856 dev_priv->gart_vm_start, 857 (long)dev_priv->gart_info.bus_addr, 858 dev_priv->gart_size); 859 860 temp = IGP_READ_MCIND(dev_priv, RS480_MC_MISC_CNTL); 861 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || 862 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) 863 IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, (RS480_GART_INDEX_REG_EN | 864 RS690_BLOCK_GFX_D3_EN)); 865 else 866 IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, RS480_GART_INDEX_REG_EN); 867 868 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN | 869 RS480_VA_SIZE_32MB)); 870 871 temp = IGP_READ_MCIND(dev_priv, RS480_GART_FEATURE_ID); 872 IGP_WRITE_MCIND(RS480_GART_FEATURE_ID, (RS480_HANG_EN | 873 RS480_TLB_ENABLE | 874 RS480_GTW_LAC_EN | 875 RS480_1LEVEL_GART)); 876 877 temp = dev_priv->gart_info.bus_addr & 0xfffff000; 878 temp |= (upper_32_bits(dev_priv->gart_info.bus_addr) & 0xff) << 4; 879 IGP_WRITE_MCIND(RS480_GART_BASE, temp); 880 881 temp = IGP_READ_MCIND(dev_priv, RS480_AGP_MODE_CNTL); 882 IGP_WRITE_MCIND(RS480_AGP_MODE_CNTL, ((1 << RS480_REQ_TYPE_SNOOP_SHIFT) | 883 RS480_REQ_TYPE_SNOOP_DIS)); 884 885 radeon_write_agp_base(dev_priv, dev_priv->gart_vm_start); 886 887 dev_priv->gart_size = 32*1024*1024; 888 temp = (((dev_priv->gart_vm_start - 1 + dev_priv->gart_size) & 889 0xffff0000) | (dev_priv->gart_vm_start >> 16)); 890 891 radeon_write_agp_location(dev_priv, temp); 892 893 temp = IGP_READ_MCIND(dev_priv, RS480_AGP_ADDRESS_SPACE_SIZE); 894 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN | 895 RS480_VA_SIZE_32MB)); 896 897 do { 898 temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL); 899 if ((temp & RS480_GART_CACHE_INVALIDATE) == 0) 900 break; 901 DRM_UDELAY(1); 902 } while (1); 903 904 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL, 905 RS480_GART_CACHE_INVALIDATE); 906 907 do { 908 temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL); 909 if ((temp & RS480_GART_CACHE_INVALIDATE) == 0) 910 break; 911 DRM_UDELAY(1); 912 } while (1); 913 914 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL, 0); 915 } else { 916 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, 0); 917 } 918 } 919 920 /* Enable or disable IGP GART on the chip */ 921 static void rs600_set_igpgart(drm_radeon_private_t *dev_priv, int on) 922 { 923 u32 temp; 924 int i; 925 926 if (on) { 927 DRM_DEBUG("programming igp gart %08X %08lX %08X\n", 928 dev_priv->gart_vm_start, 929 (long)dev_priv->gart_info.bus_addr, 930 dev_priv->gart_size); 931 932 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, (RS600_EFFECTIVE_L2_CACHE_SIZE(6) | 933 RS600_EFFECTIVE_L2_QUEUE_SIZE(6))); 934 935 for (i = 0; i < 19; i++) 936 IGP_WRITE_MCIND(RS600_MC_PT0_CLIENT0_CNTL + i, 937 (RS600_ENABLE_TRANSLATION_MODE_OVERRIDE | 938 RS600_SYSTEM_ACCESS_MODE_IN_SYS | 939 RS600_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASSTHROUGH | 940 RS600_EFFECTIVE_L1_CACHE_SIZE(3) | 941 RS600_ENABLE_FRAGMENT_PROCESSING | 942 RS600_EFFECTIVE_L1_QUEUE_SIZE(3))); 943 944 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_CNTL, (RS600_ENABLE_PAGE_TABLE | 945 RS600_PAGE_TABLE_TYPE_FLAT)); 946 947 /* disable all other contexts */ 948 for (i = 1; i < 8; i++) 949 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_CNTL + i, 0); 950 951 /* setup the page table aperture */ 952 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_FLAT_BASE_ADDR, 953 dev_priv->gart_info.bus_addr); 954 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_FLAT_START_ADDR, 955 dev_priv->gart_vm_start); 956 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_FLAT_END_ADDR, 957 (dev_priv->gart_vm_start + dev_priv->gart_size - 1)); 958 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0); 959 960 /* setup the system aperture */ 961 IGP_WRITE_MCIND(RS600_MC_PT0_SYSTEM_APERTURE_LOW_ADDR, 962 dev_priv->gart_vm_start); 963 IGP_WRITE_MCIND(RS600_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR, 964 (dev_priv->gart_vm_start + dev_priv->gart_size - 1)); 965 966 /* enable page tables */ 967 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL); 968 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, (temp | RS600_ENABLE_PT)); 969 970 temp = IGP_READ_MCIND(dev_priv, RS600_MC_CNTL1); 971 IGP_WRITE_MCIND(RS600_MC_CNTL1, (temp | RS600_ENABLE_PAGE_TABLES)); 972 973 /* invalidate the cache */ 974 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL); 975 976 temp &= ~(RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE); 977 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, temp); 978 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL); 979 980 temp |= RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE; 981 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, temp); 982 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL); 983 984 temp &= ~(RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE); 985 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, temp); 986 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL); 987 988 } else { 989 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, 0); 990 temp = IGP_READ_MCIND(dev_priv, RS600_MC_CNTL1); 991 temp &= ~RS600_ENABLE_PAGE_TABLES; 992 IGP_WRITE_MCIND(RS600_MC_CNTL1, temp); 993 } 994 } 995 996 static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on) 997 { 998 u32 tmp = RADEON_READ_PCIE(dev_priv, RADEON_PCIE_TX_GART_CNTL); 999 if (on) { 1000 1001 DRM_DEBUG("programming pcie %08X %08lX %08X\n", 1002 dev_priv->gart_vm_start, 1003 (long)dev_priv->gart_info.bus_addr, 1004 dev_priv->gart_size); 1005 RADEON_WRITE_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, 1006 dev_priv->gart_vm_start); 1007 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_BASE, 1008 dev_priv->gart_info.bus_addr); 1009 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_START_LO, 1010 dev_priv->gart_vm_start); 1011 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_END_LO, 1012 dev_priv->gart_vm_start + 1013 dev_priv->gart_size - 1); 1014 1015 radeon_write_agp_location(dev_priv, 0xffffffc0); /* ?? */ 1016 1017 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL, 1018 RADEON_PCIE_TX_GART_EN); 1019 } else { 1020 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL, 1021 tmp & ~RADEON_PCIE_TX_GART_EN); 1022 } 1023 } 1024 1025 /* Enable or disable PCI GART on the chip */ 1026 static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on) 1027 { 1028 u32 tmp; 1029 1030 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || 1031 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740) || 1032 (dev_priv->flags & RADEON_IS_IGPGART)) { 1033 radeon_set_igpgart(dev_priv, on); 1034 return; 1035 } 1036 1037 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) { 1038 rs600_set_igpgart(dev_priv, on); 1039 return; 1040 } 1041 1042 if (dev_priv->flags & RADEON_IS_PCIE) { 1043 radeon_set_pciegart(dev_priv, on); 1044 return; 1045 } 1046 1047 tmp = RADEON_READ(RADEON_AIC_CNTL); 1048 1049 if (on) { 1050 RADEON_WRITE(RADEON_AIC_CNTL, 1051 tmp | RADEON_PCIGART_TRANSLATE_EN); 1052 1053 /* set PCI GART page-table base address 1054 */ 1055 RADEON_WRITE(RADEON_AIC_PT_BASE, dev_priv->gart_info.bus_addr); 1056 1057 /* set address range for PCI address translate 1058 */ 1059 RADEON_WRITE(RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start); 1060 RADEON_WRITE(RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start 1061 + dev_priv->gart_size - 1); 1062 1063 /* Turn off AGP aperture -- is this required for PCI GART? 1064 */ 1065 radeon_write_agp_location(dev_priv, 0xffffffc0); 1066 RADEON_WRITE(RADEON_AGP_COMMAND, 0); /* clear AGP_COMMAND */ 1067 } else { 1068 RADEON_WRITE(RADEON_AIC_CNTL, 1069 tmp & ~RADEON_PCIGART_TRANSLATE_EN); 1070 } 1071 } 1072 1073 static int radeon_setup_pcigart_surface(drm_radeon_private_t *dev_priv) 1074 { 1075 struct drm_ati_pcigart_info *gart_info = &dev_priv->gart_info; 1076 struct radeon_virt_surface *vp; 1077 int i; 1078 1079 for (i = 0; i < RADEON_MAX_SURFACES * 2; i++) { 1080 if (!dev_priv->virt_surfaces[i].file_priv || 1081 dev_priv->virt_surfaces[i].file_priv == PCIGART_FILE_PRIV) 1082 break; 1083 } 1084 if (i >= 2 * RADEON_MAX_SURFACES) 1085 return -ENOMEM; 1086 vp = &dev_priv->virt_surfaces[i]; 1087 1088 for (i = 0; i < RADEON_MAX_SURFACES; i++) { 1089 struct radeon_surface *sp = &dev_priv->surfaces[i]; 1090 if (sp->refcount) 1091 continue; 1092 1093 vp->surface_index = i; 1094 vp->lower = gart_info->bus_addr; 1095 vp->upper = vp->lower + gart_info->table_size; 1096 vp->flags = 0; 1097 vp->file_priv = PCIGART_FILE_PRIV; 1098 1099 sp->refcount = 1; 1100 sp->lower = vp->lower; 1101 sp->upper = vp->upper; 1102 sp->flags = 0; 1103 1104 RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, sp->flags); 1105 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND + 16 * i, sp->lower); 1106 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND + 16 * i, sp->upper); 1107 return 0; 1108 } 1109 1110 return -ENOMEM; 1111 } 1112 1113 static int radeon_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init, 1114 struct drm_file *file_priv) 1115 { 1116 drm_radeon_private_t *dev_priv = dev->dev_private; 1117 1118 DRM_DEBUG("\n"); 1119 1120 /* if we require new memory map but we don't have it fail */ 1121 if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) { 1122 DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n"); 1123 radeon_do_cleanup_cp(dev); 1124 return -EINVAL; 1125 } 1126 1127 if (init->is_pci && (dev_priv->flags & RADEON_IS_AGP)) { 1128 DRM_DEBUG("Forcing AGP card to PCI mode\n"); 1129 dev_priv->flags &= ~RADEON_IS_AGP; 1130 } else if (!(dev_priv->flags & (RADEON_IS_AGP | RADEON_IS_PCI | RADEON_IS_PCIE)) 1131 && !init->is_pci) { 1132 DRM_DEBUG("Restoring AGP flag\n"); 1133 dev_priv->flags |= RADEON_IS_AGP; 1134 } 1135 1136 if ((!(dev_priv->flags & RADEON_IS_AGP)) && !dev->sg) { 1137 DRM_ERROR("PCI GART memory not allocated!\n"); 1138 radeon_do_cleanup_cp(dev); 1139 return -EINVAL; 1140 } 1141 1142 dev_priv->usec_timeout = init->usec_timeout; 1143 if (dev_priv->usec_timeout < 1 || 1144 dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) { 1145 DRM_DEBUG("TIMEOUT problem!\n"); 1146 radeon_do_cleanup_cp(dev); 1147 return -EINVAL; 1148 } 1149 1150 /* Enable vblank on CRTC1 for older X servers 1151 */ 1152 dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1; 1153 1154 switch(init->func) { 1155 case RADEON_INIT_R200_CP: 1156 dev_priv->microcode_version = UCODE_R200; 1157 break; 1158 case RADEON_INIT_R300_CP: 1159 dev_priv->microcode_version = UCODE_R300; 1160 break; 1161 default: 1162 dev_priv->microcode_version = UCODE_R100; 1163 } 1164 1165 dev_priv->do_boxes = 0; 1166 dev_priv->cp_mode = init->cp_mode; 1167 1168 /* We don't support anything other than bus-mastering ring mode, 1169 * but the ring can be in either AGP or PCI space for the ring 1170 * read pointer. 1171 */ 1172 if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) && 1173 (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) { 1174 DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode); 1175 radeon_do_cleanup_cp(dev); 1176 return -EINVAL; 1177 } 1178 1179 switch (init->fb_bpp) { 1180 case 16: 1181 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565; 1182 break; 1183 case 32: 1184 default: 1185 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888; 1186 break; 1187 } 1188 dev_priv->front_offset = init->front_offset; 1189 dev_priv->front_pitch = init->front_pitch; 1190 dev_priv->back_offset = init->back_offset; 1191 dev_priv->back_pitch = init->back_pitch; 1192 1193 switch (init->depth_bpp) { 1194 case 16: 1195 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z; 1196 break; 1197 case 32: 1198 default: 1199 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z; 1200 break; 1201 } 1202 dev_priv->depth_offset = init->depth_offset; 1203 dev_priv->depth_pitch = init->depth_pitch; 1204 1205 /* Hardware state for depth clears. Remove this if/when we no 1206 * longer clear the depth buffer with a 3D rectangle. Hard-code 1207 * all values to prevent unwanted 3D state from slipping through 1208 * and screwing with the clear operation. 1209 */ 1210 dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE | 1211 (dev_priv->color_fmt << 10) | 1212 (dev_priv->microcode_version == 1213 UCODE_R100 ? RADEON_ZBLOCK16 : 0)); 1214 1215 dev_priv->depth_clear.rb3d_zstencilcntl = 1216 (dev_priv->depth_fmt | 1217 RADEON_Z_TEST_ALWAYS | 1218 RADEON_STENCIL_TEST_ALWAYS | 1219 RADEON_STENCIL_S_FAIL_REPLACE | 1220 RADEON_STENCIL_ZPASS_REPLACE | 1221 RADEON_STENCIL_ZFAIL_REPLACE | RADEON_Z_WRITE_ENABLE); 1222 1223 dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW | 1224 RADEON_BFACE_SOLID | 1225 RADEON_FFACE_SOLID | 1226 RADEON_FLAT_SHADE_VTX_LAST | 1227 RADEON_DIFFUSE_SHADE_FLAT | 1228 RADEON_ALPHA_SHADE_FLAT | 1229 RADEON_SPECULAR_SHADE_FLAT | 1230 RADEON_FOG_SHADE_FLAT | 1231 RADEON_VTX_PIX_CENTER_OGL | 1232 RADEON_ROUND_MODE_TRUNC | 1233 RADEON_ROUND_PREC_8TH_PIX); 1234 1235 1236 dev_priv->ring_offset = init->ring_offset; 1237 dev_priv->ring_rptr_offset = init->ring_rptr_offset; 1238 dev_priv->buffers_offset = init->buffers_offset; 1239 dev_priv->gart_textures_offset = init->gart_textures_offset; 1240 1241 dev_priv->sarea = drm_getsarea(dev); 1242 if (!dev_priv->sarea) { 1243 DRM_ERROR("could not find sarea!\n"); 1244 radeon_do_cleanup_cp(dev); 1245 return -EINVAL; 1246 } 1247 1248 dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset); 1249 if (!dev_priv->cp_ring) { 1250 DRM_ERROR("could not find cp ring region!\n"); 1251 radeon_do_cleanup_cp(dev); 1252 return -EINVAL; 1253 } 1254 dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset); 1255 if (!dev_priv->ring_rptr) { 1256 DRM_ERROR("could not find ring read pointer!\n"); 1257 radeon_do_cleanup_cp(dev); 1258 return -EINVAL; 1259 } 1260 dev->agp_buffer_token = init->buffers_offset; 1261 dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset); 1262 if (!dev->agp_buffer_map) { 1263 DRM_ERROR("could not find dma buffer region!\n"); 1264 radeon_do_cleanup_cp(dev); 1265 return -EINVAL; 1266 } 1267 1268 if (init->gart_textures_offset) { 1269 dev_priv->gart_textures = 1270 drm_core_findmap(dev, init->gart_textures_offset); 1271 if (!dev_priv->gart_textures) { 1272 DRM_ERROR("could not find GART texture region!\n"); 1273 radeon_do_cleanup_cp(dev); 1274 return -EINVAL; 1275 } 1276 } 1277 1278 dev_priv->sarea_priv = 1279 (drm_radeon_sarea_t *) ((u8 *) dev_priv->sarea->virtual + 1280 init->sarea_priv_offset); 1281 1282 #if __OS_HAS_AGP 1283 if (dev_priv->flags & RADEON_IS_AGP) { 1284 drm_core_ioremap_wc(dev_priv->cp_ring, dev); 1285 drm_core_ioremap_wc(dev_priv->ring_rptr, dev); 1286 drm_core_ioremap_wc(dev->agp_buffer_map, dev); 1287 if (!dev_priv->cp_ring->virtual || 1288 !dev_priv->ring_rptr->virtual || 1289 !dev->agp_buffer_map->virtual) { 1290 DRM_ERROR("could not find ioremap agp regions!\n"); 1291 radeon_do_cleanup_cp(dev); 1292 return -EINVAL; 1293 } 1294 } else 1295 #endif 1296 { 1297 dev_priv->cp_ring->virtual = 1298 (void *)(unsigned long)dev_priv->cp_ring->offset; 1299 dev_priv->ring_rptr->virtual = 1300 (void *)(unsigned long)dev_priv->ring_rptr->offset; 1301 dev->agp_buffer_map->virtual = 1302 (void *)(unsigned long)dev->agp_buffer_map->offset; 1303 1304 DRM_DEBUG("dev_priv->cp_ring->virtual %p\n", 1305 dev_priv->cp_ring->virtual); 1306 DRM_DEBUG("dev_priv->ring_rptr->virtual %p\n", 1307 dev_priv->ring_rptr->virtual); 1308 DRM_DEBUG("dev->agp_buffer_map->virtual %p\n", 1309 dev->agp_buffer_map->virtual); 1310 } 1311 1312 dev_priv->fb_location = (radeon_read_fb_location(dev_priv) & 0xffff) << 16; 1313 dev_priv->fb_size = 1314 ((radeon_read_fb_location(dev_priv) & 0xffff0000u) + 0x10000) 1315 - dev_priv->fb_location; 1316 1317 dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) | 1318 ((dev_priv->front_offset 1319 + dev_priv->fb_location) >> 10)); 1320 1321 dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) | 1322 ((dev_priv->back_offset 1323 + dev_priv->fb_location) >> 10)); 1324 1325 dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) | 1326 ((dev_priv->depth_offset 1327 + dev_priv->fb_location) >> 10)); 1328 1329 dev_priv->gart_size = init->gart_size; 1330 1331 /* New let's set the memory map ... */ 1332 if (dev_priv->new_memmap) { 1333 u32 base = 0; 1334 1335 DRM_INFO("Setting GART location based on new memory map\n"); 1336 1337 /* If using AGP, try to locate the AGP aperture at the same 1338 * location in the card and on the bus, though we have to 1339 * align it down. 1340 */ 1341 #if __OS_HAS_AGP 1342 if (dev_priv->flags & RADEON_IS_AGP) { 1343 base = dev->agp->base; 1344 /* Check if valid */ 1345 if ((base + dev_priv->gart_size - 1) >= dev_priv->fb_location && 1346 base < (dev_priv->fb_location + dev_priv->fb_size - 1)) { 1347 DRM_INFO("Can't use AGP base @0x%08lx, won't fit\n", 1348 dev->agp->base); 1349 base = 0; 1350 } 1351 } 1352 #endif 1353 /* If not or if AGP is at 0 (Macs), try to put it elsewhere */ 1354 if (base == 0) { 1355 base = dev_priv->fb_location + dev_priv->fb_size; 1356 if (base < dev_priv->fb_location || 1357 ((base + dev_priv->gart_size) & 0xfffffffful) < base) 1358 base = dev_priv->fb_location 1359 - dev_priv->gart_size; 1360 } 1361 dev_priv->gart_vm_start = base & 0xffc00000u; 1362 if (dev_priv->gart_vm_start != base) 1363 DRM_INFO("GART aligned down from 0x%08x to 0x%08x\n", 1364 base, dev_priv->gart_vm_start); 1365 } else { 1366 DRM_INFO("Setting GART location based on old memory map\n"); 1367 dev_priv->gart_vm_start = dev_priv->fb_location + 1368 RADEON_READ(RADEON_CONFIG_APER_SIZE); 1369 } 1370 1371 #if __OS_HAS_AGP 1372 if (dev_priv->flags & RADEON_IS_AGP) 1373 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset 1374 - dev->agp->base 1375 + dev_priv->gart_vm_start); 1376 else 1377 #endif 1378 dev_priv->gart_buffers_offset = dev->agp_buffer_map->offset - 1379 dev->sg->vaddr + dev_priv->gart_vm_start; 1380 1381 DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size); 1382 DRM_DEBUG("dev_priv->gart_vm_start 0x%x\n", dev_priv->gart_vm_start); 1383 DRM_DEBUG("dev_priv->gart_buffers_offset 0x%lx\n", 1384 dev_priv->gart_buffers_offset); 1385 1386 dev_priv->ring.start = (u32 *) dev_priv->cp_ring->virtual; 1387 dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->virtual 1388 + init->ring_size / sizeof(u32)); 1389 dev_priv->ring.size = init->ring_size; 1390 dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8); 1391 1392 dev_priv->ring.rptr_update = /* init->rptr_update */ 4096; 1393 dev_priv->ring.rptr_update_l2qw = drm_order( /* init->rptr_update */ 4096 / 8); 1394 1395 dev_priv->ring.fetch_size = /* init->fetch_size */ 32; 1396 dev_priv->ring.fetch_size_l2ow = drm_order( /* init->fetch_size */ 32 / 16); 1397 dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1; 1398 1399 dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK; 1400 1401 #if __OS_HAS_AGP 1402 if (dev_priv->flags & RADEON_IS_AGP) { 1403 /* Turn off PCI GART */ 1404 radeon_set_pcigart(dev_priv, 0); 1405 } else 1406 #endif 1407 { 1408 u32 sctrl; 1409 int ret; 1410 1411 dev_priv->gart_info.table_mask = DMA_BIT_MASK(32); 1412 /* if we have an offset set from userspace */ 1413 if (dev_priv->pcigart_offset_set) { 1414 dev_priv->gart_info.bus_addr = 1415 dev_priv->pcigart_offset + dev_priv->fb_location; 1416 dev_priv->gart_info.mapping.offset = 1417 dev_priv->pcigart_offset + dev_priv->fb_aper_offset; 1418 dev_priv->gart_info.mapping.size = 1419 dev_priv->gart_info.table_size; 1420 1421 drm_core_ioremap_wc(&dev_priv->gart_info.mapping, dev); 1422 dev_priv->gart_info.addr = 1423 dev_priv->gart_info.mapping.virtual; 1424 1425 if (dev_priv->flags & RADEON_IS_PCIE) 1426 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCIE; 1427 else 1428 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI; 1429 dev_priv->gart_info.gart_table_location = 1430 DRM_ATI_GART_FB; 1431 1432 DRM_DEBUG("Setting phys_pci_gart to %p %08lX\n", 1433 dev_priv->gart_info.addr, 1434 dev_priv->pcigart_offset); 1435 } else { 1436 if (dev_priv->flags & RADEON_IS_IGPGART) 1437 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_IGP; 1438 else 1439 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI; 1440 dev_priv->gart_info.gart_table_location = 1441 DRM_ATI_GART_MAIN; 1442 dev_priv->gart_info.addr = NULL; 1443 dev_priv->gart_info.bus_addr = 0; 1444 if (dev_priv->flags & RADEON_IS_PCIE) { 1445 DRM_ERROR 1446 ("Cannot use PCI Express without GART in FB memory\n"); 1447 radeon_do_cleanup_cp(dev); 1448 return -EINVAL; 1449 } 1450 } 1451 1452 sctrl = RADEON_READ(RADEON_SURFACE_CNTL); 1453 RADEON_WRITE(RADEON_SURFACE_CNTL, 0); 1454 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) 1455 ret = r600_page_table_init(dev); 1456 else 1457 ret = drm_ati_pcigart_init(dev, &dev_priv->gart_info); 1458 RADEON_WRITE(RADEON_SURFACE_CNTL, sctrl); 1459 1460 if (!ret) { 1461 DRM_ERROR("failed to init PCI GART!\n"); 1462 radeon_do_cleanup_cp(dev); 1463 return -ENOMEM; 1464 } 1465 1466 ret = radeon_setup_pcigart_surface(dev_priv); 1467 if (ret) { 1468 DRM_ERROR("failed to setup GART surface!\n"); 1469 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) 1470 r600_page_table_cleanup(dev, &dev_priv->gart_info); 1471 else 1472 drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info); 1473 radeon_do_cleanup_cp(dev); 1474 return ret; 1475 } 1476 1477 /* Turn on PCI GART */ 1478 radeon_set_pcigart(dev_priv, 1); 1479 } 1480 1481 radeon_cp_load_microcode(dev_priv); 1482 radeon_cp_init_ring_buffer(dev, dev_priv, file_priv); 1483 1484 dev_priv->last_buf = 0; 1485 1486 radeon_do_engine_reset(dev); 1487 radeon_test_writeback(dev_priv); 1488 1489 return 0; 1490 } 1491 1492 static int radeon_do_cleanup_cp(struct drm_device * dev) 1493 { 1494 drm_radeon_private_t *dev_priv = dev->dev_private; 1495 DRM_DEBUG("\n"); 1496 1497 /* Make sure interrupts are disabled here because the uninstall ioctl 1498 * may not have been called from userspace and after dev_private 1499 * is freed, it's too late. 1500 */ 1501 if (dev->irq_enabled) 1502 drm_irq_uninstall(dev); 1503 1504 #if __OS_HAS_AGP 1505 if (dev_priv->flags & RADEON_IS_AGP) { 1506 if (dev_priv->cp_ring != NULL) { 1507 drm_core_ioremapfree(dev_priv->cp_ring, dev); 1508 dev_priv->cp_ring = NULL; 1509 } 1510 if (dev_priv->ring_rptr != NULL) { 1511 drm_core_ioremapfree(dev_priv->ring_rptr, dev); 1512 dev_priv->ring_rptr = NULL; 1513 } 1514 if (dev->agp_buffer_map != NULL) { 1515 drm_core_ioremapfree(dev->agp_buffer_map, dev); 1516 dev->agp_buffer_map = NULL; 1517 } 1518 } else 1519 #endif 1520 { 1521 1522 if (dev_priv->gart_info.bus_addr) { 1523 /* Turn off PCI GART */ 1524 radeon_set_pcigart(dev_priv, 0); 1525 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) 1526 r600_page_table_cleanup(dev, &dev_priv->gart_info); 1527 else { 1528 if (!drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info)) 1529 DRM_ERROR("failed to cleanup PCI GART!\n"); 1530 } 1531 } 1532 1533 if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB) 1534 { 1535 drm_core_ioremapfree(&dev_priv->gart_info.mapping, dev); 1536 dev_priv->gart_info.addr = 0; 1537 } 1538 } 1539 /* only clear to the start of flags */ 1540 memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags)); 1541 1542 return 0; 1543 } 1544 1545 /* This code will reinit the Radeon CP hardware after a resume from disc. 1546 * AFAIK, it would be very difficult to pickle the state at suspend time, so 1547 * here we make sure that all Radeon hardware initialisation is re-done without 1548 * affecting running applications. 1549 * 1550 * Charl P. Botha <http://cpbotha.net> 1551 */ 1552 static int radeon_do_resume_cp(struct drm_device *dev, struct drm_file *file_priv) 1553 { 1554 drm_radeon_private_t *dev_priv = dev->dev_private; 1555 1556 if (!dev_priv) { 1557 DRM_ERROR("Called with no initialization\n"); 1558 return -EINVAL; 1559 } 1560 1561 DRM_DEBUG("Starting radeon_do_resume_cp()\n"); 1562 1563 #if __OS_HAS_AGP 1564 if (dev_priv->flags & RADEON_IS_AGP) { 1565 /* Turn off PCI GART */ 1566 radeon_set_pcigart(dev_priv, 0); 1567 } else 1568 #endif 1569 { 1570 /* Turn on PCI GART */ 1571 radeon_set_pcigart(dev_priv, 1); 1572 } 1573 1574 radeon_cp_load_microcode(dev_priv); 1575 radeon_cp_init_ring_buffer(dev, dev_priv, file_priv); 1576 1577 radeon_do_engine_reset(dev); 1578 radeon_irq_set_state(dev, RADEON_SW_INT_ENABLE, 1); 1579 1580 DRM_DEBUG("radeon_do_resume_cp() complete\n"); 1581 1582 return 0; 1583 } 1584 1585 int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv) 1586 { 1587 drm_radeon_private_t *dev_priv = dev->dev_private; 1588 drm_radeon_init_t *init = data; 1589 1590 LOCK_TEST_WITH_RETURN(dev, file_priv); 1591 1592 if (init->func == RADEON_INIT_R300_CP) 1593 r300_init_reg_flags(dev); 1594 1595 switch (init->func) { 1596 case RADEON_INIT_CP: 1597 case RADEON_INIT_R200_CP: 1598 case RADEON_INIT_R300_CP: 1599 return radeon_do_init_cp(dev, init, file_priv); 1600 case RADEON_INIT_R600_CP: 1601 return r600_do_init_cp(dev, init, file_priv); 1602 case RADEON_CLEANUP_CP: 1603 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) 1604 return r600_do_cleanup_cp(dev); 1605 else 1606 return radeon_do_cleanup_cp(dev); 1607 } 1608 1609 return -EINVAL; 1610 } 1611 1612 int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv) 1613 { 1614 drm_radeon_private_t *dev_priv = dev->dev_private; 1615 DRM_DEBUG("\n"); 1616 1617 LOCK_TEST_WITH_RETURN(dev, file_priv); 1618 1619 if (dev_priv->cp_running) { 1620 DRM_DEBUG("while CP running\n"); 1621 return 0; 1622 } 1623 if (dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS) { 1624 DRM_DEBUG("called with bogus CP mode (%d)\n", 1625 dev_priv->cp_mode); 1626 return 0; 1627 } 1628 1629 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) 1630 r600_do_cp_start(dev_priv); 1631 else 1632 radeon_do_cp_start(dev_priv); 1633 1634 return 0; 1635 } 1636 1637 /* Stop the CP. The engine must have been idled before calling this 1638 * routine. 1639 */ 1640 int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_priv) 1641 { 1642 drm_radeon_private_t *dev_priv = dev->dev_private; 1643 drm_radeon_cp_stop_t *stop = data; 1644 int ret; 1645 DRM_DEBUG("\n"); 1646 1647 LOCK_TEST_WITH_RETURN(dev, file_priv); 1648 1649 if (!dev_priv->cp_running) 1650 return 0; 1651 1652 /* Flush any pending CP commands. This ensures any outstanding 1653 * commands are exectuted by the engine before we turn it off. 1654 */ 1655 if (stop->flush) { 1656 radeon_do_cp_flush(dev_priv); 1657 } 1658 1659 /* If we fail to make the engine go idle, we return an error 1660 * code so that the DRM ioctl wrapper can try again. 1661 */ 1662 if (stop->idle) { 1663 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) 1664 ret = r600_do_cp_idle(dev_priv); 1665 else 1666 ret = radeon_do_cp_idle(dev_priv); 1667 if (ret) 1668 return ret; 1669 } 1670 1671 /* Finally, we can turn off the CP. If the engine isn't idle, 1672 * we will get some dropped triangles as they won't be fully 1673 * rendered before the CP is shut down. 1674 */ 1675 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) 1676 r600_do_cp_stop(dev_priv); 1677 else 1678 radeon_do_cp_stop(dev_priv); 1679 1680 /* Reset the engine */ 1681 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) 1682 r600_do_engine_reset(dev); 1683 else 1684 radeon_do_engine_reset(dev); 1685 1686 return 0; 1687 } 1688 1689 void radeon_do_release(struct drm_device * dev) 1690 { 1691 drm_radeon_private_t *dev_priv = dev->dev_private; 1692 int i, ret; 1693 1694 if (dev_priv) { 1695 if (dev_priv->cp_running) { 1696 /* Stop the cp */ 1697 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) { 1698 while ((ret = r600_do_cp_idle(dev_priv)) != 0) { 1699 DRM_DEBUG("radeon_do_cp_idle %d\n", ret); 1700 mtx_sleep(&ret, &dev->dev_lock, 0, 1701 "rdnrel", 1); 1702 } 1703 } else { 1704 while ((ret = radeon_do_cp_idle(dev_priv)) != 0) { 1705 DRM_DEBUG("radeon_do_cp_idle %d\n", ret); 1706 mtx_sleep(&ret, &dev->dev_lock, 0, 1707 "rdnrel", 1); 1708 } 1709 } 1710 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) { 1711 r600_do_cp_stop(dev_priv); 1712 r600_do_engine_reset(dev); 1713 } else { 1714 radeon_do_cp_stop(dev_priv); 1715 radeon_do_engine_reset(dev); 1716 } 1717 } 1718 1719 if ((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_R600) { 1720 /* Disable *all* interrupts */ 1721 if (dev_priv->mmio) /* remove this after permanent addmaps */ 1722 RADEON_WRITE(RADEON_GEN_INT_CNTL, 0); 1723 1724 if (dev_priv->mmio) { /* remove all surfaces */ 1725 for (i = 0; i < RADEON_MAX_SURFACES; i++) { 1726 RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, 0); 1727 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND + 1728 16 * i, 0); 1729 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND + 1730 16 * i, 0); 1731 } 1732 } 1733 } 1734 1735 /* Free memory heap structures */ 1736 radeon_mem_takedown(&(dev_priv->gart_heap)); 1737 radeon_mem_takedown(&(dev_priv->fb_heap)); 1738 1739 /* deallocate kernel resources */ 1740 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) 1741 r600_do_cleanup_cp(dev); 1742 else 1743 radeon_do_cleanup_cp(dev); 1744 } 1745 } 1746 1747 /* Just reset the CP ring. Called as part of an X Server engine reset. 1748 */ 1749 int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_priv) 1750 { 1751 drm_radeon_private_t *dev_priv = dev->dev_private; 1752 DRM_DEBUG("\n"); 1753 1754 LOCK_TEST_WITH_RETURN(dev, file_priv); 1755 1756 if (!dev_priv) { 1757 DRM_DEBUG("called before init done\n"); 1758 return -EINVAL; 1759 } 1760 1761 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) 1762 r600_do_cp_reset(dev_priv); 1763 else 1764 radeon_do_cp_reset(dev_priv); 1765 1766 /* The CP is no longer running after an engine reset */ 1767 dev_priv->cp_running = 0; 1768 1769 return 0; 1770 } 1771 1772 int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_priv) 1773 { 1774 drm_radeon_private_t *dev_priv = dev->dev_private; 1775 DRM_DEBUG("\n"); 1776 1777 LOCK_TEST_WITH_RETURN(dev, file_priv); 1778 1779 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) 1780 return r600_do_cp_idle(dev_priv); 1781 else 1782 return radeon_do_cp_idle(dev_priv); 1783 } 1784 1785 /* Added by Charl P. Botha to call radeon_do_resume_cp(). 1786 */ 1787 int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv) 1788 { 1789 drm_radeon_private_t *dev_priv = dev->dev_private; 1790 DRM_DEBUG("\n"); 1791 1792 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) 1793 return r600_do_resume_cp(dev, file_priv); 1794 else 1795 return radeon_do_resume_cp(dev, file_priv); 1796 } 1797 1798 int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv) 1799 { 1800 drm_radeon_private_t *dev_priv = dev->dev_private; 1801 DRM_DEBUG("\n"); 1802 1803 LOCK_TEST_WITH_RETURN(dev, file_priv); 1804 1805 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) 1806 return r600_do_engine_reset(dev); 1807 else 1808 return radeon_do_engine_reset(dev); 1809 } 1810 1811 /* ================================================================ 1812 * Fullscreen mode 1813 */ 1814 1815 /* KW: Deprecated to say the least: 1816 */ 1817 int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv) 1818 { 1819 return 0; 1820 } 1821 1822 /* ================================================================ 1823 * Freelist management 1824 */ 1825 1826 /* Original comment: FIXME: ROTATE_BUFS is a hack to cycle through 1827 * bufs until freelist code is used. Note this hides a problem with 1828 * the scratch register * (used to keep track of last buffer 1829 * completed) being written to before * the last buffer has actually 1830 * completed rendering. 1831 * 1832 * KW: It's also a good way to find free buffers quickly. 1833 * 1834 * KW: Ideally this loop wouldn't exist, and freelist_get wouldn't 1835 * sleep. However, bugs in older versions of radeon_accel.c mean that 1836 * we essentially have to do this, else old clients will break. 1837 * 1838 * However, it does leave open a potential deadlock where all the 1839 * buffers are held by other clients, which can't release them because 1840 * they can't get the lock. 1841 */ 1842 1843 struct drm_buf *radeon_freelist_get(struct drm_device * dev) 1844 { 1845 struct drm_device_dma *dma = dev->dma; 1846 drm_radeon_private_t *dev_priv = dev->dev_private; 1847 drm_radeon_buf_priv_t *buf_priv; 1848 struct drm_buf *buf; 1849 int i, t; 1850 int start; 1851 1852 if (++dev_priv->last_buf >= dma->buf_count) 1853 dev_priv->last_buf = 0; 1854 1855 start = dev_priv->last_buf; 1856 1857 for (t = 0; t < dev_priv->usec_timeout; t++) { 1858 u32 done_age = GET_SCRATCH(dev_priv, 1); 1859 DRM_DEBUG("done_age = %d\n", done_age); 1860 for (i = 0; i < dma->buf_count; i++) { 1861 buf = dma->buflist[start]; 1862 buf_priv = buf->dev_private; 1863 if (buf->file_priv == NULL || (buf->pending && 1864 buf_priv->age <= 1865 done_age)) { 1866 dev_priv->stats.requested_bufs++; 1867 buf->pending = 0; 1868 return buf; 1869 } 1870 if (++start >= dma->buf_count) 1871 start = 0; 1872 } 1873 1874 if (t) { 1875 DRM_UDELAY(1); 1876 dev_priv->stats.freelist_loops++; 1877 } 1878 } 1879 1880 return NULL; 1881 } 1882 1883 void radeon_freelist_reset(struct drm_device * dev) 1884 { 1885 struct drm_device_dma *dma = dev->dma; 1886 drm_radeon_private_t *dev_priv = dev->dev_private; 1887 int i; 1888 1889 dev_priv->last_buf = 0; 1890 for (i = 0; i < dma->buf_count; i++) { 1891 struct drm_buf *buf = dma->buflist[i]; 1892 drm_radeon_buf_priv_t *buf_priv = buf->dev_private; 1893 buf_priv->age = 0; 1894 } 1895 } 1896 1897 /* ================================================================ 1898 * CP command submission 1899 */ 1900 1901 int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n) 1902 { 1903 drm_radeon_ring_buffer_t *ring = &dev_priv->ring; 1904 int i; 1905 u32 last_head = GET_RING_HEAD(dev_priv); 1906 1907 for (i = 0; i < dev_priv->usec_timeout; i++) { 1908 u32 head = GET_RING_HEAD(dev_priv); 1909 1910 ring->space = (head - ring->tail) * sizeof(u32); 1911 if (ring->space <= 0) 1912 ring->space += ring->size; 1913 if (ring->space > n) 1914 return 0; 1915 1916 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; 1917 1918 if (head != last_head) 1919 i = 0; 1920 last_head = head; 1921 1922 DRM_UDELAY(1); 1923 } 1924 1925 /* FIXME: This return value is ignored in the BEGIN_RING macro! */ 1926 #if RADEON_FIFO_DEBUG 1927 radeon_status(dev_priv); 1928 DRM_ERROR("failed!\n"); 1929 #endif 1930 return -EBUSY; 1931 } 1932 1933 static int radeon_cp_get_buffers(struct drm_device *dev, 1934 struct drm_file *file_priv, 1935 struct drm_dma * d) 1936 { 1937 int i; 1938 struct drm_buf *buf; 1939 1940 for (i = d->granted_count; i < d->request_count; i++) { 1941 buf = radeon_freelist_get(dev); 1942 if (!buf) 1943 return -EBUSY; /* NOTE: broken client */ 1944 1945 buf->file_priv = file_priv; 1946 1947 if (DRM_COPY_TO_USER(&d->request_indices[i], &buf->idx, 1948 sizeof(buf->idx))) 1949 return -EFAULT; 1950 if (DRM_COPY_TO_USER(&d->request_sizes[i], &buf->total, 1951 sizeof(buf->total))) 1952 return -EFAULT; 1953 1954 d->granted_count++; 1955 } 1956 return 0; 1957 } 1958 1959 int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv) 1960 { 1961 struct drm_device_dma *dma = dev->dma; 1962 int ret = 0; 1963 struct drm_dma *d = data; 1964 1965 LOCK_TEST_WITH_RETURN(dev, file_priv); 1966 1967 /* Please don't send us buffers. 1968 */ 1969 if (d->send_count != 0) { 1970 DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n", 1971 DRM_CURRENTPID, d->send_count); 1972 return -EINVAL; 1973 } 1974 1975 /* We'll send you buffers. 1976 */ 1977 if (d->request_count < 0 || d->request_count > dma->buf_count) { 1978 DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n", 1979 DRM_CURRENTPID, d->request_count, dma->buf_count); 1980 return -EINVAL; 1981 } 1982 1983 d->granted_count = 0; 1984 1985 if (d->request_count) { 1986 ret = radeon_cp_get_buffers(dev, file_priv, d); 1987 } 1988 1989 return ret; 1990 } 1991 1992 int radeon_driver_load(struct drm_device *dev, unsigned long flags) 1993 { 1994 drm_radeon_private_t *dev_priv; 1995 int ret = 0; 1996 1997 dev_priv = drm_alloc(sizeof(drm_radeon_private_t), DRM_MEM_DRIVER); 1998 if (dev_priv == NULL) 1999 return -ENOMEM; 2000 2001 memset(dev_priv, 0, sizeof(drm_radeon_private_t)); 2002 dev->dev_private = (void *)dev_priv; 2003 dev_priv->flags = flags; 2004 2005 switch (flags & RADEON_FAMILY_MASK) { 2006 case CHIP_R100: 2007 case CHIP_RV200: 2008 case CHIP_R200: 2009 case CHIP_R300: 2010 case CHIP_R350: 2011 case CHIP_R420: 2012 case CHIP_R423: 2013 case CHIP_RV410: 2014 case CHIP_RV515: 2015 case CHIP_R520: 2016 case CHIP_RV570: 2017 case CHIP_R580: 2018 dev_priv->flags |= RADEON_HAS_HIERZ; 2019 break; 2020 default: 2021 /* all other chips have no hierarchical z buffer */ 2022 break; 2023 } 2024 2025 if (drm_device_is_agp(dev)) 2026 dev_priv->flags |= RADEON_IS_AGP; 2027 else if (drm_device_is_pcie(dev)) 2028 dev_priv->flags |= RADEON_IS_PCIE; 2029 else 2030 dev_priv->flags |= RADEON_IS_PCI; 2031 2032 mtx_init(&dev_priv->cs.cs_mutex, "cs_mtx", NULL, MTX_DEF); 2033 2034 ret = drm_addmap(dev, drm_get_resource_start(dev, 2), 2035 drm_get_resource_len(dev, 2), _DRM_REGISTERS, 2036 _DRM_READ_ONLY | _DRM_DRIVER, &dev_priv->mmio); 2037 if (ret != 0) 2038 goto error; 2039 2040 ret = drm_vblank_init(dev, 2); 2041 if (ret != 0) 2042 goto error; 2043 2044 dev->max_vblank_count = 0x001fffff; 2045 2046 DRM_DEBUG("%s card detected\n", 2047 ((dev_priv->flags & RADEON_IS_AGP) ? "AGP" : 2048 (((dev_priv->flags & RADEON_IS_PCIE) ? "PCIE" : "PCI")))); 2049 2050 return ret; 2051 2052 error: 2053 radeon_driver_unload(dev); 2054 return ret; 2055 } 2056 2057 /* Create mappings for registers and framebuffer so userland doesn't necessarily 2058 * have to find them. 2059 */ 2060 int radeon_driver_firstopen(struct drm_device *dev) 2061 { 2062 int ret; 2063 drm_local_map_t *map; 2064 drm_radeon_private_t *dev_priv = dev->dev_private; 2065 2066 dev_priv->gart_info.table_size = RADEON_PCIGART_TABLE_SIZE; 2067 2068 dev_priv->fb_aper_offset = drm_get_resource_start(dev, 0); 2069 ret = drm_addmap(dev, dev_priv->fb_aper_offset, 2070 drm_get_resource_len(dev, 0), _DRM_FRAME_BUFFER, 2071 _DRM_WRITE_COMBINING, &map); 2072 if (ret != 0) 2073 return ret; 2074 2075 return 0; 2076 } 2077 2078 int radeon_driver_unload(struct drm_device *dev) 2079 { 2080 drm_radeon_private_t *dev_priv = dev->dev_private; 2081 2082 DRM_DEBUG("\n"); 2083 2084 drm_rmmap(dev, dev_priv->mmio); 2085 2086 mtx_destroy(&dev_priv->cs.cs_mutex); 2087 2088 drm_free(dev_priv, sizeof(*dev_priv), DRM_MEM_DRIVER); 2089 2090 dev->dev_private = NULL; 2091 return 0; 2092 } 2093 2094 void radeon_commit_ring(drm_radeon_private_t *dev_priv) 2095 { 2096 int i; 2097 u32 *ring; 2098 int tail_aligned; 2099 2100 /* check if the ring is padded out to 16-dword alignment */ 2101 2102 tail_aligned = dev_priv->ring.tail & (RADEON_RING_ALIGN - 1); 2103 if (tail_aligned) { 2104 int num_p2 = RADEON_RING_ALIGN - tail_aligned; 2105 2106 ring = dev_priv->ring.start; 2107 /* pad with some CP_PACKET2 */ 2108 for (i = 0; i < num_p2; i++) 2109 ring[dev_priv->ring.tail + i] = CP_PACKET2(); 2110 2111 dev_priv->ring.tail += i; 2112 2113 dev_priv->ring.space -= num_p2 * sizeof(u32); 2114 } 2115 2116 dev_priv->ring.tail &= dev_priv->ring.tail_mask; 2117 2118 DRM_MEMORYBARRIER(); 2119 GET_RING_HEAD( dev_priv ); 2120 2121 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) { 2122 RADEON_WRITE(R600_CP_RB_WPTR, dev_priv->ring.tail); 2123 /* read from PCI bus to ensure correct posting */ 2124 RADEON_READ(R600_CP_RB_RPTR); 2125 } else { 2126 RADEON_WRITE(RADEON_CP_RB_WPTR, dev_priv->ring.tail); 2127 /* read from PCI bus to ensure correct posting */ 2128 RADEON_READ(RADEON_CP_RB_RPTR); 2129 } 2130 }
Cache object: 956924d10f7287affef63f431ab9436a
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