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sys/dev/drm/radeon_drv.h
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1 /* radeon_drv.h -- Private header for radeon driver -*- linux-c -*- 2 * 3 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. 4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California. 5 * All rights reserved. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the "Software"), 9 * to deal in the Software without restriction, including without limitation 10 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 11 * and/or sell copies of the Software, and to permit persons to whom the 12 * Software is furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice (including the next 15 * paragraph) shall be included in all copies or substantial portions of the 16 * Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 24 * DEALINGS IN THE SOFTWARE. 25 * 26 * Authors: 27 * Kevin E. Martin <martin@valinux.com> 28 * Gareth Hughes <gareth@valinux.com> 29 */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD: releng/6.4/sys/dev/drm/radeon_drv.h 166475 2007-02-03 20:01:54Z flz $"); 33 34 #ifndef __RADEON_DRV_H__ 35 #define __RADEON_DRV_H__ 36 37 /* General customization: 38 */ 39 40 #define DRIVER_AUTHOR "Gareth Hughes, Keith Whitwell, others." 41 42 #define DRIVER_NAME "radeon" 43 #define DRIVER_DESC "ATI Radeon" 44 #define DRIVER_DATE "20060524" 45 46 /* Interface history: 47 * 48 * 1.1 - ?? 49 * 1.2 - Add vertex2 ioctl (keith) 50 * - Add stencil capability to clear ioctl (gareth, keith) 51 * - Increase MAX_TEXTURE_LEVELS (brian) 52 * 1.3 - Add cmdbuf ioctl (keith) 53 * - Add support for new radeon packets (keith) 54 * - Add getparam ioctl (keith) 55 * - Add flip-buffers ioctl, deprecate fullscreen foo (keith). 56 * 1.4 - Add scratch registers to get_param ioctl. 57 * 1.5 - Add r200 packets to cmdbuf ioctl 58 * - Add r200 function to init ioctl 59 * - Add 'scalar2' instruction to cmdbuf 60 * 1.6 - Add static GART memory manager 61 * Add irq handler (won't be turned on unless X server knows to) 62 * Add irq ioctls and irq_active getparam. 63 * Add wait command for cmdbuf ioctl 64 * Add GART offset query for getparam 65 * 1.7 - Add support for cube map registers: R200_PP_CUBIC_FACES_[0..5] 66 * and R200_PP_CUBIC_OFFSET_F1_[0..5]. 67 * Added packets R200_EMIT_PP_CUBIC_FACES_[0..5] and 68 * R200_EMIT_PP_CUBIC_OFFSETS_[0..5]. (brian) 69 * 1.8 - Remove need to call cleanup ioctls on last client exit (keith) 70 * Add 'GET' queries for starting additional clients on different VT's. 71 * 1.9 - Add DRM_IOCTL_RADEON_CP_RESUME ioctl. 72 * Add texture rectangle support for r100. 73 * 1.10- Add SETPARAM ioctl; first parameter to set is FB_LOCATION, which 74 * clients use to tell the DRM where they think the framebuffer is 75 * located in the card's address space 76 * 1.11- Add packet R200_EMIT_RB3D_BLENDCOLOR to support GL_EXT_blend_color 77 * and GL_EXT_blend_[func|equation]_separate on r200 78 * 1.12- Add R300 CP microcode support - this just loads the CP on r300 79 * (No 3D support yet - just microcode loading). 80 * 1.13- Add packet R200_EMIT_TCL_POINT_SPRITE_CNTL for ARB_point_parameters 81 * - Add hyperz support, add hyperz flags to clear ioctl. 82 * 1.14- Add support for color tiling 83 * - Add R100/R200 surface allocation/free support 84 * 1.15- Add support for texture micro tiling 85 * - Add support for r100 cube maps 86 * 1.16- Add R200_EMIT_PP_TRI_PERF_CNTL packet to support brilinear 87 * texture filtering on r200 88 * 1.17- Add initial support for R300 (3D). 89 * 1.18- Add support for GL_ATI_fragment_shader, new packets 90 * R200_EMIT_PP_AFS_0/1, R200_EMIT_PP_TXCTLALL_0-5 (replaces 91 * R200_EMIT_PP_TXFILTER_0-5, 2 more regs) and R200_EMIT_ATF_TFACTOR 92 * (replaces R200_EMIT_TFACTOR_0 (8 consts instead of 6) 93 * 1.19- Add support for gart table in FB memory and PCIE r300 94 * 1.20- Add support for r300 texrect 95 * 1.21- Add support for card type getparam 96 * 1.22- Add support for texture cache flushes (R300_TX_CNTL) 97 * 1.23- Add new radeon memory map work from benh 98 * 1.24- Add general-purpose packet for manipulating scratch registers (r300) 99 * 1.25- Add support for r200 vertex programs (R200_EMIT_VAP_PVS_CNTL, 100 * new packet type) 101 */ 102 103 #define DRIVER_MAJOR 1 104 #define DRIVER_MINOR 25 105 #define DRIVER_PATCHLEVEL 0 106 107 /* 108 * Radeon chip families 109 */ 110 enum radeon_family { 111 CHIP_R100, 112 CHIP_RV100, 113 CHIP_RS100, 114 CHIP_RV200, 115 CHIP_RS200, 116 CHIP_R200, 117 CHIP_RV250, 118 CHIP_RS300, 119 CHIP_RV280, 120 CHIP_R300, 121 CHIP_R350, 122 CHIP_RV350, 123 CHIP_RV380, 124 CHIP_R420, 125 CHIP_RV410, 126 CHIP_RS400, 127 CHIP_LAST, 128 }; 129 130 enum radeon_cp_microcode_version { 131 UCODE_R100, 132 UCODE_R200, 133 UCODE_R300, 134 }; 135 136 /* 137 * Chip flags 138 */ 139 enum radeon_chip_flags { 140 CHIP_FAMILY_MASK = 0x0000ffffUL, 141 CHIP_FLAGS_MASK = 0xffff0000UL, 142 CHIP_IS_MOBILITY = 0x00010000UL, 143 CHIP_IS_IGP = 0x00020000UL, 144 CHIP_SINGLE_CRTC = 0x00040000UL, 145 CHIP_IS_AGP = 0x00080000UL, 146 CHIP_HAS_HIERZ = 0x00100000UL, 147 CHIP_IS_PCIE = 0x00200000UL, 148 CHIP_NEW_MEMMAP = 0x00400000UL, 149 CHIP_IS_PCI = 0x00800000UL, 150 }; 151 152 #define GET_RING_HEAD(dev_priv) (dev_priv->writeback_works ? \ 153 DRM_READ32( (dev_priv)->ring_rptr, 0 ) : RADEON_READ(RADEON_CP_RB_RPTR)) 154 #define SET_RING_HEAD(dev_priv,val) DRM_WRITE32( (dev_priv)->ring_rptr, 0, (val) ) 155 156 typedef struct drm_radeon_freelist { 157 unsigned int age; 158 drm_buf_t *buf; 159 struct drm_radeon_freelist *next; 160 struct drm_radeon_freelist *prev; 161 } drm_radeon_freelist_t; 162 163 typedef struct drm_radeon_ring_buffer { 164 u32 *start; 165 u32 *end; 166 int size; 167 int size_l2qw; 168 169 u32 tail; 170 u32 tail_mask; 171 int space; 172 173 int high_mark; 174 } drm_radeon_ring_buffer_t; 175 176 typedef struct drm_radeon_depth_clear_t { 177 u32 rb3d_cntl; 178 u32 rb3d_zstencilcntl; 179 u32 se_cntl; 180 } drm_radeon_depth_clear_t; 181 182 struct drm_radeon_driver_file_fields { 183 int64_t radeon_fb_delta; 184 }; 185 186 struct mem_block { 187 struct mem_block *next; 188 struct mem_block *prev; 189 int start; 190 int size; 191 DRMFILE filp; /* 0: free, -1: heap, other: real files */ 192 }; 193 194 struct radeon_surface { 195 int refcount; 196 u32 lower; 197 u32 upper; 198 u32 flags; 199 }; 200 201 struct radeon_virt_surface { 202 int surface_index; 203 u32 lower; 204 u32 upper; 205 u32 flags; 206 DRMFILE filp; 207 }; 208 209 typedef struct drm_radeon_private { 210 211 drm_radeon_ring_buffer_t ring; 212 drm_radeon_sarea_t *sarea_priv; 213 214 u32 fb_location; 215 u32 fb_size; 216 int new_memmap; 217 218 int gart_size; 219 u32 gart_vm_start; 220 unsigned long gart_buffers_offset; 221 222 int cp_mode; 223 int cp_running; 224 225 drm_radeon_freelist_t *head; 226 drm_radeon_freelist_t *tail; 227 int last_buf; 228 volatile u32 *scratch; 229 int writeback_works; 230 231 int usec_timeout; 232 233 int microcode_version; 234 235 struct { 236 u32 boxes; 237 int freelist_timeouts; 238 int freelist_loops; 239 int requested_bufs; 240 int last_frame_reads; 241 int last_clear_reads; 242 int clears; 243 int texture_uploads; 244 } stats; 245 246 int do_boxes; 247 int page_flipping; 248 int current_page; 249 250 u32 color_fmt; 251 unsigned int front_offset; 252 unsigned int front_pitch; 253 unsigned int back_offset; 254 unsigned int back_pitch; 255 256 u32 depth_fmt; 257 unsigned int depth_offset; 258 unsigned int depth_pitch; 259 260 u32 front_pitch_offset; 261 u32 back_pitch_offset; 262 u32 depth_pitch_offset; 263 264 drm_radeon_depth_clear_t depth_clear; 265 266 unsigned long ring_offset; 267 unsigned long ring_rptr_offset; 268 unsigned long buffers_offset; 269 unsigned long gart_textures_offset; 270 271 drm_local_map_t *sarea; 272 drm_local_map_t *mmio; 273 drm_local_map_t *cp_ring; 274 drm_local_map_t *ring_rptr; 275 drm_local_map_t *gart_textures; 276 277 struct mem_block *gart_heap; 278 struct mem_block *fb_heap; 279 280 /* SW interrupt */ 281 wait_queue_head_t swi_queue; 282 atomic_t swi_emitted; 283 284 struct radeon_surface surfaces[RADEON_MAX_SURFACES]; 285 struct radeon_virt_surface virt_surfaces[2*RADEON_MAX_SURFACES]; 286 287 unsigned long pcigart_offset; 288 drm_ati_pcigart_info gart_info; 289 290 u32 scratch_ages[5]; 291 292 /* starting from here on, data is preserved accross an open */ 293 uint32_t flags; /* see radeon_chip_flags */ 294 295 } drm_radeon_private_t; 296 297 typedef struct drm_radeon_buf_priv { 298 u32 age; 299 } drm_radeon_buf_priv_t; 300 301 typedef struct drm_radeon_kcmd_buffer { 302 int bufsz; 303 char *buf; 304 int nbox; 305 drm_clip_rect_t __user *boxes; 306 } drm_radeon_kcmd_buffer_t; 307 308 extern int radeon_no_wb; 309 extern drm_ioctl_desc_t radeon_ioctls[]; 310 extern int radeon_max_ioctl; 311 312 /* radeon_cp.c */ 313 extern int radeon_cp_init(DRM_IOCTL_ARGS); 314 extern int radeon_cp_start(DRM_IOCTL_ARGS); 315 extern int radeon_cp_stop(DRM_IOCTL_ARGS); 316 extern int radeon_cp_reset(DRM_IOCTL_ARGS); 317 extern int radeon_cp_idle(DRM_IOCTL_ARGS); 318 extern int radeon_cp_resume(DRM_IOCTL_ARGS); 319 extern int radeon_engine_reset(DRM_IOCTL_ARGS); 320 extern int radeon_fullscreen(DRM_IOCTL_ARGS); 321 extern int radeon_cp_buffers(DRM_IOCTL_ARGS); 322 323 extern void radeon_freelist_reset(drm_device_t * dev); 324 extern drm_buf_t *radeon_freelist_get(drm_device_t * dev); 325 326 extern int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n); 327 328 extern int radeon_do_cp_idle(drm_radeon_private_t * dev_priv); 329 330 extern int radeon_mem_alloc(DRM_IOCTL_ARGS); 331 extern int radeon_mem_free(DRM_IOCTL_ARGS); 332 extern int radeon_mem_init_heap(DRM_IOCTL_ARGS); 333 extern void radeon_mem_takedown(struct mem_block **heap); 334 extern void radeon_mem_release(DRMFILE filp, struct mem_block *heap); 335 336 /* radeon_irq.c */ 337 extern int radeon_irq_emit(DRM_IOCTL_ARGS); 338 extern int radeon_irq_wait(DRM_IOCTL_ARGS); 339 340 extern void radeon_do_release(drm_device_t * dev); 341 extern int radeon_driver_vblank_wait(drm_device_t * dev, 342 unsigned int *sequence); 343 extern irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS); 344 extern void radeon_driver_irq_preinstall(drm_device_t * dev); 345 extern void radeon_driver_irq_postinstall(drm_device_t * dev); 346 extern void radeon_driver_irq_uninstall(drm_device_t * dev); 347 348 extern int radeon_driver_load(struct drm_device *dev, unsigned long flags); 349 extern int radeon_driver_unload(struct drm_device *dev); 350 extern int radeon_driver_firstopen(struct drm_device *dev); 351 extern void radeon_driver_preclose(drm_device_t * dev, DRMFILE filp); 352 extern void radeon_driver_postclose(drm_device_t * dev, drm_file_t * filp); 353 extern void radeon_driver_lastclose(drm_device_t * dev); 354 extern int radeon_driver_open(drm_device_t * dev, drm_file_t * filp_priv); 355 extern long radeon_compat_ioctl(struct file *filp, unsigned int cmd, 356 unsigned long arg); 357 358 /* r300_cmdbuf.c */ 359 extern void r300_init_reg_flags(void); 360 361 extern int r300_do_cp_cmdbuf(drm_device_t *dev, DRMFILE filp, 362 drm_file_t* filp_priv, 363 drm_radeon_kcmd_buffer_t* cmdbuf); 364 365 /* Flags for stats.boxes 366 */ 367 #define RADEON_BOX_DMA_IDLE 0x1 368 #define RADEON_BOX_RING_FULL 0x2 369 #define RADEON_BOX_FLIP 0x4 370 #define RADEON_BOX_WAIT_IDLE 0x8 371 #define RADEON_BOX_TEXTURE_LOAD 0x10 372 373 /* Register definitions, register access macros and drmAddMap constants 374 * for Radeon kernel driver. 375 */ 376 #define RADEON_AGP_COMMAND 0x0f60 377 #define RADEON_AGP_COMMAND_PCI_CONFIG 0x0060 /* offset in PCI config */ 378 # define RADEON_AGP_ENABLE (1<<8) 379 #define RADEON_AUX_SCISSOR_CNTL 0x26f0 380 # define RADEON_EXCLUSIVE_SCISSOR_0 (1 << 24) 381 # define RADEON_EXCLUSIVE_SCISSOR_1 (1 << 25) 382 # define RADEON_EXCLUSIVE_SCISSOR_2 (1 << 26) 383 # define RADEON_SCISSOR_0_ENABLE (1 << 28) 384 # define RADEON_SCISSOR_1_ENABLE (1 << 29) 385 # define RADEON_SCISSOR_2_ENABLE (1 << 30) 386 387 #define RADEON_BUS_CNTL 0x0030 388 # define RADEON_BUS_MASTER_DIS (1 << 6) 389 390 #define RADEON_CLOCK_CNTL_DATA 0x000c 391 # define RADEON_PLL_WR_EN (1 << 7) 392 #define RADEON_CLOCK_CNTL_INDEX 0x0008 393 #define RADEON_CONFIG_APER_SIZE 0x0108 394 #define RADEON_CONFIG_MEMSIZE 0x00f8 395 #define RADEON_CRTC_OFFSET 0x0224 396 #define RADEON_CRTC_OFFSET_CNTL 0x0228 397 # define RADEON_CRTC_TILE_EN (1 << 15) 398 # define RADEON_CRTC_OFFSET_FLIP_CNTL (1 << 16) 399 #define RADEON_CRTC2_OFFSET 0x0324 400 #define RADEON_CRTC2_OFFSET_CNTL 0x0328 401 402 #define RADEON_PCIE_INDEX 0x0030 403 #define RADEON_PCIE_DATA 0x0034 404 #define RADEON_PCIE_TX_GART_CNTL 0x10 405 # define RADEON_PCIE_TX_GART_EN (1 << 0) 406 # define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_PASS_THRU (0<<1) 407 # define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_CLAMP_LO (1<<1) 408 # define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD (3<<1) 409 # define RADEON_PCIE_TX_GART_MODE_32_128_CACHE (0<<3) 410 # define RADEON_PCIE_TX_GART_MODE_8_4_128_CACHE (1<<3) 411 # define RADEON_PCIE_TX_GART_CHK_RW_VALID_EN (1<<5) 412 # define RADEON_PCIE_TX_GART_INVALIDATE_TLB (1<<8) 413 #define RADEON_PCIE_TX_DISCARD_RD_ADDR_LO 0x11 414 #define RADEON_PCIE_TX_DISCARD_RD_ADDR_HI 0x12 415 #define RADEON_PCIE_TX_GART_BASE 0x13 416 #define RADEON_PCIE_TX_GART_START_LO 0x14 417 #define RADEON_PCIE_TX_GART_START_HI 0x15 418 #define RADEON_PCIE_TX_GART_END_LO 0x16 419 #define RADEON_PCIE_TX_GART_END_HI 0x17 420 421 #define RADEON_MPP_TB_CONFIG 0x01c0 422 #define RADEON_MEM_CNTL 0x0140 423 #define RADEON_MEM_SDRAM_MODE_REG 0x0158 424 #define RADEON_AGP_BASE 0x0170 425 426 #define RADEON_RB3D_COLOROFFSET 0x1c40 427 #define RADEON_RB3D_COLORPITCH 0x1c48 428 429 #define RADEON_DP_GUI_MASTER_CNTL 0x146c 430 # define RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0) 431 # define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1) 432 # define RADEON_GMC_BRUSH_SOLID_COLOR (13 << 4) 433 # define RADEON_GMC_BRUSH_NONE (15 << 4) 434 # define RADEON_GMC_DST_16BPP (4 << 8) 435 # define RADEON_GMC_DST_24BPP (5 << 8) 436 # define RADEON_GMC_DST_32BPP (6 << 8) 437 # define RADEON_GMC_DST_DATATYPE_SHIFT 8 438 # define RADEON_GMC_SRC_DATATYPE_COLOR (3 << 12) 439 # define RADEON_DP_SRC_SOURCE_MEMORY (2 << 24) 440 # define RADEON_DP_SRC_SOURCE_HOST_DATA (3 << 24) 441 # define RADEON_GMC_CLR_CMP_CNTL_DIS (1 << 28) 442 # define RADEON_GMC_WR_MSK_DIS (1 << 30) 443 # define RADEON_ROP3_S 0x00cc0000 444 # define RADEON_ROP3_P 0x00f00000 445 #define RADEON_DP_WRITE_MASK 0x16cc 446 #define RADEON_DST_PITCH_OFFSET 0x142c 447 #define RADEON_DST_PITCH_OFFSET_C 0x1c80 448 # define RADEON_DST_TILE_LINEAR (0 << 30) 449 # define RADEON_DST_TILE_MACRO (1 << 30) 450 # define RADEON_DST_TILE_MICRO (2 << 30) 451 # define RADEON_DST_TILE_BOTH (3 << 30) 452 453 #define RADEON_SCRATCH_REG0 0x15e0 454 #define RADEON_SCRATCH_REG1 0x15e4 455 #define RADEON_SCRATCH_REG2 0x15e8 456 #define RADEON_SCRATCH_REG3 0x15ec 457 #define RADEON_SCRATCH_REG4 0x15f0 458 #define RADEON_SCRATCH_REG5 0x15f4 459 #define RADEON_SCRATCH_UMSK 0x0770 460 #define RADEON_SCRATCH_ADDR 0x0774 461 462 #define RADEON_SCRATCHOFF( x ) (RADEON_SCRATCH_REG_OFFSET + 4*(x)) 463 464 #define GET_SCRATCH( x ) (dev_priv->writeback_works \ 465 ? DRM_READ32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(x) ) \ 466 : RADEON_READ( RADEON_SCRATCH_REG0 + 4*(x) ) ) 467 468 #define RADEON_GEN_INT_CNTL 0x0040 469 # define RADEON_CRTC_VBLANK_MASK (1 << 0) 470 # define RADEON_GUI_IDLE_INT_ENABLE (1 << 19) 471 # define RADEON_SW_INT_ENABLE (1 << 25) 472 473 #define RADEON_GEN_INT_STATUS 0x0044 474 # define RADEON_CRTC_VBLANK_STAT (1 << 0) 475 # define RADEON_CRTC_VBLANK_STAT_ACK (1 << 0) 476 # define RADEON_GUI_IDLE_INT_TEST_ACK (1 << 19) 477 # define RADEON_SW_INT_TEST (1 << 25) 478 # define RADEON_SW_INT_TEST_ACK (1 << 25) 479 # define RADEON_SW_INT_FIRE (1 << 26) 480 481 #define RADEON_HOST_PATH_CNTL 0x0130 482 # define RADEON_HDP_SOFT_RESET (1 << 26) 483 # define RADEON_HDP_WC_TIMEOUT_MASK (7 << 28) 484 # define RADEON_HDP_WC_TIMEOUT_28BCLK (7 << 28) 485 486 #define RADEON_ISYNC_CNTL 0x1724 487 # define RADEON_ISYNC_ANY2D_IDLE3D (1 << 0) 488 # define RADEON_ISYNC_ANY3D_IDLE2D (1 << 1) 489 # define RADEON_ISYNC_TRIG2D_IDLE3D (1 << 2) 490 # define RADEON_ISYNC_TRIG3D_IDLE2D (1 << 3) 491 # define RADEON_ISYNC_WAIT_IDLEGUI (1 << 4) 492 # define RADEON_ISYNC_CPSCRATCH_IDLEGUI (1 << 5) 493 494 #define RADEON_RBBM_GUICNTL 0x172c 495 # define RADEON_HOST_DATA_SWAP_NONE (0 << 0) 496 # define RADEON_HOST_DATA_SWAP_16BIT (1 << 0) 497 # define RADEON_HOST_DATA_SWAP_32BIT (2 << 0) 498 # define RADEON_HOST_DATA_SWAP_HDW (3 << 0) 499 500 #define RADEON_MC_AGP_LOCATION 0x014c 501 #define RADEON_MC_FB_LOCATION 0x0148 502 #define RADEON_MCLK_CNTL 0x0012 503 # define RADEON_FORCEON_MCLKA (1 << 16) 504 # define RADEON_FORCEON_MCLKB (1 << 17) 505 # define RADEON_FORCEON_YCLKA (1 << 18) 506 # define RADEON_FORCEON_YCLKB (1 << 19) 507 # define RADEON_FORCEON_MC (1 << 20) 508 # define RADEON_FORCEON_AIC (1 << 21) 509 510 #define RADEON_PP_BORDER_COLOR_0 0x1d40 511 #define RADEON_PP_BORDER_COLOR_1 0x1d44 512 #define RADEON_PP_BORDER_COLOR_2 0x1d48 513 #define RADEON_PP_CNTL 0x1c38 514 # define RADEON_SCISSOR_ENABLE (1 << 1) 515 #define RADEON_PP_LUM_MATRIX 0x1d00 516 #define RADEON_PP_MISC 0x1c14 517 #define RADEON_PP_ROT_MATRIX_0 0x1d58 518 #define RADEON_PP_TXFILTER_0 0x1c54 519 #define RADEON_PP_TXOFFSET_0 0x1c5c 520 #define RADEON_PP_TXFILTER_1 0x1c6c 521 #define RADEON_PP_TXFILTER_2 0x1c84 522 523 #define RADEON_RB2D_DSTCACHE_CTLSTAT 0x342c 524 # define RADEON_RB2D_DC_FLUSH (3 << 0) 525 # define RADEON_RB2D_DC_FREE (3 << 2) 526 # define RADEON_RB2D_DC_FLUSH_ALL 0xf 527 # define RADEON_RB2D_DC_BUSY (1 << 31) 528 #define RADEON_RB3D_CNTL 0x1c3c 529 # define RADEON_ALPHA_BLEND_ENABLE (1 << 0) 530 # define RADEON_PLANE_MASK_ENABLE (1 << 1) 531 # define RADEON_DITHER_ENABLE (1 << 2) 532 # define RADEON_ROUND_ENABLE (1 << 3) 533 # define RADEON_SCALE_DITHER_ENABLE (1 << 4) 534 # define RADEON_DITHER_INIT (1 << 5) 535 # define RADEON_ROP_ENABLE (1 << 6) 536 # define RADEON_STENCIL_ENABLE (1 << 7) 537 # define RADEON_Z_ENABLE (1 << 8) 538 # define RADEON_ZBLOCK16 (1 << 15) 539 #define RADEON_RB3D_DEPTHOFFSET 0x1c24 540 #define RADEON_RB3D_DEPTHCLEARVALUE 0x3230 541 #define RADEON_RB3D_DEPTHPITCH 0x1c28 542 #define RADEON_RB3D_PLANEMASK 0x1d84 543 #define RADEON_RB3D_STENCILREFMASK 0x1d7c 544 #define RADEON_RB3D_ZCACHE_MODE 0x3250 545 #define RADEON_RB3D_ZCACHE_CTLSTAT 0x3254 546 # define RADEON_RB3D_ZC_FLUSH (1 << 0) 547 # define RADEON_RB3D_ZC_FREE (1 << 2) 548 # define RADEON_RB3D_ZC_FLUSH_ALL 0x5 549 # define RADEON_RB3D_ZC_BUSY (1 << 31) 550 #define RADEON_RB3D_DSTCACHE_CTLSTAT 0x325c 551 # define RADEON_RB3D_DC_FLUSH (3 << 0) 552 # define RADEON_RB3D_DC_FREE (3 << 2) 553 # define RADEON_RB3D_DC_FLUSH_ALL 0xf 554 # define RADEON_RB3D_DC_BUSY (1 << 31) 555 #define RADEON_RB3D_ZSTENCILCNTL 0x1c2c 556 # define RADEON_Z_TEST_MASK (7 << 4) 557 # define RADEON_Z_TEST_ALWAYS (7 << 4) 558 # define RADEON_Z_HIERARCHY_ENABLE (1 << 8) 559 # define RADEON_STENCIL_TEST_ALWAYS (7 << 12) 560 # define RADEON_STENCIL_S_FAIL_REPLACE (2 << 16) 561 # define RADEON_STENCIL_ZPASS_REPLACE (2 << 20) 562 # define RADEON_STENCIL_ZFAIL_REPLACE (2 << 24) 563 # define RADEON_Z_COMPRESSION_ENABLE (1 << 28) 564 # define RADEON_FORCE_Z_DIRTY (1 << 29) 565 # define RADEON_Z_WRITE_ENABLE (1 << 30) 566 # define RADEON_Z_DECOMPRESSION_ENABLE (1 << 31) 567 #define RADEON_RBBM_SOFT_RESET 0x00f0 568 # define RADEON_SOFT_RESET_CP (1 << 0) 569 # define RADEON_SOFT_RESET_HI (1 << 1) 570 # define RADEON_SOFT_RESET_SE (1 << 2) 571 # define RADEON_SOFT_RESET_RE (1 << 3) 572 # define RADEON_SOFT_RESET_PP (1 << 4) 573 # define RADEON_SOFT_RESET_E2 (1 << 5) 574 # define RADEON_SOFT_RESET_RB (1 << 6) 575 # define RADEON_SOFT_RESET_HDP (1 << 7) 576 #define RADEON_RBBM_STATUS 0x0e40 577 # define RADEON_RBBM_FIFOCNT_MASK 0x007f 578 # define RADEON_RBBM_ACTIVE (1 << 31) 579 #define RADEON_RE_LINE_PATTERN 0x1cd0 580 #define RADEON_RE_MISC 0x26c4 581 #define RADEON_RE_TOP_LEFT 0x26c0 582 #define RADEON_RE_WIDTH_HEIGHT 0x1c44 583 #define RADEON_RE_STIPPLE_ADDR 0x1cc8 584 #define RADEON_RE_STIPPLE_DATA 0x1ccc 585 586 #define RADEON_SCISSOR_TL_0 0x1cd8 587 #define RADEON_SCISSOR_BR_0 0x1cdc 588 #define RADEON_SCISSOR_TL_1 0x1ce0 589 #define RADEON_SCISSOR_BR_1 0x1ce4 590 #define RADEON_SCISSOR_TL_2 0x1ce8 591 #define RADEON_SCISSOR_BR_2 0x1cec 592 #define RADEON_SE_COORD_FMT 0x1c50 593 #define RADEON_SE_CNTL 0x1c4c 594 # define RADEON_FFACE_CULL_CW (0 << 0) 595 # define RADEON_BFACE_SOLID (3 << 1) 596 # define RADEON_FFACE_SOLID (3 << 3) 597 # define RADEON_FLAT_SHADE_VTX_LAST (3 << 6) 598 # define RADEON_DIFFUSE_SHADE_FLAT (1 << 8) 599 # define RADEON_DIFFUSE_SHADE_GOURAUD (2 << 8) 600 # define RADEON_ALPHA_SHADE_FLAT (1 << 10) 601 # define RADEON_ALPHA_SHADE_GOURAUD (2 << 10) 602 # define RADEON_SPECULAR_SHADE_FLAT (1 << 12) 603 # define RADEON_SPECULAR_SHADE_GOURAUD (2 << 12) 604 # define RADEON_FOG_SHADE_FLAT (1 << 14) 605 # define RADEON_FOG_SHADE_GOURAUD (2 << 14) 606 # define RADEON_VPORT_XY_XFORM_ENABLE (1 << 24) 607 # define RADEON_VPORT_Z_XFORM_ENABLE (1 << 25) 608 # define RADEON_VTX_PIX_CENTER_OGL (1 << 27) 609 # define RADEON_ROUND_MODE_TRUNC (0 << 28) 610 # define RADEON_ROUND_PREC_8TH_PIX (1 << 30) 611 #define RADEON_SE_CNTL_STATUS 0x2140 612 #define RADEON_SE_LINE_WIDTH 0x1db8 613 #define RADEON_SE_VPORT_XSCALE 0x1d98 614 #define RADEON_SE_ZBIAS_FACTOR 0x1db0 615 #define RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED 0x2210 616 #define RADEON_SE_TCL_OUTPUT_VTX_FMT 0x2254 617 #define RADEON_SE_TCL_VECTOR_INDX_REG 0x2200 618 # define RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT 16 619 # define RADEON_VEC_INDX_DWORD_COUNT_SHIFT 28 620 #define RADEON_SE_TCL_VECTOR_DATA_REG 0x2204 621 #define RADEON_SE_TCL_SCALAR_INDX_REG 0x2208 622 # define RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT 16 623 #define RADEON_SE_TCL_SCALAR_DATA_REG 0x220C 624 #define RADEON_SURFACE_ACCESS_FLAGS 0x0bf8 625 #define RADEON_SURFACE_ACCESS_CLR 0x0bfc 626 #define RADEON_SURFACE_CNTL 0x0b00 627 # define RADEON_SURF_TRANSLATION_DIS (1 << 8) 628 # define RADEON_NONSURF_AP0_SWP_MASK (3 << 20) 629 # define RADEON_NONSURF_AP0_SWP_LITTLE (0 << 20) 630 # define RADEON_NONSURF_AP0_SWP_BIG16 (1 << 20) 631 # define RADEON_NONSURF_AP0_SWP_BIG32 (2 << 20) 632 # define RADEON_NONSURF_AP1_SWP_MASK (3 << 22) 633 # define RADEON_NONSURF_AP1_SWP_LITTLE (0 << 22) 634 # define RADEON_NONSURF_AP1_SWP_BIG16 (1 << 22) 635 # define RADEON_NONSURF_AP1_SWP_BIG32 (2 << 22) 636 #define RADEON_SURFACE0_INFO 0x0b0c 637 # define RADEON_SURF_PITCHSEL_MASK (0x1ff << 0) 638 # define RADEON_SURF_TILE_MODE_MASK (3 << 16) 639 # define RADEON_SURF_TILE_MODE_MACRO (0 << 16) 640 # define RADEON_SURF_TILE_MODE_MICRO (1 << 16) 641 # define RADEON_SURF_TILE_MODE_32BIT_Z (2 << 16) 642 # define RADEON_SURF_TILE_MODE_16BIT_Z (3 << 16) 643 #define RADEON_SURFACE0_LOWER_BOUND 0x0b04 644 #define RADEON_SURFACE0_UPPER_BOUND 0x0b08 645 # define RADEON_SURF_ADDRESS_FIXED_MASK (0x3ff << 0) 646 #define RADEON_SURFACE1_INFO 0x0b1c 647 #define RADEON_SURFACE1_LOWER_BOUND 0x0b14 648 #define RADEON_SURFACE1_UPPER_BOUND 0x0b18 649 #define RADEON_SURFACE2_INFO 0x0b2c 650 #define RADEON_SURFACE2_LOWER_BOUND 0x0b24 651 #define RADEON_SURFACE2_UPPER_BOUND 0x0b28 652 #define RADEON_SURFACE3_INFO 0x0b3c 653 #define RADEON_SURFACE3_LOWER_BOUND 0x0b34 654 #define RADEON_SURFACE3_UPPER_BOUND 0x0b38 655 #define RADEON_SURFACE4_INFO 0x0b4c 656 #define RADEON_SURFACE4_LOWER_BOUND 0x0b44 657 #define RADEON_SURFACE4_UPPER_BOUND 0x0b48 658 #define RADEON_SURFACE5_INFO 0x0b5c 659 #define RADEON_SURFACE5_LOWER_BOUND 0x0b54 660 #define RADEON_SURFACE5_UPPER_BOUND 0x0b58 661 #define RADEON_SURFACE6_INFO 0x0b6c 662 #define RADEON_SURFACE6_LOWER_BOUND 0x0b64 663 #define RADEON_SURFACE6_UPPER_BOUND 0x0b68 664 #define RADEON_SURFACE7_INFO 0x0b7c 665 #define RADEON_SURFACE7_LOWER_BOUND 0x0b74 666 #define RADEON_SURFACE7_UPPER_BOUND 0x0b78 667 #define RADEON_SW_SEMAPHORE 0x013c 668 669 #define RADEON_WAIT_UNTIL 0x1720 670 # define RADEON_WAIT_CRTC_PFLIP (1 << 0) 671 # define RADEON_WAIT_2D_IDLE (1 << 14) 672 # define RADEON_WAIT_3D_IDLE (1 << 15) 673 # define RADEON_WAIT_2D_IDLECLEAN (1 << 16) 674 # define RADEON_WAIT_3D_IDLECLEAN (1 << 17) 675 # define RADEON_WAIT_HOST_IDLECLEAN (1 << 18) 676 677 #define RADEON_RB3D_ZMASKOFFSET 0x3234 678 #define RADEON_RB3D_ZSTENCILCNTL 0x1c2c 679 # define RADEON_DEPTH_FORMAT_16BIT_INT_Z (0 << 0) 680 # define RADEON_DEPTH_FORMAT_24BIT_INT_Z (2 << 0) 681 682 /* CP registers */ 683 #define RADEON_CP_ME_RAM_ADDR 0x07d4 684 #define RADEON_CP_ME_RAM_RADDR 0x07d8 685 #define RADEON_CP_ME_RAM_DATAH 0x07dc 686 #define RADEON_CP_ME_RAM_DATAL 0x07e0 687 688 #define RADEON_CP_RB_BASE 0x0700 689 #define RADEON_CP_RB_CNTL 0x0704 690 # define RADEON_BUF_SWAP_32BIT (2 << 16) 691 # define RADEON_RB_NO_UPDATE (1 << 27) 692 #define RADEON_CP_RB_RPTR_ADDR 0x070c 693 #define RADEON_CP_RB_RPTR 0x0710 694 #define RADEON_CP_RB_WPTR 0x0714 695 696 #define RADEON_CP_RB_WPTR_DELAY 0x0718 697 # define RADEON_PRE_WRITE_TIMER_SHIFT 0 698 # define RADEON_PRE_WRITE_LIMIT_SHIFT 23 699 700 #define RADEON_CP_IB_BASE 0x0738 701 702 #define RADEON_CP_CSQ_CNTL 0x0740 703 # define RADEON_CSQ_CNT_PRIMARY_MASK (0xff << 0) 704 # define RADEON_CSQ_PRIDIS_INDDIS (0 << 28) 705 # define RADEON_CSQ_PRIPIO_INDDIS (1 << 28) 706 # define RADEON_CSQ_PRIBM_INDDIS (2 << 28) 707 # define RADEON_CSQ_PRIPIO_INDBM (3 << 28) 708 # define RADEON_CSQ_PRIBM_INDBM (4 << 28) 709 # define RADEON_CSQ_PRIPIO_INDPIO (15 << 28) 710 711 #define RADEON_AIC_CNTL 0x01d0 712 # define RADEON_PCIGART_TRANSLATE_EN (1 << 0) 713 #define RADEON_AIC_STAT 0x01d4 714 #define RADEON_AIC_PT_BASE 0x01d8 715 #define RADEON_AIC_LO_ADDR 0x01dc 716 #define RADEON_AIC_HI_ADDR 0x01e0 717 #define RADEON_AIC_TLB_ADDR 0x01e4 718 #define RADEON_AIC_TLB_DATA 0x01e8 719 720 /* CP command packets */ 721 #define RADEON_CP_PACKET0 0x00000000 722 # define RADEON_ONE_REG_WR (1 << 15) 723 #define RADEON_CP_PACKET1 0x40000000 724 #define RADEON_CP_PACKET2 0x80000000 725 #define RADEON_CP_PACKET3 0xC0000000 726 # define RADEON_CP_NOP 0x00001000 727 # define RADEON_CP_NEXT_CHAR 0x00001900 728 # define RADEON_CP_PLY_NEXTSCAN 0x00001D00 729 # define RADEON_CP_SET_SCISSORS 0x00001E00 730 /* GEN_INDX_PRIM is unsupported starting with R300 */ 731 # define RADEON_3D_RNDR_GEN_INDX_PRIM 0x00002300 732 # define RADEON_WAIT_FOR_IDLE 0x00002600 733 # define RADEON_3D_DRAW_VBUF 0x00002800 734 # define RADEON_3D_DRAW_IMMD 0x00002900 735 # define RADEON_3D_DRAW_INDX 0x00002A00 736 # define RADEON_CP_LOAD_PALETTE 0x00002C00 737 # define RADEON_3D_LOAD_VBPNTR 0x00002F00 738 # define RADEON_MPEG_IDCT_MACROBLOCK 0x00003000 739 # define RADEON_MPEG_IDCT_MACROBLOCK_REV 0x00003100 740 # define RADEON_3D_CLEAR_ZMASK 0x00003200 741 # define RADEON_CP_INDX_BUFFER 0x00003300 742 # define RADEON_CP_3D_DRAW_VBUF_2 0x00003400 743 # define RADEON_CP_3D_DRAW_IMMD_2 0x00003500 744 # define RADEON_CP_3D_DRAW_INDX_2 0x00003600 745 # define RADEON_3D_CLEAR_HIZ 0x00003700 746 # define RADEON_CP_3D_CLEAR_CMASK 0x00003802 747 # define RADEON_CNTL_HOSTDATA_BLT 0x00009400 748 # define RADEON_CNTL_PAINT_MULTI 0x00009A00 749 # define RADEON_CNTL_BITBLT_MULTI 0x00009B00 750 # define RADEON_CNTL_SET_SCISSORS 0xC0001E00 751 752 #define RADEON_CP_PACKET_MASK 0xC0000000 753 #define RADEON_CP_PACKET_COUNT_MASK 0x3fff0000 754 #define RADEON_CP_PACKET0_REG_MASK 0x000007ff 755 #define RADEON_CP_PACKET1_REG0_MASK 0x000007ff 756 #define RADEON_CP_PACKET1_REG1_MASK 0x003ff800 757 758 #define RADEON_VTX_Z_PRESENT (1 << 31) 759 #define RADEON_VTX_PKCOLOR_PRESENT (1 << 3) 760 761 #define RADEON_PRIM_TYPE_NONE (0 << 0) 762 #define RADEON_PRIM_TYPE_POINT (1 << 0) 763 #define RADEON_PRIM_TYPE_LINE (2 << 0) 764 #define RADEON_PRIM_TYPE_LINE_STRIP (3 << 0) 765 #define RADEON_PRIM_TYPE_TRI_LIST (4 << 0) 766 #define RADEON_PRIM_TYPE_TRI_FAN (5 << 0) 767 #define RADEON_PRIM_TYPE_TRI_STRIP (6 << 0) 768 #define RADEON_PRIM_TYPE_TRI_TYPE2 (7 << 0) 769 #define RADEON_PRIM_TYPE_RECT_LIST (8 << 0) 770 #define RADEON_PRIM_TYPE_3VRT_POINT_LIST (9 << 0) 771 #define RADEON_PRIM_TYPE_3VRT_LINE_LIST (10 << 0) 772 #define RADEON_PRIM_TYPE_MASK 0xf 773 #define RADEON_PRIM_WALK_IND (1 << 4) 774 #define RADEON_PRIM_WALK_LIST (2 << 4) 775 #define RADEON_PRIM_WALK_RING (3 << 4) 776 #define RADEON_COLOR_ORDER_BGRA (0 << 6) 777 #define RADEON_COLOR_ORDER_RGBA (1 << 6) 778 #define RADEON_MAOS_ENABLE (1 << 7) 779 #define RADEON_VTX_FMT_R128_MODE (0 << 8) 780 #define RADEON_VTX_FMT_RADEON_MODE (1 << 8) 781 #define RADEON_NUM_VERTICES_SHIFT 16 782 783 #define RADEON_COLOR_FORMAT_CI8 2 784 #define RADEON_COLOR_FORMAT_ARGB1555 3 785 #define RADEON_COLOR_FORMAT_RGB565 4 786 #define RADEON_COLOR_FORMAT_ARGB8888 6 787 #define RADEON_COLOR_FORMAT_RGB332 7 788 #define RADEON_COLOR_FORMAT_RGB8 9 789 #define RADEON_COLOR_FORMAT_ARGB4444 15 790 791 #define RADEON_TXFORMAT_I8 0 792 #define RADEON_TXFORMAT_AI88 1 793 #define RADEON_TXFORMAT_RGB332 2 794 #define RADEON_TXFORMAT_ARGB1555 3 795 #define RADEON_TXFORMAT_RGB565 4 796 #define RADEON_TXFORMAT_ARGB4444 5 797 #define RADEON_TXFORMAT_ARGB8888 6 798 #define RADEON_TXFORMAT_RGBA8888 7 799 #define RADEON_TXFORMAT_Y8 8 800 #define RADEON_TXFORMAT_VYUY422 10 801 #define RADEON_TXFORMAT_YVYU422 11 802 #define RADEON_TXFORMAT_DXT1 12 803 #define RADEON_TXFORMAT_DXT23 14 804 #define RADEON_TXFORMAT_DXT45 15 805 806 #define R200_PP_TXCBLEND_0 0x2f00 807 #define R200_PP_TXCBLEND_1 0x2f10 808 #define R200_PP_TXCBLEND_2 0x2f20 809 #define R200_PP_TXCBLEND_3 0x2f30 810 #define R200_PP_TXCBLEND_4 0x2f40 811 #define R200_PP_TXCBLEND_5 0x2f50 812 #define R200_PP_TXCBLEND_6 0x2f60 813 #define R200_PP_TXCBLEND_7 0x2f70 814 #define R200_SE_TCL_LIGHT_MODEL_CTL_0 0x2268 815 #define R200_PP_TFACTOR_0 0x2ee0 816 #define R200_SE_VTX_FMT_0 0x2088 817 #define R200_SE_VAP_CNTL 0x2080 818 #define R200_SE_TCL_MATRIX_SEL_0 0x2230 819 #define R200_SE_TCL_TEX_PROC_CTL_2 0x22a8 820 #define R200_SE_TCL_UCP_VERT_BLEND_CTL 0x22c0 821 #define R200_PP_TXFILTER_5 0x2ca0 822 #define R200_PP_TXFILTER_4 0x2c80 823 #define R200_PP_TXFILTER_3 0x2c60 824 #define R200_PP_TXFILTER_2 0x2c40 825 #define R200_PP_TXFILTER_1 0x2c20 826 #define R200_PP_TXFILTER_0 0x2c00 827 #define R200_PP_TXOFFSET_5 0x2d78 828 #define R200_PP_TXOFFSET_4 0x2d60 829 #define R200_PP_TXOFFSET_3 0x2d48 830 #define R200_PP_TXOFFSET_2 0x2d30 831 #define R200_PP_TXOFFSET_1 0x2d18 832 #define R200_PP_TXOFFSET_0 0x2d00 833 834 #define R200_PP_CUBIC_FACES_0 0x2c18 835 #define R200_PP_CUBIC_FACES_1 0x2c38 836 #define R200_PP_CUBIC_FACES_2 0x2c58 837 #define R200_PP_CUBIC_FACES_3 0x2c78 838 #define R200_PP_CUBIC_FACES_4 0x2c98 839 #define R200_PP_CUBIC_FACES_5 0x2cb8 840 #define R200_PP_CUBIC_OFFSET_F1_0 0x2d04 841 #define R200_PP_CUBIC_OFFSET_F2_0 0x2d08 842 #define R200_PP_CUBIC_OFFSET_F3_0 0x2d0c 843 #define R200_PP_CUBIC_OFFSET_F4_0 0x2d10 844 #define R200_PP_CUBIC_OFFSET_F5_0 0x2d14 845 #define R200_PP_CUBIC_OFFSET_F1_1 0x2d1c 846 #define R200_PP_CUBIC_OFFSET_F2_1 0x2d20 847 #define R200_PP_CUBIC_OFFSET_F3_1 0x2d24 848 #define R200_PP_CUBIC_OFFSET_F4_1 0x2d28 849 #define R200_PP_CUBIC_OFFSET_F5_1 0x2d2c 850 #define R200_PP_CUBIC_OFFSET_F1_2 0x2d34 851 #define R200_PP_CUBIC_OFFSET_F2_2 0x2d38 852 #define R200_PP_CUBIC_OFFSET_F3_2 0x2d3c 853 #define R200_PP_CUBIC_OFFSET_F4_2 0x2d40 854 #define R200_PP_CUBIC_OFFSET_F5_2 0x2d44 855 #define R200_PP_CUBIC_OFFSET_F1_3 0x2d4c 856 #define R200_PP_CUBIC_OFFSET_F2_3 0x2d50 857 #define R200_PP_CUBIC_OFFSET_F3_3 0x2d54 858 #define R200_PP_CUBIC_OFFSET_F4_3 0x2d58 859 #define R200_PP_CUBIC_OFFSET_F5_3 0x2d5c 860 #define R200_PP_CUBIC_OFFSET_F1_4 0x2d64 861 #define R200_PP_CUBIC_OFFSET_F2_4 0x2d68 862 #define R200_PP_CUBIC_OFFSET_F3_4 0x2d6c 863 #define R200_PP_CUBIC_OFFSET_F4_4 0x2d70 864 #define R200_PP_CUBIC_OFFSET_F5_4 0x2d74 865 #define R200_PP_CUBIC_OFFSET_F1_5 0x2d7c 866 #define R200_PP_CUBIC_OFFSET_F2_5 0x2d80 867 #define R200_PP_CUBIC_OFFSET_F3_5 0x2d84 868 #define R200_PP_CUBIC_OFFSET_F4_5 0x2d88 869 #define R200_PP_CUBIC_OFFSET_F5_5 0x2d8c 870 871 #define R200_RE_AUX_SCISSOR_CNTL 0x26f0 872 #define R200_SE_VTE_CNTL 0x20b0 873 #define R200_SE_TCL_OUTPUT_VTX_COMP_SEL 0x2250 874 #define R200_PP_TAM_DEBUG3 0x2d9c 875 #define R200_PP_CNTL_X 0x2cc4 876 #define R200_SE_VAP_CNTL_STATUS 0x2140 877 #define R200_RE_SCISSOR_TL_0 0x1cd8 878 #define R200_RE_SCISSOR_TL_1 0x1ce0 879 #define R200_RE_SCISSOR_TL_2 0x1ce8 880 #define R200_RB3D_DEPTHXY_OFFSET 0x1d60 881 #define R200_RE_AUX_SCISSOR_CNTL 0x26f0 882 #define R200_SE_VTX_STATE_CNTL 0x2180 883 #define R200_RE_POINTSIZE 0x2648 884 #define R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0 0x2254 885 886 #define RADEON_PP_TEX_SIZE_0 0x1d04 /* NPOT */ 887 #define RADEON_PP_TEX_SIZE_1 0x1d0c 888 #define RADEON_PP_TEX_SIZE_2 0x1d14 889 890 #define RADEON_PP_CUBIC_FACES_0 0x1d24 891 #define RADEON_PP_CUBIC_FACES_1 0x1d28 892 #define RADEON_PP_CUBIC_FACES_2 0x1d2c 893 #define RADEON_PP_CUBIC_OFFSET_T0_0 0x1dd0 /* bits [31:5] */ 894 #define RADEON_PP_CUBIC_OFFSET_T1_0 0x1e00 895 #define RADEON_PP_CUBIC_OFFSET_T2_0 0x1e14 896 897 #define RADEON_SE_TCL_STATE_FLUSH 0x2284 898 899 #define SE_VAP_CNTL__TCL_ENA_MASK 0x00000001 900 #define SE_VAP_CNTL__FORCE_W_TO_ONE_MASK 0x00010000 901 #define SE_VAP_CNTL__VF_MAX_VTX_NUM__SHIFT 0x00000012 902 #define SE_VTE_CNTL__VTX_XY_FMT_MASK 0x00000100 903 #define SE_VTE_CNTL__VTX_Z_FMT_MASK 0x00000200 904 #define SE_VTX_FMT_0__VTX_Z0_PRESENT_MASK 0x00000001 905 #define SE_VTX_FMT_0__VTX_W0_PRESENT_MASK 0x00000002 906 #define SE_VTX_FMT_0__VTX_COLOR_0_FMT__SHIFT 0x0000000b 907 #define R200_3D_DRAW_IMMD_2 0xC0003500 908 #define R200_SE_VTX_FMT_1 0x208c 909 #define R200_RE_CNTL 0x1c50 910 911 #define R200_RB3D_BLENDCOLOR 0x3218 912 913 #define R200_SE_TCL_POINT_SPRITE_CNTL 0x22c4 914 915 #define R200_PP_TRI_PERF 0x2cf8 916 917 #define R200_PP_AFS_0 0x2f80 918 #define R200_PP_AFS_1 0x2f00 /* same as txcblend_0 */ 919 920 #define R200_VAP_PVS_CNTL_1 0x22D0 921 922 /* MPEG settings from VHA code */ 923 #define RADEON_VHA_SETTO16_1 0x2694 924 #define RADEON_VHA_SETTO16_2 0x2680 925 #define RADEON_VHA_SETTO0_1 0x1840 926 #define RADEON_VHA_FB_OFFSET 0x19e4 927 #define RADEON_VHA_SETTO1AND70S 0x19d8 928 #define RADEON_VHA_DST_PITCH 0x1408 929 930 // set as reference header 931 #define RADEON_VHA_BACKFRAME0_OFF_Y 0x1840 932 #define RADEON_VHA_BACKFRAME1_OFF_PITCH_Y 0x1844 933 #define RADEON_VHA_BACKFRAME0_OFF_U 0x1848 934 #define RADEON_VHA_BACKFRAME1_OFF_PITCH_U 0x184c 935 #define RADOEN_VHA_BACKFRAME0_OFF_V 0x1850 936 #define RADEON_VHA_BACKFRAME1_OFF_PITCH_V 0x1854 937 #define RADEON_VHA_FORWFRAME0_OFF_Y 0x1858 938 #define RADEON_VHA_FORWFRAME1_OFF_PITCH_Y 0x185c 939 #define RADEON_VHA_FORWFRAME0_OFF_U 0x1860 940 #define RADEON_VHA_FORWFRAME1_OFF_PITCH_U 0x1864 941 #define RADEON_VHA_FORWFRAME0_OFF_V 0x1868 942 #define RADEON_VHA_FORWFRAME0_OFF_PITCH_V 0x1880 943 #define RADEON_VHA_BACKFRAME0_OFF_Y_2 0x1884 944 #define RADEON_VHA_BACKFRAME1_OFF_PITCH_Y_2 0x1888 945 #define RADEON_VHA_BACKFRAME0_OFF_U_2 0x188c 946 #define RADEON_VHA_BACKFRAME1_OFF_PITCH_U_2 0x1890 947 #define RADEON_VHA_BACKFRAME0_OFF_V_2 0x1894 948 #define RADEON_VHA_BACKFRAME1_OFF_PITCH_V_2 0x1898 949 950 951 952 /* Constants */ 953 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 954 955 #define RADEON_LAST_FRAME_REG RADEON_SCRATCH_REG0 956 #define RADEON_LAST_DISPATCH_REG RADEON_SCRATCH_REG1 957 #define RADEON_LAST_CLEAR_REG RADEON_SCRATCH_REG2 958 #define RADEON_LAST_SWI_REG RADEON_SCRATCH_REG3 959 #define RADEON_LAST_DISPATCH 1 960 961 #define RADEON_MAX_VB_AGE 0x7fffffff 962 #define RADEON_MAX_VB_VERTS (0xffff) 963 964 #define RADEON_RING_HIGH_MARK 128 965 966 #define RADEON_PCIGART_TABLE_SIZE (32*1024) 967 968 #define RADEON_READ(reg) DRM_READ32( dev_priv->mmio, (reg) ) 969 #define RADEON_WRITE(reg,val) DRM_WRITE32( dev_priv->mmio, (reg), (val) ) 970 #define RADEON_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) ) 971 #define RADEON_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) ) 972 973 #define RADEON_WRITE_PLL( addr, val ) \ 974 do { \ 975 RADEON_WRITE8( RADEON_CLOCK_CNTL_INDEX, \ 976 ((addr) & 0x1f) | RADEON_PLL_WR_EN ); \ 977 RADEON_WRITE( RADEON_CLOCK_CNTL_DATA, (val) ); \ 978 } while (0) 979 980 #define RADEON_WRITE_PCIE( addr, val ) \ 981 do { \ 982 RADEON_WRITE8( RADEON_PCIE_INDEX, \ 983 ((addr) & 0xff)); \ 984 RADEON_WRITE( RADEON_PCIE_DATA, (val) ); \ 985 } while (0) 986 987 #define CP_PACKET0( reg, n ) \ 988 (RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2)) 989 #define CP_PACKET0_TABLE( reg, n ) \ 990 (RADEON_CP_PACKET0 | RADEON_ONE_REG_WR | ((n) << 16) | ((reg) >> 2)) 991 #define CP_PACKET1( reg0, reg1 ) \ 992 (RADEON_CP_PACKET1 | (((reg1) >> 2) << 15) | ((reg0) >> 2)) 993 #define CP_PACKET2() \ 994 (RADEON_CP_PACKET2) 995 #define CP_PACKET3( pkt, n ) \ 996 (RADEON_CP_PACKET3 | (pkt) | ((n) << 16)) 997 998 /* ================================================================ 999 * Engine control helper macros 1000 */ 1001 1002 #define RADEON_WAIT_UNTIL_2D_IDLE() do { \ 1003 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ 1004 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \ 1005 RADEON_WAIT_HOST_IDLECLEAN) ); \ 1006 } while (0) 1007 1008 #define RADEON_WAIT_UNTIL_3D_IDLE() do { \ 1009 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ 1010 OUT_RING( (RADEON_WAIT_3D_IDLECLEAN | \ 1011 RADEON_WAIT_HOST_IDLECLEAN) ); \ 1012 } while (0) 1013 1014 #define RADEON_WAIT_UNTIL_IDLE() do { \ 1015 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ 1016 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \ 1017 RADEON_WAIT_3D_IDLECLEAN | \ 1018 RADEON_WAIT_HOST_IDLECLEAN) ); \ 1019 } while (0) 1020 1021 #define RADEON_WAIT_UNTIL_PAGE_FLIPPED() do { \ 1022 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ 1023 OUT_RING( RADEON_WAIT_CRTC_PFLIP ); \ 1024 } while (0) 1025 1026 #define RADEON_FLUSH_CACHE() do { \ 1027 OUT_RING( CP_PACKET0( RADEON_RB3D_DSTCACHE_CTLSTAT, 0 ) ); \ 1028 OUT_RING( RADEON_RB3D_DC_FLUSH ); \ 1029 } while (0) 1030 1031 #define RADEON_PURGE_CACHE() do { \ 1032 OUT_RING( CP_PACKET0( RADEON_RB3D_DSTCACHE_CTLSTAT, 0 ) ); \ 1033 OUT_RING( RADEON_RB3D_DC_FLUSH_ALL ); \ 1034 } while (0) 1035 1036 #define RADEON_FLUSH_ZCACHE() do { \ 1037 OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) ); \ 1038 OUT_RING( RADEON_RB3D_ZC_FLUSH ); \ 1039 } while (0) 1040 1041 #define RADEON_PURGE_ZCACHE() do { \ 1042 OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) ); \ 1043 OUT_RING( RADEON_RB3D_ZC_FLUSH_ALL ); \ 1044 } while (0) 1045 1046 /* ================================================================ 1047 * Misc helper macros 1048 */ 1049 1050 /* Perfbox functionality only. 1051 */ 1052 #define RING_SPACE_TEST_WITH_RETURN( dev_priv ) \ 1053 do { \ 1054 if (!(dev_priv->stats.boxes & RADEON_BOX_DMA_IDLE)) { \ 1055 u32 head = GET_RING_HEAD( dev_priv ); \ 1056 if (head == dev_priv->ring.tail) \ 1057 dev_priv->stats.boxes |= RADEON_BOX_DMA_IDLE; \ 1058 } \ 1059 } while (0) 1060 1061 #define VB_AGE_TEST_WITH_RETURN( dev_priv ) \ 1062 do { \ 1063 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; \ 1064 if ( sarea_priv->last_dispatch >= RADEON_MAX_VB_AGE ) { \ 1065 int __ret = radeon_do_cp_idle( dev_priv ); \ 1066 if ( __ret ) return __ret; \ 1067 sarea_priv->last_dispatch = 0; \ 1068 radeon_freelist_reset( dev ); \ 1069 } \ 1070 } while (0) 1071 1072 #define RADEON_DISPATCH_AGE( age ) do { \ 1073 OUT_RING( CP_PACKET0( RADEON_LAST_DISPATCH_REG, 0 ) ); \ 1074 OUT_RING( age ); \ 1075 } while (0) 1076 1077 #define RADEON_FRAME_AGE( age ) do { \ 1078 OUT_RING( CP_PACKET0( RADEON_LAST_FRAME_REG, 0 ) ); \ 1079 OUT_RING( age ); \ 1080 } while (0) 1081 1082 #define RADEON_CLEAR_AGE( age ) do { \ 1083 OUT_RING( CP_PACKET0( RADEON_LAST_CLEAR_REG, 0 ) ); \ 1084 OUT_RING( age ); \ 1085 } while (0) 1086 1087 /* ================================================================ 1088 * Ring control 1089 */ 1090 1091 #define RADEON_VERBOSE 0 1092 1093 #define RING_LOCALS int write, _nr; unsigned int mask; u32 *ring; 1094 1095 #define BEGIN_RING( n ) do { \ 1096 if ( RADEON_VERBOSE ) { \ 1097 DRM_INFO( "BEGIN_RING( %d ) in %s\n", \ 1098 n, __FUNCTION__ ); \ 1099 } \ 1100 if ( dev_priv->ring.space <= (n) * sizeof(u32) ) { \ 1101 COMMIT_RING(); \ 1102 radeon_wait_ring( dev_priv, (n) * sizeof(u32) ); \ 1103 } \ 1104 _nr = n; dev_priv->ring.space -= (n) * sizeof(u32); \ 1105 ring = dev_priv->ring.start; \ 1106 write = dev_priv->ring.tail; \ 1107 mask = dev_priv->ring.tail_mask; \ 1108 } while (0) 1109 1110 #define ADVANCE_RING() do { \ 1111 if ( RADEON_VERBOSE ) { \ 1112 DRM_INFO( "ADVANCE_RING() wr=0x%06x tail=0x%06x\n", \ 1113 write, dev_priv->ring.tail ); \ 1114 } \ 1115 if (((dev_priv->ring.tail + _nr) & mask) != write) { \ 1116 DRM_ERROR( \ 1117 "ADVANCE_RING(): mismatch: nr: %x write: %x line: %d\n", \ 1118 ((dev_priv->ring.tail + _nr) & mask), \ 1119 write, __LINE__); \ 1120 } else \ 1121 dev_priv->ring.tail = write; \ 1122 } while (0) 1123 1124 #define COMMIT_RING() do { \ 1125 /* Flush writes to ring */ \ 1126 DRM_MEMORYBARRIER(); \ 1127 GET_RING_HEAD( dev_priv ); \ 1128 RADEON_WRITE( RADEON_CP_RB_WPTR, dev_priv->ring.tail ); \ 1129 /* read from PCI bus to ensure correct posting */ \ 1130 RADEON_READ( RADEON_CP_RB_RPTR ); \ 1131 } while (0) 1132 1133 #define OUT_RING( x ) do { \ 1134 if ( RADEON_VERBOSE ) { \ 1135 DRM_INFO( " OUT_RING( 0x%08x ) at 0x%x\n", \ 1136 (unsigned int)(x), write ); \ 1137 } \ 1138 ring[write++] = (x); \ 1139 write &= mask; \ 1140 } while (0) 1141 1142 #define OUT_RING_REG( reg, val ) do { \ 1143 OUT_RING( CP_PACKET0( reg, 0 ) ); \ 1144 OUT_RING( val ); \ 1145 } while (0) 1146 1147 #define OUT_RING_TABLE( tab, sz ) do { \ 1148 int _size = (sz); \ 1149 int *_tab = (int *)(tab); \ 1150 \ 1151 if (write + _size > mask) { \ 1152 int _i = (mask+1) - write; \ 1153 _size -= _i; \ 1154 while (_i > 0) { \ 1155 *(int *)(ring + write) = *_tab++; \ 1156 write++; \ 1157 _i--; \ 1158 } \ 1159 write = 0; \ 1160 _tab += _i; \ 1161 } \ 1162 while (_size > 0) { \ 1163 *(ring + write) = *_tab++; \ 1164 write++; \ 1165 _size--; \ 1166 } \ 1167 write &= mask; \ 1168 } while (0) 1169 1170 #endif /* __RADEON_DRV_H__ */
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