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sys/dev/drm/radeon_drv.h
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1 /* radeon_drv.h -- Private header for radeon driver -*- linux-c -*- 2 * 3 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. 4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California. 5 * All rights reserved. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the "Software"), 9 * to deal in the Software without restriction, including without limitation 10 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 11 * and/or sell copies of the Software, and to permit persons to whom the 12 * Software is furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice (including the next 15 * paragraph) shall be included in all copies or substantial portions of the 16 * Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 24 * DEALINGS IN THE SOFTWARE. 25 * 26 * Authors: 27 * Kevin E. Martin <martin@valinux.com> 28 * Gareth Hughes <gareth@valinux.com> 29 */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD: releng/9.0/sys/dev/drm/radeon_drv.h 197605 2009-09-28 22:40:29Z rnoland $"); 33 34 #ifndef __RADEON_DRV_H__ 35 #define __RADEON_DRV_H__ 36 37 /* General customization: 38 */ 39 40 #define DRIVER_AUTHOR "Gareth Hughes, Keith Whitwell, others." 41 42 #define DRIVER_NAME "radeon" 43 #define DRIVER_DESC "ATI Radeon" 44 #define DRIVER_DATE "20080613" 45 46 /* Interface history: 47 * 48 * 1.1 - ?? 49 * 1.2 - Add vertex2 ioctl (keith) 50 * - Add stencil capability to clear ioctl (gareth, keith) 51 * - Increase MAX_TEXTURE_LEVELS (brian) 52 * 1.3 - Add cmdbuf ioctl (keith) 53 * - Add support for new radeon packets (keith) 54 * - Add getparam ioctl (keith) 55 * - Add flip-buffers ioctl, deprecate fullscreen foo (keith). 56 * 1.4 - Add scratch registers to get_param ioctl. 57 * 1.5 - Add r200 packets to cmdbuf ioctl 58 * - Add r200 function to init ioctl 59 * - Add 'scalar2' instruction to cmdbuf 60 * 1.6 - Add static GART memory manager 61 * Add irq handler (won't be turned on unless X server knows to) 62 * Add irq ioctls and irq_active getparam. 63 * Add wait command for cmdbuf ioctl 64 * Add GART offset query for getparam 65 * 1.7 - Add support for cube map registers: R200_PP_CUBIC_FACES_[0..5] 66 * and R200_PP_CUBIC_OFFSET_F1_[0..5]. 67 * Added packets R200_EMIT_PP_CUBIC_FACES_[0..5] and 68 * R200_EMIT_PP_CUBIC_OFFSETS_[0..5]. (brian) 69 * 1.8 - Remove need to call cleanup ioctls on last client exit (keith) 70 * Add 'GET' queries for starting additional clients on different VT's. 71 * 1.9 - Add DRM_IOCTL_RADEON_CP_RESUME ioctl. 72 * Add texture rectangle support for r100. 73 * 1.10- Add SETPARAM ioctl; first parameter to set is FB_LOCATION, which 74 * clients use to tell the DRM where they think the framebuffer is 75 * located in the card's address space 76 * 1.11- Add packet R200_EMIT_RB3D_BLENDCOLOR to support GL_EXT_blend_color 77 * and GL_EXT_blend_[func|equation]_separate on r200 78 * 1.12- Add R300 CP microcode support - this just loads the CP on r300 79 * (No 3D support yet - just microcode loading). 80 * 1.13- Add packet R200_EMIT_TCL_POINT_SPRITE_CNTL for ARB_point_parameters 81 * - Add hyperz support, add hyperz flags to clear ioctl. 82 * 1.14- Add support for color tiling 83 * - Add R100/R200 surface allocation/free support 84 * 1.15- Add support for texture micro tiling 85 * - Add support for r100 cube maps 86 * 1.16- Add R200_EMIT_PP_TRI_PERF_CNTL packet to support brilinear 87 * texture filtering on r200 88 * 1.17- Add initial support for R300 (3D). 89 * 1.18- Add support for GL_ATI_fragment_shader, new packets 90 * R200_EMIT_PP_AFS_0/1, R200_EMIT_PP_TXCTLALL_0-5 (replaces 91 * R200_EMIT_PP_TXFILTER_0-5, 2 more regs) and R200_EMIT_ATF_TFACTOR 92 * (replaces R200_EMIT_TFACTOR_0 (8 consts instead of 6) 93 * 1.19- Add support for gart table in FB memory and PCIE r300 94 * 1.20- Add support for r300 texrect 95 * 1.21- Add support for card type getparam 96 * 1.22- Add support for texture cache flushes (R300_TX_CNTL) 97 * 1.23- Add new radeon memory map work from benh 98 * 1.24- Add general-purpose packet for manipulating scratch registers (r300) 99 * 1.25- Add support for r200 vertex programs (R200_EMIT_VAP_PVS_CNTL, 100 * new packet type) 101 * 1.26- Add support for variable size PCI(E) gart aperture 102 * 1.27- Add support for IGP GART 103 * 1.28- Add support for VBL on CRTC2 104 * 1.29- R500 3D cmd buffer support 105 * 1.30- Add support for occlusion queries 106 * 1.31- Add support for num Z pipes from GET_PARAM 107 */ 108 #define DRIVER_MAJOR 1 109 #define DRIVER_MINOR 31 110 #define DRIVER_PATCHLEVEL 0 111 112 /* 113 * Radeon chip families 114 */ 115 enum radeon_family { 116 CHIP_R100, 117 CHIP_RV100, 118 CHIP_RS100, 119 CHIP_RV200, 120 CHIP_RS200, 121 CHIP_R200, 122 CHIP_RV250, 123 CHIP_RS300, 124 CHIP_RV280, 125 CHIP_R300, 126 CHIP_R350, 127 CHIP_RV350, 128 CHIP_RV380, 129 CHIP_R420, 130 CHIP_R423, 131 CHIP_RV410, 132 CHIP_RS400, 133 CHIP_RS480, 134 CHIP_RS600, 135 CHIP_RS690, 136 CHIP_RS740, 137 CHIP_RV515, 138 CHIP_R520, 139 CHIP_RV530, 140 CHIP_RV560, 141 CHIP_RV570, 142 CHIP_R580, 143 CHIP_R600, 144 CHIP_RV610, 145 CHIP_RV630, 146 CHIP_RV670, 147 CHIP_RV620, 148 CHIP_RV635, 149 CHIP_RS780, 150 CHIP_RS880, 151 CHIP_RV770, 152 CHIP_RV730, 153 CHIP_RV710, 154 CHIP_RV740, 155 CHIP_LAST, 156 }; 157 158 enum radeon_cp_microcode_version { 159 UCODE_R100, 160 UCODE_R200, 161 UCODE_R300, 162 }; 163 164 /* 165 * Chip flags 166 */ 167 enum radeon_chip_flags { 168 RADEON_FAMILY_MASK = 0x0000ffffUL, 169 RADEON_FLAGS_MASK = 0xffff0000UL, 170 RADEON_IS_MOBILITY = 0x00010000UL, 171 RADEON_IS_IGP = 0x00020000UL, 172 RADEON_SINGLE_CRTC = 0x00040000UL, 173 RADEON_IS_AGP = 0x00080000UL, 174 RADEON_HAS_HIERZ = 0x00100000UL, 175 RADEON_IS_PCIE = 0x00200000UL, 176 RADEON_NEW_MEMMAP = 0x00400000UL, 177 RADEON_IS_PCI = 0x00800000UL, 178 RADEON_IS_IGPGART = 0x01000000UL, 179 }; 180 181 typedef struct drm_radeon_freelist { 182 unsigned int age; 183 struct drm_buf *buf; 184 struct drm_radeon_freelist *next; 185 struct drm_radeon_freelist *prev; 186 } drm_radeon_freelist_t; 187 188 typedef struct drm_radeon_ring_buffer { 189 u32 *start; 190 u32 *end; 191 int size; 192 int size_l2qw; 193 194 int rptr_update; /* Double Words */ 195 int rptr_update_l2qw; /* log2 Quad Words */ 196 197 int fetch_size; /* Double Words */ 198 int fetch_size_l2ow; /* log2 Oct Words */ 199 200 u32 tail; 201 u32 tail_mask; 202 int space; 203 204 int high_mark; 205 } drm_radeon_ring_buffer_t; 206 207 typedef struct drm_radeon_depth_clear_t { 208 u32 rb3d_cntl; 209 u32 rb3d_zstencilcntl; 210 u32 se_cntl; 211 } drm_radeon_depth_clear_t; 212 213 struct drm_radeon_driver_file_fields { 214 int64_t radeon_fb_delta; 215 }; 216 217 struct mem_block { 218 struct mem_block *next; 219 struct mem_block *prev; 220 int start; 221 int size; 222 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */ 223 }; 224 225 struct radeon_surface { 226 int refcount; 227 u32 lower; 228 u32 upper; 229 u32 flags; 230 }; 231 232 struct radeon_virt_surface { 233 int surface_index; 234 u32 lower; 235 u32 upper; 236 u32 flags; 237 struct drm_file *file_priv; 238 #define PCIGART_FILE_PRIV ((void *) -1L) 239 }; 240 241 struct drm_radeon_kernel_chunk { 242 uint32_t chunk_id; 243 uint32_t length_dw; 244 uint32_t __user *chunk_data; 245 uint32_t *kdata; 246 }; 247 248 struct drm_radeon_cs_parser { 249 struct drm_device *dev; 250 struct drm_file *file_priv; 251 uint32_t num_chunks; 252 struct drm_radeon_kernel_chunk *chunks; 253 int ib_index; 254 int reloc_index; 255 uint32_t card_offset; 256 void *ib; 257 }; 258 259 /* command submission struct */ 260 struct drm_radeon_cs_priv { 261 struct mtx cs_mutex; 262 uint32_t id_wcnt; 263 uint32_t id_scnt; 264 uint32_t id_last_wcnt; 265 uint32_t id_last_scnt; 266 267 int (*parse)(struct drm_radeon_cs_parser *parser); 268 void (*id_emit)(struct drm_radeon_cs_parser *parser, uint32_t *id); 269 uint32_t (*id_last_get)(struct drm_device *dev); 270 /* this ib handling callback are for hidding memory manager drm 271 * from memory manager less drm, free have to emit ib discard 272 * sequence into the ring */ 273 int (*ib_get)(struct drm_radeon_cs_parser *parser); 274 uint32_t (*ib_get_ptr)(struct drm_device *dev, void *ib); 275 void (*ib_free)(struct drm_radeon_cs_parser *parser, int error); 276 /* do a relocation either MM or non-MM */ 277 int (*relocate)(struct drm_radeon_cs_parser *parser, 278 uint32_t *reloc, uint64_t *offset); 279 }; 280 281 #define RADEON_FLUSH_EMITED (1 << 0) 282 #define RADEON_PURGE_EMITED (1 << 1) 283 284 typedef struct drm_radeon_private { 285 drm_radeon_ring_buffer_t ring; 286 drm_radeon_sarea_t *sarea_priv; 287 288 u32 fb_location; 289 u32 fb_size; 290 int new_memmap; 291 292 int gart_size; 293 u32 gart_vm_start; 294 unsigned long gart_buffers_offset; 295 296 int cp_mode; 297 int cp_running; 298 299 drm_radeon_freelist_t *head; 300 drm_radeon_freelist_t *tail; 301 int last_buf; 302 int writeback_works; 303 304 int usec_timeout; 305 306 int microcode_version; 307 308 struct { 309 u32 boxes; 310 int freelist_timeouts; 311 int freelist_loops; 312 int requested_bufs; 313 int last_frame_reads; 314 int last_clear_reads; 315 int clears; 316 int texture_uploads; 317 } stats; 318 319 int do_boxes; 320 int page_flipping; 321 322 u32 color_fmt; 323 unsigned int front_offset; 324 unsigned int front_pitch; 325 unsigned int back_offset; 326 unsigned int back_pitch; 327 328 u32 depth_fmt; 329 unsigned int depth_offset; 330 unsigned int depth_pitch; 331 332 u32 front_pitch_offset; 333 u32 back_pitch_offset; 334 u32 depth_pitch_offset; 335 336 drm_radeon_depth_clear_t depth_clear; 337 338 unsigned long ring_offset; 339 unsigned long ring_rptr_offset; 340 unsigned long buffers_offset; 341 unsigned long gart_textures_offset; 342 343 drm_local_map_t *sarea; 344 drm_local_map_t *cp_ring; 345 drm_local_map_t *ring_rptr; 346 drm_local_map_t *gart_textures; 347 348 struct mem_block *gart_heap; 349 struct mem_block *fb_heap; 350 351 /* SW interrupt */ 352 wait_queue_head_t swi_queue; 353 atomic_t swi_emitted; 354 int vblank_crtc; 355 uint32_t irq_enable_reg; 356 int irq_enabled; 357 uint32_t r500_disp_irq_reg; 358 359 struct radeon_surface surfaces[RADEON_MAX_SURFACES]; 360 struct radeon_virt_surface virt_surfaces[2 * RADEON_MAX_SURFACES]; 361 362 unsigned long pcigart_offset; 363 unsigned int pcigart_offset_set; 364 struct drm_ati_pcigart_info gart_info; 365 366 u32 scratch_ages[5]; 367 368 /* starting from here on, data is preserved accross an open */ 369 uint32_t flags; /* see radeon_chip_flags */ 370 unsigned long fb_aper_offset; 371 372 int num_gb_pipes; 373 int num_z_pipes; 374 int track_flush; 375 drm_local_map_t *mmio; 376 377 /* r6xx/r7xx pipe/shader config */ 378 int r600_max_pipes; 379 int r600_max_tile_pipes; 380 int r600_max_simds; 381 int r600_max_backends; 382 int r600_max_gprs; 383 int r600_max_threads; 384 int r600_max_stack_entries; 385 int r600_max_hw_contexts; 386 int r600_max_gs_threads; 387 int r600_sx_max_export_size; 388 int r600_sx_max_export_pos_size; 389 int r600_sx_max_export_smx_size; 390 int r600_sq_num_cf_insts; 391 int r700_sx_num_of_sets; 392 int r700_sc_prim_fifo_size; 393 int r700_sc_hiz_tile_fifo_size; 394 int r700_sc_earlyz_tile_fifo_fize; 395 /* r6xx/r7xx drm blit vertex buffer */ 396 struct drm_buf *blit_vb; 397 398 /* CS */ 399 struct drm_radeon_cs_priv cs; 400 struct drm_buf *cs_buf; 401 402 } drm_radeon_private_t; 403 404 typedef struct drm_radeon_buf_priv { 405 u32 age; 406 } drm_radeon_buf_priv_t; 407 408 typedef struct drm_radeon_kcmd_buffer { 409 int bufsz; 410 char *buf; 411 int nbox; 412 struct drm_clip_rect __user *boxes; 413 } drm_radeon_kcmd_buffer_t; 414 415 extern int radeon_no_wb; 416 extern struct drm_ioctl_desc radeon_ioctls[]; 417 extern int radeon_max_ioctl; 418 419 extern u32 radeon_get_ring_head(drm_radeon_private_t *dev_priv); 420 extern void radeon_set_ring_head(drm_radeon_private_t *dev_priv, u32 val); 421 422 #define GET_RING_HEAD(dev_priv) radeon_get_ring_head(dev_priv) 423 #define SET_RING_HEAD(dev_priv, val) radeon_set_ring_head(dev_priv, val) 424 425 /* Check whether the given hardware address is inside the framebuffer or the 426 * GART area. 427 */ 428 static __inline__ int radeon_check_offset(drm_radeon_private_t *dev_priv, 429 u64 off) 430 { 431 u64 fb_start = dev_priv->fb_location; 432 u64 fb_end = fb_start + dev_priv->fb_size - 1; 433 u64 gart_start = dev_priv->gart_vm_start; 434 u64 gart_end = gart_start + dev_priv->gart_size - 1; 435 436 return ((off >= fb_start && off <= fb_end) || 437 (off >= gart_start && off <= gart_end)); 438 } 439 440 /* radeon_cp.c */ 441 extern int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv); 442 extern int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv); 443 extern int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_priv); 444 extern int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_priv); 445 extern int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_priv); 446 extern int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv); 447 extern int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv); 448 extern int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv); 449 extern int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv); 450 extern u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv); 451 extern void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc); 452 extern void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base); 453 extern u32 RADEON_READ_MM(drm_radeon_private_t *dev_priv, int addr); 454 455 extern void radeon_freelist_reset(struct drm_device * dev); 456 extern struct drm_buf *radeon_freelist_get(struct drm_device * dev); 457 458 extern int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n); 459 460 extern int radeon_do_cp_idle(drm_radeon_private_t * dev_priv); 461 462 extern int radeon_driver_preinit(struct drm_device *dev, unsigned long flags); 463 extern int radeon_presetup(struct drm_device *dev); 464 extern int radeon_driver_postcleanup(struct drm_device *dev); 465 466 extern int radeon_mem_alloc(struct drm_device *dev, void *data, struct drm_file *file_priv); 467 extern int radeon_mem_free(struct drm_device *dev, void *data, struct drm_file *file_priv); 468 extern int radeon_mem_init_heap(struct drm_device *dev, void *data, struct drm_file *file_priv); 469 extern void radeon_mem_takedown(struct mem_block **heap); 470 extern void radeon_mem_release(struct drm_file *file_priv, 471 struct mem_block *heap); 472 473 extern void radeon_enable_bm(struct drm_radeon_private *dev_priv); 474 extern u32 radeon_read_ring_rptr(drm_radeon_private_t *dev_priv, u32 off); 475 extern void radeon_write_ring_rptr(drm_radeon_private_t *dev_priv, u32 off, u32 val); 476 477 /* radeon_irq.c */ 478 extern void radeon_irq_set_state(struct drm_device *dev, u32 mask, int state); 479 extern int radeon_irq_emit(struct drm_device *dev, void *data, struct drm_file *file_priv); 480 extern int radeon_irq_wait(struct drm_device *dev, void *data, struct drm_file *file_priv); 481 482 extern void radeon_do_release(struct drm_device * dev); 483 extern u32 radeon_get_vblank_counter(struct drm_device *dev, int crtc); 484 extern int radeon_enable_vblank(struct drm_device *dev, int crtc); 485 extern void radeon_disable_vblank(struct drm_device *dev, int crtc); 486 extern irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS); 487 extern void radeon_driver_irq_preinstall(struct drm_device * dev); 488 extern int radeon_driver_irq_postinstall(struct drm_device *dev); 489 extern void radeon_driver_irq_uninstall(struct drm_device * dev); 490 extern void radeon_enable_interrupt(struct drm_device *dev); 491 extern int radeon_vblank_crtc_get(struct drm_device *dev); 492 extern int radeon_vblank_crtc_set(struct drm_device *dev, int64_t value); 493 494 extern int radeon_driver_load(struct drm_device *dev, unsigned long flags); 495 extern int radeon_driver_unload(struct drm_device *dev); 496 extern int radeon_driver_firstopen(struct drm_device *dev); 497 extern void radeon_driver_preclose(struct drm_device *dev, 498 struct drm_file *file_priv); 499 extern void radeon_driver_postclose(struct drm_device *dev, 500 struct drm_file *file_priv); 501 extern void radeon_driver_lastclose(struct drm_device * dev); 502 extern int radeon_driver_open(struct drm_device *dev, 503 struct drm_file *file_priv); 504 extern long radeon_compat_ioctl(struct file *filp, unsigned int cmd, 505 unsigned long arg); 506 507 /* r300_cmdbuf.c */ 508 extern void r300_init_reg_flags(struct drm_device *dev); 509 510 extern int r300_do_cp_cmdbuf(struct drm_device *dev, 511 struct drm_file *file_priv, 512 drm_radeon_kcmd_buffer_t *cmdbuf); 513 514 /* r600_cp.c */ 515 extern int r600_do_engine_reset(struct drm_device *dev); 516 extern int r600_do_cleanup_cp(struct drm_device *dev); 517 extern int r600_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init, 518 struct drm_file *file_priv); 519 extern int r600_do_resume_cp(struct drm_device *dev, struct drm_file *file_priv); 520 extern int r600_do_cp_idle(drm_radeon_private_t *dev_priv); 521 extern void r600_do_cp_start(drm_radeon_private_t *dev_priv); 522 extern void r600_do_cp_reset(drm_radeon_private_t *dev_priv); 523 extern void r600_do_cp_stop(drm_radeon_private_t *dev_priv); 524 extern int r600_cp_dispatch_indirect(struct drm_device *dev, 525 struct drm_buf *buf, int start, int end); 526 extern int r600_page_table_init(struct drm_device *dev); 527 extern void r600_page_table_cleanup(struct drm_device *dev, struct drm_ati_pcigart_info *gart_info); 528 extern void r600_cp_dispatch_swap(struct drm_device * dev); 529 extern int r600_cp_dispatch_texture(struct drm_device * dev, 530 struct drm_file *file_priv, 531 drm_radeon_texture_t * tex, 532 drm_radeon_tex_image_t * image); 533 534 /* r600_blit.c */ 535 extern int 536 r600_prepare_blit_copy(struct drm_device *dev); 537 extern void 538 r600_done_blit_copy(struct drm_device *dev); 539 extern void 540 r600_blit_copy(struct drm_device *dev, 541 uint64_t src_gpu_addr, uint64_t dst_gpu_addr, 542 int size_bytes); 543 extern void 544 r600_blit_swap(struct drm_device *dev, 545 uint64_t src_gpu_addr, uint64_t dst_gpu_addr, 546 int sx, int sy, int dx, int dy, 547 int w, int h, int src_pitch, int dst_pitch, int cpp); 548 549 /* radeon_state.c */ 550 extern void radeon_cp_discard_buffer(struct drm_device * dev, struct drm_buf * buf); 551 552 /* radeon_cs.c */ 553 extern int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *fpriv); 554 extern int r600_cs_init(struct drm_device *dev); 555 556 /* Flags for stats.boxes 557 */ 558 #define RADEON_BOX_DMA_IDLE 0x1 559 #define RADEON_BOX_RING_FULL 0x2 560 #define RADEON_BOX_FLIP 0x4 561 #define RADEON_BOX_WAIT_IDLE 0x8 562 #define RADEON_BOX_TEXTURE_LOAD 0x10 563 564 /* Register definitions, register access macros and drmAddMap constants 565 * for Radeon kernel driver. 566 */ 567 #define RADEON_MM_INDEX 0x0000 568 #define RADEON_MM_DATA 0x0004 569 570 #define RADEON_AGP_COMMAND 0x0f60 571 #define RADEON_AGP_COMMAND_PCI_CONFIG 0x0060 /* offset in PCI config */ 572 # define RADEON_AGP_ENABLE (1<<8) 573 #define RADEON_AUX_SCISSOR_CNTL 0x26f0 574 # define RADEON_EXCLUSIVE_SCISSOR_0 (1 << 24) 575 # define RADEON_EXCLUSIVE_SCISSOR_1 (1 << 25) 576 # define RADEON_EXCLUSIVE_SCISSOR_2 (1 << 26) 577 # define RADEON_SCISSOR_0_ENABLE (1 << 28) 578 # define RADEON_SCISSOR_1_ENABLE (1 << 29) 579 # define RADEON_SCISSOR_2_ENABLE (1 << 30) 580 581 /* 582 * PCIE radeons (rv370/rv380, rv410, r423/r430/r480, r5xx) 583 * don't have an explicit bus mastering disable bit. It's handled 584 * by the PCI D-states. PMI_BM_DIS disables D-state bus master 585 * handling, not bus mastering itself. 586 */ 587 #define RADEON_BUS_CNTL 0x0030 588 /* r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */ 589 # define RADEON_BUS_MASTER_DIS (1 << 6) 590 /* rs600/rs690/rs740 */ 591 # define RS600_BUS_MASTER_DIS (1 << 14) 592 # define RS600_MSI_REARM (1 << 20) 593 /* see RS400_MSI_REARM in AIC_CNTL for rs480 */ 594 595 #define RADEON_BUS_CNTL1 0x0034 596 # define RADEON_PMI_BM_DIS (1 << 2) 597 # define RADEON_PMI_INT_DIS (1 << 3) 598 599 #define RV370_BUS_CNTL 0x004c 600 # define RV370_PMI_BM_DIS (1 << 5) 601 # define RV370_PMI_INT_DIS (1 << 6) 602 603 #define RADEON_MSI_REARM_EN 0x0160 604 /* rv370/rv380, rv410, r423/r430/r480, r5xx */ 605 # define RV370_MSI_REARM_EN (1 << 0) 606 607 #define RADEON_CLOCK_CNTL_DATA 0x000c 608 # define RADEON_PLL_WR_EN (1 << 7) 609 #define RADEON_CLOCK_CNTL_INDEX 0x0008 610 #define RADEON_CONFIG_APER_SIZE 0x0108 611 #define RADEON_CONFIG_MEMSIZE 0x00f8 612 #define RADEON_CRTC_OFFSET 0x0224 613 #define RADEON_CRTC_OFFSET_CNTL 0x0228 614 # define RADEON_CRTC_TILE_EN (1 << 15) 615 # define RADEON_CRTC_OFFSET_FLIP_CNTL (1 << 16) 616 #define RADEON_CRTC2_OFFSET 0x0324 617 #define RADEON_CRTC2_OFFSET_CNTL 0x0328 618 619 #define RADEON_PCIE_INDEX 0x0030 620 #define RADEON_PCIE_DATA 0x0034 621 #define RADEON_PCIE_TX_GART_CNTL 0x10 622 # define RADEON_PCIE_TX_GART_EN (1 << 0) 623 # define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_PASS_THRU (0 << 1) 624 # define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_CLAMP_LO (1 << 1) 625 # define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD (3 << 1) 626 # define RADEON_PCIE_TX_GART_MODE_32_128_CACHE (0 << 3) 627 # define RADEON_PCIE_TX_GART_MODE_8_4_128_CACHE (1 << 3) 628 # define RADEON_PCIE_TX_GART_CHK_RW_VALID_EN (1 << 5) 629 # define RADEON_PCIE_TX_GART_INVALIDATE_TLB (1 << 8) 630 #define RADEON_PCIE_TX_DISCARD_RD_ADDR_LO 0x11 631 #define RADEON_PCIE_TX_DISCARD_RD_ADDR_HI 0x12 632 #define RADEON_PCIE_TX_GART_BASE 0x13 633 #define RADEON_PCIE_TX_GART_START_LO 0x14 634 #define RADEON_PCIE_TX_GART_START_HI 0x15 635 #define RADEON_PCIE_TX_GART_END_LO 0x16 636 #define RADEON_PCIE_TX_GART_END_HI 0x17 637 638 #define RS480_NB_MC_INDEX 0x168 639 # define RS480_NB_MC_IND_WR_EN (1 << 8) 640 #define RS480_NB_MC_DATA 0x16c 641 642 #define RS690_MC_INDEX 0x78 643 # define RS690_MC_INDEX_MASK 0x1ff 644 # define RS690_MC_INDEX_WR_EN (1 << 9) 645 # define RS690_MC_INDEX_WR_ACK 0x7f 646 #define RS690_MC_DATA 0x7c 647 648 /* MC indirect registers */ 649 #define RS480_MC_MISC_CNTL 0x18 650 # define RS480_DISABLE_GTW (1 << 1) 651 /* switch between MCIND GART and MM GART registers. 0 = mmgart, 1 = mcind gart */ 652 # define RS480_GART_INDEX_REG_EN (1 << 12) 653 # define RS690_BLOCK_GFX_D3_EN (1 << 14) 654 #define RS480_K8_FB_LOCATION 0x1e 655 #define RS480_GART_FEATURE_ID 0x2b 656 # define RS480_HANG_EN (1 << 11) 657 # define RS480_TLB_ENABLE (1 << 18) 658 # define RS480_P2P_ENABLE (1 << 19) 659 # define RS480_GTW_LAC_EN (1 << 25) 660 # define RS480_2LEVEL_GART (0 << 30) 661 # define RS480_1LEVEL_GART (1 << 30) 662 # define RS480_PDC_EN (1 << 31) 663 #define RS480_GART_BASE 0x2c 664 #define RS480_GART_CACHE_CNTRL 0x2e 665 # define RS480_GART_CACHE_INVALIDATE (1 << 0) /* wait for it to clear */ 666 #define RS480_AGP_ADDRESS_SPACE_SIZE 0x38 667 # define RS480_GART_EN (1 << 0) 668 # define RS480_VA_SIZE_32MB (0 << 1) 669 # define RS480_VA_SIZE_64MB (1 << 1) 670 # define RS480_VA_SIZE_128MB (2 << 1) 671 # define RS480_VA_SIZE_256MB (3 << 1) 672 # define RS480_VA_SIZE_512MB (4 << 1) 673 # define RS480_VA_SIZE_1GB (5 << 1) 674 # define RS480_VA_SIZE_2GB (6 << 1) 675 #define RS480_AGP_MODE_CNTL 0x39 676 # define RS480_POST_GART_Q_SIZE (1 << 18) 677 # define RS480_NONGART_SNOOP (1 << 19) 678 # define RS480_AGP_RD_BUF_SIZE (1 << 20) 679 # define RS480_REQ_TYPE_SNOOP_SHIFT 22 680 # define RS480_REQ_TYPE_SNOOP_MASK 0x3 681 # define RS480_REQ_TYPE_SNOOP_DIS (1 << 24) 682 #define RS480_MC_MISC_UMA_CNTL 0x5f 683 #define RS480_MC_MCLK_CNTL 0x7a 684 #define RS480_MC_UMA_DUALCH_CNTL 0x86 685 686 #define RS690_MC_FB_LOCATION 0x100 687 #define RS690_MC_AGP_LOCATION 0x101 688 #define RS690_MC_AGP_BASE 0x102 689 #define RS690_MC_AGP_BASE_2 0x103 690 691 #define RS600_MC_INDEX 0x70 692 # define RS600_MC_ADDR_MASK 0xffff 693 # define RS600_MC_IND_SEQ_RBS_0 (1 << 16) 694 # define RS600_MC_IND_SEQ_RBS_1 (1 << 17) 695 # define RS600_MC_IND_SEQ_RBS_2 (1 << 18) 696 # define RS600_MC_IND_SEQ_RBS_3 (1 << 19) 697 # define RS600_MC_IND_AIC_RBS (1 << 20) 698 # define RS600_MC_IND_CITF_ARB0 (1 << 21) 699 # define RS600_MC_IND_CITF_ARB1 (1 << 22) 700 # define RS600_MC_IND_WR_EN (1 << 23) 701 #define RS600_MC_DATA 0x74 702 703 #define RS600_MC_STATUS 0x0 704 # define RS600_MC_IDLE (1 << 1) 705 #define RS600_MC_FB_LOCATION 0x4 706 #define RS600_MC_AGP_LOCATION 0x5 707 #define RS600_AGP_BASE 0x6 708 #define RS600_AGP_BASE_2 0x7 709 #define RS600_MC_CNTL1 0x9 710 # define RS600_ENABLE_PAGE_TABLES (1 << 26) 711 #define RS600_MC_PT0_CNTL 0x100 712 # define RS600_ENABLE_PT (1 << 0) 713 # define RS600_EFFECTIVE_L2_CACHE_SIZE(x) ((x) << 15) 714 # define RS600_EFFECTIVE_L2_QUEUE_SIZE(x) ((x) << 21) 715 # define RS600_INVALIDATE_ALL_L1_TLBS (1 << 28) 716 # define RS600_INVALIDATE_L2_CACHE (1 << 29) 717 #define RS600_MC_PT0_CONTEXT0_CNTL 0x102 718 # define RS600_ENABLE_PAGE_TABLE (1 << 0) 719 # define RS600_PAGE_TABLE_TYPE_FLAT (0 << 1) 720 #define RS600_MC_PT0_SYSTEM_APERTURE_LOW_ADDR 0x112 721 #define RS600_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR 0x114 722 #define RS600_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR 0x11c 723 #define RS600_MC_PT0_CONTEXT0_FLAT_BASE_ADDR 0x12c 724 #define RS600_MC_PT0_CONTEXT0_FLAT_START_ADDR 0x13c 725 #define RS600_MC_PT0_CONTEXT0_FLAT_END_ADDR 0x14c 726 #define RS600_MC_PT0_CLIENT0_CNTL 0x16c 727 # define RS600_ENABLE_TRANSLATION_MODE_OVERRIDE (1 << 0) 728 # define RS600_TRANSLATION_MODE_OVERRIDE (1 << 1) 729 # define RS600_SYSTEM_ACCESS_MODE_MASK (3 << 8) 730 # define RS600_SYSTEM_ACCESS_MODE_PA_ONLY (0 << 8) 731 # define RS600_SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 8) 732 # define RS600_SYSTEM_ACCESS_MODE_IN_SYS (2 << 8) 733 # define RS600_SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 8) 734 # define RS600_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASSTHROUGH (0 << 10) 735 # define RS600_SYSTEM_APERTURE_UNMAPPED_ACCESS_DEFAULT_PAGE (1 << 10) 736 # define RS600_EFFECTIVE_L1_CACHE_SIZE(x) ((x) << 11) 737 # define RS600_ENABLE_FRAGMENT_PROCESSING (1 << 14) 738 # define RS600_EFFECTIVE_L1_QUEUE_SIZE(x) ((x) << 15) 739 # define RS600_INVALIDATE_L1_TLB (1 << 20) 740 741 #define R520_MC_IND_INDEX 0x70 742 #define R520_MC_IND_WR_EN (1 << 24) 743 #define R520_MC_IND_DATA 0x74 744 745 #define RV515_MC_FB_LOCATION 0x01 746 #define RV515_MC_AGP_LOCATION 0x02 747 #define RV515_MC_AGP_BASE 0x03 748 #define RV515_MC_AGP_BASE_2 0x04 749 750 #define R520_MC_FB_LOCATION 0x04 751 #define R520_MC_AGP_LOCATION 0x05 752 #define R520_MC_AGP_BASE 0x06 753 #define R520_MC_AGP_BASE_2 0x07 754 755 #define RADEON_MPP_TB_CONFIG 0x01c0 756 #define RADEON_MEM_CNTL 0x0140 757 #define RADEON_MEM_SDRAM_MODE_REG 0x0158 758 #define RADEON_AGP_BASE_2 0x015c /* r200+ only */ 759 #define RS480_AGP_BASE_2 0x0164 760 #define RADEON_AGP_BASE 0x0170 761 762 /* pipe config regs */ 763 #define R400_GB_PIPE_SELECT 0x402c 764 #define RV530_GB_PIPE_SELECT2 0x4124 765 #define R500_DYN_SCLK_PWMEM_PIPE 0x000d /* PLL */ 766 #define R300_GB_TILE_CONFIG 0x4018 767 # define R300_ENABLE_TILING (1 << 0) 768 # define R300_PIPE_COUNT_RV350 (0 << 1) 769 # define R300_PIPE_COUNT_R300 (3 << 1) 770 # define R300_PIPE_COUNT_R420_3P (6 << 1) 771 # define R300_PIPE_COUNT_R420 (7 << 1) 772 # define R300_TILE_SIZE_8 (0 << 4) 773 # define R300_TILE_SIZE_16 (1 << 4) 774 # define R300_TILE_SIZE_32 (2 << 4) 775 # define R300_SUBPIXEL_1_12 (0 << 16) 776 # define R300_SUBPIXEL_1_16 (1 << 16) 777 #define R300_DST_PIPE_CONFIG 0x170c 778 # define R300_PIPE_AUTO_CONFIG (1 << 31) 779 #define R300_RB2D_DSTCACHE_MODE 0x3428 780 # define R300_DC_AUTOFLUSH_ENABLE (1 << 8) 781 # define R300_DC_DC_DISABLE_IGNORE_PE (1 << 17) 782 783 #define RADEON_RB3D_COLOROFFSET 0x1c40 784 #define RADEON_RB3D_COLORPITCH 0x1c48 785 786 #define RADEON_SRC_X_Y 0x1590 787 788 #define RADEON_DP_GUI_MASTER_CNTL 0x146c 789 # define RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0) 790 # define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1) 791 # define RADEON_GMC_BRUSH_SOLID_COLOR (13 << 4) 792 # define RADEON_GMC_BRUSH_NONE (15 << 4) 793 # define RADEON_GMC_DST_16BPP (4 << 8) 794 # define RADEON_GMC_DST_24BPP (5 << 8) 795 # define RADEON_GMC_DST_32BPP (6 << 8) 796 # define RADEON_GMC_DST_DATATYPE_SHIFT 8 797 # define RADEON_GMC_SRC_DATATYPE_COLOR (3 << 12) 798 # define RADEON_DP_SRC_SOURCE_MEMORY (2 << 24) 799 # define RADEON_DP_SRC_SOURCE_HOST_DATA (3 << 24) 800 # define RADEON_GMC_CLR_CMP_CNTL_DIS (1 << 28) 801 # define RADEON_GMC_WR_MSK_DIS (1 << 30) 802 # define RADEON_ROP3_S 0x00cc0000 803 # define RADEON_ROP3_P 0x00f00000 804 #define RADEON_DP_WRITE_MASK 0x16cc 805 #define RADEON_SRC_PITCH_OFFSET 0x1428 806 #define RADEON_DST_PITCH_OFFSET 0x142c 807 #define RADEON_DST_PITCH_OFFSET_C 0x1c80 808 # define RADEON_DST_TILE_LINEAR (0 << 30) 809 # define RADEON_DST_TILE_MACRO (1 << 30) 810 # define RADEON_DST_TILE_MICRO (2 << 30) 811 # define RADEON_DST_TILE_BOTH (3 << 30) 812 813 #define RADEON_SCRATCH_REG0 0x15e0 814 #define RADEON_SCRATCH_REG1 0x15e4 815 #define RADEON_SCRATCH_REG2 0x15e8 816 #define RADEON_SCRATCH_REG3 0x15ec 817 #define RADEON_SCRATCH_REG4 0x15f0 818 #define RADEON_SCRATCH_REG5 0x15f4 819 #define RADEON_SCRATCH_UMSK 0x0770 820 #define RADEON_SCRATCH_ADDR 0x0774 821 822 #define RADEON_SCRATCHOFF( x ) (RADEON_SCRATCH_REG_OFFSET + 4*(x)) 823 824 extern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index); 825 826 #define GET_SCRATCH(dev_priv, x) radeon_get_scratch(dev_priv, x) 827 828 #define R600_SCRATCH_REG0 0x8500 829 #define R600_SCRATCH_REG1 0x8504 830 #define R600_SCRATCH_REG2 0x8508 831 #define R600_SCRATCH_REG3 0x850c 832 #define R600_SCRATCH_REG4 0x8510 833 #define R600_SCRATCH_REG5 0x8514 834 #define R600_SCRATCH_REG6 0x8518 835 #define R600_SCRATCH_REG7 0x851c 836 #define R600_SCRATCH_UMSK 0x8540 837 #define R600_SCRATCH_ADDR 0x8544 838 839 #define R600_SCRATCHOFF(x) (R600_SCRATCH_REG_OFFSET + 4*(x)) 840 841 #define RADEON_GEN_INT_CNTL 0x0040 842 # define RADEON_CRTC_VBLANK_MASK (1 << 0) 843 # define RADEON_CRTC2_VBLANK_MASK (1 << 9) 844 # define RADEON_GUI_IDLE_INT_ENABLE (1 << 19) 845 # define RADEON_SW_INT_ENABLE (1 << 25) 846 847 #define RADEON_GEN_INT_STATUS 0x0044 848 # define RADEON_CRTC_VBLANK_STAT (1 << 0) 849 # define RADEON_CRTC_VBLANK_STAT_ACK (1 << 0) 850 # define RADEON_CRTC2_VBLANK_STAT (1 << 9) 851 # define RADEON_CRTC2_VBLANK_STAT_ACK (1 << 9) 852 # define RADEON_GUI_IDLE_INT_TEST_ACK (1 << 19) 853 # define RADEON_SW_INT_TEST (1 << 25) 854 # define RADEON_SW_INT_TEST_ACK (1 << 25) 855 # define RADEON_SW_INT_FIRE (1 << 26) 856 # define R500_DISPLAY_INT_STATUS (1 << 0) 857 858 #define RADEON_HOST_PATH_CNTL 0x0130 859 # define RADEON_HDP_SOFT_RESET (1 << 26) 860 # define RADEON_HDP_WC_TIMEOUT_MASK (7 << 28) 861 # define RADEON_HDP_WC_TIMEOUT_28BCLK (7 << 28) 862 863 #define RADEON_ISYNC_CNTL 0x1724 864 # define RADEON_ISYNC_ANY2D_IDLE3D (1 << 0) 865 # define RADEON_ISYNC_ANY3D_IDLE2D (1 << 1) 866 # define RADEON_ISYNC_TRIG2D_IDLE3D (1 << 2) 867 # define RADEON_ISYNC_TRIG3D_IDLE2D (1 << 3) 868 # define RADEON_ISYNC_WAIT_IDLEGUI (1 << 4) 869 # define RADEON_ISYNC_CPSCRATCH_IDLEGUI (1 << 5) 870 871 #define RADEON_RBBM_GUICNTL 0x172c 872 # define RADEON_HOST_DATA_SWAP_NONE (0 << 0) 873 # define RADEON_HOST_DATA_SWAP_16BIT (1 << 0) 874 # define RADEON_HOST_DATA_SWAP_32BIT (2 << 0) 875 # define RADEON_HOST_DATA_SWAP_HDW (3 << 0) 876 877 #define RADEON_MC_AGP_LOCATION 0x014c 878 #define RADEON_MC_FB_LOCATION 0x0148 879 #define RADEON_MCLK_CNTL 0x0012 880 # define RADEON_FORCEON_MCLKA (1 << 16) 881 # define RADEON_FORCEON_MCLKB (1 << 17) 882 # define RADEON_FORCEON_YCLKA (1 << 18) 883 # define RADEON_FORCEON_YCLKB (1 << 19) 884 # define RADEON_FORCEON_MC (1 << 20) 885 # define RADEON_FORCEON_AIC (1 << 21) 886 887 #define RADEON_PP_BORDER_COLOR_0 0x1d40 888 #define RADEON_PP_BORDER_COLOR_1 0x1d44 889 #define RADEON_PP_BORDER_COLOR_2 0x1d48 890 #define RADEON_PP_CNTL 0x1c38 891 # define RADEON_SCISSOR_ENABLE (1 << 1) 892 #define RADEON_PP_LUM_MATRIX 0x1d00 893 #define RADEON_PP_MISC 0x1c14 894 #define RADEON_PP_ROT_MATRIX_0 0x1d58 895 #define RADEON_PP_TXFILTER_0 0x1c54 896 #define RADEON_PP_TXOFFSET_0 0x1c5c 897 #define RADEON_PP_TXFILTER_1 0x1c6c 898 #define RADEON_PP_TXFILTER_2 0x1c84 899 900 #define R300_RB2D_DSTCACHE_CTLSTAT 0x342c /* use R300_DSTCACHE_CTLSTAT */ 901 #define R300_DSTCACHE_CTLSTAT 0x1714 902 # define R300_RB2D_DC_FLUSH (3 << 0) 903 # define R300_RB2D_DC_FREE (3 << 2) 904 # define R300_RB2D_DC_FLUSH_ALL 0xf 905 # define R300_RB2D_DC_BUSY (1 << 31) 906 #define RADEON_RB3D_CNTL 0x1c3c 907 # define RADEON_ALPHA_BLEND_ENABLE (1 << 0) 908 # define RADEON_PLANE_MASK_ENABLE (1 << 1) 909 # define RADEON_DITHER_ENABLE (1 << 2) 910 # define RADEON_ROUND_ENABLE (1 << 3) 911 # define RADEON_SCALE_DITHER_ENABLE (1 << 4) 912 # define RADEON_DITHER_INIT (1 << 5) 913 # define RADEON_ROP_ENABLE (1 << 6) 914 # define RADEON_STENCIL_ENABLE (1 << 7) 915 # define RADEON_Z_ENABLE (1 << 8) 916 # define RADEON_ZBLOCK16 (1 << 15) 917 #define RADEON_RB3D_DEPTHOFFSET 0x1c24 918 #define RADEON_RB3D_DEPTHCLEARVALUE 0x3230 919 #define RADEON_RB3D_DEPTHPITCH 0x1c28 920 #define RADEON_RB3D_PLANEMASK 0x1d84 921 #define RADEON_RB3D_STENCILREFMASK 0x1d7c 922 #define RADEON_RB3D_ZCACHE_MODE 0x3250 923 #define RADEON_RB3D_ZCACHE_CTLSTAT 0x3254 924 # define RADEON_RB3D_ZC_FLUSH (1 << 0) 925 # define RADEON_RB3D_ZC_FREE (1 << 2) 926 # define RADEON_RB3D_ZC_FLUSH_ALL 0x5 927 # define RADEON_RB3D_ZC_BUSY (1 << 31) 928 #define R300_ZB_ZCACHE_CTLSTAT 0x4f18 929 # define R300_ZC_FLUSH (1 << 0) 930 # define R300_ZC_FREE (1 << 1) 931 # define R300_ZC_BUSY (1 << 31) 932 #define RADEON_RB3D_DSTCACHE_CTLSTAT 0x325c 933 # define RADEON_RB3D_DC_FLUSH (3 << 0) 934 # define RADEON_RB3D_DC_FREE (3 << 2) 935 # define RADEON_RB3D_DC_FLUSH_ALL 0xf 936 # define RADEON_RB3D_DC_BUSY (1 << 31) 937 #define R300_RB3D_DSTCACHE_CTLSTAT 0x4e4c 938 # define R300_RB3D_DC_FLUSH (2 << 0) 939 # define R300_RB3D_DC_FREE (2 << 2) 940 # define R300_RB3D_DC_FINISH (1 << 4) 941 #define RADEON_RB3D_ZSTENCILCNTL 0x1c2c 942 # define RADEON_Z_TEST_MASK (7 << 4) 943 # define RADEON_Z_TEST_ALWAYS (7 << 4) 944 # define RADEON_Z_HIERARCHY_ENABLE (1 << 8) 945 # define RADEON_STENCIL_TEST_ALWAYS (7 << 12) 946 # define RADEON_STENCIL_S_FAIL_REPLACE (2 << 16) 947 # define RADEON_STENCIL_ZPASS_REPLACE (2 << 20) 948 # define RADEON_STENCIL_ZFAIL_REPLACE (2 << 24) 949 # define RADEON_Z_COMPRESSION_ENABLE (1 << 28) 950 # define RADEON_FORCE_Z_DIRTY (1 << 29) 951 # define RADEON_Z_WRITE_ENABLE (1 << 30) 952 # define RADEON_Z_DECOMPRESSION_ENABLE (1 << 31) 953 #define RADEON_RBBM_SOFT_RESET 0x00f0 954 # define RADEON_SOFT_RESET_CP (1 << 0) 955 # define RADEON_SOFT_RESET_HI (1 << 1) 956 # define RADEON_SOFT_RESET_SE (1 << 2) 957 # define RADEON_SOFT_RESET_RE (1 << 3) 958 # define RADEON_SOFT_RESET_PP (1 << 4) 959 # define RADEON_SOFT_RESET_E2 (1 << 5) 960 # define RADEON_SOFT_RESET_RB (1 << 6) 961 # define RADEON_SOFT_RESET_HDP (1 << 7) 962 /* 963 * 6:0 Available slots in the FIFO 964 * 8 Host Interface active 965 * 9 CP request active 966 * 10 FIFO request active 967 * 11 Host Interface retry active 968 * 12 CP retry active 969 * 13 FIFO retry active 970 * 14 FIFO pipeline busy 971 * 15 Event engine busy 972 * 16 CP command stream busy 973 * 17 2D engine busy 974 * 18 2D portion of render backend busy 975 * 20 3D setup engine busy 976 * 26 GA engine busy 977 * 27 CBA 2D engine busy 978 * 31 2D engine busy or 3D engine busy or FIFO not empty or CP busy or 979 * command stream queue not empty or Ring Buffer not empty 980 */ 981 #define RADEON_RBBM_STATUS 0x0e40 982 /* Same as the previous RADEON_RBBM_STATUS; this is a mirror of that register. */ 983 /* #define RADEON_RBBM_STATUS 0x1740 */ 984 /* bits 6:0 are dword slots available in the cmd fifo */ 985 # define RADEON_RBBM_FIFOCNT_MASK 0x007f 986 # define RADEON_HIRQ_ON_RBB (1 << 8) 987 # define RADEON_CPRQ_ON_RBB (1 << 9) 988 # define RADEON_CFRQ_ON_RBB (1 << 10) 989 # define RADEON_HIRQ_IN_RTBUF (1 << 11) 990 # define RADEON_CPRQ_IN_RTBUF (1 << 12) 991 # define RADEON_CFRQ_IN_RTBUF (1 << 13) 992 # define RADEON_PIPE_BUSY (1 << 14) 993 # define RADEON_ENG_EV_BUSY (1 << 15) 994 # define RADEON_CP_CMDSTRM_BUSY (1 << 16) 995 # define RADEON_E2_BUSY (1 << 17) 996 # define RADEON_RB2D_BUSY (1 << 18) 997 # define RADEON_RB3D_BUSY (1 << 19) /* not used on r300 */ 998 # define RADEON_VAP_BUSY (1 << 20) 999 # define RADEON_RE_BUSY (1 << 21) /* not used on r300 */ 1000 # define RADEON_TAM_BUSY (1 << 22) /* not used on r300 */ 1001 # define RADEON_TDM_BUSY (1 << 23) /* not used on r300 */ 1002 # define RADEON_PB_BUSY (1 << 24) /* not used on r300 */ 1003 # define RADEON_TIM_BUSY (1 << 25) /* not used on r300 */ 1004 # define RADEON_GA_BUSY (1 << 26) 1005 # define RADEON_CBA2D_BUSY (1 << 27) 1006 # define RADEON_RBBM_ACTIVE (1 << 31) 1007 #define RADEON_RE_LINE_PATTERN 0x1cd0 1008 #define RADEON_RE_MISC 0x26c4 1009 #define RADEON_RE_TOP_LEFT 0x26c0 1010 #define RADEON_RE_WIDTH_HEIGHT 0x1c44 1011 #define RADEON_RE_STIPPLE_ADDR 0x1cc8 1012 #define RADEON_RE_STIPPLE_DATA 0x1ccc 1013 1014 #define RADEON_SCISSOR_TL_0 0x1cd8 1015 #define RADEON_SCISSOR_BR_0 0x1cdc 1016 #define RADEON_SCISSOR_TL_1 0x1ce0 1017 #define RADEON_SCISSOR_BR_1 0x1ce4 1018 #define RADEON_SCISSOR_TL_2 0x1ce8 1019 #define RADEON_SCISSOR_BR_2 0x1cec 1020 #define RADEON_SE_COORD_FMT 0x1c50 1021 #define RADEON_SE_CNTL 0x1c4c 1022 # define RADEON_FFACE_CULL_CW (0 << 0) 1023 # define RADEON_BFACE_SOLID (3 << 1) 1024 # define RADEON_FFACE_SOLID (3 << 3) 1025 # define RADEON_FLAT_SHADE_VTX_LAST (3 << 6) 1026 # define RADEON_DIFFUSE_SHADE_FLAT (1 << 8) 1027 # define RADEON_DIFFUSE_SHADE_GOURAUD (2 << 8) 1028 # define RADEON_ALPHA_SHADE_FLAT (1 << 10) 1029 # define RADEON_ALPHA_SHADE_GOURAUD (2 << 10) 1030 # define RADEON_SPECULAR_SHADE_FLAT (1 << 12) 1031 # define RADEON_SPECULAR_SHADE_GOURAUD (2 << 12) 1032 # define RADEON_FOG_SHADE_FLAT (1 << 14) 1033 # define RADEON_FOG_SHADE_GOURAUD (2 << 14) 1034 # define RADEON_VPORT_XY_XFORM_ENABLE (1 << 24) 1035 # define RADEON_VPORT_Z_XFORM_ENABLE (1 << 25) 1036 # define RADEON_VTX_PIX_CENTER_OGL (1 << 27) 1037 # define RADEON_ROUND_MODE_TRUNC (0 << 28) 1038 # define RADEON_ROUND_PREC_8TH_PIX (1 << 30) 1039 #define RADEON_SE_CNTL_STATUS 0x2140 1040 #define RADEON_SE_LINE_WIDTH 0x1db8 1041 #define RADEON_SE_VPORT_XSCALE 0x1d98 1042 #define RADEON_SE_ZBIAS_FACTOR 0x1db0 1043 #define RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED 0x2210 1044 #define RADEON_SE_TCL_OUTPUT_VTX_FMT 0x2254 1045 #define RADEON_SE_TCL_VECTOR_INDX_REG 0x2200 1046 # define RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT 16 1047 # define RADEON_VEC_INDX_DWORD_COUNT_SHIFT 28 1048 #define RADEON_SE_TCL_VECTOR_DATA_REG 0x2204 1049 #define RADEON_SE_TCL_SCALAR_INDX_REG 0x2208 1050 # define RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT 16 1051 #define RADEON_SE_TCL_SCALAR_DATA_REG 0x220C 1052 #define RADEON_SURFACE_ACCESS_FLAGS 0x0bf8 1053 #define RADEON_SURFACE_ACCESS_CLR 0x0bfc 1054 #define RADEON_SURFACE_CNTL 0x0b00 1055 # define RADEON_SURF_TRANSLATION_DIS (1 << 8) 1056 # define RADEON_NONSURF_AP0_SWP_MASK (3 << 20) 1057 # define RADEON_NONSURF_AP0_SWP_LITTLE (0 << 20) 1058 # define RADEON_NONSURF_AP0_SWP_BIG16 (1 << 20) 1059 # define RADEON_NONSURF_AP0_SWP_BIG32 (2 << 20) 1060 # define RADEON_NONSURF_AP1_SWP_MASK (3 << 22) 1061 # define RADEON_NONSURF_AP1_SWP_LITTLE (0 << 22) 1062 # define RADEON_NONSURF_AP1_SWP_BIG16 (1 << 22) 1063 # define RADEON_NONSURF_AP1_SWP_BIG32 (2 << 22) 1064 #define RADEON_SURFACE0_INFO 0x0b0c 1065 # define RADEON_SURF_PITCHSEL_MASK (0x1ff << 0) 1066 # define RADEON_SURF_TILE_MODE_MASK (3 << 16) 1067 # define RADEON_SURF_TILE_MODE_MACRO (0 << 16) 1068 # define RADEON_SURF_TILE_MODE_MICRO (1 << 16) 1069 # define RADEON_SURF_TILE_MODE_32BIT_Z (2 << 16) 1070 # define RADEON_SURF_TILE_MODE_16BIT_Z (3 << 16) 1071 #define RADEON_SURFACE0_LOWER_BOUND 0x0b04 1072 #define RADEON_SURFACE0_UPPER_BOUND 0x0b08 1073 # define RADEON_SURF_ADDRESS_FIXED_MASK (0x3ff << 0) 1074 #define RADEON_SURFACE1_INFO 0x0b1c 1075 #define RADEON_SURFACE1_LOWER_BOUND 0x0b14 1076 #define RADEON_SURFACE1_UPPER_BOUND 0x0b18 1077 #define RADEON_SURFACE2_INFO 0x0b2c 1078 #define RADEON_SURFACE2_LOWER_BOUND 0x0b24 1079 #define RADEON_SURFACE2_UPPER_BOUND 0x0b28 1080 #define RADEON_SURFACE3_INFO 0x0b3c 1081 #define RADEON_SURFACE3_LOWER_BOUND 0x0b34 1082 #define RADEON_SURFACE3_UPPER_BOUND 0x0b38 1083 #define RADEON_SURFACE4_INFO 0x0b4c 1084 #define RADEON_SURFACE4_LOWER_BOUND 0x0b44 1085 #define RADEON_SURFACE4_UPPER_BOUND 0x0b48 1086 #define RADEON_SURFACE5_INFO 0x0b5c 1087 #define RADEON_SURFACE5_LOWER_BOUND 0x0b54 1088 #define RADEON_SURFACE5_UPPER_BOUND 0x0b58 1089 #define RADEON_SURFACE6_INFO 0x0b6c 1090 #define RADEON_SURFACE6_LOWER_BOUND 0x0b64 1091 #define RADEON_SURFACE6_UPPER_BOUND 0x0b68 1092 #define RADEON_SURFACE7_INFO 0x0b7c 1093 #define RADEON_SURFACE7_LOWER_BOUND 0x0b74 1094 #define RADEON_SURFACE7_UPPER_BOUND 0x0b78 1095 #define RADEON_SW_SEMAPHORE 0x013c 1096 1097 #define RADEON_WAIT_UNTIL 0x1720 1098 # define RADEON_WAIT_CRTC_PFLIP (1 << 0) 1099 # define RADEON_WAIT_2D_IDLE (1 << 14) 1100 # define RADEON_WAIT_3D_IDLE (1 << 15) 1101 # define RADEON_WAIT_2D_IDLECLEAN (1 << 16) 1102 # define RADEON_WAIT_3D_IDLECLEAN (1 << 17) 1103 # define RADEON_WAIT_HOST_IDLECLEAN (1 << 18) 1104 1105 #define RADEON_RB3D_ZMASKOFFSET 0x3234 1106 #define RADEON_RB3D_ZSTENCILCNTL 0x1c2c 1107 # define RADEON_DEPTH_FORMAT_16BIT_INT_Z (0 << 0) 1108 # define RADEON_DEPTH_FORMAT_24BIT_INT_Z (2 << 0) 1109 1110 /* CP registers */ 1111 #define RADEON_CP_ME_RAM_ADDR 0x07d4 1112 #define RADEON_CP_ME_RAM_RADDR 0x07d8 1113 #define RADEON_CP_ME_RAM_DATAH 0x07dc 1114 #define RADEON_CP_ME_RAM_DATAL 0x07e0 1115 1116 #define RADEON_CP_RB_BASE 0x0700 1117 #define RADEON_CP_RB_CNTL 0x0704 1118 # define RADEON_BUF_SWAP_32BIT (2 << 16) 1119 # define RADEON_RB_NO_UPDATE (1 << 27) 1120 # define RADEON_RB_RPTR_WR_ENA (1 << 31) 1121 #define RADEON_CP_RB_RPTR_ADDR 0x070c 1122 #define RADEON_CP_RB_RPTR 0x0710 1123 #define RADEON_CP_RB_WPTR 0x0714 1124 1125 #define RADEON_CP_RB_WPTR_DELAY 0x0718 1126 # define RADEON_PRE_WRITE_TIMER_SHIFT 0 1127 # define RADEON_PRE_WRITE_LIMIT_SHIFT 23 1128 1129 #define RADEON_CP_IB_BASE 0x0738 1130 1131 #define RADEON_CP_CSQ_CNTL 0x0740 1132 # define RADEON_CSQ_CNT_PRIMARY_MASK (0xff << 0) 1133 # define RADEON_CSQ_PRIDIS_INDDIS (0 << 28) 1134 # define RADEON_CSQ_PRIPIO_INDDIS (1 << 28) 1135 # define RADEON_CSQ_PRIBM_INDDIS (2 << 28) 1136 # define RADEON_CSQ_PRIPIO_INDBM (3 << 28) 1137 # define RADEON_CSQ_PRIBM_INDBM (4 << 28) 1138 # define RADEON_CSQ_PRIPIO_INDPIO (15 << 28) 1139 1140 #define RADEON_AIC_CNTL 0x01d0 1141 # define RADEON_PCIGART_TRANSLATE_EN (1 << 0) 1142 # define RS400_MSI_REARM (1 << 3) 1143 #define RADEON_AIC_STAT 0x01d4 1144 #define RADEON_AIC_PT_BASE 0x01d8 1145 #define RADEON_AIC_LO_ADDR 0x01dc 1146 #define RADEON_AIC_HI_ADDR 0x01e0 1147 #define RADEON_AIC_TLB_ADDR 0x01e4 1148 #define RADEON_AIC_TLB_DATA 0x01e8 1149 1150 /* CP command packets */ 1151 #define RADEON_CP_PACKET0 0x00000000 1152 # define RADEON_ONE_REG_WR (1 << 15) 1153 #define RADEON_CP_PACKET1 0x40000000 1154 #define RADEON_CP_PACKET2 0x80000000 1155 #define RADEON_CP_PACKET3 0xC0000000 1156 # define RADEON_CP_NOP 0x00001000 1157 # define RADEON_CP_NEXT_CHAR 0x00001900 1158 # define RADEON_CP_PLY_NEXTSCAN 0x00001D00 1159 # define RADEON_CP_SET_SCISSORS 0x00001E00 1160 /* GEN_INDX_PRIM is unsupported starting with R300 */ 1161 # define RADEON_3D_RNDR_GEN_INDX_PRIM 0x00002300 1162 # define RADEON_WAIT_FOR_IDLE 0x00002600 1163 # define RADEON_3D_DRAW_VBUF 0x00002800 1164 # define RADEON_3D_DRAW_IMMD 0x00002900 1165 # define RADEON_3D_DRAW_INDX 0x00002A00 1166 # define RADEON_CP_LOAD_PALETTE 0x00002C00 1167 # define RADEON_3D_LOAD_VBPNTR 0x00002F00 1168 # define RADEON_MPEG_IDCT_MACROBLOCK 0x00003000 1169 # define RADEON_MPEG_IDCT_MACROBLOCK_REV 0x00003100 1170 # define RADEON_3D_CLEAR_ZMASK 0x00003200 1171 # define RADEON_CP_INDX_BUFFER 0x00003300 1172 # define RADEON_CP_3D_DRAW_VBUF_2 0x00003400 1173 # define RADEON_CP_3D_DRAW_IMMD_2 0x00003500 1174 # define RADEON_CP_3D_DRAW_INDX_2 0x00003600 1175 # define RADEON_3D_CLEAR_HIZ 0x00003700 1176 # define RADEON_CP_3D_CLEAR_CMASK 0x00003802 1177 # define RADEON_CNTL_HOSTDATA_BLT 0x00009400 1178 # define RADEON_CNTL_PAINT_MULTI 0x00009A00 1179 # define RADEON_CNTL_BITBLT_MULTI 0x00009B00 1180 # define RADEON_CNTL_SET_SCISSORS 0xC0001E00 1181 1182 # define R600_IT_INDIRECT_BUFFER 0x00003200 1183 # define R600_IT_ME_INITIALIZE 0x00004400 1184 # define R600_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16) 1185 # define R600_IT_EVENT_WRITE 0x00004600 1186 # define R600_IT_SET_CONFIG_REG 0x00006800 1187 # define R600_SET_CONFIG_REG_OFFSET 0x00008000 1188 # define R600_SET_CONFIG_REG_END 0x0000ac00 1189 1190 #define RADEON_CP_PACKET_MASK 0xC0000000 1191 #define RADEON_CP_PACKET_COUNT_MASK 0x3fff0000 1192 #define RADEON_CP_PACKET0_REG_MASK 0x000007ff 1193 #define RADEON_CP_PACKET1_REG0_MASK 0x000007ff 1194 #define RADEON_CP_PACKET1_REG1_MASK 0x003ff800 1195 1196 #define RADEON_VTX_Z_PRESENT (1 << 31) 1197 #define RADEON_VTX_PKCOLOR_PRESENT (1 << 3) 1198 1199 #define RADEON_PRIM_TYPE_NONE (0 << 0) 1200 #define RADEON_PRIM_TYPE_POINT (1 << 0) 1201 #define RADEON_PRIM_TYPE_LINE (2 << 0) 1202 #define RADEON_PRIM_TYPE_LINE_STRIP (3 << 0) 1203 #define RADEON_PRIM_TYPE_TRI_LIST (4 << 0) 1204 #define RADEON_PRIM_TYPE_TRI_FAN (5 << 0) 1205 #define RADEON_PRIM_TYPE_TRI_STRIP (6 << 0) 1206 #define RADEON_PRIM_TYPE_TRI_TYPE2 (7 << 0) 1207 #define RADEON_PRIM_TYPE_RECT_LIST (8 << 0) 1208 #define RADEON_PRIM_TYPE_3VRT_POINT_LIST (9 << 0) 1209 #define RADEON_PRIM_TYPE_3VRT_LINE_LIST (10 << 0) 1210 #define RADEON_PRIM_TYPE_MASK 0xf 1211 #define RADEON_PRIM_WALK_IND (1 << 4) 1212 #define RADEON_PRIM_WALK_LIST (2 << 4) 1213 #define RADEON_PRIM_WALK_RING (3 << 4) 1214 #define RADEON_COLOR_ORDER_BGRA (0 << 6) 1215 #define RADEON_COLOR_ORDER_RGBA (1 << 6) 1216 #define RADEON_MAOS_ENABLE (1 << 7) 1217 #define RADEON_VTX_FMT_R128_MODE (0 << 8) 1218 #define RADEON_VTX_FMT_RADEON_MODE (1 << 8) 1219 #define RADEON_NUM_VERTICES_SHIFT 16 1220 1221 #define RADEON_COLOR_FORMAT_CI8 2 1222 #define RADEON_COLOR_FORMAT_ARGB1555 3 1223 #define RADEON_COLOR_FORMAT_RGB565 4 1224 #define RADEON_COLOR_FORMAT_ARGB8888 6 1225 #define RADEON_COLOR_FORMAT_RGB332 7 1226 #define RADEON_COLOR_FORMAT_RGB8 9 1227 #define RADEON_COLOR_FORMAT_ARGB4444 15 1228 1229 #define RADEON_TXFORMAT_I8 0 1230 #define RADEON_TXFORMAT_AI88 1 1231 #define RADEON_TXFORMAT_RGB332 2 1232 #define RADEON_TXFORMAT_ARGB1555 3 1233 #define RADEON_TXFORMAT_RGB565 4 1234 #define RADEON_TXFORMAT_ARGB4444 5 1235 #define RADEON_TXFORMAT_ARGB8888 6 1236 #define RADEON_TXFORMAT_RGBA8888 7 1237 #define RADEON_TXFORMAT_Y8 8 1238 #define RADEON_TXFORMAT_VYUY422 10 1239 #define RADEON_TXFORMAT_YVYU422 11 1240 #define RADEON_TXFORMAT_DXT1 12 1241 #define RADEON_TXFORMAT_DXT23 14 1242 #define RADEON_TXFORMAT_DXT45 15 1243 1244 #define R200_PP_TXCBLEND_0 0x2f00 1245 #define R200_PP_TXCBLEND_1 0x2f10 1246 #define R200_PP_TXCBLEND_2 0x2f20 1247 #define R200_PP_TXCBLEND_3 0x2f30 1248 #define R200_PP_TXCBLEND_4 0x2f40 1249 #define R200_PP_TXCBLEND_5 0x2f50 1250 #define R200_PP_TXCBLEND_6 0x2f60 1251 #define R200_PP_TXCBLEND_7 0x2f70 1252 #define R200_SE_TCL_LIGHT_MODEL_CTL_0 0x2268 1253 #define R200_PP_TFACTOR_0 0x2ee0 1254 #define R200_SE_VTX_FMT_0 0x2088 1255 #define R200_SE_VAP_CNTL 0x2080 1256 #define R200_SE_TCL_MATRIX_SEL_0 0x2230 1257 #define R200_SE_TCL_TEX_PROC_CTL_2 0x22a8 1258 #define R200_SE_TCL_UCP_VERT_BLEND_CTL 0x22c0 1259 #define R200_PP_TXFILTER_5 0x2ca0 1260 #define R200_PP_TXFILTER_4 0x2c80 1261 #define R200_PP_TXFILTER_3 0x2c60 1262 #define R200_PP_TXFILTER_2 0x2c40 1263 #define R200_PP_TXFILTER_1 0x2c20 1264 #define R200_PP_TXFILTER_0 0x2c00 1265 #define R200_PP_TXOFFSET_5 0x2d78 1266 #define R200_PP_TXOFFSET_4 0x2d60 1267 #define R200_PP_TXOFFSET_3 0x2d48 1268 #define R200_PP_TXOFFSET_2 0x2d30 1269 #define R200_PP_TXOFFSET_1 0x2d18 1270 #define R200_PP_TXOFFSET_0 0x2d00 1271 1272 #define R200_PP_CUBIC_FACES_0 0x2c18 1273 #define R200_PP_CUBIC_FACES_1 0x2c38 1274 #define R200_PP_CUBIC_FACES_2 0x2c58 1275 #define R200_PP_CUBIC_FACES_3 0x2c78 1276 #define R200_PP_CUBIC_FACES_4 0x2c98 1277 #define R200_PP_CUBIC_FACES_5 0x2cb8 1278 #define R200_PP_CUBIC_OFFSET_F1_0 0x2d04 1279 #define R200_PP_CUBIC_OFFSET_F2_0 0x2d08 1280 #define R200_PP_CUBIC_OFFSET_F3_0 0x2d0c 1281 #define R200_PP_CUBIC_OFFSET_F4_0 0x2d10 1282 #define R200_PP_CUBIC_OFFSET_F5_0 0x2d14 1283 #define R200_PP_CUBIC_OFFSET_F1_1 0x2d1c 1284 #define R200_PP_CUBIC_OFFSET_F2_1 0x2d20 1285 #define R200_PP_CUBIC_OFFSET_F3_1 0x2d24 1286 #define R200_PP_CUBIC_OFFSET_F4_1 0x2d28 1287 #define R200_PP_CUBIC_OFFSET_F5_1 0x2d2c 1288 #define R200_PP_CUBIC_OFFSET_F1_2 0x2d34 1289 #define R200_PP_CUBIC_OFFSET_F2_2 0x2d38 1290 #define R200_PP_CUBIC_OFFSET_F3_2 0x2d3c 1291 #define R200_PP_CUBIC_OFFSET_F4_2 0x2d40 1292 #define R200_PP_CUBIC_OFFSET_F5_2 0x2d44 1293 #define R200_PP_CUBIC_OFFSET_F1_3 0x2d4c 1294 #define R200_PP_CUBIC_OFFSET_F2_3 0x2d50 1295 #define R200_PP_CUBIC_OFFSET_F3_3 0x2d54 1296 #define R200_PP_CUBIC_OFFSET_F4_3 0x2d58 1297 #define R200_PP_CUBIC_OFFSET_F5_3 0x2d5c 1298 #define R200_PP_CUBIC_OFFSET_F1_4 0x2d64 1299 #define R200_PP_CUBIC_OFFSET_F2_4 0x2d68 1300 #define R200_PP_CUBIC_OFFSET_F3_4 0x2d6c 1301 #define R200_PP_CUBIC_OFFSET_F4_4 0x2d70 1302 #define R200_PP_CUBIC_OFFSET_F5_4 0x2d74 1303 #define R200_PP_CUBIC_OFFSET_F1_5 0x2d7c 1304 #define R200_PP_CUBIC_OFFSET_F2_5 0x2d80 1305 #define R200_PP_CUBIC_OFFSET_F3_5 0x2d84 1306 #define R200_PP_CUBIC_OFFSET_F4_5 0x2d88 1307 #define R200_PP_CUBIC_OFFSET_F5_5 0x2d8c 1308 1309 #define R200_RE_AUX_SCISSOR_CNTL 0x26f0 1310 #define R200_SE_VTE_CNTL 0x20b0 1311 #define R200_SE_TCL_OUTPUT_VTX_COMP_SEL 0x2250 1312 #define R200_PP_TAM_DEBUG3 0x2d9c 1313 #define R200_PP_CNTL_X 0x2cc4 1314 #define R200_SE_VAP_CNTL_STATUS 0x2140 1315 #define R200_RE_SCISSOR_TL_0 0x1cd8 1316 #define R200_RE_SCISSOR_TL_1 0x1ce0 1317 #define R200_RE_SCISSOR_TL_2 0x1ce8 1318 #define R200_RB3D_DEPTHXY_OFFSET 0x1d60 1319 #define R200_RE_AUX_SCISSOR_CNTL 0x26f0 1320 #define R200_SE_VTX_STATE_CNTL 0x2180 1321 #define R200_RE_POINTSIZE 0x2648 1322 #define R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0 0x2254 1323 1324 #define RADEON_PP_TEX_SIZE_0 0x1d04 /* NPOT */ 1325 #define RADEON_PP_TEX_SIZE_1 0x1d0c 1326 #define RADEON_PP_TEX_SIZE_2 0x1d14 1327 1328 #define RADEON_PP_CUBIC_FACES_0 0x1d24 1329 #define RADEON_PP_CUBIC_FACES_1 0x1d28 1330 #define RADEON_PP_CUBIC_FACES_2 0x1d2c 1331 #define RADEON_PP_CUBIC_OFFSET_T0_0 0x1dd0 /* bits [31:5] */ 1332 #define RADEON_PP_CUBIC_OFFSET_T1_0 0x1e00 1333 #define RADEON_PP_CUBIC_OFFSET_T2_0 0x1e14 1334 1335 #define RADEON_SE_TCL_STATE_FLUSH 0x2284 1336 1337 #define SE_VAP_CNTL__TCL_ENA_MASK 0x00000001 1338 #define SE_VAP_CNTL__FORCE_W_TO_ONE_MASK 0x00010000 1339 #define SE_VAP_CNTL__VF_MAX_VTX_NUM__SHIFT 0x00000012 1340 #define SE_VTE_CNTL__VTX_XY_FMT_MASK 0x00000100 1341 #define SE_VTE_CNTL__VTX_Z_FMT_MASK 0x00000200 1342 #define SE_VTX_FMT_0__VTX_Z0_PRESENT_MASK 0x00000001 1343 #define SE_VTX_FMT_0__VTX_W0_PRESENT_MASK 0x00000002 1344 #define SE_VTX_FMT_0__VTX_COLOR_0_FMT__SHIFT 0x0000000b 1345 #define R200_3D_DRAW_IMMD_2 0xC0003500 1346 #define R200_SE_VTX_FMT_1 0x208c 1347 #define R200_RE_CNTL 0x1c50 1348 1349 #define R200_RB3D_BLENDCOLOR 0x3218 1350 1351 #define R200_SE_TCL_POINT_SPRITE_CNTL 0x22c4 1352 1353 #define R200_PP_TRI_PERF 0x2cf8 1354 1355 #define R200_PP_AFS_0 0x2f80 1356 #define R200_PP_AFS_1 0x2f00 /* same as txcblend_0 */ 1357 1358 #define R200_VAP_PVS_CNTL_1 0x22D0 1359 1360 #define RADEON_CRTC_CRNT_FRAME 0x0214 1361 #define RADEON_CRTC2_CRNT_FRAME 0x0314 1362 1363 #define R500_D1CRTC_STATUS 0x609c 1364 #define R500_D2CRTC_STATUS 0x689c 1365 #define R500_CRTC_V_BLANK (1<<0) 1366 1367 #define R500_D1CRTC_FRAME_COUNT 0x60a4 1368 #define R500_D2CRTC_FRAME_COUNT 0x68a4 1369 1370 #define R500_D1MODE_V_COUNTER 0x6530 1371 #define R500_D2MODE_V_COUNTER 0x6d30 1372 1373 #define R500_D1MODE_VBLANK_STATUS 0x6534 1374 #define R500_D2MODE_VBLANK_STATUS 0x6d34 1375 #define R500_VBLANK_OCCURED (1<<0) 1376 #define R500_VBLANK_ACK (1<<4) 1377 #define R500_VBLANK_STAT (1<<12) 1378 #define R500_VBLANK_INT (1<<16) 1379 1380 #define R500_DxMODE_INT_MASK 0x6540 1381 #define R500_D1MODE_INT_MASK (1<<0) 1382 #define R500_D2MODE_INT_MASK (1<<8) 1383 1384 #define R500_DISP_INTERRUPT_STATUS 0x7edc 1385 #define R500_D1_VBLANK_INTERRUPT (1 << 4) 1386 #define R500_D2_VBLANK_INTERRUPT (1 << 5) 1387 1388 /* R6xx/R7xx registers */ 1389 #define R600_MC_VM_FB_LOCATION 0x2180 1390 #define R600_MC_VM_AGP_TOP 0x2184 1391 #define R600_MC_VM_AGP_BOT 0x2188 1392 #define R600_MC_VM_AGP_BASE 0x218c 1393 #define R600_MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2190 1394 #define R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2194 1395 #define R600_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x2198 1396 1397 #define R700_MC_VM_FB_LOCATION 0x2024 1398 #define R700_MC_VM_AGP_TOP 0x2028 1399 #define R700_MC_VM_AGP_BOT 0x202c 1400 #define R700_MC_VM_AGP_BASE 0x2030 1401 #define R700_MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034 1402 #define R700_MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038 1403 #define R700_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203c 1404 1405 #define R600_MCD_RD_A_CNTL 0x219c 1406 #define R600_MCD_RD_B_CNTL 0x21a0 1407 1408 #define R600_MCD_WR_A_CNTL 0x21a4 1409 #define R600_MCD_WR_B_CNTL 0x21a8 1410 1411 #define R600_MCD_RD_SYS_CNTL 0x2200 1412 #define R600_MCD_WR_SYS_CNTL 0x2214 1413 1414 #define R600_MCD_RD_GFX_CNTL 0x21fc 1415 #define R600_MCD_RD_HDP_CNTL 0x2204 1416 #define R600_MCD_RD_PDMA_CNTL 0x2208 1417 #define R600_MCD_RD_SEM_CNTL 0x220c 1418 #define R600_MCD_WR_GFX_CNTL 0x2210 1419 #define R600_MCD_WR_HDP_CNTL 0x2218 1420 #define R600_MCD_WR_PDMA_CNTL 0x221c 1421 #define R600_MCD_WR_SEM_CNTL 0x2220 1422 1423 # define R600_MCD_L1_TLB (1 << 0) 1424 # define R600_MCD_L1_FRAG_PROC (1 << 1) 1425 # define R600_MCD_L1_STRICT_ORDERING (1 << 2) 1426 1427 # define R600_MCD_SYSTEM_ACCESS_MODE_MASK (3 << 6) 1428 # define R600_MCD_SYSTEM_ACCESS_MODE_PA_ONLY (0 << 6) 1429 # define R600_MCD_SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 6) 1430 # define R600_MCD_SYSTEM_ACCESS_MODE_IN_SYS (2 << 6) 1431 # define R600_MCD_SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 6) 1432 1433 # define R600_MCD_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 8) 1434 # define R600_MCD_SYSTEM_APERTURE_UNMAPPED_ACCESS_DEFAULT_PAGE (1 << 8) 1435 1436 # define R600_MCD_SEMAPHORE_MODE (1 << 10) 1437 # define R600_MCD_WAIT_L2_QUERY (1 << 11) 1438 # define R600_MCD_EFFECTIVE_L1_TLB_SIZE(x) ((x) << 12) 1439 # define R600_MCD_EFFECTIVE_L1_QUEUE_SIZE(x) ((x) << 15) 1440 1441 #define R700_MC_VM_MD_L1_TLB0_CNTL 0x2654 1442 #define R700_MC_VM_MD_L1_TLB1_CNTL 0x2658 1443 #define R700_MC_VM_MD_L1_TLB2_CNTL 0x265c 1444 1445 #define R700_MC_VM_MB_L1_TLB0_CNTL 0x2234 1446 #define R700_MC_VM_MB_L1_TLB1_CNTL 0x2238 1447 #define R700_MC_VM_MB_L1_TLB2_CNTL 0x223c 1448 #define R700_MC_VM_MB_L1_TLB3_CNTL 0x2240 1449 1450 # define R700_ENABLE_L1_TLB (1 << 0) 1451 # define R700_ENABLE_L1_FRAGMENT_PROCESSING (1 << 1) 1452 # define R700_SYSTEM_ACCESS_MODE_IN_SYS (2 << 3) 1453 # define R700_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5) 1454 # define R700_EFFECTIVE_L1_TLB_SIZE(x) ((x) << 15) 1455 # define R700_EFFECTIVE_L1_QUEUE_SIZE(x) ((x) << 18) 1456 1457 #define R700_MC_ARB_RAMCFG 0x2760 1458 # define R700_NOOFBANK_SHIFT 0 1459 # define R700_NOOFBANK_MASK 0x3 1460 # define R700_NOOFRANK_SHIFT 2 1461 # define R700_NOOFRANK_MASK 0x1 1462 # define R700_NOOFROWS_SHIFT 3 1463 # define R700_NOOFROWS_MASK 0x7 1464 # define R700_NOOFCOLS_SHIFT 6 1465 # define R700_NOOFCOLS_MASK 0x3 1466 # define R700_CHANSIZE_SHIFT 8 1467 # define R700_CHANSIZE_MASK 0x1 1468 # define R700_BURSTLENGTH_SHIFT 9 1469 # define R700_BURSTLENGTH_MASK 0x1 1470 #define R600_RAMCFG 0x2408 1471 # define R600_NOOFBANK_SHIFT 0 1472 # define R600_NOOFBANK_MASK 0x1 1473 # define R600_NOOFRANK_SHIFT 1 1474 # define R600_NOOFRANK_MASK 0x1 1475 # define R600_NOOFROWS_SHIFT 2 1476 # define R600_NOOFROWS_MASK 0x7 1477 # define R600_NOOFCOLS_SHIFT 5 1478 # define R600_NOOFCOLS_MASK 0x3 1479 # define R600_CHANSIZE_SHIFT 7 1480 # define R600_CHANSIZE_MASK 0x1 1481 # define R600_BURSTLENGTH_SHIFT 8 1482 # define R600_BURSTLENGTH_MASK 0x1 1483 1484 #define R600_VM_L2_CNTL 0x1400 1485 # define R600_VM_L2_CACHE_EN (1 << 0) 1486 # define R600_VM_L2_FRAG_PROC (1 << 1) 1487 # define R600_VM_ENABLE_PTE_CACHE_LRU_W (1 << 9) 1488 # define R600_VM_L2_CNTL_QUEUE_SIZE(x) ((x) << 13) 1489 # define R700_VM_L2_CNTL_QUEUE_SIZE(x) ((x) << 14) 1490 1491 #define R600_VM_L2_CNTL2 0x1404 1492 # define R600_VM_L2_CNTL2_INVALIDATE_ALL_L1_TLBS (1 << 0) 1493 # define R600_VM_L2_CNTL2_INVALIDATE_L2_CACHE (1 << 1) 1494 #define R600_VM_L2_CNTL3 0x1408 1495 # define R600_VM_L2_CNTL3_BANK_SELECT_0(x) ((x) << 0) 1496 # define R600_VM_L2_CNTL3_BANK_SELECT_1(x) ((x) << 5) 1497 # define R600_VM_L2_CNTL3_CACHE_UPDATE_MODE(x) ((x) << 10) 1498 # define R700_VM_L2_CNTL3_BANK_SELECT(x) ((x) << 0) 1499 # define R700_VM_L2_CNTL3_CACHE_UPDATE_MODE(x) ((x) << 6) 1500 1501 #define R600_VM_L2_STATUS 0x140c 1502 1503 #define R600_VM_CONTEXT0_CNTL 0x1410 1504 # define R600_VM_ENABLE_CONTEXT (1 << 0) 1505 # define R600_VM_PAGE_TABLE_DEPTH_FLAT (0 << 1) 1506 1507 #define R600_VM_CONTEXT0_CNTL2 0x1430 1508 #define R600_VM_CONTEXT0_REQUEST_RESPONSE 0x1470 1509 #define R600_VM_CONTEXT0_INVALIDATION_LOW_ADDR 0x1490 1510 #define R600_VM_CONTEXT0_INVALIDATION_HIGH_ADDR 0x14b0 1511 #define R600_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x1574 1512 #define R600_VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x1594 1513 #define R600_VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x15b4 1514 1515 #define R700_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153c 1516 #define R700_VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155c 1517 #define R700_VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157c 1518 1519 #define R600_HDP_HOST_PATH_CNTL 0x2c00 1520 1521 #define R600_GRBM_CNTL 0x8000 1522 # define R600_GRBM_READ_TIMEOUT(x) ((x) << 0) 1523 1524 #define R600_GRBM_STATUS 0x8010 1525 # define R600_CMDFIFO_AVAIL_MASK 0x1f 1526 # define R700_CMDFIFO_AVAIL_MASK 0xf 1527 # define R600_GUI_ACTIVE (1 << 31) 1528 #define R600_GRBM_STATUS2 0x8014 1529 #define R600_GRBM_SOFT_RESET 0x8020 1530 # define R600_SOFT_RESET_CP (1 << 0) 1531 #define R600_WAIT_UNTIL 0x8040 1532 1533 #define R600_CP_SEM_WAIT_TIMER 0x85bc 1534 #define R600_CP_ME_CNTL 0x86d8 1535 # define R600_CP_ME_HALT (1 << 28) 1536 #define R600_CP_QUEUE_THRESHOLDS 0x8760 1537 # define R600_ROQ_IB1_START(x) ((x) << 0) 1538 # define R600_ROQ_IB2_START(x) ((x) << 8) 1539 #define R600_CP_MEQ_THRESHOLDS 0x8764 1540 # define R700_STQ_SPLIT(x) ((x) << 0) 1541 # define R600_MEQ_END(x) ((x) << 16) 1542 # define R600_ROQ_END(x) ((x) << 24) 1543 #define R600_CP_PERFMON_CNTL 0x87fc 1544 #define R600_CP_RB_BASE 0xc100 1545 #define R600_CP_RB_CNTL 0xc104 1546 # define R600_RB_BUFSZ(x) ((x) << 0) 1547 # define R600_RB_BLKSZ(x) ((x) << 8) 1548 # define R600_RB_NO_UPDATE (1 << 27) 1549 # define R600_RB_RPTR_WR_ENA (1 << 31) 1550 #define R600_CP_RB_RPTR_WR 0xc108 1551 #define R600_CP_RB_RPTR_ADDR 0xc10c 1552 #define R600_CP_RB_RPTR_ADDR_HI 0xc110 1553 #define R600_CP_RB_WPTR 0xc114 1554 #define R600_CP_RB_WPTR_ADDR 0xc118 1555 #define R600_CP_RB_WPTR_ADDR_HI 0xc11c 1556 #define R600_CP_RB_RPTR 0x8700 1557 #define R600_CP_RB_WPTR_DELAY 0x8704 1558 #define R600_CP_PFP_UCODE_ADDR 0xc150 1559 #define R600_CP_PFP_UCODE_DATA 0xc154 1560 #define R600_CP_ME_RAM_RADDR 0xc158 1561 #define R600_CP_ME_RAM_WADDR 0xc15c 1562 #define R600_CP_ME_RAM_DATA 0xc160 1563 #define R600_CP_DEBUG 0xc1fc 1564 1565 #define R600_PA_CL_ENHANCE 0x8a14 1566 # define R600_CLIP_VTX_REORDER_ENA (1 << 0) 1567 # define R600_NUM_CLIP_SEQ(x) ((x) << 1) 1568 #define R600_PA_SC_LINE_STIPPLE_STATE 0x8b10 1569 #define R600_PA_SC_MULTI_CHIP_CNTL 0x8b20 1570 #define R700_PA_SC_FORCE_EOV_MAX_CNTS 0x8b24 1571 # define R700_FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0) 1572 # define R700_FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16) 1573 #define R600_PA_SC_AA_SAMPLE_LOCS_2S 0x8b40 1574 #define R600_PA_SC_AA_SAMPLE_LOCS_4S 0x8b44 1575 #define R600_PA_SC_AA_SAMPLE_LOCS_8S_WD0 0x8b48 1576 #define R600_PA_SC_AA_SAMPLE_LOCS_8S_WD1 0x8b4c 1577 # define R600_S0_X(x) ((x) << 0) 1578 # define R600_S0_Y(x) ((x) << 4) 1579 # define R600_S1_X(x) ((x) << 8) 1580 # define R600_S1_Y(x) ((x) << 12) 1581 # define R600_S2_X(x) ((x) << 16) 1582 # define R600_S2_Y(x) ((x) << 20) 1583 # define R600_S3_X(x) ((x) << 24) 1584 # define R600_S3_Y(x) ((x) << 28) 1585 # define R600_S4_X(x) ((x) << 0) 1586 # define R600_S4_Y(x) ((x) << 4) 1587 # define R600_S5_X(x) ((x) << 8) 1588 # define R600_S5_Y(x) ((x) << 12) 1589 # define R600_S6_X(x) ((x) << 16) 1590 # define R600_S6_Y(x) ((x) << 20) 1591 # define R600_S7_X(x) ((x) << 24) 1592 # define R600_S7_Y(x) ((x) << 28) 1593 #define R600_PA_SC_FIFO_SIZE 0x8bd0 1594 # define R600_SC_PRIM_FIFO_SIZE(x) ((x) << 0) 1595 # define R600_SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 8) 1596 # define R600_SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 16) 1597 #define R700_PA_SC_FIFO_SIZE_R7XX 0x8bcc 1598 # define R700_SC_PRIM_FIFO_SIZE(x) ((x) << 0) 1599 # define R700_SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 12) 1600 # define R700_SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 20) 1601 #define R600_PA_SC_ENHANCE 0x8bf0 1602 # define R600_FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0) 1603 # define R600_FORCE_EOV_MAX_TILE_CNT(x) ((x) << 12) 1604 #define R600_PA_SC_CLIPRECT_RULE 0x2820c 1605 #define R700_PA_SC_EDGERULE 0x28230 1606 #define R600_PA_SC_LINE_STIPPLE 0x28a0c 1607 #define R600_PA_SC_MODE_CNTL 0x28a4c 1608 #define R600_PA_SC_AA_CONFIG 0x28c04 1609 1610 #define R600_SX_EXPORT_BUFFER_SIZES 0x900c 1611 # define R600_COLOR_BUFFER_SIZE(x) ((x) << 0) 1612 # define R600_POSITION_BUFFER_SIZE(x) ((x) << 8) 1613 # define R600_SMX_BUFFER_SIZE(x) ((x) << 16) 1614 #define R600_SX_DEBUG_1 0x9054 1615 # define R600_SMX_EVENT_RELEASE (1 << 0) 1616 # define R600_ENABLE_NEW_SMX_ADDRESS (1 << 16) 1617 #define R700_SX_DEBUG_1 0x9058 1618 # define R700_ENABLE_NEW_SMX_ADDRESS (1 << 16) 1619 #define R600_SX_MISC 0x28350 1620 1621 #define R600_DB_DEBUG 0x9830 1622 # define R600_PREZ_MUST_WAIT_FOR_POSTZ_DONE (1 << 31) 1623 #define R600_DB_WATERMARKS 0x9838 1624 # define R600_DEPTH_FREE(x) ((x) << 0) 1625 # define R600_DEPTH_FLUSH(x) ((x) << 5) 1626 # define R600_DEPTH_PENDING_FREE(x) ((x) << 15) 1627 # define R600_DEPTH_CACHELINE_FREE(x) ((x) << 20) 1628 #define R700_DB_DEBUG3 0x98b0 1629 # define R700_DB_CLK_OFF_DELAY(x) ((x) << 11) 1630 #define RV700_DB_DEBUG4 0x9b8c 1631 # define RV700_DISABLE_TILE_COVERED_FOR_PS_ITER (1 << 6) 1632 1633 #define R600_VGT_CACHE_INVALIDATION 0x88c4 1634 # define R600_CACHE_INVALIDATION(x) ((x) << 0) 1635 # define R600_VC_ONLY 0 1636 # define R600_TC_ONLY 1 1637 # define R600_VC_AND_TC 2 1638 # define R700_AUTO_INVLD_EN(x) ((x) << 6) 1639 # define R700_NO_AUTO 0 1640 # define R700_ES_AUTO 1 1641 # define R700_GS_AUTO 2 1642 # define R700_ES_AND_GS_AUTO 3 1643 #define R600_VGT_GS_PER_ES 0x88c8 1644 #define R600_VGT_ES_PER_GS 0x88cc 1645 #define R600_VGT_GS_PER_VS 0x88e8 1646 #define R600_VGT_GS_VERTEX_REUSE 0x88d4 1647 #define R600_VGT_NUM_INSTANCES 0x8974 1648 #define R600_VGT_STRMOUT_EN 0x28ab0 1649 #define R600_VGT_EVENT_INITIATOR 0x28a90 1650 # define R600_CACHE_FLUSH_AND_INV_EVENT (0x16 << 0) 1651 #define R600_VGT_VERTEX_REUSE_BLOCK_CNTL 0x28c58 1652 # define R600_VTX_REUSE_DEPTH_MASK 0xff 1653 #define R600_VGT_OUT_DEALLOC_CNTL 0x28c5c 1654 # define R600_DEALLOC_DIST_MASK 0x7f 1655 1656 #define R600_CB_COLOR0_BASE 0x28040 1657 #define R600_CB_COLOR1_BASE 0x28044 1658 #define R600_CB_COLOR2_BASE 0x28048 1659 #define R600_CB_COLOR3_BASE 0x2804c 1660 #define R600_CB_COLOR4_BASE 0x28050 1661 #define R600_CB_COLOR5_BASE 0x28054 1662 #define R600_CB_COLOR6_BASE 0x28058 1663 #define R600_CB_COLOR7_BASE 0x2805c 1664 #define R600_CB_COLOR7_FRAG 0x280fc 1665 1666 #define R600_TC_CNTL 0x9608 1667 # define R600_TC_L2_SIZE(x) ((x) << 5) 1668 # define R600_L2_DISABLE_LATE_HIT (1 << 9) 1669 1670 #define R600_ARB_POP 0x2418 1671 # define R600_ENABLE_TC128 (1 << 30) 1672 #define R600_ARB_GDEC_RD_CNTL 0x246c 1673 1674 #define R600_TA_CNTL_AUX 0x9508 1675 # define R600_DISABLE_CUBE_WRAP (1 << 0) 1676 # define R600_DISABLE_CUBE_ANISO (1 << 1) 1677 # define R700_GETLOD_SELECT(x) ((x) << 2) 1678 # define R600_SYNC_GRADIENT (1 << 24) 1679 # define R600_SYNC_WALKER (1 << 25) 1680 # define R600_SYNC_ALIGNER (1 << 26) 1681 # define R600_BILINEAR_PRECISION_6_BIT (0 << 31) 1682 # define R600_BILINEAR_PRECISION_8_BIT (1 << 31) 1683 1684 #define R700_TCP_CNTL 0x9610 1685 1686 #define R600_SMX_DC_CTL0 0xa020 1687 # define R700_USE_HASH_FUNCTION (1 << 0) 1688 # define R700_CACHE_DEPTH(x) ((x) << 1) 1689 # define R700_FLUSH_ALL_ON_EVENT (1 << 10) 1690 # define R700_STALL_ON_EVENT (1 << 11) 1691 #define R700_SMX_EVENT_CTL 0xa02c 1692 # define R700_ES_FLUSH_CTL(x) ((x) << 0) 1693 # define R700_GS_FLUSH_CTL(x) ((x) << 3) 1694 # define R700_ACK_FLUSH_CTL(x) ((x) << 6) 1695 # define R700_SYNC_FLUSH_CTL (1 << 8) 1696 1697 #define R600_SQ_CONFIG 0x8c00 1698 # define R600_VC_ENABLE (1 << 0) 1699 # define R600_EXPORT_SRC_C (1 << 1) 1700 # define R600_DX9_CONSTS (1 << 2) 1701 # define R600_ALU_INST_PREFER_VECTOR (1 << 3) 1702 # define R600_DX10_CLAMP (1 << 4) 1703 # define R600_CLAUSE_SEQ_PRIO(x) ((x) << 8) 1704 # define R600_PS_PRIO(x) ((x) << 24) 1705 # define R600_VS_PRIO(x) ((x) << 26) 1706 # define R600_GS_PRIO(x) ((x) << 28) 1707 # define R600_ES_PRIO(x) ((x) << 30) 1708 #define R600_SQ_GPR_RESOURCE_MGMT_1 0x8c04 1709 # define R600_NUM_PS_GPRS(x) ((x) << 0) 1710 # define R600_NUM_VS_GPRS(x) ((x) << 16) 1711 # define R700_DYN_GPR_ENABLE (1 << 27) 1712 # define R600_NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28) 1713 #define R600_SQ_GPR_RESOURCE_MGMT_2 0x8c08 1714 # define R600_NUM_GS_GPRS(x) ((x) << 0) 1715 # define R600_NUM_ES_GPRS(x) ((x) << 16) 1716 #define R600_SQ_THREAD_RESOURCE_MGMT 0x8c0c 1717 # define R600_NUM_PS_THREADS(x) ((x) << 0) 1718 # define R600_NUM_VS_THREADS(x) ((x) << 8) 1719 # define R600_NUM_GS_THREADS(x) ((x) << 16) 1720 # define R600_NUM_ES_THREADS(x) ((x) << 24) 1721 #define R600_SQ_STACK_RESOURCE_MGMT_1 0x8c10 1722 # define R600_NUM_PS_STACK_ENTRIES(x) ((x) << 0) 1723 # define R600_NUM_VS_STACK_ENTRIES(x) ((x) << 16) 1724 #define R600_SQ_STACK_RESOURCE_MGMT_2 0x8c14 1725 # define R600_NUM_GS_STACK_ENTRIES(x) ((x) << 0) 1726 # define R600_NUM_ES_STACK_ENTRIES(x) ((x) << 16) 1727 #define R600_SQ_MS_FIFO_SIZES 0x8cf0 1728 # define R600_CACHE_FIFO_SIZE(x) ((x) << 0) 1729 # define R600_FETCH_FIFO_HIWATER(x) ((x) << 8) 1730 # define R600_DONE_FIFO_HIWATER(x) ((x) << 16) 1731 # define R600_ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24) 1732 #define R700_SQ_DYN_GPR_SIZE_SIMD_AB_0 0x8db0 1733 # define R700_SIMDA_RING0(x) ((x) << 0) 1734 # define R700_SIMDA_RING1(x) ((x) << 8) 1735 # define R700_SIMDB_RING0(x) ((x) << 16) 1736 # define R700_SIMDB_RING1(x) ((x) << 24) 1737 #define R700_SQ_DYN_GPR_SIZE_SIMD_AB_1 0x8db4 1738 #define R700_SQ_DYN_GPR_SIZE_SIMD_AB_2 0x8db8 1739 #define R700_SQ_DYN_GPR_SIZE_SIMD_AB_3 0x8dbc 1740 #define R700_SQ_DYN_GPR_SIZE_SIMD_AB_4 0x8dc0 1741 #define R700_SQ_DYN_GPR_SIZE_SIMD_AB_5 0x8dc4 1742 #define R700_SQ_DYN_GPR_SIZE_SIMD_AB_6 0x8dc8 1743 #define R700_SQ_DYN_GPR_SIZE_SIMD_AB_7 0x8dcc 1744 1745 #define R600_SPI_PS_IN_CONTROL_0 0x286cc 1746 # define R600_NUM_INTERP(x) ((x) << 0) 1747 # define R600_POSITION_ENA (1 << 8) 1748 # define R600_POSITION_CENTROID (1 << 9) 1749 # define R600_POSITION_ADDR(x) ((x) << 10) 1750 # define R600_PARAM_GEN(x) ((x) << 15) 1751 # define R600_PARAM_GEN_ADDR(x) ((x) << 19) 1752 # define R600_BARYC_SAMPLE_CNTL(x) ((x) << 26) 1753 # define R600_PERSP_GRADIENT_ENA (1 << 28) 1754 # define R600_LINEAR_GRADIENT_ENA (1 << 29) 1755 # define R600_POSITION_SAMPLE (1 << 30) 1756 # define R600_BARYC_AT_SAMPLE_ENA (1 << 31) 1757 #define R600_SPI_PS_IN_CONTROL_1 0x286d0 1758 # define R600_GEN_INDEX_PIX (1 << 0) 1759 # define R600_GEN_INDEX_PIX_ADDR(x) ((x) << 1) 1760 # define R600_FRONT_FACE_ENA (1 << 8) 1761 # define R600_FRONT_FACE_CHAN(x) ((x) << 9) 1762 # define R600_FRONT_FACE_ALL_BITS (1 << 11) 1763 # define R600_FRONT_FACE_ADDR(x) ((x) << 12) 1764 # define R600_FOG_ADDR(x) ((x) << 17) 1765 # define R600_FIXED_PT_POSITION_ENA (1 << 24) 1766 # define R600_FIXED_PT_POSITION_ADDR(x) ((x) << 25) 1767 # define R700_POSITION_ULC (1 << 30) 1768 #define R600_SPI_INPUT_Z 0x286d8 1769 1770 #define R600_SPI_CONFIG_CNTL 0x9100 1771 # define R600_GPR_WRITE_PRIORITY(x) ((x) << 0) 1772 # define R600_DISABLE_INTERP_1 (1 << 5) 1773 #define R600_SPI_CONFIG_CNTL_1 0x913c 1774 # define R600_VTX_DONE_DELAY(x) ((x) << 0) 1775 # define R600_INTERP_ONE_PRIM_PER_ROW (1 << 4) 1776 1777 #define R600_GB_TILING_CONFIG 0x98f0 1778 # define R600_PIPE_TILING(x) ((x) << 1) 1779 # define R600_BANK_TILING(x) ((x) << 4) 1780 # define R600_GROUP_SIZE(x) ((x) << 6) 1781 # define R600_ROW_TILING(x) ((x) << 8) 1782 # define R600_BANK_SWAPS(x) ((x) << 11) 1783 # define R600_SAMPLE_SPLIT(x) ((x) << 14) 1784 # define R600_BACKEND_MAP(x) ((x) << 16) 1785 #define R600_DCP_TILING_CONFIG 0x6ca0 1786 #define R600_HDP_TILING_CONFIG 0x2f3c 1787 1788 #define R600_CC_RB_BACKEND_DISABLE 0x98f4 1789 #define R700_CC_SYS_RB_BACKEND_DISABLE 0x3f88 1790 # define R600_BACKEND_DISABLE(x) ((x) << 16) 1791 1792 #define R600_CC_GC_SHADER_PIPE_CONFIG 0x8950 1793 #define R600_GC_USER_SHADER_PIPE_CONFIG 0x8954 1794 # define R600_INACTIVE_QD_PIPES(x) ((x) << 8) 1795 # define R600_INACTIVE_QD_PIPES_MASK (0xff << 8) 1796 # define R600_INACTIVE_SIMDS(x) ((x) << 16) 1797 # define R600_INACTIVE_SIMDS_MASK (0xff << 16) 1798 1799 #define R700_CGTS_SYS_TCC_DISABLE 0x3f90 1800 #define R700_CGTS_USER_SYS_TCC_DISABLE 0x3f94 1801 #define R700_CGTS_TCC_DISABLE 0x9148 1802 #define R700_CGTS_USER_TCC_DISABLE 0x914c 1803 1804 /* Constants */ 1805 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 1806 1807 #define RADEON_LAST_FRAME_REG RADEON_SCRATCH_REG0 1808 #define RADEON_LAST_DISPATCH_REG RADEON_SCRATCH_REG1 1809 #define RADEON_LAST_CLEAR_REG RADEON_SCRATCH_REG2 1810 #define RADEON_LAST_SWI_REG RADEON_SCRATCH_REG3 1811 #define RADEON_LAST_DISPATCH 1 1812 1813 #define R600_LAST_FRAME_REG R600_SCRATCH_REG0 1814 #define R600_LAST_DISPATCH_REG R600_SCRATCH_REG1 1815 #define R600_LAST_CLEAR_REG R600_SCRATCH_REG2 1816 #define R600_LAST_SWI_REG R600_SCRATCH_REG3 1817 1818 #define RADEON_MAX_VB_AGE 0x7fffffff 1819 #define RADEON_MAX_VB_VERTS (0xffff) 1820 1821 #define RADEON_RING_HIGH_MARK 128 1822 1823 #define RADEON_PCIGART_TABLE_SIZE (32*1024) 1824 1825 #define RADEON_READ(reg) DRM_READ32( dev_priv->mmio, (reg) ) 1826 #define RADEON_WRITE(reg, val) \ 1827 do { \ 1828 if (reg < 0x10000) { \ 1829 DRM_WRITE32(dev_priv->mmio, (reg), (val)); \ 1830 } else { \ 1831 DRM_WRITE32(dev_priv->mmio, RADEON_MM_INDEX, (reg)); \ 1832 DRM_WRITE32(dev_priv->mmio, RADEON_MM_DATA, (val)); \ 1833 } \ 1834 } while (0) 1835 #define RADEON_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) ) 1836 #define RADEON_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) ) 1837 1838 #define RADEON_WRITE_PLL(addr, val) \ 1839 do { \ 1840 RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, \ 1841 ((addr) & 0x1f) | RADEON_PLL_WR_EN ); \ 1842 RADEON_WRITE(RADEON_CLOCK_CNTL_DATA, (val)); \ 1843 } while (0) 1844 1845 #define RADEON_WRITE_PCIE(addr, val) \ 1846 do { \ 1847 RADEON_WRITE8(RADEON_PCIE_INDEX, \ 1848 ((addr) & 0xff)); \ 1849 RADEON_WRITE(RADEON_PCIE_DATA, (val)); \ 1850 } while (0) 1851 1852 #define R500_WRITE_MCIND(addr, val) \ 1853 do { \ 1854 RADEON_WRITE(R520_MC_IND_INDEX, 0xff0000 | ((addr) & 0xff)); \ 1855 RADEON_WRITE(R520_MC_IND_DATA, (val)); \ 1856 RADEON_WRITE(R520_MC_IND_INDEX, 0); \ 1857 } while (0) 1858 1859 #define RS480_WRITE_MCIND(addr, val) \ 1860 do { \ 1861 RADEON_WRITE(RS480_NB_MC_INDEX, \ 1862 ((addr) & 0xff) | RS480_NB_MC_IND_WR_EN); \ 1863 RADEON_WRITE(RS480_NB_MC_DATA, (val)); \ 1864 RADEON_WRITE(RS480_NB_MC_INDEX, 0xff); \ 1865 } while (0) 1866 1867 #define RS690_WRITE_MCIND(addr, val) \ 1868 do { \ 1869 RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_EN | ((addr) & RS690_MC_INDEX_MASK)); \ 1870 RADEON_WRITE(RS690_MC_DATA, val); \ 1871 RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_ACK); \ 1872 } while (0) 1873 1874 #define RS600_WRITE_MCIND(addr, val) \ 1875 do { \ 1876 RADEON_WRITE(RS600_MC_INDEX, RS600_MC_IND_WR_EN | RS600_MC_IND_CITF_ARB0 | ((addr) & RS600_MC_ADDR_MASK)); \ 1877 RADEON_WRITE(RS600_MC_DATA, val); \ 1878 } while (0) 1879 1880 #define IGP_WRITE_MCIND(addr, val) \ 1881 do { \ 1882 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || \ 1883 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) \ 1884 RS690_WRITE_MCIND(addr, val); \ 1885 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) \ 1886 RS600_WRITE_MCIND(addr, val); \ 1887 else \ 1888 RS480_WRITE_MCIND(addr, val); \ 1889 } while (0) 1890 1891 #define CP_PACKET0( reg, n ) \ 1892 (RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2)) 1893 #define CP_PACKET0_TABLE( reg, n ) \ 1894 (RADEON_CP_PACKET0 | RADEON_ONE_REG_WR | ((n) << 16) | ((reg) >> 2)) 1895 #define CP_PACKET1( reg0, reg1 ) \ 1896 (RADEON_CP_PACKET1 | (((reg1) >> 2) << 15) | ((reg0) >> 2)) 1897 #define CP_PACKET2() \ 1898 (RADEON_CP_PACKET2) 1899 #define CP_PACKET3( pkt, n ) \ 1900 (RADEON_CP_PACKET3 | (pkt) | ((n) << 16)) 1901 1902 /* ================================================================ 1903 * Engine control helper macros 1904 */ 1905 1906 #define RADEON_WAIT_UNTIL_2D_IDLE() do { \ 1907 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) \ 1908 OUT_RING( CP_PACKET0( R600_WAIT_UNTIL, 0 ) ); \ 1909 else \ 1910 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ 1911 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \ 1912 RADEON_WAIT_HOST_IDLECLEAN) ); \ 1913 } while (0) 1914 1915 #define RADEON_WAIT_UNTIL_3D_IDLE() do { \ 1916 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) \ 1917 OUT_RING( CP_PACKET0( R600_WAIT_UNTIL, 0 ) ); \ 1918 else \ 1919 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ 1920 OUT_RING( (RADEON_WAIT_3D_IDLECLEAN | \ 1921 RADEON_WAIT_HOST_IDLECLEAN) ); \ 1922 } while (0) 1923 1924 #define RADEON_WAIT_UNTIL_IDLE() do { \ 1925 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) \ 1926 OUT_RING( CP_PACKET0( R600_WAIT_UNTIL, 0 ) ); \ 1927 else \ 1928 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ 1929 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \ 1930 RADEON_WAIT_3D_IDLECLEAN | \ 1931 RADEON_WAIT_HOST_IDLECLEAN) ); \ 1932 } while (0) 1933 1934 #define RADEON_WAIT_UNTIL_PAGE_FLIPPED() do { \ 1935 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) \ 1936 OUT_RING( CP_PACKET0( R600_WAIT_UNTIL, 0 ) ); \ 1937 else \ 1938 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \ 1939 OUT_RING( RADEON_WAIT_CRTC_PFLIP ); \ 1940 } while (0) 1941 1942 #define RADEON_FLUSH_CACHE() do { \ 1943 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \ 1944 OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \ 1945 OUT_RING(RADEON_RB3D_DC_FLUSH); \ 1946 } else { \ 1947 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); \ 1948 OUT_RING(R300_RB3D_DC_FLUSH); \ 1949 } \ 1950 } while (0) 1951 1952 #define RADEON_PURGE_CACHE() do { \ 1953 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \ 1954 OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \ 1955 OUT_RING(RADEON_RB3D_DC_FLUSH | RADEON_RB3D_DC_FREE); \ 1956 } else { \ 1957 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); \ 1958 OUT_RING(R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE); \ 1959 } \ 1960 } while (0) 1961 1962 #define RADEON_FLUSH_ZCACHE() do { \ 1963 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \ 1964 OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); \ 1965 OUT_RING(RADEON_RB3D_ZC_FLUSH); \ 1966 } else { \ 1967 OUT_RING(CP_PACKET0(R300_ZB_ZCACHE_CTLSTAT, 0)); \ 1968 OUT_RING(R300_ZC_FLUSH); \ 1969 } \ 1970 } while (0) 1971 1972 #define RADEON_PURGE_ZCACHE() do { \ 1973 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \ 1974 OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); \ 1975 OUT_RING(RADEON_RB3D_ZC_FLUSH | RADEON_RB3D_ZC_FREE); \ 1976 } else { \ 1977 OUT_RING(CP_PACKET0(R300_ZB_ZCACHE_CTLSTAT, 0)); \ 1978 OUT_RING(R300_ZC_FLUSH | R300_ZC_FREE); \ 1979 } \ 1980 } while (0) 1981 1982 /* ================================================================ 1983 * Misc helper macros 1984 */ 1985 1986 /* Perfbox functionality only. 1987 */ 1988 #define RING_SPACE_TEST_WITH_RETURN( dev_priv ) \ 1989 do { \ 1990 if (!(dev_priv->stats.boxes & RADEON_BOX_DMA_IDLE)) { \ 1991 u32 head = GET_RING_HEAD( dev_priv ); \ 1992 if (head == dev_priv->ring.tail) \ 1993 dev_priv->stats.boxes |= RADEON_BOX_DMA_IDLE; \ 1994 } \ 1995 } while (0) 1996 1997 #define VB_AGE_TEST_WITH_RETURN( dev_priv ) \ 1998 do { \ 1999 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; \ 2000 if ( sarea_priv->last_dispatch >= RADEON_MAX_VB_AGE ) { \ 2001 int __ret; \ 2002 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) \ 2003 __ret = r600_do_cp_idle(dev_priv); \ 2004 else \ 2005 __ret = radeon_do_cp_idle(dev_priv); \ 2006 if ( __ret ) return __ret; \ 2007 sarea_priv->last_dispatch = 0; \ 2008 radeon_freelist_reset( dev ); \ 2009 } \ 2010 } while (0) 2011 2012 #define RADEON_DISPATCH_AGE( age ) do { \ 2013 OUT_RING( CP_PACKET0( RADEON_LAST_DISPATCH_REG, 0 ) ); \ 2014 OUT_RING( age ); \ 2015 } while (0) 2016 2017 #define RADEON_FRAME_AGE( age ) do { \ 2018 OUT_RING( CP_PACKET0( RADEON_LAST_FRAME_REG, 0 ) ); \ 2019 OUT_RING( age ); \ 2020 } while (0) 2021 2022 #define RADEON_CLEAR_AGE( age ) do { \ 2023 OUT_RING( CP_PACKET0( RADEON_LAST_CLEAR_REG, 0 ) ); \ 2024 OUT_RING( age ); \ 2025 } while (0) 2026 2027 #define R600_DISPATCH_AGE(age) do { \ 2028 OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); \ 2029 OUT_RING((R600_LAST_DISPATCH_REG - R600_SET_CONFIG_REG_OFFSET) >> 2); \ 2030 OUT_RING(age); \ 2031 } while (0) 2032 2033 #define R600_FRAME_AGE(age) do { \ 2034 OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); \ 2035 OUT_RING((R600_LAST_FRAME_REG - R600_SET_CONFIG_REG_OFFSET) >> 2); \ 2036 OUT_RING(age); \ 2037 } while (0) 2038 2039 #define R600_CLEAR_AGE(age) do { \ 2040 OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); \ 2041 OUT_RING((R600_LAST_CLEAR_REG - R600_SET_CONFIG_REG_OFFSET) >> 2); \ 2042 OUT_RING(age); \ 2043 } while (0) 2044 2045 /* ================================================================ 2046 * Ring control 2047 */ 2048 2049 #define RADEON_VERBOSE 0 2050 2051 #define RING_LOCALS int write, _nr, _align_nr; unsigned int mask; u32 *ring; 2052 2053 #define RADEON_RING_ALIGN 16 2054 2055 #define BEGIN_RING( n ) do { \ 2056 if ( RADEON_VERBOSE ) { \ 2057 DRM_INFO( "BEGIN_RING( %d )\n", (n)); \ 2058 } \ 2059 _align_nr = RADEON_RING_ALIGN - ((dev_priv->ring.tail + n) & (RADEON_RING_ALIGN - 1)); \ 2060 _align_nr += n; \ 2061 if ( dev_priv->ring.space <= (_align_nr) * sizeof(u32) ) { \ 2062 COMMIT_RING(); \ 2063 radeon_wait_ring( dev_priv, (_align_nr) * sizeof(u32) ); \ 2064 } \ 2065 _nr = n; dev_priv->ring.space -= (n) * sizeof(u32); \ 2066 ring = dev_priv->ring.start; \ 2067 write = dev_priv->ring.tail; \ 2068 mask = dev_priv->ring.tail_mask; \ 2069 } while (0) 2070 2071 #define ADVANCE_RING() do { \ 2072 if ( RADEON_VERBOSE ) { \ 2073 DRM_INFO( "ADVANCE_RING() wr=0x%06x tail=0x%06x\n", \ 2074 write, dev_priv->ring.tail ); \ 2075 } \ 2076 if (((dev_priv->ring.tail + _nr) & mask) != write) { \ 2077 DRM_ERROR( \ 2078 "ADVANCE_RING(): mismatch: nr: %x write: %x line: %d\n", \ 2079 ((dev_priv->ring.tail + _nr) & mask), \ 2080 write, __LINE__); \ 2081 } else \ 2082 dev_priv->ring.tail = write; \ 2083 } while (0) 2084 2085 extern void radeon_commit_ring(drm_radeon_private_t *dev_priv); 2086 2087 #define COMMIT_RING() do { \ 2088 radeon_commit_ring(dev_priv); \ 2089 } while(0) 2090 2091 #define OUT_RING( x ) do { \ 2092 if ( RADEON_VERBOSE ) { \ 2093 DRM_INFO( " OUT_RING( 0x%08x ) at 0x%x\n", \ 2094 (unsigned int)(x), write ); \ 2095 } \ 2096 ring[write++] = (x); \ 2097 write &= mask; \ 2098 } while (0) 2099 2100 #define OUT_RING_REG( reg, val ) do { \ 2101 OUT_RING( CP_PACKET0( reg, 0 ) ); \ 2102 OUT_RING( val ); \ 2103 } while (0) 2104 2105 #define OUT_RING_TABLE( tab, sz ) do { \ 2106 int _size = (sz); \ 2107 int *_tab = (int *)(tab); \ 2108 \ 2109 if (write + _size > mask) { \ 2110 int _i = (mask+1) - write; \ 2111 _size -= _i; \ 2112 while (_i > 0 ) { \ 2113 *(int *)(ring + write) = *_tab++; \ 2114 write++; \ 2115 _i--; \ 2116 } \ 2117 write = 0; \ 2118 _tab += _i; \ 2119 } \ 2120 while (_size > 0) { \ 2121 *(ring + write) = *_tab++; \ 2122 write++; \ 2123 _size--; \ 2124 } \ 2125 write &= mask; \ 2126 } while (0) 2127 2128 #endif /* __RADEON_DRV_H__ */
Cache object: 7cf4d71dd8651d6c87519aa7d557cafd
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