FreeBSD/Linux Kernel Cross Reference
sys/dev/dwc/if_dwc.c
1 /*-
2 * Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com>
3 * All rights reserved.
4 *
5 * This software was developed by SRI International and the University of
6 * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
7 * ("CTSRD"), as part of the DARPA CRASH research programme.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 */
30
31 /*
32 * Ethernet media access controller (EMAC)
33 * Chapter 17, Altera Cyclone V Device Handbook (CV-5V2 2014.07.22)
34 *
35 * EMAC is an instance of the Synopsys DesignWare 3504-0
36 * Universal 10/100/1000 Ethernet MAC (DWC_gmac).
37 */
38
39 #include <sys/cdefs.h>
40 __FBSDID("$FreeBSD: releng/12.0/sys/dev/dwc/if_dwc.c 333813 2018-05-18 20:13:34Z mmacy $");
41
42 #include <sys/param.h>
43 #include <sys/systm.h>
44 #include <sys/bus.h>
45 #include <sys/gpio.h>
46 #include <sys/kernel.h>
47 #include <sys/lock.h>
48 #include <sys/malloc.h>
49 #include <sys/mbuf.h>
50 #include <sys/module.h>
51 #include <sys/mutex.h>
52 #include <sys/rman.h>
53 #include <sys/socket.h>
54 #include <sys/sockio.h>
55
56 #include <net/bpf.h>
57 #include <net/if.h>
58 #include <net/ethernet.h>
59 #include <net/if_dl.h>
60 #include <net/if_media.h>
61 #include <net/if_types.h>
62 #include <net/if_var.h>
63
64 #include <machine/bus.h>
65
66 #include <dev/dwc/if_dwc.h>
67 #include <dev/dwc/if_dwcvar.h>
68 #include <dev/mii/mii.h>
69 #include <dev/mii/miivar.h>
70 #include <dev/ofw/ofw_bus.h>
71 #include <dev/ofw/ofw_bus_subr.h>
72
73 #ifdef EXT_RESOURCES
74 #include <dev/extres/clk/clk.h>
75 #include <dev/extres/hwreset/hwreset.h>
76 #endif
77
78 #include "if_dwc_if.h"
79 #include "gpio_if.h"
80 #include "miibus_if.h"
81
82 #define READ4(_sc, _reg) \
83 bus_read_4((_sc)->res[0], _reg)
84 #define WRITE4(_sc, _reg, _val) \
85 bus_write_4((_sc)->res[0], _reg, _val)
86
87 #define MAC_RESET_TIMEOUT 100
88 #define WATCHDOG_TIMEOUT_SECS 5
89 #define STATS_HARVEST_INTERVAL 2
90
91 #define DWC_LOCK(sc) mtx_lock(&(sc)->mtx)
92 #define DWC_UNLOCK(sc) mtx_unlock(&(sc)->mtx)
93 #define DWC_ASSERT_LOCKED(sc) mtx_assert(&(sc)->mtx, MA_OWNED)
94 #define DWC_ASSERT_UNLOCKED(sc) mtx_assert(&(sc)->mtx, MA_NOTOWNED)
95
96 #define DDESC_TDES0_OWN (1U << 31)
97 #define DDESC_TDES0_TXINT (1U << 30)
98 #define DDESC_TDES0_TXLAST (1U << 29)
99 #define DDESC_TDES0_TXFIRST (1U << 28)
100 #define DDESC_TDES0_TXCRCDIS (1U << 27)
101 #define DDESC_TDES0_TXRINGEND (1U << 21)
102 #define DDESC_TDES0_TXCHAIN (1U << 20)
103
104 #define DDESC_RDES0_OWN (1U << 31)
105 #define DDESC_RDES0_FL_MASK 0x3fff
106 #define DDESC_RDES0_FL_SHIFT 16 /* Frame Length */
107 #define DDESC_RDES1_CHAINED (1U << 14)
108
109 /* Alt descriptor bits. */
110 #define DDESC_CNTL_TXINT (1U << 31)
111 #define DDESC_CNTL_TXLAST (1U << 30)
112 #define DDESC_CNTL_TXFIRST (1U << 29)
113 #define DDESC_CNTL_TXCRCDIS (1U << 26)
114 #define DDESC_CNTL_TXRINGEND (1U << 25)
115 #define DDESC_CNTL_TXCHAIN (1U << 24)
116
117 #define DDESC_CNTL_CHAINED (1U << 24)
118
119 /*
120 * A hardware buffer descriptor. Rx and Tx buffers have the same descriptor
121 * layout, but the bits in the fields have different meanings.
122 */
123 struct dwc_hwdesc
124 {
125 uint32_t tdes0; /* status for alt layout */
126 uint32_t tdes1; /* cntl for alt layout */
127 uint32_t addr; /* pointer to buffer data */
128 uint32_t addr_next; /* link to next descriptor */
129 };
130
131 /*
132 * The hardware imposes alignment restrictions on various objects involved in
133 * DMA transfers. These values are expressed in bytes (not bits).
134 */
135 #define DWC_DESC_RING_ALIGN 2048
136
137 static struct resource_spec dwc_spec[] = {
138 { SYS_RES_MEMORY, 0, RF_ACTIVE },
139 { SYS_RES_IRQ, 0, RF_ACTIVE },
140 { -1, 0 }
141 };
142
143 static void dwc_txfinish_locked(struct dwc_softc *sc);
144 static void dwc_rxfinish_locked(struct dwc_softc *sc);
145 static void dwc_stop_locked(struct dwc_softc *sc);
146 static void dwc_setup_rxfilter(struct dwc_softc *sc);
147
148 static inline uint32_t
149 next_rxidx(struct dwc_softc *sc, uint32_t curidx)
150 {
151
152 return ((curidx + 1) % RX_DESC_COUNT);
153 }
154
155 static inline uint32_t
156 next_txidx(struct dwc_softc *sc, uint32_t curidx)
157 {
158
159 return ((curidx + 1) % TX_DESC_COUNT);
160 }
161
162 static void
163 dwc_get1paddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
164 {
165
166 if (error != 0)
167 return;
168 *(bus_addr_t *)arg = segs[0].ds_addr;
169 }
170
171 inline static uint32_t
172 dwc_setup_txdesc(struct dwc_softc *sc, int idx, bus_addr_t paddr,
173 uint32_t len)
174 {
175 uint32_t flags;
176 uint32_t nidx;
177
178 nidx = next_txidx(sc, idx);
179
180 /* Addr/len 0 means we're clearing the descriptor after xmit done. */
181 if (paddr == 0 || len == 0) {
182 flags = 0;
183 --sc->txcount;
184 } else {
185 if (sc->mactype == DWC_GMAC_ALT_DESC)
186 flags = DDESC_CNTL_TXCHAIN | DDESC_CNTL_TXFIRST
187 | DDESC_CNTL_TXLAST | DDESC_CNTL_TXINT;
188 else
189 flags = DDESC_TDES0_TXCHAIN | DDESC_TDES0_TXFIRST
190 | DDESC_TDES0_TXLAST | DDESC_TDES0_TXINT;
191 ++sc->txcount;
192 }
193
194 sc->txdesc_ring[idx].addr = (uint32_t)(paddr);
195 if (sc->mactype == DWC_GMAC_ALT_DESC) {
196 sc->txdesc_ring[idx].tdes0 = 0;
197 sc->txdesc_ring[idx].tdes1 = flags | len;
198 } else {
199 sc->txdesc_ring[idx].tdes0 = flags;
200 sc->txdesc_ring[idx].tdes1 = len;
201 }
202
203 if (paddr && len) {
204 wmb();
205 sc->txdesc_ring[idx].tdes0 |= DDESC_TDES0_OWN;
206 wmb();
207 }
208
209 return (nidx);
210 }
211
212 static int
213 dwc_setup_txbuf(struct dwc_softc *sc, int idx, struct mbuf **mp)
214 {
215 struct bus_dma_segment seg;
216 int error, nsegs;
217 struct mbuf * m;
218
219 if ((m = m_defrag(*mp, M_NOWAIT)) == NULL)
220 return (ENOMEM);
221 *mp = m;
222
223 error = bus_dmamap_load_mbuf_sg(sc->txbuf_tag, sc->txbuf_map[idx].map,
224 m, &seg, &nsegs, 0);
225 if (error != 0) {
226 return (ENOMEM);
227 }
228
229 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
230
231 bus_dmamap_sync(sc->txbuf_tag, sc->txbuf_map[idx].map,
232 BUS_DMASYNC_PREWRITE);
233
234 sc->txbuf_map[idx].mbuf = m;
235
236 dwc_setup_txdesc(sc, idx, seg.ds_addr, seg.ds_len);
237
238 return (0);
239 }
240
241 static void
242 dwc_txstart_locked(struct dwc_softc *sc)
243 {
244 struct ifnet *ifp;
245 struct mbuf *m;
246 int enqueued;
247
248 DWC_ASSERT_LOCKED(sc);
249
250 if (!sc->link_is_up)
251 return;
252
253 ifp = sc->ifp;
254
255 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) {
256 return;
257 }
258
259 enqueued = 0;
260
261 for (;;) {
262 if (sc->txcount == (TX_DESC_COUNT-1)) {
263 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
264 break;
265 }
266
267 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
268 if (m == NULL)
269 break;
270 if (dwc_setup_txbuf(sc, sc->tx_idx_head, &m) != 0) {
271 IFQ_DRV_PREPEND(&ifp->if_snd, m);
272 break;
273 }
274 BPF_MTAP(ifp, m);
275 sc->tx_idx_head = next_txidx(sc, sc->tx_idx_head);
276 ++enqueued;
277 }
278
279 if (enqueued != 0) {
280 WRITE4(sc, TRANSMIT_POLL_DEMAND, 0x1);
281 sc->tx_watchdog_count = WATCHDOG_TIMEOUT_SECS;
282 }
283 }
284
285 static void
286 dwc_txstart(struct ifnet *ifp)
287 {
288 struct dwc_softc *sc = ifp->if_softc;
289
290 DWC_LOCK(sc);
291 dwc_txstart_locked(sc);
292 DWC_UNLOCK(sc);
293 }
294
295 static void
296 dwc_stop_locked(struct dwc_softc *sc)
297 {
298 struct ifnet *ifp;
299 uint32_t reg;
300
301 DWC_ASSERT_LOCKED(sc);
302
303 ifp = sc->ifp;
304 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
305 sc->tx_watchdog_count = 0;
306 sc->stats_harvest_count = 0;
307
308 callout_stop(&sc->dwc_callout);
309
310 /* Stop DMA TX */
311 reg = READ4(sc, OPERATION_MODE);
312 reg &= ~(MODE_ST);
313 WRITE4(sc, OPERATION_MODE, reg);
314
315 /* Flush TX */
316 reg = READ4(sc, OPERATION_MODE);
317 reg |= (MODE_FTF);
318 WRITE4(sc, OPERATION_MODE, reg);
319
320 /* Stop transmitters */
321 reg = READ4(sc, MAC_CONFIGURATION);
322 reg &= ~(CONF_TE | CONF_RE);
323 WRITE4(sc, MAC_CONFIGURATION, reg);
324
325 /* Stop DMA RX */
326 reg = READ4(sc, OPERATION_MODE);
327 reg &= ~(MODE_SR);
328 WRITE4(sc, OPERATION_MODE, reg);
329 }
330
331 static void dwc_clear_stats(struct dwc_softc *sc)
332 {
333 uint32_t reg;
334
335 reg = READ4(sc, MMC_CONTROL);
336 reg |= (MMC_CONTROL_CNTRST);
337 WRITE4(sc, MMC_CONTROL, reg);
338 }
339
340 static void
341 dwc_harvest_stats(struct dwc_softc *sc)
342 {
343 struct ifnet *ifp;
344
345 /* We don't need to harvest too often. */
346 if (++sc->stats_harvest_count < STATS_HARVEST_INTERVAL)
347 return;
348
349 sc->stats_harvest_count = 0;
350 ifp = sc->ifp;
351
352 if_inc_counter(ifp, IFCOUNTER_IPACKETS, READ4(sc, RXFRAMECOUNT_GB));
353 if_inc_counter(ifp, IFCOUNTER_IMCASTS, READ4(sc, RXMULTICASTFRAMES_G));
354 if_inc_counter(ifp, IFCOUNTER_IERRORS,
355 READ4(sc, RXOVERSIZE_G) + READ4(sc, RXUNDERSIZE_G) +
356 READ4(sc, RXCRCERROR) + READ4(sc, RXALIGNMENTERROR) +
357 READ4(sc, RXRUNTERROR) + READ4(sc, RXJABBERERROR) +
358 READ4(sc, RXLENGTHERROR));
359
360 if_inc_counter(ifp, IFCOUNTER_OPACKETS, READ4(sc, TXFRAMECOUNT_G));
361 if_inc_counter(ifp, IFCOUNTER_OMCASTS, READ4(sc, TXMULTICASTFRAMES_G));
362 if_inc_counter(ifp, IFCOUNTER_OERRORS,
363 READ4(sc, TXOVERSIZE_G) + READ4(sc, TXEXCESSDEF) +
364 READ4(sc, TXCARRIERERR) + READ4(sc, TXUNDERFLOWERROR));
365
366 if_inc_counter(ifp, IFCOUNTER_COLLISIONS,
367 READ4(sc, TXEXESSCOL) + READ4(sc, TXLATECOL));
368
369 dwc_clear_stats(sc);
370 }
371
372 static void
373 dwc_tick(void *arg)
374 {
375 struct dwc_softc *sc;
376 struct ifnet *ifp;
377 int link_was_up;
378
379 sc = arg;
380
381 DWC_ASSERT_LOCKED(sc);
382
383 ifp = sc->ifp;
384
385 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
386 return;
387
388 /*
389 * Typical tx watchdog. If this fires it indicates that we enqueued
390 * packets for output and never got a txdone interrupt for them. Maybe
391 * it's a missed interrupt somehow, just pretend we got one.
392 */
393 if (sc->tx_watchdog_count > 0) {
394 if (--sc->tx_watchdog_count == 0) {
395 dwc_txfinish_locked(sc);
396 }
397 }
398
399 /* Gather stats from hardware counters. */
400 dwc_harvest_stats(sc);
401
402 /* Check the media status. */
403 link_was_up = sc->link_is_up;
404 mii_tick(sc->mii_softc);
405 if (sc->link_is_up && !link_was_up)
406 dwc_txstart_locked(sc);
407
408 /* Schedule another check one second from now. */
409 callout_reset(&sc->dwc_callout, hz, dwc_tick, sc);
410 }
411
412 static void
413 dwc_init_locked(struct dwc_softc *sc)
414 {
415 struct ifnet *ifp = sc->ifp;
416 uint32_t reg;
417
418 DWC_ASSERT_LOCKED(sc);
419
420 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
421 return;
422
423 ifp->if_drv_flags |= IFF_DRV_RUNNING;
424
425 dwc_setup_rxfilter(sc);
426
427 /* Initializa DMA and enable transmitters */
428 reg = READ4(sc, OPERATION_MODE);
429 reg |= (MODE_TSF | MODE_OSF | MODE_FUF);
430 reg &= ~(MODE_RSF);
431 reg |= (MODE_RTC_LEV32 << MODE_RTC_SHIFT);
432 WRITE4(sc, OPERATION_MODE, reg);
433
434 WRITE4(sc, INTERRUPT_ENABLE, INT_EN_DEFAULT);
435
436 /* Start DMA */
437 reg = READ4(sc, OPERATION_MODE);
438 reg |= (MODE_ST | MODE_SR);
439 WRITE4(sc, OPERATION_MODE, reg);
440
441 /* Enable transmitters */
442 reg = READ4(sc, MAC_CONFIGURATION);
443 reg |= (CONF_JD | CONF_ACS | CONF_BE);
444 reg |= (CONF_TE | CONF_RE);
445 WRITE4(sc, MAC_CONFIGURATION, reg);
446
447 /*
448 * Call mii_mediachg() which will call back into dwc_miibus_statchg()
449 * to set up the remaining config registers based on current media.
450 */
451 mii_mediachg(sc->mii_softc);
452 callout_reset(&sc->dwc_callout, hz, dwc_tick, sc);
453 }
454
455 static void
456 dwc_init(void *if_softc)
457 {
458 struct dwc_softc *sc = if_softc;
459
460 DWC_LOCK(sc);
461 dwc_init_locked(sc);
462 DWC_UNLOCK(sc);
463 }
464
465 inline static uint32_t
466 dwc_setup_rxdesc(struct dwc_softc *sc, int idx, bus_addr_t paddr)
467 {
468 uint32_t nidx;
469
470 sc->rxdesc_ring[idx].addr = (uint32_t)paddr;
471 nidx = next_rxidx(sc, idx);
472 sc->rxdesc_ring[idx].addr_next = sc->rxdesc_ring_paddr + \
473 (nidx * sizeof(struct dwc_hwdesc));
474 if (sc->mactype == DWC_GMAC_ALT_DESC)
475 sc->rxdesc_ring[idx].tdes1 = DDESC_CNTL_CHAINED | RX_MAX_PACKET;
476 else
477 sc->rxdesc_ring[idx].tdes1 = DDESC_RDES1_CHAINED | MCLBYTES;
478
479 wmb();
480 sc->rxdesc_ring[idx].tdes0 = DDESC_RDES0_OWN;
481 wmb();
482
483 return (nidx);
484 }
485
486 static int
487 dwc_setup_rxbuf(struct dwc_softc *sc, int idx, struct mbuf *m)
488 {
489 struct bus_dma_segment seg;
490 int error, nsegs;
491
492 m_adj(m, ETHER_ALIGN);
493
494 error = bus_dmamap_load_mbuf_sg(sc->rxbuf_tag, sc->rxbuf_map[idx].map,
495 m, &seg, &nsegs, 0);
496 if (error != 0) {
497 return (error);
498 }
499
500 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
501
502 bus_dmamap_sync(sc->rxbuf_tag, sc->rxbuf_map[idx].map,
503 BUS_DMASYNC_PREREAD);
504
505 sc->rxbuf_map[idx].mbuf = m;
506 dwc_setup_rxdesc(sc, idx, seg.ds_addr);
507
508 return (0);
509 }
510
511 static struct mbuf *
512 dwc_alloc_mbufcl(struct dwc_softc *sc)
513 {
514 struct mbuf *m;
515
516 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
517 if (m != NULL)
518 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size;
519
520 return (m);
521 }
522
523 static void
524 dwc_media_status(struct ifnet * ifp, struct ifmediareq *ifmr)
525 {
526 struct dwc_softc *sc;
527 struct mii_data *mii;
528
529 sc = ifp->if_softc;
530 mii = sc->mii_softc;
531 DWC_LOCK(sc);
532 mii_pollstat(mii);
533 ifmr->ifm_active = mii->mii_media_active;
534 ifmr->ifm_status = mii->mii_media_status;
535 DWC_UNLOCK(sc);
536 }
537
538 static int
539 dwc_media_change_locked(struct dwc_softc *sc)
540 {
541
542 return (mii_mediachg(sc->mii_softc));
543 }
544
545 static int
546 dwc_media_change(struct ifnet * ifp)
547 {
548 struct dwc_softc *sc;
549 int error;
550
551 sc = ifp->if_softc;
552
553 DWC_LOCK(sc);
554 error = dwc_media_change_locked(sc);
555 DWC_UNLOCK(sc);
556 return (error);
557 }
558
559 static const uint8_t nibbletab[] = {
560 /* 0x0 0000 -> 0000 */ 0x0,
561 /* 0x1 0001 -> 1000 */ 0x8,
562 /* 0x2 0010 -> 0100 */ 0x4,
563 /* 0x3 0011 -> 1100 */ 0xc,
564 /* 0x4 0100 -> 0010 */ 0x2,
565 /* 0x5 0101 -> 1010 */ 0xa,
566 /* 0x6 0110 -> 0110 */ 0x6,
567 /* 0x7 0111 -> 1110 */ 0xe,
568 /* 0x8 1000 -> 0001 */ 0x1,
569 /* 0x9 1001 -> 1001 */ 0x9,
570 /* 0xa 1010 -> 0101 */ 0x5,
571 /* 0xb 1011 -> 1101 */ 0xd,
572 /* 0xc 1100 -> 0011 */ 0x3,
573 /* 0xd 1101 -> 1011 */ 0xb,
574 /* 0xe 1110 -> 0111 */ 0x7,
575 /* 0xf 1111 -> 1111 */ 0xf, };
576
577 static uint8_t
578 bitreverse(uint8_t x)
579 {
580
581 return (nibbletab[x & 0xf] << 4) | nibbletab[x >> 4];
582 }
583
584 static void
585 dwc_setup_rxfilter(struct dwc_softc *sc)
586 {
587 struct ifmultiaddr *ifma;
588 struct ifnet *ifp;
589 uint8_t *eaddr, val;
590 uint32_t crc, ffval, hashbit, hashreg, hi, lo, hash[8];
591 int nhash, i;
592
593 DWC_ASSERT_LOCKED(sc);
594
595 ifp = sc->ifp;
596 nhash = sc->mactype == DWC_GMAC_ALT_DESC ? 2 : 8;
597
598 /*
599 * Set the multicast (group) filter hash.
600 */
601 if ((ifp->if_flags & IFF_ALLMULTI) != 0) {
602 ffval = (FRAME_FILTER_PM);
603 for (i = 0; i < nhash; i++)
604 hash[i] = ~0;
605 } else {
606 ffval = (FRAME_FILTER_HMC);
607 for (i = 0; i < nhash; i++)
608 hash[i] = 0;
609 if_maddr_rlock(ifp);
610 CK_STAILQ_FOREACH(ifma, &sc->ifp->if_multiaddrs, ifma_link) {
611 if (ifma->ifma_addr->sa_family != AF_LINK)
612 continue;
613 crc = ether_crc32_le(LLADDR((struct sockaddr_dl *)
614 ifma->ifma_addr), ETHER_ADDR_LEN);
615
616 /* Take lower 8 bits and reverse it */
617 val = bitreverse(~crc & 0xff);
618 if (sc->mactype == DWC_GMAC_ALT_DESC)
619 val >>= nhash; /* Only need lower 6 bits */
620 hashreg = (val >> 5);
621 hashbit = (val & 31);
622 hash[hashreg] |= (1 << hashbit);
623 }
624 if_maddr_runlock(ifp);
625 }
626
627 /*
628 * Set the individual address filter hash.
629 */
630 if (ifp->if_flags & IFF_PROMISC)
631 ffval |= (FRAME_FILTER_PR);
632
633 /*
634 * Set the primary address.
635 */
636 eaddr = IF_LLADDR(ifp);
637 lo = eaddr[0] | (eaddr[1] << 8) | (eaddr[2] << 16) |
638 (eaddr[3] << 24);
639 hi = eaddr[4] | (eaddr[5] << 8);
640 WRITE4(sc, MAC_ADDRESS_LOW(0), lo);
641 WRITE4(sc, MAC_ADDRESS_HIGH(0), hi);
642 WRITE4(sc, MAC_FRAME_FILTER, ffval);
643 if (sc->mactype == DWC_GMAC_ALT_DESC) {
644 WRITE4(sc, GMAC_MAC_HTLOW, hash[0]);
645 WRITE4(sc, GMAC_MAC_HTHIGH, hash[1]);
646 } else {
647 for (i = 0; i < nhash; i++)
648 WRITE4(sc, HASH_TABLE_REG(i), hash[i]);
649 }
650 }
651
652 static int
653 dwc_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
654 {
655 struct dwc_softc *sc;
656 struct mii_data *mii;
657 struct ifreq *ifr;
658 int mask, error;
659
660 sc = ifp->if_softc;
661 ifr = (struct ifreq *)data;
662
663 error = 0;
664 switch (cmd) {
665 case SIOCSIFFLAGS:
666 DWC_LOCK(sc);
667 if (ifp->if_flags & IFF_UP) {
668 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
669 if ((ifp->if_flags ^ sc->if_flags) &
670 (IFF_PROMISC | IFF_ALLMULTI))
671 dwc_setup_rxfilter(sc);
672 } else {
673 if (!sc->is_detaching)
674 dwc_init_locked(sc);
675 }
676 } else {
677 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
678 dwc_stop_locked(sc);
679 }
680 sc->if_flags = ifp->if_flags;
681 DWC_UNLOCK(sc);
682 break;
683 case SIOCADDMULTI:
684 case SIOCDELMULTI:
685 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
686 DWC_LOCK(sc);
687 dwc_setup_rxfilter(sc);
688 DWC_UNLOCK(sc);
689 }
690 break;
691 case SIOCSIFMEDIA:
692 case SIOCGIFMEDIA:
693 mii = sc->mii_softc;
694 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
695 break;
696 case SIOCSIFCAP:
697 mask = ifp->if_capenable ^ ifr->ifr_reqcap;
698 if (mask & IFCAP_VLAN_MTU) {
699 /* No work to do except acknowledge the change took */
700 ifp->if_capenable ^= IFCAP_VLAN_MTU;
701 }
702 break;
703
704 default:
705 error = ether_ioctl(ifp, cmd, data);
706 break;
707 }
708
709 return (error);
710 }
711
712 static void
713 dwc_txfinish_locked(struct dwc_softc *sc)
714 {
715 struct dwc_bufmap *bmap;
716 struct dwc_hwdesc *desc;
717 struct ifnet *ifp;
718
719 DWC_ASSERT_LOCKED(sc);
720
721 ifp = sc->ifp;
722 while (sc->tx_idx_tail != sc->tx_idx_head) {
723 desc = &sc->txdesc_ring[sc->tx_idx_tail];
724 if ((desc->tdes0 & DDESC_TDES0_OWN) != 0)
725 break;
726 bmap = &sc->txbuf_map[sc->tx_idx_tail];
727 bus_dmamap_sync(sc->txbuf_tag, bmap->map,
728 BUS_DMASYNC_POSTWRITE);
729 bus_dmamap_unload(sc->txbuf_tag, bmap->map);
730 m_freem(bmap->mbuf);
731 bmap->mbuf = NULL;
732 dwc_setup_txdesc(sc, sc->tx_idx_tail, 0, 0);
733 sc->tx_idx_tail = next_txidx(sc, sc->tx_idx_tail);
734 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
735 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
736 }
737
738 /* If there are no buffers outstanding, muzzle the watchdog. */
739 if (sc->tx_idx_tail == sc->tx_idx_head) {
740 sc->tx_watchdog_count = 0;
741 }
742 }
743
744 static void
745 dwc_rxfinish_locked(struct dwc_softc *sc)
746 {
747 struct ifnet *ifp;
748 struct mbuf *m0;
749 struct mbuf *m;
750 int error, idx, len;
751 uint32_t rdes0;
752
753 ifp = sc->ifp;
754
755 for (;;) {
756 idx = sc->rx_idx;
757
758 rdes0 = sc->rxdesc_ring[idx].tdes0;
759 if ((rdes0 & DDESC_RDES0_OWN) != 0)
760 break;
761
762 bus_dmamap_sync(sc->rxbuf_tag, sc->rxbuf_map[idx].map,
763 BUS_DMASYNC_POSTREAD);
764 bus_dmamap_unload(sc->rxbuf_tag, sc->rxbuf_map[idx].map);
765
766 len = (rdes0 >> DDESC_RDES0_FL_SHIFT) & DDESC_RDES0_FL_MASK;
767 if (len != 0) {
768 m = sc->rxbuf_map[idx].mbuf;
769 m->m_pkthdr.rcvif = ifp;
770 m->m_pkthdr.len = len;
771 m->m_len = len;
772 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
773
774 /* Remove trailing FCS */
775 m_adj(m, -ETHER_CRC_LEN);
776
777 DWC_UNLOCK(sc);
778 (*ifp->if_input)(ifp, m);
779 DWC_LOCK(sc);
780 } else {
781 /* XXX Zero-length packet ? */
782 }
783
784 if ((m0 = dwc_alloc_mbufcl(sc)) != NULL) {
785 if ((error = dwc_setup_rxbuf(sc, idx, m0)) != 0) {
786 /*
787 * XXX Now what?
788 * We've got a hole in the rx ring.
789 */
790 }
791 } else
792 if_inc_counter(sc->ifp, IFCOUNTER_IQDROPS, 1);
793
794 sc->rx_idx = next_rxidx(sc, sc->rx_idx);
795 }
796 }
797
798 static void
799 dwc_intr(void *arg)
800 {
801 struct dwc_softc *sc;
802 uint32_t reg;
803
804 sc = arg;
805
806 DWC_LOCK(sc);
807
808 reg = READ4(sc, INTERRUPT_STATUS);
809 if (reg)
810 READ4(sc, SGMII_RGMII_SMII_CTRL_STATUS);
811
812 reg = READ4(sc, DMA_STATUS);
813 if (reg & DMA_STATUS_NIS) {
814 if (reg & DMA_STATUS_RI)
815 dwc_rxfinish_locked(sc);
816
817 if (reg & DMA_STATUS_TI) {
818 dwc_txfinish_locked(sc);
819 dwc_txstart_locked(sc);
820 }
821 }
822
823 if (reg & DMA_STATUS_AIS) {
824 if (reg & DMA_STATUS_FBI) {
825 /* Fatal bus error */
826 device_printf(sc->dev,
827 "Ethernet DMA error, restarting controller.\n");
828 dwc_stop_locked(sc);
829 dwc_init_locked(sc);
830 }
831 }
832
833 WRITE4(sc, DMA_STATUS, reg & DMA_STATUS_INTR_MASK);
834 DWC_UNLOCK(sc);
835 }
836
837 static int
838 setup_dma(struct dwc_softc *sc)
839 {
840 struct mbuf *m;
841 int error;
842 int nidx;
843 int idx;
844
845 /*
846 * Set up TX descriptor ring, descriptors, and dma maps.
847 */
848 error = bus_dma_tag_create(
849 bus_get_dma_tag(sc->dev), /* Parent tag. */
850 DWC_DESC_RING_ALIGN, 0, /* alignment, boundary */
851 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
852 BUS_SPACE_MAXADDR, /* highaddr */
853 NULL, NULL, /* filter, filterarg */
854 TX_DESC_SIZE, 1, /* maxsize, nsegments */
855 TX_DESC_SIZE, /* maxsegsize */
856 0, /* flags */
857 NULL, NULL, /* lockfunc, lockarg */
858 &sc->txdesc_tag);
859 if (error != 0) {
860 device_printf(sc->dev,
861 "could not create TX ring DMA tag.\n");
862 goto out;
863 }
864
865 error = bus_dmamem_alloc(sc->txdesc_tag, (void**)&sc->txdesc_ring,
866 BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO,
867 &sc->txdesc_map);
868 if (error != 0) {
869 device_printf(sc->dev,
870 "could not allocate TX descriptor ring.\n");
871 goto out;
872 }
873
874 error = bus_dmamap_load(sc->txdesc_tag, sc->txdesc_map,
875 sc->txdesc_ring, TX_DESC_SIZE, dwc_get1paddr,
876 &sc->txdesc_ring_paddr, 0);
877 if (error != 0) {
878 device_printf(sc->dev,
879 "could not load TX descriptor ring map.\n");
880 goto out;
881 }
882
883 for (idx = 0; idx < TX_DESC_COUNT; idx++) {
884 nidx = next_txidx(sc, idx);
885 sc->txdesc_ring[idx].addr_next = sc->txdesc_ring_paddr +
886 (nidx * sizeof(struct dwc_hwdesc));
887 }
888
889 error = bus_dma_tag_create(
890 bus_get_dma_tag(sc->dev), /* Parent tag. */
891 1, 0, /* alignment, boundary */
892 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
893 BUS_SPACE_MAXADDR, /* highaddr */
894 NULL, NULL, /* filter, filterarg */
895 MCLBYTES, 1, /* maxsize, nsegments */
896 MCLBYTES, /* maxsegsize */
897 0, /* flags */
898 NULL, NULL, /* lockfunc, lockarg */
899 &sc->txbuf_tag);
900 if (error != 0) {
901 device_printf(sc->dev,
902 "could not create TX ring DMA tag.\n");
903 goto out;
904 }
905
906 for (idx = 0; idx < TX_DESC_COUNT; idx++) {
907 error = bus_dmamap_create(sc->txbuf_tag, BUS_DMA_COHERENT,
908 &sc->txbuf_map[idx].map);
909 if (error != 0) {
910 device_printf(sc->dev,
911 "could not create TX buffer DMA map.\n");
912 goto out;
913 }
914 dwc_setup_txdesc(sc, idx, 0, 0);
915 }
916
917 /*
918 * Set up RX descriptor ring, descriptors, dma maps, and mbufs.
919 */
920 error = bus_dma_tag_create(
921 bus_get_dma_tag(sc->dev), /* Parent tag. */
922 DWC_DESC_RING_ALIGN, 0, /* alignment, boundary */
923 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
924 BUS_SPACE_MAXADDR, /* highaddr */
925 NULL, NULL, /* filter, filterarg */
926 RX_DESC_SIZE, 1, /* maxsize, nsegments */
927 RX_DESC_SIZE, /* maxsegsize */
928 0, /* flags */
929 NULL, NULL, /* lockfunc, lockarg */
930 &sc->rxdesc_tag);
931 if (error != 0) {
932 device_printf(sc->dev,
933 "could not create RX ring DMA tag.\n");
934 goto out;
935 }
936
937 error = bus_dmamem_alloc(sc->rxdesc_tag, (void **)&sc->rxdesc_ring,
938 BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO,
939 &sc->rxdesc_map);
940 if (error != 0) {
941 device_printf(sc->dev,
942 "could not allocate RX descriptor ring.\n");
943 goto out;
944 }
945
946 error = bus_dmamap_load(sc->rxdesc_tag, sc->rxdesc_map,
947 sc->rxdesc_ring, RX_DESC_SIZE, dwc_get1paddr,
948 &sc->rxdesc_ring_paddr, 0);
949 if (error != 0) {
950 device_printf(sc->dev,
951 "could not load RX descriptor ring map.\n");
952 goto out;
953 }
954
955 error = bus_dma_tag_create(
956 bus_get_dma_tag(sc->dev), /* Parent tag. */
957 1, 0, /* alignment, boundary */
958 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
959 BUS_SPACE_MAXADDR, /* highaddr */
960 NULL, NULL, /* filter, filterarg */
961 MCLBYTES, 1, /* maxsize, nsegments */
962 MCLBYTES, /* maxsegsize */
963 0, /* flags */
964 NULL, NULL, /* lockfunc, lockarg */
965 &sc->rxbuf_tag);
966 if (error != 0) {
967 device_printf(sc->dev,
968 "could not create RX buf DMA tag.\n");
969 goto out;
970 }
971
972 for (idx = 0; idx < RX_DESC_COUNT; idx++) {
973 error = bus_dmamap_create(sc->rxbuf_tag, BUS_DMA_COHERENT,
974 &sc->rxbuf_map[idx].map);
975 if (error != 0) {
976 device_printf(sc->dev,
977 "could not create RX buffer DMA map.\n");
978 goto out;
979 }
980 if ((m = dwc_alloc_mbufcl(sc)) == NULL) {
981 device_printf(sc->dev, "Could not alloc mbuf\n");
982 error = ENOMEM;
983 goto out;
984 }
985 if ((error = dwc_setup_rxbuf(sc, idx, m)) != 0) {
986 device_printf(sc->dev,
987 "could not create new RX buffer.\n");
988 goto out;
989 }
990 }
991
992 out:
993 if (error != 0)
994 return (ENXIO);
995
996 return (0);
997 }
998
999 static int
1000 dwc_get_hwaddr(struct dwc_softc *sc, uint8_t *hwaddr)
1001 {
1002 uint32_t hi, lo, rnd;
1003
1004 /*
1005 * Try to recover a MAC address from the running hardware. If there's
1006 * something non-zero there, assume the bootloader did the right thing
1007 * and just use it.
1008 *
1009 * Otherwise, set the address to a convenient locally assigned address,
1010 * 'bsd' + random 24 low-order bits. 'b' is 0x62, which has the locally
1011 * assigned bit set, and the broadcast/multicast bit clear.
1012 */
1013 lo = READ4(sc, MAC_ADDRESS_LOW(0));
1014 hi = READ4(sc, MAC_ADDRESS_HIGH(0)) & 0xffff;
1015 if ((lo != 0xffffffff) || (hi != 0xffff)) {
1016 hwaddr[0] = (lo >> 0) & 0xff;
1017 hwaddr[1] = (lo >> 8) & 0xff;
1018 hwaddr[2] = (lo >> 16) & 0xff;
1019 hwaddr[3] = (lo >> 24) & 0xff;
1020 hwaddr[4] = (hi >> 0) & 0xff;
1021 hwaddr[5] = (hi >> 8) & 0xff;
1022 } else {
1023 rnd = arc4random() & 0x00ffffff;
1024 hwaddr[0] = 'b';
1025 hwaddr[1] = 's';
1026 hwaddr[2] = 'd';
1027 hwaddr[3] = rnd >> 16;
1028 hwaddr[4] = rnd >> 8;
1029 hwaddr[5] = rnd >> 0;
1030 }
1031
1032 return (0);
1033 }
1034
1035 #define GPIO_ACTIVE_LOW 1
1036
1037 static int
1038 dwc_reset(device_t dev)
1039 {
1040 pcell_t gpio_prop[4];
1041 pcell_t delay_prop[3];
1042 phandle_t node, gpio_node;
1043 device_t gpio;
1044 uint32_t pin, flags;
1045 uint32_t pin_value;
1046
1047 node = ofw_bus_get_node(dev);
1048 if (OF_getencprop(node, "snps,reset-gpio",
1049 gpio_prop, sizeof(gpio_prop)) <= 0)
1050 return (0);
1051
1052 if (OF_getencprop(node, "snps,reset-delays-us",
1053 delay_prop, sizeof(delay_prop)) <= 0) {
1054 device_printf(dev,
1055 "Wrong property for snps,reset-delays-us");
1056 return (ENXIO);
1057 }
1058
1059 gpio_node = OF_node_from_xref(gpio_prop[0]);
1060 if ((gpio = OF_device_from_xref(gpio_prop[0])) == NULL) {
1061 device_printf(dev,
1062 "Can't find gpio controller for phy reset\n");
1063 return (ENXIO);
1064 }
1065
1066 if (GPIO_MAP_GPIOS(gpio, node, gpio_node,
1067 nitems(gpio_prop) - 1,
1068 gpio_prop + 1, &pin, &flags) != 0) {
1069 device_printf(dev, "Can't map gpio for phy reset\n");
1070 return (ENXIO);
1071 }
1072
1073 pin_value = GPIO_PIN_LOW;
1074 if (OF_hasprop(node, "snps,reset-active-low"))
1075 pin_value = GPIO_PIN_HIGH;
1076
1077 if (flags & GPIO_ACTIVE_LOW)
1078 pin_value = !pin_value;
1079
1080 GPIO_PIN_SETFLAGS(gpio, pin, GPIO_PIN_OUTPUT);
1081 GPIO_PIN_SET(gpio, pin, pin_value);
1082 DELAY(delay_prop[0]);
1083 GPIO_PIN_SET(gpio, pin, !pin_value);
1084 DELAY(delay_prop[1]);
1085 GPIO_PIN_SET(gpio, pin, pin_value);
1086 DELAY(delay_prop[2]);
1087
1088 return (0);
1089 }
1090
1091 #ifdef EXT_RESOURCES
1092 static int
1093 dwc_clock_init(device_t dev)
1094 {
1095 hwreset_t rst;
1096 clk_t clk;
1097 int error;
1098
1099 /* Enable clock */
1100 if (clk_get_by_ofw_name(dev, 0, "stmmaceth", &clk) == 0) {
1101 error = clk_enable(clk);
1102 if (error != 0) {
1103 device_printf(dev, "could not enable main clock\n");
1104 return (error);
1105 }
1106 }
1107
1108 /* De-assert reset */
1109 if (hwreset_get_by_ofw_name(dev, 0, "stmmaceth", &rst) == 0) {
1110 error = hwreset_deassert(rst);
1111 if (error != 0) {
1112 device_printf(dev, "could not de-assert reset\n");
1113 return (error);
1114 }
1115 }
1116
1117 return (0);
1118 }
1119 #endif
1120
1121 static int
1122 dwc_probe(device_t dev)
1123 {
1124
1125 if (!ofw_bus_status_okay(dev))
1126 return (ENXIO);
1127
1128 if (!ofw_bus_is_compatible(dev, "snps,dwmac"))
1129 return (ENXIO);
1130
1131 device_set_desc(dev, "Gigabit Ethernet Controller");
1132 return (BUS_PROBE_DEFAULT);
1133 }
1134
1135 static int
1136 dwc_attach(device_t dev)
1137 {
1138 uint8_t macaddr[ETHER_ADDR_LEN];
1139 struct dwc_softc *sc;
1140 struct ifnet *ifp;
1141 int error, i;
1142 uint32_t reg;
1143
1144 sc = device_get_softc(dev);
1145 sc->dev = dev;
1146 sc->rx_idx = 0;
1147 sc->txcount = TX_DESC_COUNT;
1148 sc->mii_clk = IF_DWC_MII_CLK(dev);
1149 sc->mactype = IF_DWC_MAC_TYPE(dev);
1150
1151 if (IF_DWC_INIT(dev) != 0)
1152 return (ENXIO);
1153
1154 #ifdef EXT_RESOURCES
1155 if (dwc_clock_init(dev) != 0)
1156 return (ENXIO);
1157 #endif
1158
1159 if (bus_alloc_resources(dev, dwc_spec, sc->res)) {
1160 device_printf(dev, "could not allocate resources\n");
1161 return (ENXIO);
1162 }
1163
1164 /* Memory interface */
1165 sc->bst = rman_get_bustag(sc->res[0]);
1166 sc->bsh = rman_get_bushandle(sc->res[0]);
1167
1168 /* Read MAC before reset */
1169 if (dwc_get_hwaddr(sc, macaddr)) {
1170 device_printf(sc->dev, "can't get mac\n");
1171 return (ENXIO);
1172 }
1173
1174 /* Reset the PHY if needed */
1175 if (dwc_reset(dev) != 0) {
1176 device_printf(dev, "Can't reset the PHY\n");
1177 return (ENXIO);
1178 }
1179
1180 /* Reset */
1181 reg = READ4(sc, BUS_MODE);
1182 reg |= (BUS_MODE_SWR);
1183 WRITE4(sc, BUS_MODE, reg);
1184
1185 for (i = 0; i < MAC_RESET_TIMEOUT; i++) {
1186 if ((READ4(sc, BUS_MODE) & BUS_MODE_SWR) == 0)
1187 break;
1188 DELAY(10);
1189 }
1190 if (i >= MAC_RESET_TIMEOUT) {
1191 device_printf(sc->dev, "Can't reset DWC.\n");
1192 return (ENXIO);
1193 }
1194
1195 if (sc->mactype == DWC_GMAC_ALT_DESC) {
1196 reg = BUS_MODE_FIXEDBURST;
1197 reg |= (BUS_MODE_PRIORXTX_41 << BUS_MODE_PRIORXTX_SHIFT);
1198 } else
1199 reg = (BUS_MODE_EIGHTXPBL);
1200 reg |= (BUS_MODE_PBL_BEATS_8 << BUS_MODE_PBL_SHIFT);
1201 WRITE4(sc, BUS_MODE, reg);
1202
1203 /*
1204 * DMA must be stop while changing descriptor list addresses.
1205 */
1206 reg = READ4(sc, OPERATION_MODE);
1207 reg &= ~(MODE_ST | MODE_SR);
1208 WRITE4(sc, OPERATION_MODE, reg);
1209
1210 if (setup_dma(sc))
1211 return (ENXIO);
1212
1213 /* Setup addresses */
1214 WRITE4(sc, RX_DESCR_LIST_ADDR, sc->rxdesc_ring_paddr);
1215 WRITE4(sc, TX_DESCR_LIST_ADDR, sc->txdesc_ring_paddr);
1216
1217 mtx_init(&sc->mtx, device_get_nameunit(sc->dev),
1218 MTX_NETWORK_LOCK, MTX_DEF);
1219
1220 callout_init_mtx(&sc->dwc_callout, &sc->mtx, 0);
1221
1222 /* Setup interrupt handler. */
1223 error = bus_setup_intr(dev, sc->res[1], INTR_TYPE_NET | INTR_MPSAFE,
1224 NULL, dwc_intr, sc, &sc->intr_cookie);
1225 if (error != 0) {
1226 device_printf(dev, "could not setup interrupt handler.\n");
1227 return (ENXIO);
1228 }
1229
1230 /* Set up the ethernet interface. */
1231 sc->ifp = ifp = if_alloc(IFT_ETHER);
1232
1233 ifp->if_softc = sc;
1234 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1235 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1236 ifp->if_capabilities = IFCAP_VLAN_MTU;
1237 ifp->if_capenable = ifp->if_capabilities;
1238 ifp->if_start = dwc_txstart;
1239 ifp->if_ioctl = dwc_ioctl;
1240 ifp->if_init = dwc_init;
1241 IFQ_SET_MAXLEN(&ifp->if_snd, TX_DESC_COUNT - 1);
1242 ifp->if_snd.ifq_drv_maxlen = TX_DESC_COUNT - 1;
1243 IFQ_SET_READY(&ifp->if_snd);
1244
1245 /* Attach the mii driver. */
1246 error = mii_attach(dev, &sc->miibus, ifp, dwc_media_change,
1247 dwc_media_status, BMSR_DEFCAPMASK, MII_PHY_ANY,
1248 MII_OFFSET_ANY, 0);
1249
1250 if (error != 0) {
1251 device_printf(dev, "PHY attach failed\n");
1252 return (ENXIO);
1253 }
1254 sc->mii_softc = device_get_softc(sc->miibus);
1255
1256 /* All ready to run, attach the ethernet interface. */
1257 ether_ifattach(ifp, macaddr);
1258 sc->is_attached = true;
1259
1260 return (0);
1261 }
1262
1263 static int
1264 dwc_miibus_read_reg(device_t dev, int phy, int reg)
1265 {
1266 struct dwc_softc *sc;
1267 uint16_t mii;
1268 size_t cnt;
1269 int rv = 0;
1270
1271 sc = device_get_softc(dev);
1272
1273 mii = ((phy & GMII_ADDRESS_PA_MASK) << GMII_ADDRESS_PA_SHIFT)
1274 | ((reg & GMII_ADDRESS_GR_MASK) << GMII_ADDRESS_GR_SHIFT)
1275 | (sc->mii_clk << GMII_ADDRESS_CR_SHIFT)
1276 | GMII_ADDRESS_GB; /* Busy flag */
1277
1278 WRITE4(sc, GMII_ADDRESS, mii);
1279
1280 for (cnt = 0; cnt < 1000; cnt++) {
1281 if (!(READ4(sc, GMII_ADDRESS) & GMII_ADDRESS_GB)) {
1282 rv = READ4(sc, GMII_DATA);
1283 break;
1284 }
1285 DELAY(10);
1286 }
1287
1288 return rv;
1289 }
1290
1291 static int
1292 dwc_miibus_write_reg(device_t dev, int phy, int reg, int val)
1293 {
1294 struct dwc_softc *sc;
1295 uint16_t mii;
1296 size_t cnt;
1297
1298 sc = device_get_softc(dev);
1299
1300 mii = ((phy & GMII_ADDRESS_PA_MASK) << GMII_ADDRESS_PA_SHIFT)
1301 | ((reg & GMII_ADDRESS_GR_MASK) << GMII_ADDRESS_GR_SHIFT)
1302 | (sc->mii_clk << GMII_ADDRESS_CR_SHIFT)
1303 | GMII_ADDRESS_GB | GMII_ADDRESS_GW;
1304
1305 WRITE4(sc, GMII_DATA, val);
1306 WRITE4(sc, GMII_ADDRESS, mii);
1307
1308 for (cnt = 0; cnt < 1000; cnt++) {
1309 if (!(READ4(sc, GMII_ADDRESS) & GMII_ADDRESS_GB)) {
1310 break;
1311 }
1312 DELAY(10);
1313 }
1314
1315 return (0);
1316 }
1317
1318 static void
1319 dwc_miibus_statchg(device_t dev)
1320 {
1321 struct dwc_softc *sc;
1322 struct mii_data *mii;
1323 uint32_t reg;
1324
1325 /*
1326 * Called by the MII bus driver when the PHY establishes
1327 * link to set the MAC interface registers.
1328 */
1329
1330 sc = device_get_softc(dev);
1331
1332 DWC_ASSERT_LOCKED(sc);
1333
1334 mii = sc->mii_softc;
1335
1336 if (mii->mii_media_status & IFM_ACTIVE)
1337 sc->link_is_up = true;
1338 else
1339 sc->link_is_up = false;
1340
1341 reg = READ4(sc, MAC_CONFIGURATION);
1342 switch (IFM_SUBTYPE(mii->mii_media_active)) {
1343 case IFM_1000_T:
1344 case IFM_1000_SX:
1345 reg &= ~(CONF_FES | CONF_PS);
1346 break;
1347 case IFM_100_TX:
1348 reg |= (CONF_FES | CONF_PS);
1349 break;
1350 case IFM_10_T:
1351 reg &= ~(CONF_FES);
1352 reg |= (CONF_PS);
1353 break;
1354 case IFM_NONE:
1355 sc->link_is_up = false;
1356 return;
1357 default:
1358 sc->link_is_up = false;
1359 device_printf(dev, "Unsupported media %u\n",
1360 IFM_SUBTYPE(mii->mii_media_active));
1361 return;
1362 }
1363 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0)
1364 reg |= (CONF_DM);
1365 else
1366 reg &= ~(CONF_DM);
1367 WRITE4(sc, MAC_CONFIGURATION, reg);
1368 }
1369
1370 static device_method_t dwc_methods[] = {
1371 DEVMETHOD(device_probe, dwc_probe),
1372 DEVMETHOD(device_attach, dwc_attach),
1373
1374 /* MII Interface */
1375 DEVMETHOD(miibus_readreg, dwc_miibus_read_reg),
1376 DEVMETHOD(miibus_writereg, dwc_miibus_write_reg),
1377 DEVMETHOD(miibus_statchg, dwc_miibus_statchg),
1378
1379 { 0, 0 }
1380 };
1381
1382 driver_t dwc_driver = {
1383 "dwc",
1384 dwc_methods,
1385 sizeof(struct dwc_softc),
1386 };
1387
1388 static devclass_t dwc_devclass;
1389
1390 DRIVER_MODULE(dwc, simplebus, dwc_driver, dwc_devclass, 0, 0);
1391 DRIVER_MODULE(miibus, dwc, miibus_driver, miibus_devclass, 0, 0);
1392
1393 MODULE_DEPEND(dwc, ether, 1, 1, 1);
1394 MODULE_DEPEND(dwc, miibus, 1, 1, 1);
Cache object: 5b77e0821aec63abff0759962a35e1fe
|