The Design and Implementation of the FreeBSD Operating System, Second Edition
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FreeBSD/Linux Kernel Cross Reference
sys/dev/e1000/e1000_82540.c

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    1 /******************************************************************************
    2 
    3   Copyright (c) 2001-2010, Intel Corporation 
    4   All rights reserved.
    5   
    6   Redistribution and use in source and binary forms, with or without 
    7   modification, are permitted provided that the following conditions are met:
    8   
    9    1. Redistributions of source code must retain the above copyright notice, 
   10       this list of conditions and the following disclaimer.
   11   
   12    2. Redistributions in binary form must reproduce the above copyright 
   13       notice, this list of conditions and the following disclaimer in the 
   14       documentation and/or other materials provided with the distribution.
   15   
   16    3. Neither the name of the Intel Corporation nor the names of its 
   17       contributors may be used to endorse or promote products derived from 
   18       this software without specific prior written permission.
   19   
   20   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
   21   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
   22   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
   23   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 
   24   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 
   25   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 
   26   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
   27   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
   28   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
   29   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   30   POSSIBILITY OF SUCH DAMAGE.
   31 
   32 ******************************************************************************/
   33 /*$FreeBSD: releng/9.0/sys/dev/e1000/e1000_82540.c 218588 2011-02-12 00:07:40Z jfv $*/
   34 
   35 /*
   36  * 82540EM Gigabit Ethernet Controller
   37  * 82540EP Gigabit Ethernet Controller
   38  * 82545EM Gigabit Ethernet Controller (Copper)
   39  * 82545EM Gigabit Ethernet Controller (Fiber)
   40  * 82545GM Gigabit Ethernet Controller
   41  * 82546EB Gigabit Ethernet Controller (Copper)
   42  * 82546EB Gigabit Ethernet Controller (Fiber)
   43  * 82546GB Gigabit Ethernet Controller
   44  */
   45 
   46 #include "e1000_api.h"
   47 
   48 static s32  e1000_init_phy_params_82540(struct e1000_hw *hw);
   49 static s32  e1000_init_nvm_params_82540(struct e1000_hw *hw);
   50 static s32  e1000_init_mac_params_82540(struct e1000_hw *hw);
   51 static s32  e1000_adjust_serdes_amplitude_82540(struct e1000_hw *hw);
   52 static void e1000_clear_hw_cntrs_82540(struct e1000_hw *hw);
   53 static s32  e1000_init_hw_82540(struct e1000_hw *hw);
   54 static s32  e1000_reset_hw_82540(struct e1000_hw *hw);
   55 static s32  e1000_set_phy_mode_82540(struct e1000_hw *hw);
   56 static s32  e1000_set_vco_speed_82540(struct e1000_hw *hw);
   57 static s32  e1000_setup_copper_link_82540(struct e1000_hw *hw);
   58 static s32  e1000_setup_fiber_serdes_link_82540(struct e1000_hw *hw);
   59 static void e1000_power_down_phy_copper_82540(struct e1000_hw *hw);
   60 static s32  e1000_read_mac_addr_82540(struct e1000_hw *hw);
   61 
   62 /**
   63  * e1000_init_phy_params_82540 - Init PHY func ptrs.
   64  * @hw: pointer to the HW structure
   65  **/
   66 static s32 e1000_init_phy_params_82540(struct e1000_hw *hw)
   67 {
   68         struct e1000_phy_info *phy = &hw->phy;
   69         s32 ret_val = E1000_SUCCESS;
   70 
   71         phy->addr                      = 1;
   72         phy->autoneg_mask              = AUTONEG_ADVERTISE_SPEED_DEFAULT;
   73         phy->reset_delay_us            = 10000;
   74         phy->type                      = e1000_phy_m88;
   75 
   76         /* Function Pointers */
   77         phy->ops.check_polarity        = e1000_check_polarity_m88;
   78         phy->ops.commit                = e1000_phy_sw_reset_generic;
   79         phy->ops.force_speed_duplex    = e1000_phy_force_speed_duplex_m88;
   80         phy->ops.get_cable_length      = e1000_get_cable_length_m88;
   81         phy->ops.get_cfg_done          = e1000_get_cfg_done_generic;
   82         phy->ops.read_reg              = e1000_read_phy_reg_m88;
   83         phy->ops.reset                 = e1000_phy_hw_reset_generic;
   84         phy->ops.write_reg             = e1000_write_phy_reg_m88;
   85         phy->ops.get_info              = e1000_get_phy_info_m88;
   86         phy->ops.power_up              = e1000_power_up_phy_copper;
   87         phy->ops.power_down            = e1000_power_down_phy_copper_82540;
   88 
   89         ret_val = e1000_get_phy_id(hw);
   90         if (ret_val)
   91                 goto out;
   92 
   93         /* Verify phy id */
   94         switch (hw->mac.type) {
   95         case e1000_82540:
   96         case e1000_82545:
   97         case e1000_82545_rev_3:
   98         case e1000_82546:
   99         case e1000_82546_rev_3:
  100                 if (phy->id == M88E1011_I_PHY_ID)
  101                         break;
  102                 /* Fall Through */
  103         default:
  104                 ret_val = -E1000_ERR_PHY;
  105                 goto out;
  106                 break;
  107         }
  108 
  109 out:
  110         return ret_val;
  111 }
  112 
  113 /**
  114  * e1000_init_nvm_params_82540 - Init NVM func ptrs.
  115  * @hw: pointer to the HW structure
  116  **/
  117 static s32 e1000_init_nvm_params_82540(struct e1000_hw *hw)
  118 {
  119         struct e1000_nvm_info *nvm = &hw->nvm;
  120         u32 eecd = E1000_READ_REG(hw, E1000_EECD);
  121 
  122         DEBUGFUNC("e1000_init_nvm_params_82540");
  123 
  124         nvm->type               = e1000_nvm_eeprom_microwire;
  125         nvm->delay_usec         = 50;
  126         nvm->opcode_bits        = 3;
  127         switch (nvm->override) {
  128         case e1000_nvm_override_microwire_large:
  129                 nvm->address_bits       = 8;
  130                 nvm->word_size          = 256;
  131                 break;
  132         case e1000_nvm_override_microwire_small:
  133                 nvm->address_bits       = 6;
  134                 nvm->word_size          = 64;
  135                 break;
  136         default:
  137                 nvm->address_bits       = eecd & E1000_EECD_SIZE ? 8 : 6;
  138                 nvm->word_size          = eecd & E1000_EECD_SIZE ? 256 : 64;
  139                 break;
  140         }
  141 
  142         /* Function Pointers */
  143         nvm->ops.acquire            = e1000_acquire_nvm_generic;
  144         nvm->ops.read               = e1000_read_nvm_microwire;
  145         nvm->ops.release            = e1000_release_nvm_generic;
  146         nvm->ops.update             = e1000_update_nvm_checksum_generic;
  147         nvm->ops.valid_led_default  = e1000_valid_led_default_generic;
  148         nvm->ops.validate           = e1000_validate_nvm_checksum_generic;
  149         nvm->ops.write              = e1000_write_nvm_microwire;
  150 
  151         return E1000_SUCCESS;
  152 }
  153 
  154 /**
  155  * e1000_init_mac_params_82540 - Init MAC func ptrs.
  156  * @hw: pointer to the HW structure
  157  **/
  158 static s32 e1000_init_mac_params_82540(struct e1000_hw *hw)
  159 {
  160         struct e1000_mac_info *mac = &hw->mac;
  161         s32 ret_val = E1000_SUCCESS;
  162 
  163         DEBUGFUNC("e1000_init_mac_params_82540");
  164 
  165         /* Set media type */
  166         switch (hw->device_id) {
  167         case E1000_DEV_ID_82545EM_FIBER:
  168         case E1000_DEV_ID_82545GM_FIBER:
  169         case E1000_DEV_ID_82546EB_FIBER:
  170         case E1000_DEV_ID_82546GB_FIBER:
  171                 hw->phy.media_type = e1000_media_type_fiber;
  172                 break;
  173         case E1000_DEV_ID_82545GM_SERDES:
  174         case E1000_DEV_ID_82546GB_SERDES:
  175                 hw->phy.media_type = e1000_media_type_internal_serdes;
  176                 break;
  177         default:
  178                 hw->phy.media_type = e1000_media_type_copper;
  179                 break;
  180         }
  181 
  182         /* Set mta register count */
  183         mac->mta_reg_count = 128;
  184         /* Set rar entry count */
  185         mac->rar_entry_count = E1000_RAR_ENTRIES;
  186 
  187         /* Function pointers */
  188 
  189         /* bus type/speed/width */
  190         mac->ops.get_bus_info = e1000_get_bus_info_pci_generic;
  191         /* function id */
  192         mac->ops.set_lan_id = e1000_set_lan_id_multi_port_pci;
  193         /* reset */
  194         mac->ops.reset_hw = e1000_reset_hw_82540;
  195         /* hw initialization */
  196         mac->ops.init_hw = e1000_init_hw_82540;
  197         /* link setup */
  198         mac->ops.setup_link = e1000_setup_link_generic;
  199         /* physical interface setup */
  200         mac->ops.setup_physical_interface =
  201                 (hw->phy.media_type == e1000_media_type_copper)
  202                         ? e1000_setup_copper_link_82540
  203                         : e1000_setup_fiber_serdes_link_82540;
  204         /* check for link */
  205         switch (hw->phy.media_type) {
  206         case e1000_media_type_copper:
  207                 mac->ops.check_for_link = e1000_check_for_copper_link_generic;
  208                 break;
  209         case e1000_media_type_fiber:
  210                 mac->ops.check_for_link = e1000_check_for_fiber_link_generic;
  211                 break;
  212         case e1000_media_type_internal_serdes:
  213                 mac->ops.check_for_link = e1000_check_for_serdes_link_generic;
  214                 break;
  215         default:
  216                 ret_val = -E1000_ERR_CONFIG;
  217                 goto out;
  218                 break;
  219         }
  220         /* link info */
  221         mac->ops.get_link_up_info =
  222                 (hw->phy.media_type == e1000_media_type_copper)
  223                         ? e1000_get_speed_and_duplex_copper_generic
  224                         : e1000_get_speed_and_duplex_fiber_serdes_generic;
  225         /* multicast address update */
  226         mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
  227         /* writing VFTA */
  228         mac->ops.write_vfta = e1000_write_vfta_generic;
  229         /* clearing VFTA */
  230         mac->ops.clear_vfta = e1000_clear_vfta_generic;
  231         /* read mac address */
  232         mac->ops.read_mac_addr = e1000_read_mac_addr_82540;
  233         /* ID LED init */
  234         mac->ops.id_led_init = e1000_id_led_init_generic;
  235         /* setup LED */
  236         mac->ops.setup_led = e1000_setup_led_generic;
  237         /* cleanup LED */
  238         mac->ops.cleanup_led = e1000_cleanup_led_generic;
  239         /* turn on/off LED */
  240         mac->ops.led_on = e1000_led_on_generic;
  241         mac->ops.led_off = e1000_led_off_generic;
  242         /* clear hardware counters */
  243         mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82540;
  244 
  245 out:
  246         return ret_val;
  247 }
  248 
  249 /**
  250  * e1000_init_function_pointers_82540 - Init func ptrs.
  251  * @hw: pointer to the HW structure
  252  *
  253  * Called to initialize all function pointers and parameters.
  254  **/
  255 void e1000_init_function_pointers_82540(struct e1000_hw *hw)
  256 {
  257         DEBUGFUNC("e1000_init_function_pointers_82540");
  258 
  259         hw->mac.ops.init_params = e1000_init_mac_params_82540;
  260         hw->nvm.ops.init_params = e1000_init_nvm_params_82540;
  261         hw->phy.ops.init_params = e1000_init_phy_params_82540;
  262 }
  263 
  264 /**
  265  *  e1000_reset_hw_82540 - Reset hardware
  266  *  @hw: pointer to the HW structure
  267  *
  268  *  This resets the hardware into a known state.
  269  **/
  270 static s32 e1000_reset_hw_82540(struct e1000_hw *hw)
  271 {
  272         u32 ctrl, manc;
  273         s32 ret_val = E1000_SUCCESS;
  274 
  275         DEBUGFUNC("e1000_reset_hw_82540");
  276 
  277         DEBUGOUT("Masking off all interrupts\n");
  278         E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF);
  279 
  280         E1000_WRITE_REG(hw, E1000_RCTL, 0);
  281         E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
  282         E1000_WRITE_FLUSH(hw);
  283 
  284         /*
  285          * Delay to allow any outstanding PCI transactions to complete
  286          * before resetting the device.
  287          */
  288         msec_delay(10);
  289 
  290         ctrl = E1000_READ_REG(hw, E1000_CTRL);
  291 
  292         DEBUGOUT("Issuing a global reset to 82540/82545/82546 MAC\n");
  293         switch (hw->mac.type) {
  294         case e1000_82545_rev_3:
  295         case e1000_82546_rev_3:
  296                 E1000_WRITE_REG(hw, E1000_CTRL_DUP, ctrl | E1000_CTRL_RST);
  297                 break;
  298         default:
  299                 /*
  300                  * These controllers can't ack the 64-bit write when
  301                  * issuing the reset, so we use IO-mapping as a
  302                  * workaround to issue the reset.
  303                  */
  304                 E1000_WRITE_REG_IO(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
  305                 break;
  306         }
  307 
  308         /* Wait for EEPROM reload */
  309         msec_delay(5);
  310 
  311         /* Disable HW ARPs on ASF enabled adapters */
  312         manc = E1000_READ_REG(hw, E1000_MANC);
  313         manc &= ~E1000_MANC_ARP_EN;
  314         E1000_WRITE_REG(hw, E1000_MANC, manc);
  315 
  316         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
  317         E1000_READ_REG(hw, E1000_ICR);
  318 
  319         return ret_val;
  320 }
  321 
  322 /**
  323  *  e1000_init_hw_82540 - Initialize hardware
  324  *  @hw: pointer to the HW structure
  325  *
  326  *  This inits the hardware readying it for operation.
  327  **/
  328 static s32 e1000_init_hw_82540(struct e1000_hw *hw)
  329 {
  330         struct e1000_mac_info *mac = &hw->mac;
  331         u32 txdctl, ctrl_ext;
  332         s32 ret_val = E1000_SUCCESS;
  333         u16 i;
  334 
  335         DEBUGFUNC("e1000_init_hw_82540");
  336 
  337         /* Initialize identification LED */
  338         ret_val = mac->ops.id_led_init(hw);
  339         if (ret_val) {
  340                 DEBUGOUT("Error initializing identification LED\n");
  341                 /* This is not fatal and we should not stop init due to this */
  342         }
  343 
  344         /* Disabling VLAN filtering */
  345         DEBUGOUT("Initializing the IEEE VLAN\n");
  346         if (mac->type < e1000_82545_rev_3)
  347                 E1000_WRITE_REG(hw, E1000_VET, 0);
  348 
  349         mac->ops.clear_vfta(hw);
  350 
  351         /* Setup the receive address. */
  352         e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
  353 
  354         /* Zero out the Multicast HASH table */
  355         DEBUGOUT("Zeroing the MTA\n");
  356         for (i = 0; i < mac->mta_reg_count; i++) {
  357                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
  358                 /*
  359                  * Avoid back to back register writes by adding the register
  360                  * read (flush).  This is to protect against some strange
  361                  * bridge configurations that may issue Memory Write Block
  362                  * (MWB) to our register space.  The *_rev_3 hardware at
  363                  * least doesn't respond correctly to every other dword in an
  364                  * MWB to our register space.
  365                  */
  366                 E1000_WRITE_FLUSH(hw);
  367         }
  368 
  369         if (mac->type < e1000_82545_rev_3)
  370                 e1000_pcix_mmrbc_workaround_generic(hw);
  371 
  372         /* Setup link and flow control */
  373         ret_val = mac->ops.setup_link(hw);
  374 
  375         txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0));
  376         txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
  377                  E1000_TXDCTL_FULL_TX_DESC_WB;
  378         E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl);
  379 
  380         /*
  381          * Clear all of the statistics registers (clear on read).  It is
  382          * important that we do this after we have tried to establish link
  383          * because the symbol error count will increment wildly if there
  384          * is no link.
  385          */
  386         e1000_clear_hw_cntrs_82540(hw);
  387 
  388         if ((hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER) ||
  389             (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3)) {
  390                 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
  391                 /*
  392                  * Relaxed ordering must be disabled to avoid a parity
  393                  * error crash in a PCI slot.
  394                  */
  395                 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
  396                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
  397         }
  398 
  399         return ret_val;
  400 }
  401 
  402 /**
  403  *  e1000_setup_copper_link_82540 - Configure copper link settings
  404  *  @hw: pointer to the HW structure
  405  *
  406  *  Calls the appropriate function to configure the link for auto-neg or forced
  407  *  speed and duplex.  Then we check for link, once link is established calls
  408  *  to configure collision distance and flow control are called.  If link is
  409  *  not established, we return -E1000_ERR_PHY (-2).
  410  **/
  411 static s32 e1000_setup_copper_link_82540(struct e1000_hw *hw)
  412 {
  413         u32 ctrl;
  414         s32 ret_val = E1000_SUCCESS;
  415         u16 data;
  416 
  417         DEBUGFUNC("e1000_setup_copper_link_82540");
  418 
  419         ctrl = E1000_READ_REG(hw, E1000_CTRL);
  420         ctrl |= E1000_CTRL_SLU;
  421         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
  422         E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
  423 
  424         ret_val = e1000_set_phy_mode_82540(hw);
  425         if (ret_val)
  426                 goto out;
  427 
  428         if (hw->mac.type == e1000_82545_rev_3 ||
  429             hw->mac.type == e1000_82546_rev_3) {
  430                 ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &data);
  431                 if (ret_val)
  432                         goto out;
  433                 data |= 0x00000008;
  434                 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, data);
  435                 if (ret_val)
  436                         goto out;
  437         }
  438 
  439         ret_val = e1000_copper_link_setup_m88(hw);
  440         if (ret_val)
  441                 goto out;
  442 
  443         ret_val = e1000_setup_copper_link_generic(hw);
  444 
  445 out:
  446         return ret_val;
  447 }
  448 
  449 /**
  450  *  e1000_setup_fiber_serdes_link_82540 - Setup link for fiber/serdes
  451  *  @hw: pointer to the HW structure
  452  *
  453  *  Set the output amplitude to the value in the EEPROM and adjust the VCO
  454  *  speed to improve Bit Error Rate (BER) performance.  Configures collision
  455  *  distance and flow control for fiber and serdes links.  Upon successful
  456  *  setup, poll for link.
  457  **/
  458 static s32 e1000_setup_fiber_serdes_link_82540(struct e1000_hw *hw)
  459 {
  460         struct e1000_mac_info *mac = &hw->mac;
  461         s32 ret_val = E1000_SUCCESS;
  462 
  463         DEBUGFUNC("e1000_setup_fiber_serdes_link_82540");
  464 
  465         switch (mac->type) {
  466         case e1000_82545_rev_3:
  467         case e1000_82546_rev_3:
  468                 if (hw->phy.media_type == e1000_media_type_internal_serdes) {
  469                         /*
  470                          * If we're on serdes media, adjust the output
  471                          * amplitude to value set in the EEPROM.
  472                          */
  473                         ret_val = e1000_adjust_serdes_amplitude_82540(hw);
  474                         if (ret_val)
  475                                 goto out;
  476                 }
  477                 /* Adjust VCO speed to improve BER performance */
  478                 ret_val = e1000_set_vco_speed_82540(hw);
  479                 if (ret_val)
  480                         goto out;
  481         default:
  482                 break;
  483         }
  484 
  485         ret_val = e1000_setup_fiber_serdes_link_generic(hw);
  486 
  487 out:
  488         return ret_val;
  489 }
  490 
  491 /**
  492  *  e1000_adjust_serdes_amplitude_82540 - Adjust amplitude based on EEPROM
  493  *  @hw: pointer to the HW structure
  494  *
  495  *  Adjust the SERDES output amplitude based on the EEPROM settings.
  496  **/
  497 static s32 e1000_adjust_serdes_amplitude_82540(struct e1000_hw *hw)
  498 {
  499         s32 ret_val = E1000_SUCCESS;
  500         u16 nvm_data;
  501 
  502         DEBUGFUNC("e1000_adjust_serdes_amplitude_82540");
  503 
  504         ret_val = hw->nvm.ops.read(hw, NVM_SERDES_AMPLITUDE, 1, &nvm_data);
  505         if (ret_val)
  506                 goto out;
  507 
  508         if (nvm_data != NVM_RESERVED_WORD) {
  509                 /* Adjust serdes output amplitude only. */
  510                 nvm_data &= NVM_SERDES_AMPLITUDE_MASK;
  511                 ret_val = hw->phy.ops.write_reg(hw,
  512                                              M88E1000_PHY_EXT_CTRL,
  513                                              nvm_data);
  514                 if (ret_val)
  515                         goto out;
  516         }
  517 
  518 out:
  519         return ret_val;
  520 }
  521 
  522 /**
  523  *  e1000_set_vco_speed_82540 - Set VCO speed for better performance
  524  *  @hw: pointer to the HW structure
  525  *
  526  *  Set the VCO speed to improve Bit Error Rate (BER) performance.
  527  **/
  528 static s32 e1000_set_vco_speed_82540(struct e1000_hw *hw)
  529 {
  530         s32  ret_val = E1000_SUCCESS;
  531         u16 default_page = 0;
  532         u16 phy_data;
  533 
  534         DEBUGFUNC("e1000_set_vco_speed_82540");
  535 
  536         /* Set PHY register 30, page 5, bit 8 to 0 */
  537 
  538         ret_val = hw->phy.ops.read_reg(hw,
  539                                     M88E1000_PHY_PAGE_SELECT,
  540                                     &default_page);
  541         if (ret_val)
  542                 goto out;
  543 
  544         ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005);
  545         if (ret_val)
  546                 goto out;
  547 
  548         ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
  549         if (ret_val)
  550                 goto out;
  551 
  552         phy_data &= ~M88E1000_PHY_VCO_REG_BIT8;
  553         ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
  554         if (ret_val)
  555                 goto out;
  556 
  557         /* Set PHY register 30, page 4, bit 11 to 1 */
  558 
  559         ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004);
  560         if (ret_val)
  561                 goto out;
  562 
  563         ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
  564         if (ret_val)
  565                 goto out;
  566 
  567         phy_data |= M88E1000_PHY_VCO_REG_BIT11;
  568         ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
  569         if (ret_val)
  570                 goto out;
  571 
  572         ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT,
  573                                       default_page);
  574 
  575 out:
  576         return ret_val;
  577 }
  578 
  579 /**
  580  *  e1000_set_phy_mode_82540 - Set PHY to class A mode
  581  *  @hw: pointer to the HW structure
  582  *
  583  *  Sets the PHY to class A mode and assumes the following operations will
  584  *  follow to enable the new class mode:
  585  *    1.  Do a PHY soft reset.
  586  *    2.  Restart auto-negotiation or force link.
  587  **/
  588 static s32 e1000_set_phy_mode_82540(struct e1000_hw *hw)
  589 {
  590         struct e1000_phy_info *phy = &hw->phy;
  591         s32 ret_val = E1000_SUCCESS;
  592         u16 nvm_data;
  593 
  594         DEBUGFUNC("e1000_set_phy_mode_82540");
  595 
  596         if (hw->mac.type != e1000_82545_rev_3)
  597                 goto out;
  598 
  599         ret_val = hw->nvm.ops.read(hw, NVM_PHY_CLASS_WORD, 1, &nvm_data);
  600         if (ret_val) {
  601                 ret_val = -E1000_ERR_PHY;
  602                 goto out;
  603         }
  604 
  605         if ((nvm_data != NVM_RESERVED_WORD) && (nvm_data & NVM_PHY_CLASS_A)) {
  606                 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT,
  607                                               0x000B);
  608                 if (ret_val) {
  609                         ret_val = -E1000_ERR_PHY;
  610                         goto out;
  611                 }
  612                 ret_val = hw->phy.ops.write_reg(hw,
  613                                               M88E1000_PHY_GEN_CONTROL,
  614                                               0x8104);
  615                 if (ret_val) {
  616                         ret_val = -E1000_ERR_PHY;
  617                         goto out;
  618                 }
  619 
  620                 phy->reset_disable = FALSE;
  621         }
  622 
  623 out:
  624         return ret_val;
  625 }
  626 
  627 /**
  628  * e1000_power_down_phy_copper_82540 - Remove link in case of PHY power down
  629  * @hw: pointer to the HW structure
  630  *
  631  * In the case of a PHY power down to save power, or to turn off link during a
  632  * driver unload, or wake on lan is not enabled, remove the link.
  633  **/
  634 static void e1000_power_down_phy_copper_82540(struct e1000_hw *hw)
  635 {
  636         /* If the management interface is not enabled, then power down */
  637         if (!(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_SMBUS_EN))
  638                 e1000_power_down_phy_copper(hw);
  639 
  640         return;
  641 }
  642 
  643 /**
  644  *  e1000_clear_hw_cntrs_82540 - Clear device specific hardware counters
  645  *  @hw: pointer to the HW structure
  646  *
  647  *  Clears the hardware counters by reading the counter registers.
  648  **/
  649 static void e1000_clear_hw_cntrs_82540(struct e1000_hw *hw)
  650 {
  651         DEBUGFUNC("e1000_clear_hw_cntrs_82540");
  652 
  653         e1000_clear_hw_cntrs_base_generic(hw);
  654 
  655         E1000_READ_REG(hw, E1000_PRC64);
  656         E1000_READ_REG(hw, E1000_PRC127);
  657         E1000_READ_REG(hw, E1000_PRC255);
  658         E1000_READ_REG(hw, E1000_PRC511);
  659         E1000_READ_REG(hw, E1000_PRC1023);
  660         E1000_READ_REG(hw, E1000_PRC1522);
  661         E1000_READ_REG(hw, E1000_PTC64);
  662         E1000_READ_REG(hw, E1000_PTC127);
  663         E1000_READ_REG(hw, E1000_PTC255);
  664         E1000_READ_REG(hw, E1000_PTC511);
  665         E1000_READ_REG(hw, E1000_PTC1023);
  666         E1000_READ_REG(hw, E1000_PTC1522);
  667 
  668         E1000_READ_REG(hw, E1000_ALGNERRC);
  669         E1000_READ_REG(hw, E1000_RXERRC);
  670         E1000_READ_REG(hw, E1000_TNCRS);
  671         E1000_READ_REG(hw, E1000_CEXTERR);
  672         E1000_READ_REG(hw, E1000_TSCTC);
  673         E1000_READ_REG(hw, E1000_TSCTFC);
  674 
  675         E1000_READ_REG(hw, E1000_MGTPRC);
  676         E1000_READ_REG(hw, E1000_MGTPDC);
  677         E1000_READ_REG(hw, E1000_MGTPTC);
  678 }
  679 
  680 /**
  681  *  e1000_read_mac_addr_82540 - Read device MAC address
  682  *  @hw: pointer to the HW structure
  683  *
  684  *  Reads the device MAC address from the EEPROM and stores the value.
  685  *  Since devices with two ports use the same EEPROM, we increment the
  686  *  last bit in the MAC address for the second port.
  687  *
  688  *  This version is being used over generic because of customer issues
  689  *  with VmWare and Virtual Box when using generic. It seems in
  690  *  the emulated 82545, RAR[0] does NOT have a valid address after a
  691  *  reset, this older method works and using this breaks nothing for
  692  *  these legacy adapters.
  693  **/
  694 s32 e1000_read_mac_addr_82540(struct e1000_hw *hw)
  695 {
  696         s32  ret_val = E1000_SUCCESS;
  697         u16 offset, nvm_data, i;
  698 
  699         DEBUGFUNC("e1000_read_mac_addr");
  700 
  701         for (i = 0; i < ETH_ADDR_LEN; i += 2) {
  702                 offset = i >> 1;
  703                 ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data);
  704                 if (ret_val) {
  705                         DEBUGOUT("NVM Read Error\n");
  706                         goto out;
  707                 }
  708                 hw->mac.perm_addr[i] = (u8)(nvm_data & 0xFF);
  709                 hw->mac.perm_addr[i+1] = (u8)(nvm_data >> 8);
  710         }
  711 
  712         /* Flip last bit of mac address if we're on second port */
  713         if (hw->bus.func == E1000_FUNC_1)
  714                 hw->mac.perm_addr[5] ^= 1;
  715 
  716         for (i = 0; i < ETH_ADDR_LEN; i++)
  717                 hw->mac.addr[i] = hw->mac.perm_addr[i];
  718 
  719 out:
  720         return ret_val;
  721 }

Cache object: a4c08c1397e2a76a79ac5072f95c1025


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