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sys/dev/e1000/e1000_82541.c
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1 /****************************************************************************** 2 SPDX-License-Identifier: BSD-3-Clause 3 4 Copyright (c) 2001-2020, Intel Corporation 5 All rights reserved. 6 7 Redistribution and use in source and binary forms, with or without 8 modification, are permitted provided that the following conditions are met: 9 10 1. Redistributions of source code must retain the above copyright notice, 11 this list of conditions and the following disclaimer. 12 13 2. Redistributions in binary form must reproduce the above copyright 14 notice, this list of conditions and the following disclaimer in the 15 documentation and/or other materials provided with the distribution. 16 17 3. Neither the name of the Intel Corporation nor the names of its 18 contributors may be used to endorse or promote products derived from 19 this software without specific prior written permission. 20 21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 POSSIBILITY OF SUCH DAMAGE. 32 33 ******************************************************************************/ 34 /*$FreeBSD$*/ 35 36 /* 37 * 82541EI Gigabit Ethernet Controller 38 * 82541ER Gigabit Ethernet Controller 39 * 82541GI Gigabit Ethernet Controller 40 * 82541PI Gigabit Ethernet Controller 41 * 82547EI Gigabit Ethernet Controller 42 * 82547GI Gigabit Ethernet Controller 43 */ 44 45 #include "e1000_api.h" 46 47 static s32 e1000_init_phy_params_82541(struct e1000_hw *hw); 48 static s32 e1000_init_nvm_params_82541(struct e1000_hw *hw); 49 static s32 e1000_init_mac_params_82541(struct e1000_hw *hw); 50 static s32 e1000_reset_hw_82541(struct e1000_hw *hw); 51 static s32 e1000_init_hw_82541(struct e1000_hw *hw); 52 static s32 e1000_get_link_up_info_82541(struct e1000_hw *hw, u16 *speed, 53 u16 *duplex); 54 static s32 e1000_phy_hw_reset_82541(struct e1000_hw *hw); 55 static s32 e1000_setup_copper_link_82541(struct e1000_hw *hw); 56 static s32 e1000_check_for_link_82541(struct e1000_hw *hw); 57 static s32 e1000_get_cable_length_igp_82541(struct e1000_hw *hw); 58 static s32 e1000_set_d3_lplu_state_82541(struct e1000_hw *hw, 59 bool active); 60 static s32 e1000_setup_led_82541(struct e1000_hw *hw); 61 static s32 e1000_cleanup_led_82541(struct e1000_hw *hw); 62 static void e1000_clear_hw_cntrs_82541(struct e1000_hw *hw); 63 static s32 e1000_read_mac_addr_82541(struct e1000_hw *hw); 64 static s32 e1000_config_dsp_after_link_change_82541(struct e1000_hw *hw, 65 bool link_up); 66 static s32 e1000_phy_init_script_82541(struct e1000_hw *hw); 67 static void e1000_power_down_phy_copper_82541(struct e1000_hw *hw); 68 69 static const u16 e1000_igp_cable_length_table[] = { 70 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 10, 10, 10, 10, 10, 71 10, 10, 20, 20, 20, 20, 20, 25, 25, 25, 25, 25, 25, 25, 30, 30, 30, 30, 72 40, 40, 40, 40, 40, 40, 40, 40, 40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 73 60, 60, 60, 60, 60, 60, 60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 74 80, 90, 90, 90, 90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 75 100, 100, 100, 100, 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 76 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 120, 120, 77 120, 120, 120, 120, 120, 120, 120, 120}; 78 #define IGP01E1000_AGC_LENGTH_TABLE_SIZE \ 79 (sizeof(e1000_igp_cable_length_table) / \ 80 sizeof(e1000_igp_cable_length_table[0])) 81 82 /** 83 * e1000_init_phy_params_82541 - Init PHY func ptrs. 84 * @hw: pointer to the HW structure 85 **/ 86 static s32 e1000_init_phy_params_82541(struct e1000_hw *hw) 87 { 88 struct e1000_phy_info *phy = &hw->phy; 89 s32 ret_val; 90 91 DEBUGFUNC("e1000_init_phy_params_82541"); 92 93 phy->addr = 1; 94 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 95 phy->reset_delay_us = 10000; 96 phy->type = e1000_phy_igp; 97 98 /* Function Pointers */ 99 phy->ops.check_polarity = e1000_check_polarity_igp; 100 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp; 101 phy->ops.get_cable_length = e1000_get_cable_length_igp_82541; 102 phy->ops.get_cfg_done = e1000_get_cfg_done_generic; 103 phy->ops.get_info = e1000_get_phy_info_igp; 104 phy->ops.read_reg = e1000_read_phy_reg_igp; 105 phy->ops.reset = e1000_phy_hw_reset_82541; 106 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82541; 107 phy->ops.write_reg = e1000_write_phy_reg_igp; 108 phy->ops.power_up = e1000_power_up_phy_copper; 109 phy->ops.power_down = e1000_power_down_phy_copper_82541; 110 111 ret_val = e1000_get_phy_id(hw); 112 if (ret_val) 113 goto out; 114 115 /* Verify phy id */ 116 if (phy->id != IGP01E1000_I_PHY_ID) { 117 ret_val = -E1000_ERR_PHY; 118 goto out; 119 } 120 121 out: 122 return ret_val; 123 } 124 125 /** 126 * e1000_init_nvm_params_82541 - Init NVM func ptrs. 127 * @hw: pointer to the HW structure 128 **/ 129 static s32 e1000_init_nvm_params_82541(struct e1000_hw *hw) 130 { 131 struct e1000_nvm_info *nvm = &hw->nvm; 132 s32 ret_val = E1000_SUCCESS; 133 u32 eecd = E1000_READ_REG(hw, E1000_EECD); 134 u16 size; 135 136 DEBUGFUNC("e1000_init_nvm_params_82541"); 137 138 switch (nvm->override) { 139 case e1000_nvm_override_spi_large: 140 nvm->type = e1000_nvm_eeprom_spi; 141 eecd |= E1000_EECD_ADDR_BITS; 142 break; 143 case e1000_nvm_override_spi_small: 144 nvm->type = e1000_nvm_eeprom_spi; 145 eecd &= ~E1000_EECD_ADDR_BITS; 146 break; 147 case e1000_nvm_override_microwire_large: 148 nvm->type = e1000_nvm_eeprom_microwire; 149 eecd |= E1000_EECD_SIZE; 150 break; 151 case e1000_nvm_override_microwire_small: 152 nvm->type = e1000_nvm_eeprom_microwire; 153 eecd &= ~E1000_EECD_SIZE; 154 break; 155 default: 156 nvm->type = eecd & E1000_EECD_TYPE ? e1000_nvm_eeprom_spi 157 : e1000_nvm_eeprom_microwire; 158 break; 159 } 160 161 if (nvm->type == e1000_nvm_eeprom_spi) { 162 nvm->address_bits = (eecd & E1000_EECD_ADDR_BITS) ? 16 : 8; 163 nvm->delay_usec = 1; 164 nvm->opcode_bits = 8; 165 nvm->page_size = (eecd & E1000_EECD_ADDR_BITS) ? 32 : 8; 166 167 /* Function Pointers */ 168 nvm->ops.acquire = e1000_acquire_nvm_generic; 169 nvm->ops.read = e1000_read_nvm_spi; 170 nvm->ops.release = e1000_release_nvm_generic; 171 nvm->ops.update = e1000_update_nvm_checksum_generic; 172 nvm->ops.valid_led_default = e1000_valid_led_default_generic; 173 nvm->ops.validate = e1000_validate_nvm_checksum_generic; 174 nvm->ops.write = e1000_write_nvm_spi; 175 176 /* 177 * nvm->word_size must be discovered after the pointers 178 * are set so we can verify the size from the nvm image 179 * itself. Temporarily set it to a dummy value so the 180 * read will work. 181 */ 182 nvm->word_size = 64; 183 ret_val = nvm->ops.read(hw, NVM_CFG, 1, &size); 184 if (ret_val) 185 goto out; 186 size = (size & NVM_SIZE_MASK) >> NVM_SIZE_SHIFT; 187 /* 188 * if size != 0, it can be added to a constant and become 189 * the left-shift value to set the word_size. Otherwise, 190 * word_size stays at 64. 191 */ 192 if (size) { 193 size += NVM_WORD_SIZE_BASE_SHIFT_82541; 194 nvm->word_size = 1 << size; 195 } 196 } else { 197 nvm->address_bits = (eecd & E1000_EECD_ADDR_BITS) ? 8 : 6; 198 nvm->delay_usec = 50; 199 nvm->opcode_bits = 3; 200 nvm->word_size = (eecd & E1000_EECD_ADDR_BITS) ? 256 : 64; 201 202 /* Function Pointers */ 203 nvm->ops.acquire = e1000_acquire_nvm_generic; 204 nvm->ops.read = e1000_read_nvm_microwire; 205 nvm->ops.release = e1000_release_nvm_generic; 206 nvm->ops.update = e1000_update_nvm_checksum_generic; 207 nvm->ops.valid_led_default = e1000_valid_led_default_generic; 208 nvm->ops.validate = e1000_validate_nvm_checksum_generic; 209 nvm->ops.write = e1000_write_nvm_microwire; 210 } 211 212 out: 213 return ret_val; 214 } 215 216 /** 217 * e1000_init_mac_params_82541 - Init MAC func ptrs. 218 * @hw: pointer to the HW structure 219 **/ 220 static s32 e1000_init_mac_params_82541(struct e1000_hw *hw) 221 { 222 struct e1000_mac_info *mac = &hw->mac; 223 224 DEBUGFUNC("e1000_init_mac_params_82541"); 225 226 /* Set media type */ 227 hw->phy.media_type = e1000_media_type_copper; 228 /* Set mta register count */ 229 mac->mta_reg_count = 128; 230 /* Set rar entry count */ 231 mac->rar_entry_count = E1000_RAR_ENTRIES; 232 /* Set if part includes ASF firmware */ 233 mac->asf_firmware_present = true; 234 235 /* Function Pointers */ 236 237 /* bus type/speed/width */ 238 mac->ops.get_bus_info = e1000_get_bus_info_pci_generic; 239 /* function id */ 240 mac->ops.set_lan_id = e1000_set_lan_id_single_port; 241 /* reset */ 242 mac->ops.reset_hw = e1000_reset_hw_82541; 243 /* hw initialization */ 244 mac->ops.init_hw = e1000_init_hw_82541; 245 /* link setup */ 246 mac->ops.setup_link = e1000_setup_link_generic; 247 /* physical interface link setup */ 248 mac->ops.setup_physical_interface = e1000_setup_copper_link_82541; 249 /* check for link */ 250 mac->ops.check_for_link = e1000_check_for_link_82541; 251 /* link info */ 252 mac->ops.get_link_up_info = e1000_get_link_up_info_82541; 253 /* multicast address update */ 254 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic; 255 /* writing VFTA */ 256 mac->ops.write_vfta = e1000_write_vfta_generic; 257 /* clearing VFTA */ 258 mac->ops.clear_vfta = e1000_clear_vfta_generic; 259 /* read mac address */ 260 mac->ops.read_mac_addr = e1000_read_mac_addr_82541; 261 /* ID LED init */ 262 mac->ops.id_led_init = e1000_id_led_init_generic; 263 /* setup LED */ 264 mac->ops.setup_led = e1000_setup_led_82541; 265 /* cleanup LED */ 266 mac->ops.cleanup_led = e1000_cleanup_led_82541; 267 /* turn on/off LED */ 268 mac->ops.led_on = e1000_led_on_generic; 269 mac->ops.led_off = e1000_led_off_generic; 270 /* clear hardware counters */ 271 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82541; 272 273 return E1000_SUCCESS; 274 } 275 276 /** 277 * e1000_init_function_pointers_82541 - Init func ptrs. 278 * @hw: pointer to the HW structure 279 * 280 * Called to initialize all function pointers and parameters. 281 **/ 282 void e1000_init_function_pointers_82541(struct e1000_hw *hw) 283 { 284 DEBUGFUNC("e1000_init_function_pointers_82541"); 285 286 hw->mac.ops.init_params = e1000_init_mac_params_82541; 287 hw->nvm.ops.init_params = e1000_init_nvm_params_82541; 288 hw->phy.ops.init_params = e1000_init_phy_params_82541; 289 } 290 291 /** 292 * e1000_reset_hw_82541 - Reset hardware 293 * @hw: pointer to the HW structure 294 * 295 * This resets the hardware into a known state. 296 **/ 297 static s32 e1000_reset_hw_82541(struct e1000_hw *hw) 298 { 299 u32 ledctl, ctrl, manc; 300 301 DEBUGFUNC("e1000_reset_hw_82541"); 302 303 DEBUGOUT("Masking off all interrupts\n"); 304 E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF); 305 306 E1000_WRITE_REG(hw, E1000_RCTL, 0); 307 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); 308 E1000_WRITE_FLUSH(hw); 309 310 /* 311 * Delay to allow any outstanding PCI transactions to complete 312 * before resetting the device. 313 */ 314 msec_delay(10); 315 316 ctrl = E1000_READ_REG(hw, E1000_CTRL); 317 318 /* Must reset the Phy before resetting the MAC */ 319 if ((hw->mac.type == e1000_82541) || (hw->mac.type == e1000_82547)) { 320 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl | E1000_CTRL_PHY_RST)); 321 E1000_WRITE_FLUSH(hw); 322 msec_delay(5); 323 } 324 325 DEBUGOUT("Issuing a global reset to 82541/82547 MAC\n"); 326 switch (hw->mac.type) { 327 case e1000_82541: 328 case e1000_82541_rev_2: 329 /* 330 * These controllers can't ack the 64-bit write when 331 * issuing the reset, so we use IO-mapping as a 332 * workaround to issue the reset. 333 */ 334 E1000_WRITE_REG_IO(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); 335 break; 336 default: 337 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); 338 break; 339 } 340 341 /* Wait for NVM reload */ 342 msec_delay(20); 343 344 /* Disable HW ARPs on ASF enabled adapters */ 345 manc = E1000_READ_REG(hw, E1000_MANC); 346 manc &= ~E1000_MANC_ARP_EN; 347 E1000_WRITE_REG(hw, E1000_MANC, manc); 348 349 if ((hw->mac.type == e1000_82541) || (hw->mac.type == e1000_82547)) { 350 e1000_phy_init_script_82541(hw); 351 352 /* Configure activity LED after Phy reset */ 353 ledctl = E1000_READ_REG(hw, E1000_LEDCTL); 354 ledctl &= IGP_ACTIVITY_LED_MASK; 355 ledctl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 356 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl); 357 } 358 359 /* Once again, mask the interrupts */ 360 DEBUGOUT("Masking off all interrupts\n"); 361 E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF); 362 363 /* Clear any pending interrupt events. */ 364 E1000_READ_REG(hw, E1000_ICR); 365 366 return E1000_SUCCESS; 367 } 368 369 /** 370 * e1000_init_hw_82541 - Initialize hardware 371 * @hw: pointer to the HW structure 372 * 373 * This inits the hardware readying it for operation. 374 **/ 375 static s32 e1000_init_hw_82541(struct e1000_hw *hw) 376 { 377 struct e1000_mac_info *mac = &hw->mac; 378 struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541; 379 u32 i, txdctl; 380 s32 ret_val; 381 382 DEBUGFUNC("e1000_init_hw_82541"); 383 384 /* Initialize identification LED */ 385 ret_val = mac->ops.id_led_init(hw); 386 if (ret_val) { 387 DEBUGOUT("Error initializing identification LED\n"); 388 /* This is not fatal and we should not stop init due to this */ 389 } 390 391 /* Storing the Speed Power Down value for later use */ 392 ret_val = hw->phy.ops.read_reg(hw, IGP01E1000_GMII_FIFO, 393 &dev_spec->spd_default); 394 if (ret_val) 395 goto out; 396 397 /* Disabling VLAN filtering */ 398 DEBUGOUT("Initializing the IEEE VLAN\n"); 399 mac->ops.clear_vfta(hw); 400 401 /* Setup the receive address. */ 402 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count); 403 404 /* Zero out the Multicast HASH table */ 405 DEBUGOUT("Zeroing the MTA\n"); 406 for (i = 0; i < mac->mta_reg_count; i++) { 407 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 408 /* 409 * Avoid back to back register writes by adding the register 410 * read (flush). This is to protect against some strange 411 * bridge configurations that may issue Memory Write Block 412 * (MWB) to our register space. 413 */ 414 E1000_WRITE_FLUSH(hw); 415 } 416 417 /* Setup link and flow control */ 418 ret_val = mac->ops.setup_link(hw); 419 420 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0)); 421 txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) | 422 E1000_TXDCTL_FULL_TX_DESC_WB; 423 E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl); 424 425 /* 426 * Clear all of the statistics registers (clear on read). It is 427 * important that we do this after we have tried to establish link 428 * because the symbol error count will increment wildly if there 429 * is no link. 430 */ 431 e1000_clear_hw_cntrs_82541(hw); 432 433 out: 434 return ret_val; 435 } 436 437 /** 438 * e1000_get_link_up_info_82541 - Report speed and duplex 439 * @hw: pointer to the HW structure 440 * @speed: pointer to speed buffer 441 * @duplex: pointer to duplex buffer 442 * 443 * Retrieve the current speed and duplex configuration. 444 **/ 445 static s32 e1000_get_link_up_info_82541(struct e1000_hw *hw, u16 *speed, 446 u16 *duplex) 447 { 448 struct e1000_phy_info *phy = &hw->phy; 449 s32 ret_val; 450 u16 data; 451 452 DEBUGFUNC("e1000_get_link_up_info_82541"); 453 454 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, duplex); 455 if (ret_val) 456 goto out; 457 458 if (!phy->speed_downgraded) 459 goto out; 460 461 /* 462 * IGP01 PHY may advertise full duplex operation after speed 463 * downgrade even if it is operating at half duplex. 464 * Here we set the duplex settings to match the duplex in the 465 * link partner's capabilities. 466 */ 467 ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_EXP, &data); 468 if (ret_val) 469 goto out; 470 471 if (!(data & NWAY_ER_LP_NWAY_CAPS)) { 472 *duplex = HALF_DUPLEX; 473 } else { 474 ret_val = phy->ops.read_reg(hw, PHY_LP_ABILITY, &data); 475 if (ret_val) 476 goto out; 477 478 if (*speed == SPEED_100) { 479 if (!(data & NWAY_LPAR_100TX_FD_CAPS)) 480 *duplex = HALF_DUPLEX; 481 } else if (*speed == SPEED_10) { 482 if (!(data & NWAY_LPAR_10T_FD_CAPS)) 483 *duplex = HALF_DUPLEX; 484 } 485 } 486 487 out: 488 return ret_val; 489 } 490 491 /** 492 * e1000_phy_hw_reset_82541 - PHY hardware reset 493 * @hw: pointer to the HW structure 494 * 495 * Verify the reset block is not blocking us from resetting. Acquire 496 * semaphore (if necessary) and read/set/write the device control reset 497 * bit in the PHY. Wait the appropriate delay time for the device to 498 * reset and release the semaphore (if necessary). 499 **/ 500 static s32 e1000_phy_hw_reset_82541(struct e1000_hw *hw) 501 { 502 s32 ret_val; 503 u32 ledctl; 504 505 DEBUGFUNC("e1000_phy_hw_reset_82541"); 506 507 ret_val = e1000_phy_hw_reset_generic(hw); 508 if (ret_val) 509 goto out; 510 511 e1000_phy_init_script_82541(hw); 512 513 if ((hw->mac.type == e1000_82541) || (hw->mac.type == e1000_82547)) { 514 /* Configure activity LED after PHY reset */ 515 ledctl = E1000_READ_REG(hw, E1000_LEDCTL); 516 ledctl &= IGP_ACTIVITY_LED_MASK; 517 ledctl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 518 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl); 519 } 520 521 out: 522 return ret_val; 523 } 524 525 /** 526 * e1000_setup_copper_link_82541 - Configure copper link settings 527 * @hw: pointer to the HW structure 528 * 529 * Calls the appropriate function to configure the link for auto-neg or forced 530 * speed and duplex. Then we check for link, once link is established calls 531 * to configure collision distance and flow control are called. If link is 532 * not established, we return -E1000_ERR_PHY (-2). 533 **/ 534 static s32 e1000_setup_copper_link_82541(struct e1000_hw *hw) 535 { 536 struct e1000_phy_info *phy = &hw->phy; 537 struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541; 538 s32 ret_val; 539 u32 ctrl, ledctl; 540 541 DEBUGFUNC("e1000_setup_copper_link_82541"); 542 543 ctrl = E1000_READ_REG(hw, E1000_CTRL); 544 ctrl |= E1000_CTRL_SLU; 545 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 546 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 547 548 549 /* Earlier revs of the IGP phy require us to force MDI. */ 550 if (hw->mac.type == e1000_82541 || hw->mac.type == e1000_82547) { 551 dev_spec->dsp_config = e1000_dsp_config_disabled; 552 phy->mdix = 1; 553 } else { 554 dev_spec->dsp_config = e1000_dsp_config_enabled; 555 } 556 557 ret_val = e1000_copper_link_setup_igp(hw); 558 if (ret_val) 559 goto out; 560 561 if (hw->mac.autoneg) { 562 if (dev_spec->ffe_config == e1000_ffe_config_active) 563 dev_spec->ffe_config = e1000_ffe_config_enabled; 564 } 565 566 /* Configure activity LED after Phy reset */ 567 ledctl = E1000_READ_REG(hw, E1000_LEDCTL); 568 ledctl &= IGP_ACTIVITY_LED_MASK; 569 ledctl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 570 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl); 571 572 ret_val = e1000_setup_copper_link_generic(hw); 573 574 out: 575 return ret_val; 576 } 577 578 /** 579 * e1000_check_for_link_82541 - Check/Store link connection 580 * @hw: pointer to the HW structure 581 * 582 * This checks the link condition of the adapter and stores the 583 * results in the hw->mac structure. 584 **/ 585 static s32 e1000_check_for_link_82541(struct e1000_hw *hw) 586 { 587 struct e1000_mac_info *mac = &hw->mac; 588 s32 ret_val; 589 bool link; 590 591 DEBUGFUNC("e1000_check_for_link_82541"); 592 593 /* 594 * We only want to go out to the PHY registers to see if Auto-Neg 595 * has completed and/or if our link status has changed. The 596 * get_link_status flag is set upon receiving a Link Status 597 * Change or Rx Sequence Error interrupt. 598 */ 599 if (!mac->get_link_status) { 600 ret_val = E1000_SUCCESS; 601 goto out; 602 } 603 604 /* 605 * First we want to see if the MII Status Register reports 606 * link. If so, then we want to get the current speed/duplex 607 * of the PHY. 608 */ 609 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 610 if (ret_val) 611 goto out; 612 613 if (!link) { 614 ret_val = e1000_config_dsp_after_link_change_82541(hw, false); 615 goto out; /* No link detected */ 616 } 617 618 mac->get_link_status = false; 619 620 /* 621 * Check if there was DownShift, must be checked 622 * immediately after link-up 623 */ 624 e1000_check_downshift_generic(hw); 625 626 /* 627 * If we are forcing speed/duplex, then we simply return since 628 * we have already determined whether we have link or not. 629 */ 630 if (!mac->autoneg) { 631 ret_val = -E1000_ERR_CONFIG; 632 goto out; 633 } 634 635 ret_val = e1000_config_dsp_after_link_change_82541(hw, true); 636 637 /* 638 * Auto-Neg is enabled. Auto Speed Detection takes care 639 * of MAC speed/duplex configuration. So we only need to 640 * configure Collision Distance in the MAC. 641 */ 642 mac->ops.config_collision_dist(hw); 643 644 /* 645 * Configure Flow Control now that Auto-Neg has completed. 646 * First, we need to restore the desired flow control 647 * settings because we may have had to re-autoneg with a 648 * different link partner. 649 */ 650 ret_val = e1000_config_fc_after_link_up_generic(hw); 651 if (ret_val) 652 DEBUGOUT("Error configuring flow control\n"); 653 654 out: 655 return ret_val; 656 } 657 658 /** 659 * e1000_config_dsp_after_link_change_82541 - Config DSP after link 660 * @hw: pointer to the HW structure 661 * @link_up: boolean flag for link up status 662 * 663 * Return E1000_ERR_PHY when failing to read/write the PHY, else E1000_SUCCESS 664 * at any other case. 665 * 666 * 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a 667 * gigabit link is achieved to improve link quality. 668 **/ 669 static s32 e1000_config_dsp_after_link_change_82541(struct e1000_hw *hw, 670 bool link_up) 671 { 672 struct e1000_phy_info *phy = &hw->phy; 673 struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541; 674 s32 ret_val; 675 u32 idle_errs = 0; 676 u16 phy_data, phy_saved_data, speed, duplex, i; 677 u16 ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_20; 678 u16 dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = { 679 IGP01E1000_PHY_AGC_PARAM_A, 680 IGP01E1000_PHY_AGC_PARAM_B, 681 IGP01E1000_PHY_AGC_PARAM_C, 682 IGP01E1000_PHY_AGC_PARAM_D}; 683 684 DEBUGFUNC("e1000_config_dsp_after_link_change_82541"); 685 686 if (link_up) { 687 ret_val = hw->mac.ops.get_link_up_info(hw, &speed, &duplex); 688 if (ret_val) { 689 DEBUGOUT("Error getting link speed and duplex\n"); 690 goto out; 691 } 692 693 if (speed != SPEED_1000) { 694 ret_val = E1000_SUCCESS; 695 goto out; 696 } 697 698 ret_val = phy->ops.get_cable_length(hw); 699 if (ret_val) 700 goto out; 701 702 if ((dev_spec->dsp_config == e1000_dsp_config_enabled) && 703 phy->min_cable_length >= 50) { 704 705 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { 706 ret_val = phy->ops.read_reg(hw, 707 dsp_reg_array[i], 708 &phy_data); 709 if (ret_val) 710 goto out; 711 712 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX; 713 714 ret_val = phy->ops.write_reg(hw, 715 dsp_reg_array[i], 716 phy_data); 717 if (ret_val) 718 goto out; 719 } 720 dev_spec->dsp_config = e1000_dsp_config_activated; 721 } 722 723 if ((dev_spec->ffe_config != e1000_ffe_config_enabled) || 724 (phy->min_cable_length >= 50)) { 725 ret_val = E1000_SUCCESS; 726 goto out; 727 } 728 729 /* clear previous idle error counts */ 730 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data); 731 if (ret_val) 732 goto out; 733 734 for (i = 0; i < ffe_idle_err_timeout; i++) { 735 usec_delay(1000); 736 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, 737 &phy_data); 738 if (ret_val) 739 goto out; 740 741 idle_errs += (phy_data & SR_1000T_IDLE_ERROR_CNT); 742 if (idle_errs > SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) { 743 dev_spec->ffe_config = e1000_ffe_config_active; 744 745 ret_val = phy->ops.write_reg(hw, 746 IGP01E1000_PHY_DSP_FFE, 747 IGP01E1000_PHY_DSP_FFE_CM_CP); 748 if (ret_val) 749 goto out; 750 break; 751 } 752 753 if (idle_errs) 754 ffe_idle_err_timeout = 755 FFE_IDLE_ERR_COUNT_TIMEOUT_100; 756 } 757 } else { 758 if (dev_spec->dsp_config == e1000_dsp_config_activated) { 759 /* 760 * Save off the current value of register 0x2F5B 761 * to be restored at the end of the routines. 762 */ 763 ret_val = phy->ops.read_reg(hw, 0x2F5B, 764 &phy_saved_data); 765 if (ret_val) 766 goto out; 767 768 /* Disable the PHY transmitter */ 769 ret_val = phy->ops.write_reg(hw, 0x2F5B, 0x0003); 770 if (ret_val) 771 goto out; 772 773 msec_delay_irq(20); 774 775 ret_val = phy->ops.write_reg(hw, 0x0000, 776 IGP01E1000_IEEE_FORCE_GIG); 777 if (ret_val) 778 goto out; 779 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { 780 ret_val = phy->ops.read_reg(hw, 781 dsp_reg_array[i], 782 &phy_data); 783 if (ret_val) 784 goto out; 785 786 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX; 787 phy_data |= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS; 788 789 ret_val = phy->ops.write_reg(hw, 790 dsp_reg_array[i], 791 phy_data); 792 if (ret_val) 793 goto out; 794 } 795 796 ret_val = phy->ops.write_reg(hw, 0x0000, 797 IGP01E1000_IEEE_RESTART_AUTONEG); 798 if (ret_val) 799 goto out; 800 801 msec_delay_irq(20); 802 803 /* Now enable the transmitter */ 804 ret_val = phy->ops.write_reg(hw, 0x2F5B, 805 phy_saved_data); 806 if (ret_val) 807 goto out; 808 809 dev_spec->dsp_config = e1000_dsp_config_enabled; 810 } 811 812 if (dev_spec->ffe_config != e1000_ffe_config_active) { 813 ret_val = E1000_SUCCESS; 814 goto out; 815 } 816 817 /* 818 * Save off the current value of register 0x2F5B 819 * to be restored at the end of the routines. 820 */ 821 ret_val = phy->ops.read_reg(hw, 0x2F5B, &phy_saved_data); 822 if (ret_val) 823 goto out; 824 825 /* Disable the PHY transmitter */ 826 ret_val = phy->ops.write_reg(hw, 0x2F5B, 0x0003); 827 if (ret_val) 828 goto out; 829 830 msec_delay_irq(20); 831 832 ret_val = phy->ops.write_reg(hw, 0x0000, 833 IGP01E1000_IEEE_FORCE_GIG); 834 if (ret_val) 835 goto out; 836 837 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_DSP_FFE, 838 IGP01E1000_PHY_DSP_FFE_DEFAULT); 839 if (ret_val) 840 goto out; 841 842 ret_val = phy->ops.write_reg(hw, 0x0000, 843 IGP01E1000_IEEE_RESTART_AUTONEG); 844 if (ret_val) 845 goto out; 846 847 msec_delay_irq(20); 848 849 /* Now enable the transmitter */ 850 ret_val = phy->ops.write_reg(hw, 0x2F5B, phy_saved_data); 851 852 if (ret_val) 853 goto out; 854 855 dev_spec->ffe_config = e1000_ffe_config_enabled; 856 } 857 858 out: 859 return ret_val; 860 } 861 862 /** 863 * e1000_get_cable_length_igp_82541 - Determine cable length for igp PHY 864 * @hw: pointer to the HW structure 865 * 866 * The automatic gain control (agc) normalizes the amplitude of the 867 * received signal, adjusting for the attenuation produced by the 868 * cable. By reading the AGC registers, which represent the 869 * combination of coarse and fine gain value, the value can be put 870 * into a lookup table to obtain the approximate cable length 871 * for each channel. 872 **/ 873 static s32 e1000_get_cable_length_igp_82541(struct e1000_hw *hw) 874 { 875 struct e1000_phy_info *phy = &hw->phy; 876 s32 ret_val = E1000_SUCCESS; 877 u16 i, data; 878 u16 cur_agc_value, agc_value = 0; 879 u16 min_agc_value = IGP01E1000_AGC_LENGTH_TABLE_SIZE; 880 u16 agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = {IGP01E1000_PHY_AGC_A, 881 IGP01E1000_PHY_AGC_B, 882 IGP01E1000_PHY_AGC_C, 883 IGP01E1000_PHY_AGC_D}; 884 885 DEBUGFUNC("e1000_get_cable_length_igp_82541"); 886 887 /* Read the AGC registers for all channels */ 888 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { 889 ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &data); 890 if (ret_val) 891 goto out; 892 893 cur_agc_value = data >> IGP01E1000_AGC_LENGTH_SHIFT; 894 895 /* Bounds checking */ 896 if ((cur_agc_value >= IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) || 897 (cur_agc_value == 0)) { 898 ret_val = -E1000_ERR_PHY; 899 goto out; 900 } 901 902 agc_value += cur_agc_value; 903 904 if (min_agc_value > cur_agc_value) 905 min_agc_value = cur_agc_value; 906 } 907 908 /* Remove the minimal AGC result for length < 50m */ 909 if (agc_value < IGP01E1000_PHY_CHANNEL_NUM * 50) { 910 agc_value -= min_agc_value; 911 /* Average the three remaining channels for the length. */ 912 agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1); 913 } else { 914 /* Average the channels for the length. */ 915 agc_value /= IGP01E1000_PHY_CHANNEL_NUM; 916 } 917 918 phy->min_cable_length = (e1000_igp_cable_length_table[agc_value] > 919 IGP01E1000_AGC_RANGE) 920 ? (e1000_igp_cable_length_table[agc_value] - 921 IGP01E1000_AGC_RANGE) 922 : 0; 923 phy->max_cable_length = e1000_igp_cable_length_table[agc_value] + 924 IGP01E1000_AGC_RANGE; 925 926 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; 927 928 out: 929 return ret_val; 930 } 931 932 /** 933 * e1000_set_d3_lplu_state_82541 - Sets low power link up state for D3 934 * @hw: pointer to the HW structure 935 * @active: boolean used to enable/disable lplu 936 * 937 * Success returns 0, Failure returns 1 938 * 939 * The low power link up (lplu) state is set to the power management level D3 940 * and SmartSpeed is disabled when active is true, else clear lplu for D3 941 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU 942 * is used during Dx states where the power conservation is most important. 943 * During driver activity, SmartSpeed should be enabled so performance is 944 * maintained. 945 **/ 946 static s32 e1000_set_d3_lplu_state_82541(struct e1000_hw *hw, bool active) 947 { 948 struct e1000_phy_info *phy = &hw->phy; 949 s32 ret_val; 950 u16 data; 951 952 DEBUGFUNC("e1000_set_d3_lplu_state_82541"); 953 954 switch (hw->mac.type) { 955 case e1000_82541_rev_2: 956 case e1000_82547_rev_2: 957 break; 958 default: 959 ret_val = e1000_set_d3_lplu_state_generic(hw, active); 960 goto out; 961 break; 962 } 963 964 ret_val = phy->ops.read_reg(hw, IGP01E1000_GMII_FIFO, &data); 965 if (ret_val) 966 goto out; 967 968 if (!active) { 969 data &= ~IGP01E1000_GMII_FLEX_SPD; 970 ret_val = phy->ops.write_reg(hw, IGP01E1000_GMII_FIFO, data); 971 if (ret_val) 972 goto out; 973 974 /* 975 * LPLU and SmartSpeed are mutually exclusive. LPLU is used 976 * during Dx states where the power conservation is most 977 * important. During driver activity we should enable 978 * SmartSpeed, so performance is maintained. 979 */ 980 if (phy->smart_speed == e1000_smart_speed_on) { 981 ret_val = phy->ops.read_reg(hw, 982 IGP01E1000_PHY_PORT_CONFIG, 983 &data); 984 if (ret_val) 985 goto out; 986 987 data |= IGP01E1000_PSCFR_SMART_SPEED; 988 ret_val = phy->ops.write_reg(hw, 989 IGP01E1000_PHY_PORT_CONFIG, 990 data); 991 if (ret_val) 992 goto out; 993 } else if (phy->smart_speed == e1000_smart_speed_off) { 994 ret_val = phy->ops.read_reg(hw, 995 IGP01E1000_PHY_PORT_CONFIG, 996 &data); 997 if (ret_val) 998 goto out; 999 1000 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1001 ret_val = phy->ops.write_reg(hw, 1002 IGP01E1000_PHY_PORT_CONFIG, 1003 data); 1004 if (ret_val) 1005 goto out; 1006 } 1007 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || 1008 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || 1009 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { 1010 data |= IGP01E1000_GMII_FLEX_SPD; 1011 ret_val = phy->ops.write_reg(hw, IGP01E1000_GMII_FIFO, data); 1012 if (ret_val) 1013 goto out; 1014 1015 /* When LPLU is enabled, we should disable SmartSpeed */ 1016 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 1017 &data); 1018 if (ret_val) 1019 goto out; 1020 1021 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1022 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 1023 data); 1024 } 1025 1026 out: 1027 return ret_val; 1028 } 1029 1030 /** 1031 * e1000_setup_led_82541 - Configures SW controllable LED 1032 * @hw: pointer to the HW structure 1033 * 1034 * This prepares the SW controllable LED for use and saves the current state 1035 * of the LED so it can be later restored. 1036 **/ 1037 static s32 e1000_setup_led_82541(struct e1000_hw *hw) 1038 { 1039 struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541; 1040 s32 ret_val; 1041 1042 DEBUGFUNC("e1000_setup_led_82541"); 1043 1044 ret_val = hw->phy.ops.read_reg(hw, IGP01E1000_GMII_FIFO, 1045 &dev_spec->spd_default); 1046 if (ret_val) 1047 goto out; 1048 1049 ret_val = hw->phy.ops.write_reg(hw, IGP01E1000_GMII_FIFO, 1050 (u16)(dev_spec->spd_default & 1051 ~IGP01E1000_GMII_SPD)); 1052 if (ret_val) 1053 goto out; 1054 1055 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1); 1056 1057 out: 1058 return ret_val; 1059 } 1060 1061 /** 1062 * e1000_cleanup_led_82541 - Set LED config to default operation 1063 * @hw: pointer to the HW structure 1064 * 1065 * Remove the current LED configuration and set the LED configuration 1066 * to the default value, saved from the EEPROM. 1067 **/ 1068 static s32 e1000_cleanup_led_82541(struct e1000_hw *hw) 1069 { 1070 struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541; 1071 s32 ret_val; 1072 1073 DEBUGFUNC("e1000_cleanup_led_82541"); 1074 1075 ret_val = hw->phy.ops.write_reg(hw, IGP01E1000_GMII_FIFO, 1076 dev_spec->spd_default); 1077 if (ret_val) 1078 goto out; 1079 1080 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default); 1081 1082 out: 1083 return ret_val; 1084 } 1085 1086 /** 1087 * e1000_phy_init_script_82541 - Initialize GbE PHY 1088 * @hw: pointer to the HW structure 1089 * 1090 * Initializes the IGP PHY. 1091 **/ 1092 static s32 e1000_phy_init_script_82541(struct e1000_hw *hw) 1093 { 1094 struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541; 1095 u32 ret_val; 1096 u16 phy_saved_data; 1097 1098 DEBUGFUNC("e1000_phy_init_script_82541"); 1099 1100 if (!dev_spec->phy_init_script) { 1101 ret_val = E1000_SUCCESS; 1102 goto out; 1103 } 1104 1105 /* Delay after phy reset to enable NVM configuration to load */ 1106 msec_delay(20); 1107 1108 /* 1109 * Save off the current value of register 0x2F5B to be restored at 1110 * the end of this routine. 1111 */ 1112 ret_val = hw->phy.ops.read_reg(hw, 0x2F5B, &phy_saved_data); 1113 1114 /* Disabled the PHY transmitter */ 1115 hw->phy.ops.write_reg(hw, 0x2F5B, 0x0003); 1116 1117 msec_delay(20); 1118 1119 hw->phy.ops.write_reg(hw, 0x0000, 0x0140); 1120 1121 msec_delay(5); 1122 1123 switch (hw->mac.type) { 1124 case e1000_82541: 1125 case e1000_82547: 1126 hw->phy.ops.write_reg(hw, 0x1F95, 0x0001); 1127 1128 hw->phy.ops.write_reg(hw, 0x1F71, 0xBD21); 1129 1130 hw->phy.ops.write_reg(hw, 0x1F79, 0x0018); 1131 1132 hw->phy.ops.write_reg(hw, 0x1F30, 0x1600); 1133 1134 hw->phy.ops.write_reg(hw, 0x1F31, 0x0014); 1135 1136 hw->phy.ops.write_reg(hw, 0x1F32, 0x161C); 1137 1138 hw->phy.ops.write_reg(hw, 0x1F94, 0x0003); 1139 1140 hw->phy.ops.write_reg(hw, 0x1F96, 0x003F); 1141 1142 hw->phy.ops.write_reg(hw, 0x2010, 0x0008); 1143 break; 1144 case e1000_82541_rev_2: 1145 case e1000_82547_rev_2: 1146 hw->phy.ops.write_reg(hw, 0x1F73, 0x0099); 1147 break; 1148 default: 1149 break; 1150 } 1151 1152 hw->phy.ops.write_reg(hw, 0x0000, 0x3300); 1153 1154 msec_delay(20); 1155 1156 /* Now enable the transmitter */ 1157 hw->phy.ops.write_reg(hw, 0x2F5B, phy_saved_data); 1158 1159 if (hw->mac.type == e1000_82547) { 1160 u16 fused, fine, coarse; 1161 1162 /* Move to analog registers page */ 1163 hw->phy.ops.read_reg(hw, IGP01E1000_ANALOG_SPARE_FUSE_STATUS, 1164 &fused); 1165 1166 if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) { 1167 hw->phy.ops.read_reg(hw, IGP01E1000_ANALOG_FUSE_STATUS, 1168 &fused); 1169 1170 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK; 1171 coarse = fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK; 1172 1173 if (coarse > IGP01E1000_ANALOG_FUSE_COARSE_THRESH) { 1174 coarse -= IGP01E1000_ANALOG_FUSE_COARSE_10; 1175 fine -= IGP01E1000_ANALOG_FUSE_FINE_1; 1176 } else if (coarse == 1177 IGP01E1000_ANALOG_FUSE_COARSE_THRESH) 1178 fine -= IGP01E1000_ANALOG_FUSE_FINE_10; 1179 1180 fused = (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) | 1181 (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) | 1182 (coarse & IGP01E1000_ANALOG_FUSE_COARSE_MASK); 1183 1184 hw->phy.ops.write_reg(hw, 1185 IGP01E1000_ANALOG_FUSE_CONTROL, 1186 fused); 1187 hw->phy.ops.write_reg(hw, 1188 IGP01E1000_ANALOG_FUSE_BYPASS, 1189 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL); 1190 } 1191 } 1192 1193 out: 1194 return ret_val; 1195 } 1196 1197 /** 1198 * e1000_init_script_state_82541 - Enable/Disable PHY init script 1199 * @hw: pointer to the HW structure 1200 * @state: boolean value used to enable/disable PHY init script 1201 * 1202 * Allows the driver to enable/disable the PHY init script, if the PHY is an 1203 * IGP PHY. 1204 **/ 1205 void e1000_init_script_state_82541(struct e1000_hw *hw, bool state) 1206 { 1207 struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541; 1208 1209 DEBUGFUNC("e1000_init_script_state_82541"); 1210 1211 if (hw->phy.type != e1000_phy_igp) { 1212 DEBUGOUT("Initialization script not necessary.\n"); 1213 goto out; 1214 } 1215 1216 dev_spec->phy_init_script = state; 1217 1218 out: 1219 return; 1220 } 1221 1222 /** 1223 * e1000_power_down_phy_copper_82541 - Remove link in case of PHY power down 1224 * @hw: pointer to the HW structure 1225 * 1226 * In the case of a PHY power down to save power, or to turn off link during a 1227 * driver unload, or wake on lan is not enabled, remove the link. 1228 **/ 1229 static void e1000_power_down_phy_copper_82541(struct e1000_hw *hw) 1230 { 1231 /* If the management interface is not enabled, then power down */ 1232 if (!(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_SMBUS_EN)) 1233 e1000_power_down_phy_copper(hw); 1234 1235 return; 1236 } 1237 1238 /** 1239 * e1000_clear_hw_cntrs_82541 - Clear device specific hardware counters 1240 * @hw: pointer to the HW structure 1241 * 1242 * Clears the hardware counters by reading the counter registers. 1243 **/ 1244 static void e1000_clear_hw_cntrs_82541(struct e1000_hw *hw) 1245 { 1246 DEBUGFUNC("e1000_clear_hw_cntrs_82541"); 1247 1248 e1000_clear_hw_cntrs_base_generic(hw); 1249 1250 E1000_READ_REG(hw, E1000_PRC64); 1251 E1000_READ_REG(hw, E1000_PRC127); 1252 E1000_READ_REG(hw, E1000_PRC255); 1253 E1000_READ_REG(hw, E1000_PRC511); 1254 E1000_READ_REG(hw, E1000_PRC1023); 1255 E1000_READ_REG(hw, E1000_PRC1522); 1256 E1000_READ_REG(hw, E1000_PTC64); 1257 E1000_READ_REG(hw, E1000_PTC127); 1258 E1000_READ_REG(hw, E1000_PTC255); 1259 E1000_READ_REG(hw, E1000_PTC511); 1260 E1000_READ_REG(hw, E1000_PTC1023); 1261 E1000_READ_REG(hw, E1000_PTC1522); 1262 1263 E1000_READ_REG(hw, E1000_ALGNERRC); 1264 E1000_READ_REG(hw, E1000_RXERRC); 1265 E1000_READ_REG(hw, E1000_TNCRS); 1266 E1000_READ_REG(hw, E1000_CEXTERR); 1267 E1000_READ_REG(hw, E1000_TSCTC); 1268 E1000_READ_REG(hw, E1000_TSCTFC); 1269 1270 E1000_READ_REG(hw, E1000_MGTPRC); 1271 E1000_READ_REG(hw, E1000_MGTPDC); 1272 E1000_READ_REG(hw, E1000_MGTPTC); 1273 } 1274 1275 /** 1276 * e1000_read_mac_addr_82541 - Read device MAC address 1277 * @hw: pointer to the HW structure 1278 * 1279 * Reads the device MAC address from the EEPROM and stores the value. 1280 **/ 1281 static s32 e1000_read_mac_addr_82541(struct e1000_hw *hw) 1282 { 1283 s32 ret_val = E1000_SUCCESS; 1284 u16 offset, nvm_data, i; 1285 1286 DEBUGFUNC("e1000_read_mac_addr"); 1287 1288 for (i = 0; i < ETHER_ADDR_LEN; i += 2) { 1289 offset = i >> 1; 1290 ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data); 1291 if (ret_val) { 1292 DEBUGOUT("NVM Read Error\n"); 1293 goto out; 1294 } 1295 hw->mac.perm_addr[i] = (u8)(nvm_data & 0xFF); 1296 hw->mac.perm_addr[i+1] = (u8)(nvm_data >> 8); 1297 } 1298 1299 for (i = 0; i < ETHER_ADDR_LEN; i++) 1300 hw->mac.addr[i] = hw->mac.perm_addr[i]; 1301 1302 out: 1303 return ret_val; 1304 } 1305
Cache object: 701c859ab62af10194d857cb39c69232
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