1 /******************************************************************************
2 SPDX-License-Identifier: BSD-3-Clause
3
4 Copyright (c) 2001-2020, Intel Corporation
5 All rights reserved.
6
7 Redistribution and use in source and binary forms, with or without
8 modification, are permitted provided that the following conditions are met:
9
10 1. Redistributions of source code must retain the above copyright notice,
11 this list of conditions and the following disclaimer.
12
13 2. Redistributions in binary form must reproduce the above copyright
14 notice, this list of conditions and the following disclaimer in the
15 documentation and/or other materials provided with the distribution.
16
17 3. Neither the name of the Intel Corporation nor the names of its
18 contributors may be used to endorse or promote products derived from
19 this software without specific prior written permission.
20
21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 POSSIBILITY OF SUCH DAMAGE.
32
33 ******************************************************************************/
34 /*$FreeBSD$*/
35
36 #ifndef _E1000_82541_H_
37 #define _E1000_82541_H_
38
39 #define NVM_WORD_SIZE_BASE_SHIFT_82541 (NVM_WORD_SIZE_BASE_SHIFT + 1)
40
41 #define IGP01E1000_PHY_CHANNEL_NUM 4
42
43 #define IGP01E1000_PHY_AGC_A 0x1172
44 #define IGP01E1000_PHY_AGC_B 0x1272
45 #define IGP01E1000_PHY_AGC_C 0x1472
46 #define IGP01E1000_PHY_AGC_D 0x1872
47
48 #define IGP01E1000_PHY_AGC_PARAM_A 0x1171
49 #define IGP01E1000_PHY_AGC_PARAM_B 0x1271
50 #define IGP01E1000_PHY_AGC_PARAM_C 0x1471
51 #define IGP01E1000_PHY_AGC_PARAM_D 0x1871
52
53 #define IGP01E1000_PHY_EDAC_MU_INDEX 0xC000
54 #define IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS 0x8000
55
56 #define IGP01E1000_PHY_DSP_RESET 0x1F33
57
58 #define IGP01E1000_PHY_DSP_FFE 0x1F35
59 #define IGP01E1000_PHY_DSP_FFE_CM_CP 0x0069
60 #define IGP01E1000_PHY_DSP_FFE_DEFAULT 0x002A
61
62 #define IGP01E1000_IEEE_FORCE_GIG 0x0140
63 #define IGP01E1000_IEEE_RESTART_AUTONEG 0x3300
64
65 #define IGP01E1000_AGC_LENGTH_SHIFT 7
66 #define IGP01E1000_AGC_RANGE 10
67
68 #define FFE_IDLE_ERR_COUNT_TIMEOUT_20 20
69 #define FFE_IDLE_ERR_COUNT_TIMEOUT_100 100
70
71 #define IGP01E1000_ANALOG_FUSE_STATUS 0x20D0
72 #define IGP01E1000_ANALOG_SPARE_FUSE_STATUS 0x20D1
73 #define IGP01E1000_ANALOG_FUSE_CONTROL 0x20DC
74 #define IGP01E1000_ANALOG_FUSE_BYPASS 0x20DE
75
76 #define IGP01E1000_ANALOG_SPARE_FUSE_ENABLED 0x0100
77 #define IGP01E1000_ANALOG_FUSE_FINE_MASK 0x0F80
78 #define IGP01E1000_ANALOG_FUSE_COARSE_MASK 0x0070
79 #define IGP01E1000_ANALOG_FUSE_COARSE_THRESH 0x0040
80 #define IGP01E1000_ANALOG_FUSE_COARSE_10 0x0010
81 #define IGP01E1000_ANALOG_FUSE_FINE_1 0x0080
82 #define IGP01E1000_ANALOG_FUSE_FINE_10 0x0500
83 #define IGP01E1000_ANALOG_FUSE_POLY_MASK 0xF000
84 #define IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL 0x0002
85
86 #define IGP01E1000_MSE_CHANNEL_D 0x000F
87 #define IGP01E1000_MSE_CHANNEL_C 0x00F0
88 #define IGP01E1000_MSE_CHANNEL_B 0x0F00
89 #define IGP01E1000_MSE_CHANNEL_A 0xF000
90
91
92 void e1000_init_script_state_82541(struct e1000_hw *hw, bool state);
93 #endif
Cache object: 2f07b4743e23ec97f33cdd28664950dc
|