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sys/dev/e1000/e1000_hw.h
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1 /****************************************************************************** 2 3 Copyright (c) 2001-2010, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD: releng/9.0/sys/dev/e1000/e1000_hw.h 218530 2011-02-11 01:00:26Z jfv $*/ 34 35 #ifndef _E1000_HW_H_ 36 #define _E1000_HW_H_ 37 38 #include "e1000_osdep.h" 39 #include "e1000_regs.h" 40 #include "e1000_defines.h" 41 42 struct e1000_hw; 43 44 #define E1000_DEV_ID_82542 0x1000 45 #define E1000_DEV_ID_82543GC_FIBER 0x1001 46 #define E1000_DEV_ID_82543GC_COPPER 0x1004 47 #define E1000_DEV_ID_82544EI_COPPER 0x1008 48 #define E1000_DEV_ID_82544EI_FIBER 0x1009 49 #define E1000_DEV_ID_82544GC_COPPER 0x100C 50 #define E1000_DEV_ID_82544GC_LOM 0x100D 51 #define E1000_DEV_ID_82540EM 0x100E 52 #define E1000_DEV_ID_82540EM_LOM 0x1015 53 #define E1000_DEV_ID_82540EP_LOM 0x1016 54 #define E1000_DEV_ID_82540EP 0x1017 55 #define E1000_DEV_ID_82540EP_LP 0x101E 56 #define E1000_DEV_ID_82545EM_COPPER 0x100F 57 #define E1000_DEV_ID_82545EM_FIBER 0x1011 58 #define E1000_DEV_ID_82545GM_COPPER 0x1026 59 #define E1000_DEV_ID_82545GM_FIBER 0x1027 60 #define E1000_DEV_ID_82545GM_SERDES 0x1028 61 #define E1000_DEV_ID_82546EB_COPPER 0x1010 62 #define E1000_DEV_ID_82546EB_FIBER 0x1012 63 #define E1000_DEV_ID_82546EB_QUAD_COPPER 0x101D 64 #define E1000_DEV_ID_82546GB_COPPER 0x1079 65 #define E1000_DEV_ID_82546GB_FIBER 0x107A 66 #define E1000_DEV_ID_82546GB_SERDES 0x107B 67 #define E1000_DEV_ID_82546GB_PCIE 0x108A 68 #define E1000_DEV_ID_82546GB_QUAD_COPPER 0x1099 69 #define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5 70 #define E1000_DEV_ID_82541EI 0x1013 71 #define E1000_DEV_ID_82541EI_MOBILE 0x1018 72 #define E1000_DEV_ID_82541ER_LOM 0x1014 73 #define E1000_DEV_ID_82541ER 0x1078 74 #define E1000_DEV_ID_82541GI 0x1076 75 #define E1000_DEV_ID_82541GI_LF 0x107C 76 #define E1000_DEV_ID_82541GI_MOBILE 0x1077 77 #define E1000_DEV_ID_82547EI 0x1019 78 #define E1000_DEV_ID_82547EI_MOBILE 0x101A 79 #define E1000_DEV_ID_82547GI 0x1075 80 #define E1000_DEV_ID_82571EB_COPPER 0x105E 81 #define E1000_DEV_ID_82571EB_FIBER 0x105F 82 #define E1000_DEV_ID_82571EB_SERDES 0x1060 83 #define E1000_DEV_ID_82571EB_SERDES_DUAL 0x10D9 84 #define E1000_DEV_ID_82571EB_SERDES_QUAD 0x10DA 85 #define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4 86 #define E1000_DEV_ID_82571PT_QUAD_COPPER 0x10D5 87 #define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5 88 #define E1000_DEV_ID_82571EB_QUAD_COPPER_LP 0x10BC 89 #define E1000_DEV_ID_82572EI_COPPER 0x107D 90 #define E1000_DEV_ID_82572EI_FIBER 0x107E 91 #define E1000_DEV_ID_82572EI_SERDES 0x107F 92 #define E1000_DEV_ID_82572EI 0x10B9 93 #define E1000_DEV_ID_82573E 0x108B 94 #define E1000_DEV_ID_82573E_IAMT 0x108C 95 #define E1000_DEV_ID_82573L 0x109A 96 #define E1000_DEV_ID_82574L 0x10D3 97 #define E1000_DEV_ID_82574LA 0x10F6 98 #define E1000_DEV_ID_82583V 0x150C 99 #define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096 100 #define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098 101 #define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA 102 #define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB 103 #define E1000_DEV_ID_ICH8_82567V_3 0x1501 104 #define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049 105 #define E1000_DEV_ID_ICH8_IGP_AMT 0x104A 106 #define E1000_DEV_ID_ICH8_IGP_C 0x104B 107 #define E1000_DEV_ID_ICH8_IFE 0x104C 108 #define E1000_DEV_ID_ICH8_IFE_GT 0x10C4 109 #define E1000_DEV_ID_ICH8_IFE_G 0x10C5 110 #define E1000_DEV_ID_ICH8_IGP_M 0x104D 111 #define E1000_DEV_ID_ICH9_IGP_M 0x10BF 112 #define E1000_DEV_ID_ICH9_IGP_M_AMT 0x10F5 113 #define E1000_DEV_ID_ICH9_IGP_M_V 0x10CB 114 #define E1000_DEV_ID_ICH9_IGP_AMT 0x10BD 115 #define E1000_DEV_ID_ICH9_BM 0x10E5 116 #define E1000_DEV_ID_ICH9_IGP_C 0x294C 117 #define E1000_DEV_ID_ICH9_IFE 0x10C0 118 #define E1000_DEV_ID_ICH9_IFE_GT 0x10C3 119 #define E1000_DEV_ID_ICH9_IFE_G 0x10C2 120 #define E1000_DEV_ID_ICH10_R_BM_LM 0x10CC 121 #define E1000_DEV_ID_ICH10_R_BM_LF 0x10CD 122 #define E1000_DEV_ID_ICH10_R_BM_V 0x10CE 123 #define E1000_DEV_ID_ICH10_HANKSVILLE 0xF0FE 124 #define E1000_DEV_ID_ICH10_D_BM_LM 0x10DE 125 #define E1000_DEV_ID_ICH10_D_BM_LF 0x10DF 126 #define E1000_DEV_ID_ICH10_D_BM_V 0x1525 127 128 #define E1000_DEV_ID_PCH_M_HV_LM 0x10EA 129 #define E1000_DEV_ID_PCH_M_HV_LC 0x10EB 130 #define E1000_DEV_ID_PCH_D_HV_DM 0x10EF 131 #define E1000_DEV_ID_PCH_D_HV_DC 0x10F0 132 #define E1000_DEV_ID_PCH2_LV_LM 0x1502 133 #define E1000_DEV_ID_PCH2_LV_V 0x1503 134 #define E1000_DEV_ID_82576 0x10C9 135 #define E1000_DEV_ID_82576_FIBER 0x10E6 136 #define E1000_DEV_ID_82576_SERDES 0x10E7 137 #define E1000_DEV_ID_82576_QUAD_COPPER 0x10E8 138 #define E1000_DEV_ID_82576_QUAD_COPPER_ET2 0x1526 139 #define E1000_DEV_ID_82576_NS 0x150A 140 #define E1000_DEV_ID_82576_NS_SERDES 0x1518 141 #define E1000_DEV_ID_82576_SERDES_QUAD 0x150D 142 #define E1000_DEV_ID_82576_VF 0x10CA 143 #define E1000_DEV_ID_I350_VF 0x1520 144 #define E1000_DEV_ID_82575EB_COPPER 0x10A7 145 #define E1000_DEV_ID_82575EB_FIBER_SERDES 0x10A9 146 #define E1000_DEV_ID_82575GB_QUAD_COPPER 0x10D6 147 #define E1000_DEV_ID_82575GB_QUAD_COPPER_PM 0x10E2 148 #define E1000_DEV_ID_82580_COPPER 0x150E 149 #define E1000_DEV_ID_82580_FIBER 0x150F 150 #define E1000_DEV_ID_82580_SERDES 0x1510 151 #define E1000_DEV_ID_82580_SGMII 0x1511 152 #define E1000_DEV_ID_82580_COPPER_DUAL 0x1516 153 #define E1000_DEV_ID_82580_QUAD_FIBER 0x1527 154 #define E1000_DEV_ID_I350_COPPER 0x1521 155 #define E1000_DEV_ID_I350_FIBER 0x1522 156 #define E1000_DEV_ID_I350_SERDES 0x1523 157 #define E1000_DEV_ID_I350_SGMII 0x1524 158 #define E1000_DEV_ID_DH89XXCC_SGMII 0x0438 159 #define E1000_DEV_ID_DH89XXCC_SERDES 0x043A 160 #define E1000_DEV_ID_DH89XXCC_BACKPLANE 0x043C 161 #define E1000_DEV_ID_DH89XXCC_SFP 0x0440 162 #define E1000_REVISION_0 0 163 #define E1000_REVISION_1 1 164 #define E1000_REVISION_2 2 165 #define E1000_REVISION_3 3 166 #define E1000_REVISION_4 4 167 168 #define E1000_FUNC_0 0 169 #define E1000_FUNC_1 1 170 #define E1000_FUNC_2 2 171 #define E1000_FUNC_3 3 172 173 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0 0 174 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1 3 175 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN2 6 176 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN3 9 177 178 enum e1000_mac_type { 179 e1000_undefined = 0, 180 e1000_82542, 181 e1000_82543, 182 e1000_82544, 183 e1000_82540, 184 e1000_82545, 185 e1000_82545_rev_3, 186 e1000_82546, 187 e1000_82546_rev_3, 188 e1000_82541, 189 e1000_82541_rev_2, 190 e1000_82547, 191 e1000_82547_rev_2, 192 e1000_82571, 193 e1000_82572, 194 e1000_82573, 195 e1000_82574, 196 e1000_82583, 197 e1000_80003es2lan, 198 e1000_ich8lan, 199 e1000_ich9lan, 200 e1000_ich10lan, 201 e1000_pchlan, 202 e1000_pch2lan, 203 e1000_82575, 204 e1000_82576, 205 e1000_82580, 206 e1000_i350, 207 e1000_vfadapt, 208 e1000_vfadapt_i350, 209 e1000_num_macs /* List is 1-based, so subtract 1 for TRUE count. */ 210 }; 211 212 enum e1000_media_type { 213 e1000_media_type_unknown = 0, 214 e1000_media_type_copper = 1, 215 e1000_media_type_fiber = 2, 216 e1000_media_type_internal_serdes = 3, 217 e1000_num_media_types 218 }; 219 220 enum e1000_nvm_type { 221 e1000_nvm_unknown = 0, 222 e1000_nvm_none, 223 e1000_nvm_eeprom_spi, 224 e1000_nvm_eeprom_microwire, 225 e1000_nvm_flash_hw, 226 e1000_nvm_flash_sw 227 }; 228 229 enum e1000_nvm_override { 230 e1000_nvm_override_none = 0, 231 e1000_nvm_override_spi_small, 232 e1000_nvm_override_spi_large, 233 e1000_nvm_override_microwire_small, 234 e1000_nvm_override_microwire_large 235 }; 236 237 enum e1000_phy_type { 238 e1000_phy_unknown = 0, 239 e1000_phy_none, 240 e1000_phy_m88, 241 e1000_phy_igp, 242 e1000_phy_igp_2, 243 e1000_phy_gg82563, 244 e1000_phy_igp_3, 245 e1000_phy_ife, 246 e1000_phy_bm, 247 e1000_phy_82578, 248 e1000_phy_82577, 249 e1000_phy_82579, 250 e1000_phy_82580, 251 e1000_phy_vf, 252 }; 253 254 enum e1000_bus_type { 255 e1000_bus_type_unknown = 0, 256 e1000_bus_type_pci, 257 e1000_bus_type_pcix, 258 e1000_bus_type_pci_express, 259 e1000_bus_type_reserved 260 }; 261 262 enum e1000_bus_speed { 263 e1000_bus_speed_unknown = 0, 264 e1000_bus_speed_33, 265 e1000_bus_speed_66, 266 e1000_bus_speed_100, 267 e1000_bus_speed_120, 268 e1000_bus_speed_133, 269 e1000_bus_speed_2500, 270 e1000_bus_speed_5000, 271 e1000_bus_speed_reserved 272 }; 273 274 enum e1000_bus_width { 275 e1000_bus_width_unknown = 0, 276 e1000_bus_width_pcie_x1, 277 e1000_bus_width_pcie_x2, 278 e1000_bus_width_pcie_x4 = 4, 279 e1000_bus_width_pcie_x8 = 8, 280 e1000_bus_width_32, 281 e1000_bus_width_64, 282 e1000_bus_width_reserved 283 }; 284 285 enum e1000_1000t_rx_status { 286 e1000_1000t_rx_status_not_ok = 0, 287 e1000_1000t_rx_status_ok, 288 e1000_1000t_rx_status_undefined = 0xFF 289 }; 290 291 enum e1000_rev_polarity { 292 e1000_rev_polarity_normal = 0, 293 e1000_rev_polarity_reversed, 294 e1000_rev_polarity_undefined = 0xFF 295 }; 296 297 enum e1000_fc_mode { 298 e1000_fc_none = 0, 299 e1000_fc_rx_pause, 300 e1000_fc_tx_pause, 301 e1000_fc_full, 302 e1000_fc_default = 0xFF 303 }; 304 305 enum e1000_ffe_config { 306 e1000_ffe_config_enabled = 0, 307 e1000_ffe_config_active, 308 e1000_ffe_config_blocked 309 }; 310 311 enum e1000_dsp_config { 312 e1000_dsp_config_disabled = 0, 313 e1000_dsp_config_enabled, 314 e1000_dsp_config_activated, 315 e1000_dsp_config_undefined = 0xFF 316 }; 317 318 enum e1000_ms_type { 319 e1000_ms_hw_default = 0, 320 e1000_ms_force_master, 321 e1000_ms_force_slave, 322 e1000_ms_auto 323 }; 324 325 enum e1000_smart_speed { 326 e1000_smart_speed_default = 0, 327 e1000_smart_speed_on, 328 e1000_smart_speed_off 329 }; 330 331 enum e1000_serdes_link_state { 332 e1000_serdes_link_down = 0, 333 e1000_serdes_link_autoneg_progress, 334 e1000_serdes_link_autoneg_complete, 335 e1000_serdes_link_forced_up 336 }; 337 338 #define __le16 u16 339 #define __le32 u32 340 #define __le64 u64 341 /* Receive Descriptor */ 342 struct e1000_rx_desc { 343 __le64 buffer_addr; /* Address of the descriptor's data buffer */ 344 __le16 length; /* Length of data DMAed into data buffer */ 345 __le16 csum; /* Packet checksum */ 346 u8 status; /* Descriptor status */ 347 u8 errors; /* Descriptor Errors */ 348 __le16 special; 349 }; 350 351 /* Receive Descriptor - Extended */ 352 union e1000_rx_desc_extended { 353 struct { 354 __le64 buffer_addr; 355 __le64 reserved; 356 } read; 357 struct { 358 struct { 359 __le32 mrq; /* Multiple Rx Queues */ 360 union { 361 __le32 rss; /* RSS Hash */ 362 struct { 363 __le16 ip_id; /* IP id */ 364 __le16 csum; /* Packet Checksum */ 365 } csum_ip; 366 } hi_dword; 367 } lower; 368 struct { 369 __le32 status_error; /* ext status/error */ 370 __le16 length; 371 __le16 vlan; /* VLAN tag */ 372 } upper; 373 } wb; /* writeback */ 374 }; 375 376 #define MAX_PS_BUFFERS 4 377 /* Receive Descriptor - Packet Split */ 378 union e1000_rx_desc_packet_split { 379 struct { 380 /* one buffer for protocol header(s), three data buffers */ 381 __le64 buffer_addr[MAX_PS_BUFFERS]; 382 } read; 383 struct { 384 struct { 385 __le32 mrq; /* Multiple Rx Queues */ 386 union { 387 __le32 rss; /* RSS Hash */ 388 struct { 389 __le16 ip_id; /* IP id */ 390 __le16 csum; /* Packet Checksum */ 391 } csum_ip; 392 } hi_dword; 393 } lower; 394 struct { 395 __le32 status_error; /* ext status/error */ 396 __le16 length0; /* length of buffer 0 */ 397 __le16 vlan; /* VLAN tag */ 398 } middle; 399 struct { 400 __le16 header_status; 401 __le16 length[3]; /* length of buffers 1-3 */ 402 } upper; 403 __le64 reserved; 404 } wb; /* writeback */ 405 }; 406 407 /* Transmit Descriptor */ 408 struct e1000_tx_desc { 409 __le64 buffer_addr; /* Address of the descriptor's data buffer */ 410 union { 411 __le32 data; 412 struct { 413 __le16 length; /* Data buffer length */ 414 u8 cso; /* Checksum offset */ 415 u8 cmd; /* Descriptor control */ 416 } flags; 417 } lower; 418 union { 419 __le32 data; 420 struct { 421 u8 status; /* Descriptor status */ 422 u8 css; /* Checksum start */ 423 __le16 special; 424 } fields; 425 } upper; 426 }; 427 428 /* Offload Context Descriptor */ 429 struct e1000_context_desc { 430 union { 431 __le32 ip_config; 432 struct { 433 u8 ipcss; /* IP checksum start */ 434 u8 ipcso; /* IP checksum offset */ 435 __le16 ipcse; /* IP checksum end */ 436 } ip_fields; 437 } lower_setup; 438 union { 439 __le32 tcp_config; 440 struct { 441 u8 tucss; /* TCP checksum start */ 442 u8 tucso; /* TCP checksum offset */ 443 __le16 tucse; /* TCP checksum end */ 444 } tcp_fields; 445 } upper_setup; 446 __le32 cmd_and_length; 447 union { 448 __le32 data; 449 struct { 450 u8 status; /* Descriptor status */ 451 u8 hdr_len; /* Header length */ 452 __le16 mss; /* Maximum segment size */ 453 } fields; 454 } tcp_seg_setup; 455 }; 456 457 /* Offload data descriptor */ 458 struct e1000_data_desc { 459 __le64 buffer_addr; /* Address of the descriptor's buffer address */ 460 union { 461 __le32 data; 462 struct { 463 __le16 length; /* Data buffer length */ 464 u8 typ_len_ext; 465 u8 cmd; 466 } flags; 467 } lower; 468 union { 469 __le32 data; 470 struct { 471 u8 status; /* Descriptor status */ 472 u8 popts; /* Packet Options */ 473 __le16 special; 474 } fields; 475 } upper; 476 }; 477 478 /* Statistics counters collected by the MAC */ 479 struct e1000_hw_stats { 480 u64 crcerrs; 481 u64 algnerrc; 482 u64 symerrs; 483 u64 rxerrc; 484 u64 mpc; 485 u64 scc; 486 u64 ecol; 487 u64 mcc; 488 u64 latecol; 489 u64 colc; 490 u64 dc; 491 u64 tncrs; 492 u64 sec; 493 u64 cexterr; 494 u64 rlec; 495 u64 xonrxc; 496 u64 xontxc; 497 u64 xoffrxc; 498 u64 xofftxc; 499 u64 fcruc; 500 u64 prc64; 501 u64 prc127; 502 u64 prc255; 503 u64 prc511; 504 u64 prc1023; 505 u64 prc1522; 506 u64 gprc; 507 u64 bprc; 508 u64 mprc; 509 u64 gptc; 510 u64 gorc; 511 u64 gotc; 512 u64 rnbc; 513 u64 ruc; 514 u64 rfc; 515 u64 roc; 516 u64 rjc; 517 u64 mgprc; 518 u64 mgpdc; 519 u64 mgptc; 520 u64 tor; 521 u64 tot; 522 u64 tpr; 523 u64 tpt; 524 u64 ptc64; 525 u64 ptc127; 526 u64 ptc255; 527 u64 ptc511; 528 u64 ptc1023; 529 u64 ptc1522; 530 u64 mptc; 531 u64 bptc; 532 u64 tsctc; 533 u64 tsctfc; 534 u64 iac; 535 u64 icrxptc; 536 u64 icrxatc; 537 u64 ictxptc; 538 u64 ictxatc; 539 u64 ictxqec; 540 u64 ictxqmtc; 541 u64 icrxdmtc; 542 u64 icrxoc; 543 u64 cbtmpc; 544 u64 htdpmc; 545 u64 cbrdpc; 546 u64 cbrmpc; 547 u64 rpthc; 548 u64 hgptc; 549 u64 htcbdpc; 550 u64 hgorc; 551 u64 hgotc; 552 u64 lenerrs; 553 u64 scvpc; 554 u64 hrmpc; 555 u64 doosync; 556 }; 557 558 struct e1000_vf_stats { 559 u64 base_gprc; 560 u64 base_gptc; 561 u64 base_gorc; 562 u64 base_gotc; 563 u64 base_mprc; 564 u64 base_gotlbc; 565 u64 base_gptlbc; 566 u64 base_gorlbc; 567 u64 base_gprlbc; 568 569 u32 last_gprc; 570 u32 last_gptc; 571 u32 last_gorc; 572 u32 last_gotc; 573 u32 last_mprc; 574 u32 last_gotlbc; 575 u32 last_gptlbc; 576 u32 last_gorlbc; 577 u32 last_gprlbc; 578 579 u64 gprc; 580 u64 gptc; 581 u64 gorc; 582 u64 gotc; 583 u64 mprc; 584 u64 gotlbc; 585 u64 gptlbc; 586 u64 gorlbc; 587 u64 gprlbc; 588 }; 589 590 struct e1000_phy_stats { 591 u32 idle_errors; 592 u32 receive_errors; 593 }; 594 595 struct e1000_host_mng_dhcp_cookie { 596 u32 signature; 597 u8 status; 598 u8 reserved0; 599 u16 vlan_id; 600 u32 reserved1; 601 u16 reserved2; 602 u8 reserved3; 603 u8 checksum; 604 }; 605 606 /* Host Interface "Rev 1" */ 607 struct e1000_host_command_header { 608 u8 command_id; 609 u8 command_length; 610 u8 command_options; 611 u8 checksum; 612 }; 613 614 #define E1000_HI_MAX_DATA_LENGTH 252 615 struct e1000_host_command_info { 616 struct e1000_host_command_header command_header; 617 u8 command_data[E1000_HI_MAX_DATA_LENGTH]; 618 }; 619 620 /* Host Interface "Rev 2" */ 621 struct e1000_host_mng_command_header { 622 u8 command_id; 623 u8 checksum; 624 u16 reserved1; 625 u16 reserved2; 626 u16 command_length; 627 }; 628 629 #define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8 630 struct e1000_host_mng_command_info { 631 struct e1000_host_mng_command_header command_header; 632 u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH]; 633 }; 634 635 #include "e1000_mac.h" 636 #include "e1000_phy.h" 637 #include "e1000_nvm.h" 638 #include "e1000_manage.h" 639 #include "e1000_mbx.h" 640 641 struct e1000_mac_operations { 642 /* Function pointers for the MAC. */ 643 s32 (*init_params)(struct e1000_hw *); 644 s32 (*id_led_init)(struct e1000_hw *); 645 s32 (*blink_led)(struct e1000_hw *); 646 s32 (*check_for_link)(struct e1000_hw *); 647 bool (*check_mng_mode)(struct e1000_hw *hw); 648 s32 (*cleanup_led)(struct e1000_hw *); 649 void (*clear_hw_cntrs)(struct e1000_hw *); 650 void (*clear_vfta)(struct e1000_hw *); 651 s32 (*get_bus_info)(struct e1000_hw *); 652 void (*set_lan_id)(struct e1000_hw *); 653 s32 (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *); 654 s32 (*led_on)(struct e1000_hw *); 655 s32 (*led_off)(struct e1000_hw *); 656 void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32); 657 s32 (*reset_hw)(struct e1000_hw *); 658 s32 (*init_hw)(struct e1000_hw *); 659 void (*shutdown_serdes)(struct e1000_hw *); 660 void (*power_up_serdes)(struct e1000_hw *); 661 s32 (*setup_link)(struct e1000_hw *); 662 s32 (*setup_physical_interface)(struct e1000_hw *); 663 s32 (*setup_led)(struct e1000_hw *); 664 void (*write_vfta)(struct e1000_hw *, u32, u32); 665 void (*config_collision_dist)(struct e1000_hw *); 666 void (*rar_set)(struct e1000_hw *, u8*, u32); 667 s32 (*read_mac_addr)(struct e1000_hw *); 668 s32 (*validate_mdi_setting)(struct e1000_hw *); 669 s32 (*mng_host_if_write)(struct e1000_hw *, u8*, u16, u16, u8*); 670 s32 (*mng_write_cmd_header)(struct e1000_hw *hw, 671 struct e1000_host_mng_command_header*); 672 s32 (*mng_enable_host_if)(struct e1000_hw *); 673 s32 (*wait_autoneg)(struct e1000_hw *); 674 }; 675 676 struct e1000_phy_operations { 677 s32 (*init_params)(struct e1000_hw *); 678 s32 (*acquire)(struct e1000_hw *); 679 s32 (*cfg_on_link_up)(struct e1000_hw *); 680 s32 (*check_polarity)(struct e1000_hw *); 681 s32 (*check_reset_block)(struct e1000_hw *); 682 s32 (*commit)(struct e1000_hw *); 683 s32 (*force_speed_duplex)(struct e1000_hw *); 684 s32 (*get_cfg_done)(struct e1000_hw *hw); 685 s32 (*get_cable_length)(struct e1000_hw *); 686 s32 (*get_info)(struct e1000_hw *); 687 s32 (*read_reg)(struct e1000_hw *, u32, u16 *); 688 s32 (*read_reg_locked)(struct e1000_hw *, u32, u16 *); 689 void (*release)(struct e1000_hw *); 690 s32 (*reset)(struct e1000_hw *); 691 s32 (*set_d0_lplu_state)(struct e1000_hw *, bool); 692 s32 (*set_d3_lplu_state)(struct e1000_hw *, bool); 693 s32 (*write_reg)(struct e1000_hw *, u32, u16); 694 s32 (*write_reg_locked)(struct e1000_hw *, u32, u16); 695 void (*power_up)(struct e1000_hw *); 696 void (*power_down)(struct e1000_hw *); 697 }; 698 699 struct e1000_nvm_operations { 700 s32 (*init_params)(struct e1000_hw *); 701 s32 (*acquire)(struct e1000_hw *); 702 s32 (*read)(struct e1000_hw *, u16, u16, u16 *); 703 void (*release)(struct e1000_hw *); 704 void (*reload)(struct e1000_hw *); 705 s32 (*update)(struct e1000_hw *); 706 s32 (*valid_led_default)(struct e1000_hw *, u16 *); 707 s32 (*validate)(struct e1000_hw *); 708 s32 (*write)(struct e1000_hw *, u16, u16, u16 *); 709 }; 710 711 struct e1000_mac_info { 712 struct e1000_mac_operations ops; 713 u8 addr[ETH_ADDR_LEN]; 714 u8 perm_addr[ETH_ADDR_LEN]; 715 716 enum e1000_mac_type type; 717 718 u32 collision_delta; 719 u32 ledctl_default; 720 u32 ledctl_mode1; 721 u32 ledctl_mode2; 722 u32 mc_filter_type; 723 u32 tx_packet_delta; 724 u32 txcw; 725 726 u16 current_ifs_val; 727 u16 ifs_max_val; 728 u16 ifs_min_val; 729 u16 ifs_ratio; 730 u16 ifs_step_size; 731 u16 mta_reg_count; 732 u16 uta_reg_count; 733 734 /* Maximum size of the MTA register table in all supported adapters */ 735 #define MAX_MTA_REG 128 736 u32 mta_shadow[MAX_MTA_REG]; 737 u16 rar_entry_count; 738 739 u8 forced_speed_duplex; 740 741 bool adaptive_ifs; 742 bool has_fwsm; 743 bool arc_subsystem_valid; 744 bool asf_firmware_present; 745 bool autoneg; 746 bool autoneg_failed; 747 bool get_link_status; 748 bool in_ifs_mode; 749 bool report_tx_early; 750 enum e1000_serdes_link_state serdes_link_state; 751 bool serdes_has_link; 752 bool tx_pkt_filtering; 753 }; 754 755 struct e1000_phy_info { 756 struct e1000_phy_operations ops; 757 enum e1000_phy_type type; 758 759 enum e1000_1000t_rx_status local_rx; 760 enum e1000_1000t_rx_status remote_rx; 761 enum e1000_ms_type ms_type; 762 enum e1000_ms_type original_ms_type; 763 enum e1000_rev_polarity cable_polarity; 764 enum e1000_smart_speed smart_speed; 765 766 u32 addr; 767 u32 id; 768 u32 reset_delay_us; /* in usec */ 769 u32 revision; 770 771 enum e1000_media_type media_type; 772 773 u16 autoneg_advertised; 774 u16 autoneg_mask; 775 u16 cable_length; 776 u16 max_cable_length; 777 u16 min_cable_length; 778 779 u8 mdix; 780 781 bool disable_polarity_correction; 782 bool is_mdix; 783 bool polarity_correction; 784 bool reset_disable; 785 bool speed_downgraded; 786 bool autoneg_wait_to_complete; 787 }; 788 789 struct e1000_nvm_info { 790 struct e1000_nvm_operations ops; 791 enum e1000_nvm_type type; 792 enum e1000_nvm_override override; 793 794 u32 flash_bank_size; 795 u32 flash_base_addr; 796 797 u16 word_size; 798 u16 delay_usec; 799 u16 address_bits; 800 u16 opcode_bits; 801 u16 page_size; 802 }; 803 804 struct e1000_bus_info { 805 enum e1000_bus_type type; 806 enum e1000_bus_speed speed; 807 enum e1000_bus_width width; 808 809 u16 func; 810 u16 pci_cmd_word; 811 }; 812 813 struct e1000_fc_info { 814 u32 high_water; /* Flow control high-water mark */ 815 u32 low_water; /* Flow control low-water mark */ 816 u16 pause_time; /* Flow control pause timer */ 817 u16 refresh_time; /* Flow control refresh timer */ 818 bool send_xon; /* Flow control send XON */ 819 bool strict_ieee; /* Strict IEEE mode */ 820 enum e1000_fc_mode current_mode; /* FC mode in effect */ 821 enum e1000_fc_mode requested_mode; /* FC mode requested by caller */ 822 }; 823 824 struct e1000_mbx_operations { 825 s32 (*init_params)(struct e1000_hw *hw); 826 s32 (*read)(struct e1000_hw *, u32 *, u16, u16); 827 s32 (*write)(struct e1000_hw *, u32 *, u16, u16); 828 s32 (*read_posted)(struct e1000_hw *, u32 *, u16, u16); 829 s32 (*write_posted)(struct e1000_hw *, u32 *, u16, u16); 830 s32 (*check_for_msg)(struct e1000_hw *, u16); 831 s32 (*check_for_ack)(struct e1000_hw *, u16); 832 s32 (*check_for_rst)(struct e1000_hw *, u16); 833 }; 834 835 struct e1000_mbx_stats { 836 u32 msgs_tx; 837 u32 msgs_rx; 838 839 u32 acks; 840 u32 reqs; 841 u32 rsts; 842 }; 843 844 struct e1000_mbx_info { 845 struct e1000_mbx_operations ops; 846 struct e1000_mbx_stats stats; 847 u32 timeout; 848 u32 usec_delay; 849 u16 size; 850 }; 851 852 struct e1000_dev_spec_82541 { 853 enum e1000_dsp_config dsp_config; 854 enum e1000_ffe_config ffe_config; 855 u16 spd_default; 856 bool phy_init_script; 857 }; 858 859 struct e1000_dev_spec_82542 { 860 bool dma_fairness; 861 }; 862 863 struct e1000_dev_spec_82543 { 864 u32 tbi_compatibility; 865 bool dma_fairness; 866 bool init_phy_disabled; 867 }; 868 869 struct e1000_dev_spec_82571 { 870 bool laa_is_present; 871 u32 smb_counter; 872 E1000_MUTEX swflag_mutex; 873 }; 874 875 struct e1000_dev_spec_80003es2lan { 876 bool mdic_wa_enable; 877 }; 878 879 struct e1000_shadow_ram { 880 u16 value; 881 bool modified; 882 }; 883 884 #define E1000_SHADOW_RAM_WORDS 2048 885 886 struct e1000_dev_spec_ich8lan { 887 bool kmrn_lock_loss_workaround_enabled; 888 struct e1000_shadow_ram shadow_ram[E1000_SHADOW_RAM_WORDS]; 889 E1000_MUTEX nvm_mutex; 890 E1000_MUTEX swflag_mutex; 891 bool nvm_k1_enabled; 892 bool eee_disable; 893 }; 894 895 struct e1000_dev_spec_82575 { 896 bool sgmii_active; 897 bool global_device_reset; 898 bool eee_disable; 899 }; 900 901 struct e1000_dev_spec_vf { 902 u32 vf_number; 903 u32 v2p_mailbox; 904 }; 905 906 struct e1000_hw { 907 void *back; 908 909 u8 *hw_addr; 910 u8 *flash_address; 911 unsigned long io_base; 912 913 struct e1000_mac_info mac; 914 struct e1000_fc_info fc; 915 struct e1000_phy_info phy; 916 struct e1000_nvm_info nvm; 917 struct e1000_bus_info bus; 918 struct e1000_mbx_info mbx; 919 struct e1000_host_mng_dhcp_cookie mng_cookie; 920 921 union { 922 struct e1000_dev_spec_82541 _82541; 923 struct e1000_dev_spec_82542 _82542; 924 struct e1000_dev_spec_82543 _82543; 925 struct e1000_dev_spec_82571 _82571; 926 struct e1000_dev_spec_80003es2lan _80003es2lan; 927 struct e1000_dev_spec_ich8lan ich8lan; 928 struct e1000_dev_spec_82575 _82575; 929 struct e1000_dev_spec_vf vf; 930 } dev_spec; 931 932 u16 device_id; 933 u16 subsystem_vendor_id; 934 u16 subsystem_device_id; 935 u16 vendor_id; 936 937 u8 revision_id; 938 }; 939 940 #include "e1000_82541.h" 941 #include "e1000_82543.h" 942 #include "e1000_82571.h" 943 #include "e1000_80003es2lan.h" 944 #include "e1000_ich8lan.h" 945 #include "e1000_82575.h" 946 947 /* These functions must be implemented by drivers */ 948 void e1000_pci_clear_mwi(struct e1000_hw *hw); 949 void e1000_pci_set_mwi(struct e1000_hw *hw); 950 s32 e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value); 951 s32 e1000_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value); 952 void e1000_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value); 953 void e1000_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value); 954 955 #endif
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