Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/dev/e1000/if_em.h
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1 /****************************************************************************** 2 3 Copyright (c) 2001-2011, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD: releng/9.0/sys/dev/e1000/if_em.h 220251 2011-04-01 18:48:31Z jfv $*/ 34 35 36 #ifndef _EM_H_DEFINED_ 37 #define _EM_H_DEFINED_ 38 39 40 /* Tunables */ 41 42 /* 43 * EM_TXD: Maximum number of Transmit Descriptors 44 * Valid Range: 80-256 for 82542 and 82543-based adapters 45 * 80-4096 for others 46 * Default Value: 256 47 * This value is the number of transmit descriptors allocated by the driver. 48 * Increasing this value allows the driver to queue more transmits. Each 49 * descriptor is 16 bytes. 50 * Since TDLEN should be multiple of 128bytes, the number of transmit 51 * desscriptors should meet the following condition. 52 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0 53 */ 54 #define EM_MIN_TXD 80 55 #define EM_MAX_TXD 4096 56 #define EM_DEFAULT_TXD 1024 57 58 /* 59 * EM_RXD - Maximum number of receive Descriptors 60 * Valid Range: 80-256 for 82542 and 82543-based adapters 61 * 80-4096 for others 62 * Default Value: 256 63 * This value is the number of receive descriptors allocated by the driver. 64 * Increasing this value allows the driver to buffer more incoming packets. 65 * Each descriptor is 16 bytes. A receive buffer is also allocated for each 66 * descriptor. The maximum MTU size is 16110. 67 * Since TDLEN should be multiple of 128bytes, the number of transmit 68 * desscriptors should meet the following condition. 69 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0 70 */ 71 #define EM_MIN_RXD 80 72 #define EM_MAX_RXD 4096 73 #define EM_DEFAULT_RXD 1024 74 75 /* 76 * EM_TIDV - Transmit Interrupt Delay Value 77 * Valid Range: 0-65535 (0=off) 78 * Default Value: 64 79 * This value delays the generation of transmit interrupts in units of 80 * 1.024 microseconds. Transmit interrupt reduction can improve CPU 81 * efficiency if properly tuned for specific network traffic. If the 82 * system is reporting dropped transmits, this value may be set too high 83 * causing the driver to run out of available transmit descriptors. 84 */ 85 #define EM_TIDV 64 86 87 /* 88 * EM_TADV - Transmit Absolute Interrupt Delay Value 89 * (Not valid for 82542/82543/82544) 90 * Valid Range: 0-65535 (0=off) 91 * Default Value: 64 92 * This value, in units of 1.024 microseconds, limits the delay in which a 93 * transmit interrupt is generated. Useful only if EM_TIDV is non-zero, 94 * this value ensures that an interrupt is generated after the initial 95 * packet is sent on the wire within the set amount of time. Proper tuning, 96 * along with EM_TIDV, may improve traffic throughput in specific 97 * network conditions. 98 */ 99 #define EM_TADV 64 100 101 /* 102 * EM_RDTR - Receive Interrupt Delay Timer (Packet Timer) 103 * Valid Range: 0-65535 (0=off) 104 * Default Value: 0 105 * This value delays the generation of receive interrupts in units of 1.024 106 * microseconds. Receive interrupt reduction can improve CPU efficiency if 107 * properly tuned for specific network traffic. Increasing this value adds 108 * extra latency to frame reception and can end up decreasing the throughput 109 * of TCP traffic. If the system is reporting dropped receives, this value 110 * may be set too high, causing the driver to run out of available receive 111 * descriptors. 112 * 113 * CAUTION: When setting EM_RDTR to a value other than 0, adapters 114 * may hang (stop transmitting) under certain network conditions. 115 * If this occurs a WATCHDOG message is logged in the system 116 * event log. In addition, the controller is automatically reset, 117 * restoring the network connection. To eliminate the potential 118 * for the hang ensure that EM_RDTR is set to 0. 119 */ 120 #define EM_RDTR 0 121 122 /* 123 * Receive Interrupt Absolute Delay Timer (Not valid for 82542/82543/82544) 124 * Valid Range: 0-65535 (0=off) 125 * Default Value: 64 126 * This value, in units of 1.024 microseconds, limits the delay in which a 127 * receive interrupt is generated. Useful only if EM_RDTR is non-zero, 128 * this value ensures that an interrupt is generated after the initial 129 * packet is received within the set amount of time. Proper tuning, 130 * along with EM_RDTR, may improve traffic throughput in specific network 131 * conditions. 132 */ 133 #define EM_RADV 64 134 135 /* 136 * This parameter controls the max duration of transmit watchdog. 137 */ 138 #define EM_WATCHDOG (10 * hz) 139 140 /* 141 * This parameter controls when the driver calls the routine to reclaim 142 * transmit descriptors. 143 */ 144 #define EM_TX_CLEANUP_THRESHOLD (adapter->num_tx_desc / 8) 145 146 /* 147 * This parameter controls whether or not autonegotation is enabled. 148 * 0 - Disable autonegotiation 149 * 1 - Enable autonegotiation 150 */ 151 #define DO_AUTO_NEG 1 152 153 /* 154 * This parameter control whether or not the driver will wait for 155 * autonegotiation to complete. 156 * 1 - Wait for autonegotiation to complete 157 * 0 - Don't wait for autonegotiation to complete 158 */ 159 #define WAIT_FOR_AUTO_NEG_DEFAULT 0 160 161 /* Tunables -- End */ 162 163 #define AUTONEG_ADV_DEFAULT (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ 164 ADVERTISE_100_HALF | ADVERTISE_100_FULL | \ 165 ADVERTISE_1000_FULL) 166 167 #define AUTO_ALL_MODES 0 168 169 /* PHY master/slave setting */ 170 #define EM_MASTER_SLAVE e1000_ms_hw_default 171 172 /* 173 * Micellaneous constants 174 */ 175 #define EM_VENDOR_ID 0x8086 176 #define EM_FLASH 0x0014 177 178 #define EM_JUMBO_PBA 0x00000028 179 #define EM_DEFAULT_PBA 0x00000030 180 #define EM_SMARTSPEED_DOWNSHIFT 3 181 #define EM_SMARTSPEED_MAX 15 182 #define EM_MAX_LOOP 10 183 184 #define MAX_NUM_MULTICAST_ADDRESSES 128 185 #define PCI_ANY_ID (~0U) 186 #define ETHER_ALIGN 2 187 #define EM_FC_PAUSE_TIME 0x0680 188 #define EM_EEPROM_APME 0x400; 189 #define EM_82544_APME 0x0004; 190 191 #define EM_QUEUE_IDLE 0 192 #define EM_QUEUE_WORKING 1 193 #define EM_QUEUE_HUNG 2 194 195 /* 196 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be 197 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will 198 * also optimize cache line size effect. H/W supports up to cache line size 128. 199 */ 200 #define EM_DBA_ALIGN 128 201 202 #define SPEED_MODE_BIT (1<<21) /* On PCI-E MACs only */ 203 204 /* PCI Config defines */ 205 #define EM_BAR_TYPE(v) ((v) & EM_BAR_TYPE_MASK) 206 #define EM_BAR_TYPE_MASK 0x00000001 207 #define EM_BAR_TYPE_MMEM 0x00000000 208 #define EM_BAR_TYPE_FLASH 0x0014 209 #define EM_BAR_MEM_TYPE(v) ((v) & EM_BAR_MEM_TYPE_MASK) 210 #define EM_BAR_MEM_TYPE_MASK 0x00000006 211 #define EM_BAR_MEM_TYPE_32BIT 0x00000000 212 #define EM_BAR_MEM_TYPE_64BIT 0x00000004 213 #define EM_MSIX_BAR 3 /* On 82575 */ 214 215 #if !defined(SYSCTL_ADD_UQUAD) 216 #define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD 217 #endif 218 219 /* Defines for printing debug information */ 220 #define DEBUG_INIT 0 221 #define DEBUG_IOCTL 0 222 #define DEBUG_HW 0 223 224 #define INIT_DEBUGOUT(S) if (DEBUG_INIT) printf(S "\n") 225 #define INIT_DEBUGOUT1(S, A) if (DEBUG_INIT) printf(S "\n", A) 226 #define INIT_DEBUGOUT2(S, A, B) if (DEBUG_INIT) printf(S "\n", A, B) 227 #define IOCTL_DEBUGOUT(S) if (DEBUG_IOCTL) printf(S "\n") 228 #define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) printf(S "\n", A) 229 #define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) printf(S "\n", A, B) 230 #define HW_DEBUGOUT(S) if (DEBUG_HW) printf(S "\n") 231 #define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A) 232 #define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B) 233 234 #define EM_MAX_SCATTER 32 235 #define EM_VFTA_SIZE 128 236 #define EM_TSO_SIZE (65535 + sizeof(struct ether_vlan_header)) 237 #define EM_TSO_SEG_SIZE 4096 /* Max dma segment size */ 238 #define EM_MSIX_MASK 0x01F00000 /* For 82574 use */ 239 #define EM_MSIX_LINK 0x01000000 /* For 82574 use */ 240 #define ETH_ZLEN 60 241 #define ETH_ADDR_LEN 6 242 #define CSUM_OFFLOAD 7 /* Offload bits in mbuf flag */ 243 244 /* 245 * 82574 has a nonstandard address for EIAC 246 * and since its only used in MSIX, and in 247 * the em driver only 82574 uses MSIX we can 248 * solve it just using this define. 249 */ 250 #define EM_EIAC 0x000DC 251 252 /* 253 * Bus dma allocation structure used by 254 * e1000_dma_malloc and e1000_dma_free. 255 */ 256 struct em_dma_alloc { 257 bus_addr_t dma_paddr; 258 caddr_t dma_vaddr; 259 bus_dma_tag_t dma_tag; 260 bus_dmamap_t dma_map; 261 bus_dma_segment_t dma_seg; 262 int dma_nseg; 263 }; 264 265 struct adapter; 266 267 struct em_int_delay_info { 268 struct adapter *adapter; /* Back-pointer to the adapter struct */ 269 int offset; /* Register offset to read/write */ 270 int value; /* Current value in usecs */ 271 }; 272 273 /* 274 * The transmit ring, one per tx queue 275 */ 276 struct tx_ring { 277 struct adapter *adapter; 278 struct mtx tx_mtx; 279 char mtx_name[16]; 280 u32 me; 281 u32 msix; 282 u32 ims; 283 int queue_status; 284 int watchdog_time; 285 struct em_dma_alloc txdma; 286 struct e1000_tx_desc *tx_base; 287 struct task tx_task; 288 struct taskqueue *tq; 289 u32 next_avail_desc; 290 u32 next_to_clean; 291 struct em_buffer *tx_buffers; 292 volatile u16 tx_avail; 293 u32 tx_tso; /* last tx was tso */ 294 u16 last_hw_offload; 295 u8 last_hw_ipcso; 296 u8 last_hw_ipcss; 297 u8 last_hw_tucso; 298 u8 last_hw_tucss; 299 #if __FreeBSD_version >= 800000 300 struct buf_ring *br; 301 #endif 302 /* Interrupt resources */ 303 bus_dma_tag_t txtag; 304 void *tag; 305 struct resource *res; 306 unsigned long tx_irq; 307 unsigned long no_desc_avail; 308 }; 309 310 /* 311 * The Receive ring, one per rx queue 312 */ 313 struct rx_ring { 314 struct adapter *adapter; 315 u32 me; 316 u32 msix; 317 u32 ims; 318 struct mtx rx_mtx; 319 char mtx_name[16]; 320 u32 payload; 321 struct task rx_task; 322 struct taskqueue *tq; 323 struct e1000_rx_desc *rx_base; 324 struct em_dma_alloc rxdma; 325 u32 next_to_refresh; 326 u32 next_to_check; 327 struct em_buffer *rx_buffers; 328 struct mbuf *fmp; 329 struct mbuf *lmp; 330 331 /* Interrupt resources */ 332 void *tag; 333 struct resource *res; 334 bus_dma_tag_t rxtag; 335 bool discard; 336 337 /* Soft stats */ 338 unsigned long rx_irq; 339 unsigned long rx_discarded; 340 unsigned long rx_packets; 341 unsigned long rx_bytes; 342 }; 343 344 345 /* Our adapter structure */ 346 struct adapter { 347 struct ifnet *ifp; 348 struct e1000_hw hw; 349 350 /* FreeBSD operating-system-specific structures. */ 351 struct e1000_osdep osdep; 352 struct device *dev; 353 struct cdev *led_dev; 354 355 struct resource *memory; 356 struct resource *flash; 357 struct resource *msix_mem; 358 359 struct resource *res; 360 void *tag; 361 u32 linkvec; 362 u32 ivars; 363 364 struct ifmedia media; 365 struct callout timer; 366 int msix; 367 int if_flags; 368 int max_frame_size; 369 int min_frame_size; 370 int pause_frames; 371 struct mtx core_mtx; 372 int em_insert_vlan_header; 373 u32 ims; 374 bool in_detach; 375 376 /* Task for FAST handling */ 377 struct task link_task; 378 struct task que_task; 379 struct taskqueue *tq; /* private task queue */ 380 381 eventhandler_tag vlan_attach; 382 eventhandler_tag vlan_detach; 383 384 u16 num_vlans; 385 u16 num_queues; 386 387 /* 388 * Transmit rings: 389 * Allocated at run time, an array of rings. 390 */ 391 struct tx_ring *tx_rings; 392 int num_tx_desc; 393 u32 txd_cmd; 394 395 /* 396 * Receive rings: 397 * Allocated at run time, an array of rings. 398 */ 399 struct rx_ring *rx_rings; 400 int num_rx_desc; 401 u32 rx_process_limit; 402 u32 rx_mbuf_sz; 403 404 /* Management and WOL features */ 405 u32 wol; 406 bool has_manage; 407 bool has_amt; 408 409 /* Multicast array memory */ 410 u8 *mta; 411 412 /* 413 ** Shadow VFTA table, this is needed because 414 ** the real vlan filter table gets cleared during 415 ** a soft reset and the driver needs to be able 416 ** to repopulate it. 417 */ 418 u32 shadow_vfta[EM_VFTA_SIZE]; 419 420 /* Info about the interface */ 421 u8 link_active; 422 u16 link_speed; 423 u16 link_duplex; 424 u32 smartspeed; 425 u32 fc_setting; 426 427 struct em_int_delay_info tx_int_delay; 428 struct em_int_delay_info tx_abs_int_delay; 429 struct em_int_delay_info rx_int_delay; 430 struct em_int_delay_info rx_abs_int_delay; 431 432 /* Misc stats maintained by the driver */ 433 unsigned long dropped_pkts; 434 unsigned long mbuf_alloc_failed; 435 unsigned long mbuf_cluster_failed; 436 unsigned long no_tx_map_avail; 437 unsigned long no_tx_dma_setup; 438 unsigned long rx_overruns; 439 unsigned long watchdog_events; 440 unsigned long link_irq; 441 442 struct e1000_hw_stats stats; 443 }; 444 445 /******************************************************************************** 446 * vendor_info_array 447 * 448 * This array contains the list of Subvendor/Subdevice IDs on which the driver 449 * should load. 450 * 451 ********************************************************************************/ 452 typedef struct _em_vendor_info_t { 453 unsigned int vendor_id; 454 unsigned int device_id; 455 unsigned int subvendor_id; 456 unsigned int subdevice_id; 457 unsigned int index; 458 } em_vendor_info_t; 459 460 struct em_buffer { 461 int next_eop; /* Index of the desc to watch */ 462 struct mbuf *m_head; 463 bus_dmamap_t map; /* bus_dma map for packet */ 464 }; 465 466 467 /* 468 ** Find the number of unrefreshed RX descriptors 469 */ 470 static inline u16 471 e1000_rx_unrefreshed(struct rx_ring *rxr) 472 { 473 struct adapter *adapter = rxr->adapter; 474 475 if (rxr->next_to_check > rxr->next_to_refresh) 476 return (rxr->next_to_check - rxr->next_to_refresh - 1); 477 else 478 return ((adapter->num_rx_desc + rxr->next_to_check) - 479 rxr->next_to_refresh - 1); 480 } 481 482 #define EM_CORE_LOCK_INIT(_sc, _name) \ 483 mtx_init(&(_sc)->core_mtx, _name, "EM Core Lock", MTX_DEF) 484 #define EM_TX_LOCK_INIT(_sc, _name) \ 485 mtx_init(&(_sc)->tx_mtx, _name, "EM TX Lock", MTX_DEF) 486 #define EM_RX_LOCK_INIT(_sc, _name) \ 487 mtx_init(&(_sc)->rx_mtx, _name, "EM RX Lock", MTX_DEF) 488 #define EM_CORE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->core_mtx) 489 #define EM_TX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->tx_mtx) 490 #define EM_RX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->rx_mtx) 491 #define EM_CORE_LOCK(_sc) mtx_lock(&(_sc)->core_mtx) 492 #define EM_TX_LOCK(_sc) mtx_lock(&(_sc)->tx_mtx) 493 #define EM_TX_TRYLOCK(_sc) mtx_trylock(&(_sc)->tx_mtx) 494 #define EM_RX_LOCK(_sc) mtx_lock(&(_sc)->rx_mtx) 495 #define EM_CORE_UNLOCK(_sc) mtx_unlock(&(_sc)->core_mtx) 496 #define EM_TX_UNLOCK(_sc) mtx_unlock(&(_sc)->tx_mtx) 497 #define EM_RX_UNLOCK(_sc) mtx_unlock(&(_sc)->rx_mtx) 498 #define EM_CORE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->core_mtx, MA_OWNED) 499 #define EM_TX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->tx_mtx, MA_OWNED) 500 #define EM_RX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->rx_mtx, MA_OWNED) 501 502 #endif /* _EM_H_DEFINED_ */
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