The Design and Implementation of the FreeBSD Operating System, Second Edition
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FreeBSD/Linux Kernel Cross Reference
sys/dev/e1000/if_igb.h

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    1 /******************************************************************************
    2 
    3   Copyright (c) 2001-2011, Intel Corporation 
    4   All rights reserved.
    5   
    6   Redistribution and use in source and binary forms, with or without 
    7   modification, are permitted provided that the following conditions are met:
    8   
    9    1. Redistributions of source code must retain the above copyright notice, 
   10       this list of conditions and the following disclaimer.
   11   
   12    2. Redistributions in binary form must reproduce the above copyright 
   13       notice, this list of conditions and the following disclaimer in the 
   14       documentation and/or other materials provided with the distribution.
   15   
   16    3. Neither the name of the Intel Corporation nor the names of its 
   17       contributors may be used to endorse or promote products derived from 
   18       this software without specific prior written permission.
   19   
   20   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
   21   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
   22   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
   23   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 
   24   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 
   25   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 
   26   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
   27   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
   28   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
   29   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   30   POSSIBILITY OF SUCH DAMAGE.
   31 
   32 ******************************************************************************/
   33 /*$FreeBSD: releng/9.0/sys/dev/e1000/if_igb.h 223676 2011-06-29 16:20:52Z jhb $*/
   34 
   35 #ifndef _IGB_H_DEFINED_
   36 #define _IGB_H_DEFINED_
   37 
   38 /* Tunables */
   39 
   40 /*
   41  * IGB_TXD: Maximum number of Transmit Descriptors
   42  *
   43  *   This value is the number of transmit descriptors allocated by the driver.
   44  *   Increasing this value allows the driver to queue more transmits. Each
   45  *   descriptor is 16 bytes.
   46  *   Since TDLEN should be multiple of 128bytes, the number of transmit
   47  *   desscriptors should meet the following condition.
   48  *      (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0
   49  */
   50 #define IGB_MIN_TXD             256
   51 #define IGB_DEFAULT_TXD         1024
   52 #define IGB_MAX_TXD             4096
   53 
   54 /*
   55  * IGB_RXD: Maximum number of Transmit Descriptors
   56  *
   57  *   This value is the number of receive descriptors allocated by the driver.
   58  *   Increasing this value allows the driver to buffer more incoming packets.
   59  *   Each descriptor is 16 bytes.  A receive buffer is also allocated for each
   60  *   descriptor. The maximum MTU size is 16110.
   61  *   Since TDLEN should be multiple of 128bytes, the number of transmit
   62  *   desscriptors should meet the following condition.
   63  *      (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0
   64  */
   65 #define IGB_MIN_RXD             256
   66 #define IGB_DEFAULT_RXD         1024
   67 #define IGB_MAX_RXD             4096
   68 
   69 /*
   70  * IGB_TIDV - Transmit Interrupt Delay Value
   71  * Valid Range: 0-65535 (0=off)
   72  * Default Value: 64
   73  *   This value delays the generation of transmit interrupts in units of
   74  *   1.024 microseconds. Transmit interrupt reduction can improve CPU
   75  *   efficiency if properly tuned for specific network traffic. If the
   76  *   system is reporting dropped transmits, this value may be set too high
   77  *   causing the driver to run out of available transmit descriptors.
   78  */
   79 #define IGB_TIDV                         64
   80 
   81 /*
   82  * IGB_TADV - Transmit Absolute Interrupt Delay Value
   83  * Valid Range: 0-65535 (0=off)
   84  * Default Value: 64
   85  *   This value, in units of 1.024 microseconds, limits the delay in which a
   86  *   transmit interrupt is generated. Useful only if IGB_TIDV is non-zero,
   87  *   this value ensures that an interrupt is generated after the initial
   88  *   packet is sent on the wire within the set amount of time.  Proper tuning,
   89  *   along with IGB_TIDV, may improve traffic throughput in specific
   90  *   network conditions.
   91  */
   92 #define IGB_TADV                         64
   93 
   94 /*
   95  * IGB_RDTR - Receive Interrupt Delay Timer (Packet Timer)
   96  * Valid Range: 0-65535 (0=off)
   97  * Default Value: 0
   98  *   This value delays the generation of receive interrupts in units of 1.024
   99  *   microseconds.  Receive interrupt reduction can improve CPU efficiency if
  100  *   properly tuned for specific network traffic. Increasing this value adds
  101  *   extra latency to frame reception and can end up decreasing the throughput
  102  *   of TCP traffic. If the system is reporting dropped receives, this value
  103  *   may be set too high, causing the driver to run out of available receive
  104  *   descriptors.
  105  *
  106  *   CAUTION: When setting IGB_RDTR to a value other than 0, adapters
  107  *            may hang (stop transmitting) under certain network conditions.
  108  *            If this occurs a WATCHDOG message is logged in the system
  109  *            event log. In addition, the controller is automatically reset,
  110  *            restoring the network connection. To eliminate the potential
  111  *            for the hang ensure that IGB_RDTR is set to 0.
  112  */
  113 #define IGB_RDTR                         0
  114 
  115 /*
  116  * Receive Interrupt Absolute Delay Timer (Not valid for 82542/82543/82544)
  117  * Valid Range: 0-65535 (0=off)
  118  * Default Value: 64
  119  *   This value, in units of 1.024 microseconds, limits the delay in which a
  120  *   receive interrupt is generated. Useful only if IGB_RDTR is non-zero,
  121  *   this value ensures that an interrupt is generated after the initial
  122  *   packet is received within the set amount of time.  Proper tuning,
  123  *   along with IGB_RDTR, may improve traffic throughput in specific network
  124  *   conditions.
  125  */
  126 #define IGB_RADV                         64
  127 
  128 /*
  129  * This parameter controls the duration of transmit watchdog timer.
  130  */
  131 #define IGB_WATCHDOG                   (10 * hz)
  132 
  133 /*
  134  * This parameter controls when the driver calls the routine to reclaim
  135  * transmit descriptors. Cleaning earlier seems a win.
  136  */
  137 #define IGB_TX_CLEANUP_THRESHOLD        (adapter->num_tx_desc / 2)
  138 
  139 /*
  140  * This parameter controls whether or not autonegotation is enabled.
  141  *              0 - Disable autonegotiation
  142  *              1 - Enable  autonegotiation
  143  */
  144 #define DO_AUTO_NEG                     1
  145 
  146 /*
  147  * This parameter control whether or not the driver will wait for
  148  * autonegotiation to complete.
  149  *              1 - Wait for autonegotiation to complete
  150  *              0 - Don't wait for autonegotiation to complete
  151  */
  152 #define WAIT_FOR_AUTO_NEG_DEFAULT       0
  153 
  154 /* Tunables -- End */
  155 
  156 #define AUTONEG_ADV_DEFAULT     (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \
  157                                 ADVERTISE_100_HALF | ADVERTISE_100_FULL | \
  158                                 ADVERTISE_1000_FULL)
  159 
  160 #define AUTO_ALL_MODES          0
  161 
  162 /* PHY master/slave setting */
  163 #define IGB_MASTER_SLAVE                e1000_ms_hw_default
  164 
  165 /*
  166  * Micellaneous constants
  167  */
  168 #define IGB_VENDOR_ID                   0x8086
  169 
  170 #define IGB_JUMBO_PBA                   0x00000028
  171 #define IGB_DEFAULT_PBA                 0x00000030
  172 #define IGB_SMARTSPEED_DOWNSHIFT        3
  173 #define IGB_SMARTSPEED_MAX              15
  174 #define IGB_MAX_LOOP                    10
  175 
  176 #define IGB_RX_PTHRESH                  (hw->mac.type <= e1000_82576 ? 16 : 8)
  177 #define IGB_RX_HTHRESH                  8
  178 #define IGB_RX_WTHRESH                  1
  179 
  180 #define IGB_TX_PTHRESH                  8
  181 #define IGB_TX_HTHRESH                  1
  182 #define IGB_TX_WTHRESH                  ((hw->mac.type != e1000_82575 && \
  183                                           adapter->msix_mem) ? 1 : 16)
  184 
  185 #define MAX_NUM_MULTICAST_ADDRESSES     128
  186 #define PCI_ANY_ID                      (~0U)
  187 #define ETHER_ALIGN                     2
  188 #define IGB_TX_BUFFER_SIZE              ((uint32_t) 1514)
  189 #define IGB_FC_PAUSE_TIME               0x0680
  190 #define IGB_EEPROM_APME                 0x400;
  191 #define IGB_QUEUE_IDLE                  0
  192 #define IGB_QUEUE_WORKING               1
  193 #define IGB_QUEUE_HUNG                  2
  194 
  195 /*
  196  * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be
  197  * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will
  198  * also optimize cache line size effect. H/W supports up to cache line size 128.
  199  */
  200 #define IGB_DBA_ALIGN                   128
  201 
  202 #define SPEED_MODE_BIT (1<<21)          /* On PCI-E MACs only */
  203 
  204 /* PCI Config defines */
  205 #define IGB_MSIX_BAR            3
  206 
  207 /* Defines for printing debug information */
  208 #define DEBUG_INIT  0
  209 #define DEBUG_IOCTL 0
  210 #define DEBUG_HW    0
  211 
  212 #define INIT_DEBUGOUT(S)            if (DEBUG_INIT)  printf(S "\n")
  213 #define INIT_DEBUGOUT1(S, A)        if (DEBUG_INIT)  printf(S "\n", A)
  214 #define INIT_DEBUGOUT2(S, A, B)     if (DEBUG_INIT)  printf(S "\n", A, B)
  215 #define IOCTL_DEBUGOUT(S)           if (DEBUG_IOCTL) printf(S "\n")
  216 #define IOCTL_DEBUGOUT1(S, A)       if (DEBUG_IOCTL) printf(S "\n", A)
  217 #define IOCTL_DEBUGOUT2(S, A, B)    if (DEBUG_IOCTL) printf(S "\n", A, B)
  218 #define HW_DEBUGOUT(S)              if (DEBUG_HW) printf(S "\n")
  219 #define HW_DEBUGOUT1(S, A)          if (DEBUG_HW) printf(S "\n", A)
  220 #define HW_DEBUGOUT2(S, A, B)       if (DEBUG_HW) printf(S "\n", A, B)
  221 
  222 #define IGB_MAX_SCATTER         64
  223 #define IGB_VFTA_SIZE           128
  224 #define IGB_BR_SIZE             4096    /* ring buf size */
  225 #define IGB_TSO_SIZE            (65535 + sizeof(struct ether_vlan_header))
  226 #define IGB_TSO_SEG_SIZE        4096    /* Max dma segment size */
  227 #define IGB_HDR_BUF             128
  228 #define IGB_PKTTYPE_MASK        0x0000FFF0
  229 #define ETH_ZLEN                60
  230 #define ETH_ADDR_LEN            6
  231 
  232 /* Offload bits in mbuf flag */
  233 #if __FreeBSD_version >= 800000
  234 #define CSUM_OFFLOAD            (CSUM_IP|CSUM_TCP|CSUM_UDP|CSUM_SCTP)
  235 #else
  236 #define CSUM_OFFLOAD            (CSUM_IP|CSUM_TCP|CSUM_UDP)
  237 #endif
  238 
  239 /* Define the starting Interrupt rate per Queue */
  240 #define IGB_INTS_PER_SEC        8000
  241 #define IGB_DEFAULT_ITR         ((1000000/IGB_INTS_PER_SEC) << 2)
  242 
  243 #define IGB_LINK_ITR            2000
  244 
  245 /* Precision Time Sync (IEEE 1588) defines */
  246 #define ETHERTYPE_IEEE1588      0x88F7
  247 #define PICOSECS_PER_TICK       20833
  248 #define TSYNC_PORT              319 /* UDP port for the protocol */
  249 
  250 /*
  251  * Bus dma allocation structure used by
  252  * e1000_dma_malloc and e1000_dma_free.
  253  */
  254 struct igb_dma_alloc {
  255         bus_addr_t              dma_paddr;
  256         caddr_t                 dma_vaddr;
  257         bus_dma_tag_t           dma_tag;
  258         bus_dmamap_t            dma_map;
  259         bus_dma_segment_t       dma_seg;
  260         int                     dma_nseg;
  261 };
  262 
  263 
  264 /*
  265 ** Driver queue struct: this is the interrupt container
  266 **  for the associated tx and rx ring.
  267 */
  268 struct igb_queue {
  269         struct adapter          *adapter;
  270         u32                     msix;           /* This queue's MSIX vector */
  271         u32                     eims;           /* This queue's EIMS bit */
  272         u32                     eitr_setting;
  273         struct resource         *res;
  274         void                    *tag;
  275         struct tx_ring          *txr;
  276         struct rx_ring          *rxr;
  277         struct task             que_task;
  278         struct taskqueue        *tq;
  279         u64                     irqs;
  280 };
  281 
  282 /*
  283  * Transmit ring: one per queue
  284  */
  285 struct tx_ring {
  286         struct adapter          *adapter;
  287         u32                     me;
  288         struct mtx              tx_mtx;
  289         char                    mtx_name[16];
  290         struct igb_dma_alloc    txdma;
  291         struct e1000_tx_desc    *tx_base;
  292         u32                     next_avail_desc;
  293         u32                     next_to_clean;
  294         volatile u16            tx_avail;
  295         struct igb_tx_buffer    *tx_buffers;
  296 #if __FreeBSD_version >= 800000
  297         struct buf_ring         *br;
  298 #endif
  299         bus_dma_tag_t           txtag;
  300         struct task             txq_task;
  301 
  302         u32                     bytes;
  303         u32                     packets;
  304 
  305         int                     queue_status;
  306         int                     watchdog_time;
  307         int                     tdt;
  308         int                     tdh;
  309         u64                     no_desc_avail;
  310         u64                     tx_packets;
  311 };
  312 
  313 /*
  314  * Receive ring: one per queue
  315  */
  316 struct rx_ring {
  317         struct adapter          *adapter;
  318         u32                     me;
  319         struct igb_dma_alloc    rxdma;
  320         union e1000_adv_rx_desc *rx_base;
  321         struct lro_ctrl         lro;
  322         bool                    lro_enabled;
  323         bool                    hdr_split;
  324         bool                    discard;
  325         struct mtx              rx_mtx;
  326         char                    mtx_name[16];
  327         u32                     next_to_refresh;
  328         u32                     next_to_check;
  329         struct igb_rx_buf       *rx_buffers;
  330         bus_dma_tag_t           htag;           /* dma tag for rx head */
  331         bus_dma_tag_t           ptag;           /* dma tag for rx packet */
  332         /*
  333          * First/last mbuf pointers, for
  334          * collecting multisegment RX packets.
  335          */
  336         struct mbuf            *fmp;
  337         struct mbuf            *lmp;
  338 
  339         u32                     bytes;
  340         u32                     packets;
  341         int                     rdt;
  342         int                     rdh;
  343 
  344         /* Soft stats */
  345         u64                     rx_split_packets;
  346         u64                     rx_discarded;
  347         u64                     rx_packets;
  348         u64                     rx_bytes;
  349 };
  350 
  351 struct adapter {
  352         struct ifnet    *ifp;
  353         struct e1000_hw hw;
  354 
  355         struct e1000_osdep osdep;
  356         struct device   *dev;
  357         struct cdev     *led_dev;
  358 
  359         struct resource *pci_mem;
  360         struct resource *msix_mem;
  361         struct resource *res;
  362         void            *tag;
  363         u32             que_mask;
  364 
  365         int             linkvec;
  366         int             link_mask;
  367         struct task     link_task;
  368         int             link_irq;
  369 
  370         struct ifmedia  media;
  371         struct callout  timer;
  372         int             msix;   /* total vectors allocated */
  373         int             if_flags;
  374         int             max_frame_size;
  375         int             min_frame_size;
  376         int             pause_frames;
  377         struct mtx      core_mtx;
  378         int             igb_insert_vlan_header;
  379         u16             num_queues;
  380         u16             vf_ifp;  /* a VF interface */
  381 
  382         eventhandler_tag vlan_attach;
  383         eventhandler_tag vlan_detach;
  384         u32             num_vlans;
  385 
  386         /* Management and WOL features */
  387         int             wol;
  388         int             has_manage;
  389 
  390         /*
  391         ** Shadow VFTA table, this is needed because
  392         ** the real vlan filter table gets cleared during
  393         ** a soft reset and the driver needs to be able
  394         ** to repopulate it.
  395         */
  396         u32             shadow_vfta[IGB_VFTA_SIZE];
  397 
  398         /* Info about the interface */
  399         u16             link_active;
  400         u16             fc;
  401         u16             link_speed;
  402         u16             link_duplex;
  403         u32             smartspeed;
  404         u32             dmac;
  405         int             enable_aim;
  406 
  407         /* Interface queues */
  408         struct igb_queue        *queues;
  409 
  410         /*
  411          * Transmit rings
  412          */
  413         struct tx_ring          *tx_rings;
  414         u16                     num_tx_desc;
  415 
  416         /* Multicast array pointer */
  417         u8                      *mta;
  418 
  419         /* 
  420          * Receive rings
  421          */
  422         struct rx_ring          *rx_rings;
  423         bool                    rx_hdr_split;
  424         u16                     num_rx_desc;
  425         int                     rx_process_limit;
  426         u32                     rx_mbuf_sz;
  427         u32                     rx_mask;
  428 
  429         /* Misc stats maintained by the driver */
  430         unsigned long   dropped_pkts;
  431         unsigned long   mbuf_defrag_failed;
  432         unsigned long   mbuf_header_failed;
  433         unsigned long   mbuf_packet_failed;
  434         unsigned long   no_tx_map_avail;
  435         unsigned long   no_tx_dma_setup;
  436         unsigned long   watchdog_events;
  437         unsigned long   rx_overruns;
  438         unsigned long   device_control;
  439         unsigned long   rx_control;
  440         unsigned long   int_mask;
  441         unsigned long   eint_mask;
  442         unsigned long   packet_buf_alloc_rx;
  443         unsigned long   packet_buf_alloc_tx;
  444 
  445         boolean_t       in_detach;
  446 
  447 #ifdef IGB_IEEE1588
  448         /* IEEE 1588 precision time support */
  449         struct cyclecounter     cycles;
  450         struct nettimer         clock;
  451         struct nettime_compare  compare;
  452         struct hwtstamp_ctrl    hwtstamp;
  453 #endif
  454 
  455         void                    *stats;
  456 };
  457 
  458 /* ******************************************************************************
  459  * vendor_info_array
  460  *
  461  * This array contains the list of Subvendor/Subdevice IDs on which the driver
  462  * should load.
  463  *
  464  * ******************************************************************************/
  465 typedef struct _igb_vendor_info_t {
  466         unsigned int vendor_id;
  467         unsigned int device_id;
  468         unsigned int subvendor_id;
  469         unsigned int subdevice_id;
  470         unsigned int index;
  471 } igb_vendor_info_t;
  472 
  473 
  474 struct igb_tx_buffer {
  475         int             next_eop;  /* Index of the desc to watch */
  476         struct mbuf    *m_head;
  477         bus_dmamap_t    map;         /* bus_dma map for packet */
  478 };
  479 
  480 struct igb_rx_buf {
  481         struct mbuf    *m_head;
  482         struct mbuf    *m_pack;
  483         bus_dmamap_t    hmap;   /* bus_dma map for header */
  484         bus_dmamap_t    pmap;   /* bus_dma map for packet */
  485 };
  486 
  487 /*
  488 ** Find the number of unrefreshed RX descriptors
  489 */
  490 static inline u16
  491 igb_rx_unrefreshed(struct rx_ring *rxr)
  492 {
  493         struct adapter  *adapter = rxr->adapter;
  494  
  495         if (rxr->next_to_check > rxr->next_to_refresh)
  496                 return (rxr->next_to_check - rxr->next_to_refresh - 1);
  497         else
  498                 return ((adapter->num_rx_desc + rxr->next_to_check) -
  499                     rxr->next_to_refresh - 1);
  500 }
  501 
  502 #define IGB_CORE_LOCK_INIT(_sc, _name) \
  503         mtx_init(&(_sc)->core_mtx, _name, "IGB Core Lock", MTX_DEF)
  504 #define IGB_CORE_LOCK_DESTROY(_sc)      mtx_destroy(&(_sc)->core_mtx)
  505 #define IGB_CORE_LOCK(_sc)              mtx_lock(&(_sc)->core_mtx)
  506 #define IGB_CORE_UNLOCK(_sc)            mtx_unlock(&(_sc)->core_mtx)
  507 #define IGB_CORE_LOCK_ASSERT(_sc)       mtx_assert(&(_sc)->core_mtx, MA_OWNED)
  508 
  509 #define IGB_TX_LOCK_DESTROY(_sc)        mtx_destroy(&(_sc)->tx_mtx)
  510 #define IGB_TX_LOCK(_sc)                mtx_lock(&(_sc)->tx_mtx)
  511 #define IGB_TX_UNLOCK(_sc)              mtx_unlock(&(_sc)->tx_mtx)
  512 #define IGB_TX_TRYLOCK(_sc)             mtx_trylock(&(_sc)->tx_mtx)
  513 #define IGB_TX_LOCK_ASSERT(_sc)         mtx_assert(&(_sc)->tx_mtx, MA_OWNED)
  514 
  515 #define IGB_RX_LOCK_DESTROY(_sc)        mtx_destroy(&(_sc)->rx_mtx)
  516 #define IGB_RX_LOCK(_sc)                mtx_lock(&(_sc)->rx_mtx)
  517 #define IGB_RX_UNLOCK(_sc)              mtx_unlock(&(_sc)->rx_mtx)
  518 #define IGB_RX_LOCK_ASSERT(_sc)         mtx_assert(&(_sc)->rx_mtx, MA_OWNED)
  519 
  520 #define UPDATE_VF_REG(reg, last, cur)           \
  521 {                                               \
  522         u32 new = E1000_READ_REG(hw, reg);      \
  523         if (new < last)                         \
  524                 cur += 0x100000000LL;           \
  525         last = new;                             \
  526         cur &= 0xFFFFFFFF00000000LL;            \
  527         cur |= new;                             \
  528 }
  529 
  530 #if __FreeBSD_version >= 800000 && __FreeBSD_version < 800504
  531 static __inline int
  532 drbr_needs_enqueue(struct ifnet *ifp, struct buf_ring *br)
  533 {
  534 #ifdef ALTQ
  535         if (ALTQ_IS_ENABLED(&ifp->if_snd))
  536                 return (1);
  537 #endif
  538         return (!buf_ring_empty(br));
  539 }
  540 #endif
  541 
  542 #endif /* _IGB_H_DEFINED_ */
  543 
  544 

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