Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/dev/e1000/if_igb.h
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1 /****************************************************************************** 2 3 Copyright (c) 2001-2013, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD$*/ 34 35 #ifndef _IGB_H_DEFINED_ 36 #define _IGB_H_DEFINED_ 37 38 /* Tunables */ 39 40 /* 41 * IGB_TXD: Maximum number of Transmit Descriptors 42 * 43 * This value is the number of transmit descriptors allocated by the driver. 44 * Increasing this value allows the driver to queue more transmits. Each 45 * descriptor is 16 bytes. 46 * Since TDLEN should be multiple of 128bytes, the number of transmit 47 * desscriptors should meet the following condition. 48 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0 49 */ 50 #define IGB_MIN_TXD 256 51 #define IGB_DEFAULT_TXD 1024 52 #define IGB_MAX_TXD 4096 53 54 /* 55 * IGB_RXD: Maximum number of Receive Descriptors 56 * 57 * This value is the number of receive descriptors allocated by the driver. 58 * Increasing this value allows the driver to buffer more incoming packets. 59 * Each descriptor is 16 bytes. A receive buffer is also allocated for each 60 * descriptor. The maximum MTU size is 16110. 61 * Since TDLEN should be multiple of 128bytes, the number of transmit 62 * desscriptors should meet the following condition. 63 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0 64 */ 65 #define IGB_MIN_RXD 256 66 #define IGB_DEFAULT_RXD 1024 67 #define IGB_MAX_RXD 4096 68 69 /* 70 * IGB_TIDV - Transmit Interrupt Delay Value 71 * Valid Range: 0-65535 (0=off) 72 * Default Value: 64 73 * This value delays the generation of transmit interrupts in units of 74 * 1.024 microseconds. Transmit interrupt reduction can improve CPU 75 * efficiency if properly tuned for specific network traffic. If the 76 * system is reporting dropped transmits, this value may be set too high 77 * causing the driver to run out of available transmit descriptors. 78 */ 79 #define IGB_TIDV 64 80 81 /* 82 * IGB_TADV - Transmit Absolute Interrupt Delay Value 83 * Valid Range: 0-65535 (0=off) 84 * Default Value: 64 85 * This value, in units of 1.024 microseconds, limits the delay in which a 86 * transmit interrupt is generated. Useful only if IGB_TIDV is non-zero, 87 * this value ensures that an interrupt is generated after the initial 88 * packet is sent on the wire within the set amount of time. Proper tuning, 89 * along with IGB_TIDV, may improve traffic throughput in specific 90 * network conditions. 91 */ 92 #define IGB_TADV 64 93 94 /* 95 * IGB_RDTR - Receive Interrupt Delay Timer (Packet Timer) 96 * Valid Range: 0-65535 (0=off) 97 * Default Value: 0 98 * This value delays the generation of receive interrupts in units of 1.024 99 * microseconds. Receive interrupt reduction can improve CPU efficiency if 100 * properly tuned for specific network traffic. Increasing this value adds 101 * extra latency to frame reception and can end up decreasing the throughput 102 * of TCP traffic. If the system is reporting dropped receives, this value 103 * may be set too high, causing the driver to run out of available receive 104 * descriptors. 105 * 106 * CAUTION: When setting IGB_RDTR to a value other than 0, adapters 107 * may hang (stop transmitting) under certain network conditions. 108 * If this occurs a WATCHDOG message is logged in the system 109 * event log. In addition, the controller is automatically reset, 110 * restoring the network connection. To eliminate the potential 111 * for the hang ensure that IGB_RDTR is set to 0. 112 */ 113 #define IGB_RDTR 0 114 115 /* 116 * Receive Interrupt Absolute Delay Timer (Not valid for 82542/82543/82544) 117 * Valid Range: 0-65535 (0=off) 118 * Default Value: 64 119 * This value, in units of 1.024 microseconds, limits the delay in which a 120 * receive interrupt is generated. Useful only if IGB_RDTR is non-zero, 121 * this value ensures that an interrupt is generated after the initial 122 * packet is received within the set amount of time. Proper tuning, 123 * along with IGB_RDTR, may improve traffic throughput in specific network 124 * conditions. 125 */ 126 #define IGB_RADV 64 127 128 /* 129 * This parameter controls the duration of transmit watchdog timer. 130 */ 131 #define IGB_WATCHDOG (10 * hz) 132 133 /* 134 * This parameter controls when the driver calls the routine to reclaim 135 * transmit descriptors. Cleaning earlier seems a win. 136 */ 137 #define IGB_TX_CLEANUP_THRESHOLD (adapter->num_tx_desc / 2) 138 139 /* 140 * This parameter controls whether or not autonegotation is enabled. 141 * 0 - Disable autonegotiation 142 * 1 - Enable autonegotiation 143 */ 144 #define DO_AUTO_NEG 1 145 146 /* 147 * This parameter control whether or not the driver will wait for 148 * autonegotiation to complete. 149 * 1 - Wait for autonegotiation to complete 150 * 0 - Don't wait for autonegotiation to complete 151 */ 152 #define WAIT_FOR_AUTO_NEG_DEFAULT 0 153 154 /* Tunables -- End */ 155 156 #define AUTONEG_ADV_DEFAULT (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ 157 ADVERTISE_100_HALF | ADVERTISE_100_FULL | \ 158 ADVERTISE_1000_FULL) 159 160 #define AUTO_ALL_MODES 0 161 162 /* PHY master/slave setting */ 163 #define IGB_MASTER_SLAVE e1000_ms_hw_default 164 165 /* Support AutoMediaDetect for Marvell M88 PHY in i354 */ 166 #define IGB_MEDIA_RESET (1 << 0) 167 168 /* 169 * Micellaneous constants 170 */ 171 #define IGB_VENDOR_ID 0x8086 172 173 #define IGB_JUMBO_PBA 0x00000028 174 #define IGB_DEFAULT_PBA 0x00000030 175 #define IGB_SMARTSPEED_DOWNSHIFT 3 176 #define IGB_SMARTSPEED_MAX 15 177 #define IGB_MAX_LOOP 10 178 179 #define IGB_RX_PTHRESH ((hw->mac.type == e1000_i354) ? 12 : \ 180 ((hw->mac.type <= e1000_82576) ? 16 : 8)) 181 #define IGB_RX_HTHRESH 8 182 #define IGB_RX_WTHRESH ((hw->mac.type == e1000_82576 && \ 183 adapter->msix_mem) ? 1 : 4) 184 185 #define IGB_TX_PTHRESH ((hw->mac.type == e1000_i354) ? 20 : 8) 186 #define IGB_TX_HTHRESH 1 187 #define IGB_TX_WTHRESH ((hw->mac.type != e1000_82575 && \ 188 adapter->msix_mem) ? 1 : 16) 189 190 #define MAX_NUM_MULTICAST_ADDRESSES 128 191 #define PCI_ANY_ID (~0U) 192 #define ETHER_ALIGN 2 193 #define IGB_TX_BUFFER_SIZE ((uint32_t) 1514) 194 #define IGB_FC_PAUSE_TIME 0x0680 195 #define IGB_EEPROM_APME 0x400; 196 /* Queue minimum free for use */ 197 #define IGB_QUEUE_THRESHOLD (adapter->num_tx_desc / 8) 198 199 /* 200 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be 201 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will 202 * also optimize cache line size effect. H/W supports up to cache line size 128. 203 */ 204 #define IGB_DBA_ALIGN 128 205 206 #define SPEED_MODE_BIT (1<<21) /* On PCI-E MACs only */ 207 208 /* PCI Config defines */ 209 #define IGB_MSIX_BAR 3 210 211 /* Defines for printing debug information */ 212 #define DEBUG_INIT 0 213 #define DEBUG_IOCTL 0 214 #define DEBUG_HW 0 215 216 #define INIT_DEBUGOUT(S) if (DEBUG_INIT) printf(S "\n") 217 #define INIT_DEBUGOUT1(S, A) if (DEBUG_INIT) printf(S "\n", A) 218 #define INIT_DEBUGOUT2(S, A, B) if (DEBUG_INIT) printf(S "\n", A, B) 219 #define IOCTL_DEBUGOUT(S) if (DEBUG_IOCTL) printf(S "\n") 220 #define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) printf(S "\n", A) 221 #define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) printf(S "\n", A, B) 222 #define HW_DEBUGOUT(S) if (DEBUG_HW) printf(S "\n") 223 #define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A) 224 #define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B) 225 226 #define IGB_MAX_SCATTER 64 227 #define IGB_VFTA_SIZE 128 228 #define IGB_BR_SIZE 4096 /* ring buf size */ 229 #define IGB_TSO_SIZE (65535 + sizeof(struct ether_vlan_header)) 230 #define IGB_TSO_SEG_SIZE 4096 /* Max dma segment size */ 231 #define IGB_TXPBSIZE 20408 232 #define IGB_HDR_BUF 128 233 #define IGB_PKTTYPE_MASK 0x0000FFF0 234 #define IGB_DMCTLX_DCFLUSH_DIS 0x80000000 /* Disable DMA Coalesce Flush */ 235 #define ETH_ZLEN 60 236 #define ETH_ADDR_LEN 6 237 238 /* Offload bits in mbuf flag */ 239 #if __FreeBSD_version >= 800000 240 #define CSUM_OFFLOAD (CSUM_IP|CSUM_TCP|CSUM_UDP|CSUM_SCTP) 241 #else 242 #define CSUM_OFFLOAD (CSUM_IP|CSUM_TCP|CSUM_UDP) 243 #endif 244 245 /* Define the starting Interrupt rate per Queue */ 246 #define IGB_INTS_PER_SEC 8000 247 #define IGB_DEFAULT_ITR ((1000000/IGB_INTS_PER_SEC) << 2) 248 249 #define IGB_LINK_ITR 2000 250 #define I210_LINK_DELAY 1000 251 252 /* Precision Time Sync (IEEE 1588) defines */ 253 #define ETHERTYPE_IEEE1588 0x88F7 254 #define PICOSECS_PER_TICK 20833 255 #define TSYNC_PORT 319 /* UDP port for the protocol */ 256 257 /* 258 * Bus dma allocation structure used by 259 * e1000_dma_malloc and e1000_dma_free. 260 */ 261 struct igb_dma_alloc { 262 bus_addr_t dma_paddr; 263 caddr_t dma_vaddr; 264 bus_dma_tag_t dma_tag; 265 bus_dmamap_t dma_map; 266 bus_dma_segment_t dma_seg; 267 int dma_nseg; 268 }; 269 270 271 /* 272 ** Driver queue struct: this is the interrupt container 273 ** for the associated tx and rx ring. 274 */ 275 struct igb_queue { 276 struct adapter *adapter; 277 u32 msix; /* This queue's MSIX vector */ 278 u32 eims; /* This queue's EIMS bit */ 279 u32 eitr_setting; 280 struct resource *res; 281 void *tag; 282 struct tx_ring *txr; 283 struct rx_ring *rxr; 284 struct task que_task; 285 struct taskqueue *tq; 286 u64 irqs; 287 }; 288 289 /* 290 * The transmit ring, one per queue 291 */ 292 struct tx_ring { 293 struct adapter *adapter; 294 struct mtx tx_mtx; 295 u32 me; 296 int watchdog_time; 297 union e1000_adv_tx_desc *tx_base; 298 struct igb_tx_buf *tx_buffers; 299 struct igb_dma_alloc txdma; 300 volatile u16 tx_avail; 301 u16 next_avail_desc; 302 u16 next_to_clean; 303 u16 process_limit; 304 u16 num_desc; 305 enum { 306 IGB_QUEUE_IDLE = 1, 307 IGB_QUEUE_WORKING = 2, 308 IGB_QUEUE_HUNG = 4, 309 IGB_QUEUE_DEPLETED = 8, 310 } queue_status; 311 u32 txd_cmd; 312 bus_dma_tag_t txtag; 313 char mtx_name[16]; 314 #ifndef IGB_LEGACY_TX 315 struct buf_ring *br; 316 struct task txq_task; 317 #endif 318 u32 bytes; /* used for AIM */ 319 u32 packets; 320 /* Soft Stats */ 321 unsigned long tso_tx; 322 unsigned long no_tx_map_avail; 323 unsigned long no_tx_dma_setup; 324 u64 no_desc_avail; 325 u64 total_packets; 326 }; 327 328 /* 329 * Receive ring: one per queue 330 */ 331 struct rx_ring { 332 struct adapter *adapter; 333 u32 me; 334 struct igb_dma_alloc rxdma; 335 union e1000_adv_rx_desc *rx_base; 336 struct lro_ctrl lro; 337 bool lro_enabled; 338 bool hdr_split; 339 bool discard; 340 struct mtx rx_mtx; 341 char mtx_name[16]; 342 u32 next_to_refresh; 343 u32 next_to_check; 344 struct igb_rx_buf *rx_buffers; 345 bus_dma_tag_t htag; /* dma tag for rx head */ 346 bus_dma_tag_t ptag; /* dma tag for rx packet */ 347 /* 348 * First/last mbuf pointers, for 349 * collecting multisegment RX packets. 350 */ 351 struct mbuf *fmp; 352 struct mbuf *lmp; 353 354 u32 bytes; 355 u32 packets; 356 int rdt; 357 int rdh; 358 359 /* Soft stats */ 360 u64 rx_split_packets; 361 u64 rx_discarded; 362 u64 rx_packets; 363 u64 rx_bytes; 364 }; 365 366 struct adapter { 367 struct ifnet *ifp; 368 struct e1000_hw hw; 369 370 struct e1000_osdep osdep; 371 struct device *dev; 372 struct cdev *led_dev; 373 374 struct resource *pci_mem; 375 struct resource *msix_mem; 376 int memrid; 377 378 /* 379 * Interrupt resources: this set is 380 * either used for legacy, or for Link 381 * when doing MSIX 382 */ 383 void *tag; 384 struct resource *res; 385 386 struct ifmedia media; 387 struct callout timer; 388 int msix; 389 int if_flags; 390 int pause_frames; 391 392 struct mtx core_mtx; 393 394 eventhandler_tag vlan_attach; 395 eventhandler_tag vlan_detach; 396 397 u16 num_vlans; 398 u16 num_queues; 399 400 /* 401 ** Shadow VFTA table, this is needed because 402 ** the real vlan filter table gets cleared during 403 ** a soft reset and the driver needs to be able 404 ** to repopulate it. 405 */ 406 u32 shadow_vfta[IGB_VFTA_SIZE]; 407 408 /* Info about the interface */ 409 u32 optics; 410 u32 fc; /* local flow ctrl setting */ 411 int advertise; /* link speeds */ 412 bool link_active; 413 u16 max_frame_size; 414 u16 num_segs; 415 u16 link_speed; 416 bool link_up; 417 u32 linkvec; 418 u16 link_duplex; 419 u32 dmac; 420 int link_mask; 421 422 /* Flags */ 423 u32 flags; 424 425 /* Mbuf cluster size */ 426 u32 rx_mbuf_sz; 427 428 /* Support for pluggable optics */ 429 bool sfp_probe; 430 struct task link_task; /* Link tasklet */ 431 struct task mod_task; /* SFP tasklet */ 432 struct task msf_task; /* Multispeed Fiber */ 433 struct taskqueue *tq; 434 435 /* 436 ** Queues: 437 ** This is the irq holder, it has 438 ** and RX/TX pair or rings associated 439 ** with it. 440 */ 441 struct igb_queue *queues; 442 443 /* 444 * Transmit rings: 445 * Allocated at run time, an array of rings. 446 */ 447 struct tx_ring *tx_rings; 448 u32 num_tx_desc; 449 450 /* 451 * Receive rings: 452 * Allocated at run time, an array of rings. 453 */ 454 struct rx_ring *rx_rings; 455 u64 que_mask; 456 u32 num_rx_desc; 457 458 /* Multicast array memory */ 459 u8 *mta; 460 461 /* Misc stats maintained by the driver */ 462 unsigned long dropped_pkts; 463 unsigned long mbuf_defrag_failed; 464 unsigned long mbuf_header_failed; 465 unsigned long mbuf_packet_failed; 466 unsigned long no_tx_dma_setup; 467 unsigned long watchdog_events; 468 unsigned long link_irq; 469 unsigned long rx_overruns; 470 unsigned long device_control; 471 unsigned long rx_control; 472 unsigned long int_mask; 473 unsigned long eint_mask; 474 unsigned long packet_buf_alloc_rx; 475 unsigned long packet_buf_alloc_tx; 476 /* Used in pf and vf */ 477 void *stats; 478 479 int enable_aim; 480 int has_manage; 481 int wol; 482 int rx_process_limit; 483 u16 vf_ifp; /* a VF interface */ 484 bool in_detach; /* Used only in igb_ioctl */ 485 486 }; 487 488 /* ****************************************************************************** 489 * vendor_info_array 490 * 491 * This array contains the list of Subvendor/Subdevice IDs on which the driver 492 * should load. 493 * 494 * ******************************************************************************/ 495 typedef struct _igb_vendor_info_t { 496 unsigned int vendor_id; 497 unsigned int device_id; 498 unsigned int subvendor_id; 499 unsigned int subdevice_id; 500 unsigned int index; 501 } igb_vendor_info_t; 502 503 struct igb_tx_buf { 504 union e1000_adv_tx_desc *eop; 505 struct mbuf *m_head; 506 bus_dmamap_t map; 507 }; 508 509 struct igb_rx_buf { 510 struct mbuf *m_head; 511 struct mbuf *m_pack; 512 bus_dmamap_t hmap; /* bus_dma map for header */ 513 bus_dmamap_t pmap; /* bus_dma map for packet */ 514 }; 515 516 /* 517 ** Find the number of unrefreshed RX descriptors 518 */ 519 static inline u16 520 igb_rx_unrefreshed(struct rx_ring *rxr) 521 { 522 struct adapter *adapter = rxr->adapter; 523 524 if (rxr->next_to_check > rxr->next_to_refresh) 525 return (rxr->next_to_check - rxr->next_to_refresh - 1); 526 else 527 return ((adapter->num_rx_desc + rxr->next_to_check) - 528 rxr->next_to_refresh - 1); 529 } 530 531 #define IGB_CORE_LOCK_INIT(_sc, _name) \ 532 mtx_init(&(_sc)->core_mtx, _name, "IGB Core Lock", MTX_DEF) 533 #define IGB_CORE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->core_mtx) 534 #define IGB_CORE_LOCK(_sc) mtx_lock(&(_sc)->core_mtx) 535 #define IGB_CORE_UNLOCK(_sc) mtx_unlock(&(_sc)->core_mtx) 536 #define IGB_CORE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->core_mtx, MA_OWNED) 537 538 #define IGB_TX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->tx_mtx) 539 #define IGB_TX_LOCK(_sc) mtx_lock(&(_sc)->tx_mtx) 540 #define IGB_TX_UNLOCK(_sc) mtx_unlock(&(_sc)->tx_mtx) 541 #define IGB_TX_TRYLOCK(_sc) mtx_trylock(&(_sc)->tx_mtx) 542 #define IGB_TX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->tx_mtx, MA_OWNED) 543 544 #define IGB_RX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->rx_mtx) 545 #define IGB_RX_LOCK(_sc) mtx_lock(&(_sc)->rx_mtx) 546 #define IGB_RX_UNLOCK(_sc) mtx_unlock(&(_sc)->rx_mtx) 547 #define IGB_RX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->rx_mtx, MA_OWNED) 548 549 #define UPDATE_VF_REG(reg, last, cur) \ 550 { \ 551 u32 new = E1000_READ_REG(hw, reg); \ 552 if (new < last) \ 553 cur += 0x100000000LL; \ 554 last = new; \ 555 cur &= 0xFFFFFFFF00000000LL; \ 556 cur |= new; \ 557 } 558 559 #if __FreeBSD_version >= 800000 && __FreeBSD_version < 800504 560 static __inline int 561 drbr_needs_enqueue(struct ifnet *ifp, struct buf_ring *br) 562 { 563 #ifdef ALTQ 564 if (ALTQ_IS_ENABLED(&ifp->if_snd)) 565 return (1); 566 #endif 567 return (!buf_ring_empty(br)); 568 } 569 #endif 570 571 #endif /* _IGB_H_DEFINED_ */ 572 573
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