The Design and Implementation of the FreeBSD Operating System, Second Edition
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FreeBSD/Linux Kernel Cross Reference
sys/dev/e1000/if_lem.h

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    1 /******************************************************************************
    2 
    3   Copyright (c) 2001-2010, Intel Corporation 
    4   All rights reserved.
    5   
    6   Redistribution and use in source and binary forms, with or without 
    7   modification, are permitted provided that the following conditions are met:
    8   
    9    1. Redistributions of source code must retain the above copyright notice, 
   10       this list of conditions and the following disclaimer.
   11   
   12    2. Redistributions in binary form must reproduce the above copyright 
   13       notice, this list of conditions and the following disclaimer in the 
   14       documentation and/or other materials provided with the distribution.
   15   
   16    3. Neither the name of the Intel Corporation nor the names of its 
   17       contributors may be used to endorse or promote products derived from 
   18       this software without specific prior written permission.
   19   
   20   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
   21   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
   22   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
   23   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 
   24   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 
   25   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 
   26   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
   27   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
   28   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
   29   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   30   POSSIBILITY OF SUCH DAMAGE.
   31 
   32 ******************************************************************************/
   33 /*$FreeBSD: releng/9.0/sys/dev/e1000/if_lem.h 219764 2011-03-19 00:31:35Z jfv $*/
   34 
   35 
   36 #ifndef _LEM_H_DEFINED_
   37 #define _LEM_H_DEFINED_
   38 
   39 
   40 /* Tunables */
   41 
   42 /*
   43  * EM_TXD: Maximum number of Transmit Descriptors
   44  * Valid Range: 80-256 for 82542 and 82543-based adapters
   45  *              80-4096 for others
   46  * Default Value: 256
   47  *   This value is the number of transmit descriptors allocated by the driver.
   48  *   Increasing this value allows the driver to queue more transmits. Each
   49  *   descriptor is 16 bytes.
   50  *   Since TDLEN should be multiple of 128bytes, the number of transmit
   51  *   desscriptors should meet the following condition.
   52  *      (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0
   53  */
   54 #define EM_MIN_TXD              80
   55 #define EM_MAX_TXD_82543        256
   56 #define EM_MAX_TXD              4096
   57 #define EM_DEFAULT_TXD          EM_MAX_TXD_82543
   58 
   59 /*
   60  * EM_RXD - Maximum number of receive Descriptors
   61  * Valid Range: 80-256 for 82542 and 82543-based adapters
   62  *              80-4096 for others
   63  * Default Value: 256
   64  *   This value is the number of receive descriptors allocated by the driver.
   65  *   Increasing this value allows the driver to buffer more incoming packets.
   66  *   Each descriptor is 16 bytes.  A receive buffer is also allocated for each
   67  *   descriptor. The maximum MTU size is 16110.
   68  *   Since TDLEN should be multiple of 128bytes, the number of transmit
   69  *   desscriptors should meet the following condition.
   70  *      (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0
   71  */
   72 #define EM_MIN_RXD              80
   73 #define EM_MAX_RXD_82543        256
   74 #define EM_MAX_RXD              4096
   75 #define EM_DEFAULT_RXD  EM_MAX_RXD_82543
   76 
   77 /*
   78  * EM_TIDV - Transmit Interrupt Delay Value
   79  * Valid Range: 0-65535 (0=off)
   80  * Default Value: 64
   81  *   This value delays the generation of transmit interrupts in units of
   82  *   1.024 microseconds. Transmit interrupt reduction can improve CPU
   83  *   efficiency if properly tuned for specific network traffic. If the
   84  *   system is reporting dropped transmits, this value may be set too high
   85  *   causing the driver to run out of available transmit descriptors.
   86  */
   87 #define EM_TIDV                         64
   88 
   89 /*
   90  * EM_TADV - Transmit Absolute Interrupt Delay Value
   91  * (Not valid for 82542/82543/82544)
   92  * Valid Range: 0-65535 (0=off)
   93  * Default Value: 64
   94  *   This value, in units of 1.024 microseconds, limits the delay in which a
   95  *   transmit interrupt is generated. Useful only if EM_TIDV is non-zero,
   96  *   this value ensures that an interrupt is generated after the initial
   97  *   packet is sent on the wire within the set amount of time.  Proper tuning,
   98  *   along with EM_TIDV, may improve traffic throughput in specific
   99  *   network conditions.
  100  */
  101 #define EM_TADV                         64
  102 
  103 /*
  104  * EM_RDTR - Receive Interrupt Delay Timer (Packet Timer)
  105  * Valid Range: 0-65535 (0=off)
  106  * Default Value: 0
  107  *   This value delays the generation of receive interrupts in units of 1.024
  108  *   microseconds.  Receive interrupt reduction can improve CPU efficiency if
  109  *   properly tuned for specific network traffic. Increasing this value adds
  110  *   extra latency to frame reception and can end up decreasing the throughput
  111  *   of TCP traffic. If the system is reporting dropped receives, this value
  112  *   may be set too high, causing the driver to run out of available receive
  113  *   descriptors.
  114  *
  115  *   CAUTION: When setting EM_RDTR to a value other than 0, adapters
  116  *            may hang (stop transmitting) under certain network conditions.
  117  *            If this occurs a WATCHDOG message is logged in the system
  118  *            event log. In addition, the controller is automatically reset,
  119  *            restoring the network connection. To eliminate the potential
  120  *            for the hang ensure that EM_RDTR is set to 0.
  121  */
  122 #define EM_RDTR                         0
  123 
  124 /*
  125  * Receive Interrupt Absolute Delay Timer (Not valid for 82542/82543/82544)
  126  * Valid Range: 0-65535 (0=off)
  127  * Default Value: 64
  128  *   This value, in units of 1.024 microseconds, limits the delay in which a
  129  *   receive interrupt is generated. Useful only if EM_RDTR is non-zero,
  130  *   this value ensures that an interrupt is generated after the initial
  131  *   packet is received within the set amount of time.  Proper tuning,
  132  *   along with EM_RDTR, may improve traffic throughput in specific network
  133  *   conditions.
  134  */
  135 #define EM_RADV                         64
  136 
  137 /*
  138  * This parameter controls the max duration of transmit watchdog.
  139  */
  140 #define EM_WATCHDOG                   (10 * hz)
  141 
  142 /*
  143  * This parameter controls when the driver calls the routine to reclaim
  144  * transmit descriptors.
  145  */
  146 #define EM_TX_CLEANUP_THRESHOLD (adapter->num_tx_desc / 8)
  147 #define EM_TX_OP_THRESHOLD      (adapter->num_tx_desc / 32)
  148 
  149 /*
  150  * This parameter controls whether or not autonegotation is enabled.
  151  *              0 - Disable autonegotiation
  152  *              1 - Enable  autonegotiation
  153  */
  154 #define DO_AUTO_NEG                     1
  155 
  156 /*
  157  * This parameter control whether or not the driver will wait for
  158  * autonegotiation to complete.
  159  *              1 - Wait for autonegotiation to complete
  160  *              0 - Don't wait for autonegotiation to complete
  161  */
  162 #define WAIT_FOR_AUTO_NEG_DEFAULT       0
  163 
  164 /* Tunables -- End */
  165 
  166 #define AUTONEG_ADV_DEFAULT     (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \
  167                                 ADVERTISE_100_HALF | ADVERTISE_100_FULL | \
  168                                 ADVERTISE_1000_FULL)
  169 
  170 #define AUTO_ALL_MODES          0
  171 
  172 /* PHY master/slave setting */
  173 #define EM_MASTER_SLAVE         e1000_ms_hw_default
  174 
  175 /*
  176  * Micellaneous constants
  177  */
  178 #define EM_VENDOR_ID                    0x8086
  179 #define EM_FLASH                        0x0014 
  180 
  181 #define EM_JUMBO_PBA                    0x00000028
  182 #define EM_DEFAULT_PBA                  0x00000030
  183 #define EM_SMARTSPEED_DOWNSHIFT         3
  184 #define EM_SMARTSPEED_MAX               15
  185 #define EM_MAX_LOOP                     10
  186 
  187 #define MAX_NUM_MULTICAST_ADDRESSES     128
  188 #define PCI_ANY_ID                      (~0U)
  189 #define ETHER_ALIGN                     2
  190 #define EM_FC_PAUSE_TIME                0x0680
  191 #define EM_EEPROM_APME                  0x400;
  192 #define EM_82544_APME                   0x0004;
  193 
  194 /* Code compatilbility between 6 and 7 */
  195 #ifndef ETHER_BPF_MTAP
  196 #define ETHER_BPF_MTAP                  BPF_MTAP
  197 #endif
  198 
  199 /*
  200  * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be
  201  * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will
  202  * also optimize cache line size effect. H/W supports up to cache line size 128.
  203  */
  204 #define EM_DBA_ALIGN                    128
  205 
  206 #define SPEED_MODE_BIT (1<<21)          /* On PCI-E MACs only */
  207 
  208 /* PCI Config defines */
  209 #define EM_BAR_TYPE(v)          ((v) & EM_BAR_TYPE_MASK)
  210 #define EM_BAR_TYPE_MASK        0x00000001
  211 #define EM_BAR_TYPE_MMEM        0x00000000
  212 #define EM_BAR_TYPE_IO          0x00000001
  213 #define EM_BAR_TYPE_FLASH       0x0014 
  214 #define EM_BAR_MEM_TYPE(v)      ((v) & EM_BAR_MEM_TYPE_MASK)
  215 #define EM_BAR_MEM_TYPE_MASK    0x00000006
  216 #define EM_BAR_MEM_TYPE_32BIT   0x00000000
  217 #define EM_BAR_MEM_TYPE_64BIT   0x00000004
  218 #define EM_MSIX_BAR             3       /* On 82575 */
  219 
  220 #if !defined(SYSCTL_ADD_UQUAD)
  221 #define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD
  222 #endif
  223 
  224 /* Defines for printing debug information */
  225 #define DEBUG_INIT  0
  226 #define DEBUG_IOCTL 0
  227 #define DEBUG_HW    0
  228 
  229 #define INIT_DEBUGOUT(S)            if (DEBUG_INIT)  printf(S "\n")
  230 #define INIT_DEBUGOUT1(S, A)        if (DEBUG_INIT)  printf(S "\n", A)
  231 #define INIT_DEBUGOUT2(S, A, B)     if (DEBUG_INIT)  printf(S "\n", A, B)
  232 #define IOCTL_DEBUGOUT(S)           if (DEBUG_IOCTL) printf(S "\n")
  233 #define IOCTL_DEBUGOUT1(S, A)       if (DEBUG_IOCTL) printf(S "\n", A)
  234 #define IOCTL_DEBUGOUT2(S, A, B)    if (DEBUG_IOCTL) printf(S "\n", A, B)
  235 #define HW_DEBUGOUT(S)              if (DEBUG_HW) printf(S "\n")
  236 #define HW_DEBUGOUT1(S, A)          if (DEBUG_HW) printf(S "\n", A)
  237 #define HW_DEBUGOUT2(S, A, B)       if (DEBUG_HW) printf(S "\n", A, B)
  238 
  239 #define EM_MAX_SCATTER          64
  240 #define EM_VFTA_SIZE            128
  241 #define EM_TSO_SIZE             (65535 + sizeof(struct ether_vlan_header))
  242 #define EM_TSO_SEG_SIZE         4096    /* Max dma segment size */
  243 #define EM_MSIX_MASK            0x01F00000 /* For 82574 use */
  244 #define ETH_ZLEN                60
  245 #define ETH_ADDR_LEN            6
  246 #define CSUM_OFFLOAD            7       /* Offload bits in mbuf flag */
  247 
  248 /*
  249  * 82574 has a nonstandard address for EIAC
  250  * and since its only used in MSIX, and in
  251  * the em driver only 82574 uses MSIX we can
  252  * solve it just using this define.
  253  */
  254 #define EM_EIAC 0x000DC
  255 
  256 /* Used in for 82547 10Mb Half workaround */
  257 #define EM_PBA_BYTES_SHIFT      0xA
  258 #define EM_TX_HEAD_ADDR_SHIFT   7
  259 #define EM_PBA_TX_MASK          0xFFFF0000
  260 #define EM_FIFO_HDR             0x10
  261 #define EM_82547_PKT_THRESH     0x3e0
  262 
  263 /* Precision Time Sync (IEEE 1588) defines */
  264 #define ETHERTYPE_IEEE1588      0x88F7
  265 #define PICOSECS_PER_TICK       20833
  266 #define TSYNC_PORT              319 /* UDP port for the protocol */
  267 
  268 /*
  269  * Bus dma allocation structure used by
  270  * e1000_dma_malloc and e1000_dma_free.
  271  */
  272 struct em_dma_alloc {
  273         bus_addr_t              dma_paddr;
  274         caddr_t                 dma_vaddr;
  275         bus_dma_tag_t           dma_tag;
  276         bus_dmamap_t            dma_map;
  277         bus_dma_segment_t       dma_seg;
  278         int                     dma_nseg;
  279 };
  280 
  281 struct adapter;
  282 
  283 struct em_int_delay_info {
  284         struct adapter *adapter;        /* Back-pointer to the adapter struct */
  285         int offset;                     /* Register offset to read/write */
  286         int value;                      /* Current value in usecs */
  287 };
  288 
  289 /* Our adapter structure */
  290 struct adapter {
  291         struct ifnet    *ifp;
  292 #if __FreeBSD_version >= 800000
  293         struct buf_ring *br;
  294 #endif
  295         struct e1000_hw hw;
  296 
  297         /* FreeBSD operating-system-specific structures. */
  298         struct e1000_osdep osdep;
  299         struct device   *dev;
  300         struct cdev     *led_dev;
  301 
  302         struct resource *memory;
  303         struct resource *flash;
  304         struct resource *msix;
  305 
  306         struct resource *ioport;
  307         int             io_rid;
  308 
  309         /* 82574 may use 3 int vectors */
  310         struct resource *res[3];
  311         void            *tag[3];
  312         int             rid[3];
  313 
  314         struct ifmedia  media;
  315         struct callout  timer;
  316         struct callout  tx_fifo_timer;
  317         bool            watchdog_check;
  318         int             watchdog_time;
  319         int             msi;
  320         int             if_flags;
  321         int             max_frame_size;
  322         int             min_frame_size;
  323         struct mtx      core_mtx;
  324         struct mtx      tx_mtx;
  325         struct mtx      rx_mtx;
  326         int             em_insert_vlan_header;
  327 
  328         /* Task for FAST handling */
  329         struct task     link_task;
  330         struct task     rxtx_task;
  331         struct task     rx_task;
  332         struct task     tx_task;
  333         struct taskqueue *tq;           /* private task queue */
  334 
  335         eventhandler_tag vlan_attach;
  336         eventhandler_tag vlan_detach;
  337         u32     num_vlans;
  338 
  339         /* Management and WOL features */
  340         u32             wol;
  341         bool            has_manage;
  342         bool            has_amt;
  343 
  344         /* Multicast array memory */
  345         u8              *mta;
  346 
  347         /*
  348         ** Shadow VFTA table, this is needed because
  349         ** the real vlan filter table gets cleared during
  350         ** a soft reset and the driver needs to be able
  351         ** to repopulate it.
  352         */
  353         u32             shadow_vfta[EM_VFTA_SIZE];
  354 
  355         /* Info about the interface */
  356         uint8_t         link_active;
  357         uint16_t        link_speed;
  358         uint16_t        link_duplex;
  359         uint32_t        smartspeed;
  360         uint32_t        fc_setting;
  361 
  362         struct em_int_delay_info tx_int_delay;
  363         struct em_int_delay_info tx_abs_int_delay;
  364         struct em_int_delay_info rx_int_delay;
  365         struct em_int_delay_info rx_abs_int_delay;
  366 
  367         /*
  368          * Transmit definitions
  369          *
  370          * We have an array of num_tx_desc descriptors (handled
  371          * by the controller) paired with an array of tx_buffers
  372          * (at tx_buffer_area).
  373          * The index of the next available descriptor is next_avail_tx_desc.
  374          * The number of remaining tx_desc is num_tx_desc_avail.
  375          */
  376         struct em_dma_alloc     txdma;          /* bus_dma glue for tx desc */
  377         struct e1000_tx_desc    *tx_desc_base;
  378         uint32_t                next_avail_tx_desc;
  379         uint32_t                next_tx_to_clean;
  380         volatile uint16_t       num_tx_desc_avail;
  381         uint16_t                num_tx_desc;
  382         uint16_t                last_hw_offload;
  383         uint32_t                txd_cmd;
  384         struct em_buffer        *tx_buffer_area;
  385         bus_dma_tag_t           txtag;          /* dma tag for tx */
  386         uint32_t                tx_tso;         /* last tx was tso */
  387 
  388         /* 
  389          * Receive definitions
  390          *
  391          * we have an array of num_rx_desc rx_desc (handled by the
  392          * controller), and paired with an array of rx_buffers
  393          * (at rx_buffer_area).
  394          * The next pair to check on receive is at offset next_rx_desc_to_check
  395          */
  396         struct em_dma_alloc     rxdma;          /* bus_dma glue for rx desc */
  397         struct e1000_rx_desc    *rx_desc_base;
  398         uint32_t                next_rx_desc_to_check;
  399         uint32_t                rx_buffer_len;
  400         uint16_t                num_rx_desc;
  401         int                     rx_process_limit;
  402         struct em_buffer        *rx_buffer_area;
  403         bus_dma_tag_t           rxtag;
  404         bus_dmamap_t            rx_sparemap;
  405 
  406         /*
  407          * First/last mbuf pointers, for
  408          * collecting multisegment RX packets.
  409          */
  410         struct mbuf            *fmp;
  411         struct mbuf            *lmp;
  412 
  413         /* Misc stats maintained by the driver */
  414         unsigned long   dropped_pkts;
  415         unsigned long   mbuf_alloc_failed;
  416         unsigned long   mbuf_cluster_failed;
  417         unsigned long   no_tx_desc_avail1;
  418         unsigned long   no_tx_desc_avail2;
  419         unsigned long   no_tx_map_avail;
  420         unsigned long   no_tx_dma_setup;
  421         unsigned long   watchdog_events;
  422         unsigned long   rx_overruns;
  423         unsigned long   rx_irq;
  424         unsigned long   tx_irq;
  425         unsigned long   link_irq;
  426 
  427         /* 82547 workaround */
  428         uint32_t        tx_fifo_size;
  429         uint32_t        tx_fifo_head;
  430         uint32_t        tx_fifo_head_addr;
  431         uint64_t        tx_fifo_reset_cnt;
  432         uint64_t        tx_fifo_wrk_cnt;
  433         uint32_t        tx_head_addr;
  434 
  435         /* For 82544 PCIX Workaround */
  436         boolean_t       pcix_82544;
  437         boolean_t       in_detach;
  438 
  439 
  440         struct e1000_hw_stats stats;
  441 };
  442 
  443 /* ******************************************************************************
  444  * vendor_info_array
  445  *
  446  * This array contains the list of Subvendor/Subdevice IDs on which the driver
  447  * should load.
  448  *
  449  * ******************************************************************************/
  450 typedef struct _em_vendor_info_t {
  451         unsigned int vendor_id;
  452         unsigned int device_id;
  453         unsigned int subvendor_id;
  454         unsigned int subdevice_id;
  455         unsigned int index;
  456 } em_vendor_info_t;
  457 
  458 struct em_buffer {
  459         int             next_eop;  /* Index of the desc to watch */
  460         struct mbuf    *m_head;
  461         bus_dmamap_t    map;         /* bus_dma map for packet */
  462 };
  463 
  464 /* For 82544 PCIX  Workaround */
  465 typedef struct _ADDRESS_LENGTH_PAIR
  466 {
  467         uint64_t   address;
  468         uint32_t   length;
  469 } ADDRESS_LENGTH_PAIR, *PADDRESS_LENGTH_PAIR;
  470 
  471 typedef struct _DESCRIPTOR_PAIR
  472 {
  473         ADDRESS_LENGTH_PAIR descriptor[4];
  474         uint32_t   elements;
  475 } DESC_ARRAY, *PDESC_ARRAY;
  476 
  477 #define EM_CORE_LOCK_INIT(_sc, _name) \
  478         mtx_init(&(_sc)->core_mtx, _name, "EM Core Lock", MTX_DEF)
  479 #define EM_TX_LOCK_INIT(_sc, _name) \
  480         mtx_init(&(_sc)->tx_mtx, _name, "EM TX Lock", MTX_DEF)
  481 #define EM_RX_LOCK_INIT(_sc, _name) \
  482         mtx_init(&(_sc)->rx_mtx, _name, "EM RX Lock", MTX_DEF)
  483 #define EM_CORE_LOCK_DESTROY(_sc)       mtx_destroy(&(_sc)->core_mtx)
  484 #define EM_TX_LOCK_DESTROY(_sc)         mtx_destroy(&(_sc)->tx_mtx)
  485 #define EM_RX_LOCK_DESTROY(_sc)         mtx_destroy(&(_sc)->rx_mtx)
  486 #define EM_CORE_LOCK(_sc)               mtx_lock(&(_sc)->core_mtx)
  487 #define EM_TX_LOCK(_sc)                 mtx_lock(&(_sc)->tx_mtx)
  488 #define EM_TX_TRYLOCK(_sc)              mtx_trylock(&(_sc)->tx_mtx)
  489 #define EM_RX_LOCK(_sc)                 mtx_lock(&(_sc)->rx_mtx)
  490 #define EM_CORE_UNLOCK(_sc)             mtx_unlock(&(_sc)->core_mtx)
  491 #define EM_TX_UNLOCK(_sc)               mtx_unlock(&(_sc)->tx_mtx)
  492 #define EM_RX_UNLOCK(_sc)               mtx_unlock(&(_sc)->rx_mtx)
  493 #define EM_CORE_LOCK_ASSERT(_sc)        mtx_assert(&(_sc)->core_mtx, MA_OWNED)
  494 #define EM_TX_LOCK_ASSERT(_sc)          mtx_assert(&(_sc)->tx_mtx, MA_OWNED)
  495 
  496 #endif /* _LEM_H_DEFINED_ */

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