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sys/dev/em/e1000_80003es2lan.c
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1 /******************************************************************************* 2 3 Copyright (c) 2001-2007, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 *******************************************************************************/ 33 /* $FreeBSD$ */ 34 35 /* 36 * e1000_80003es2lan 37 */ 38 39 #include "e1000_api.h" 40 #include "e1000_80003es2lan.h" 41 42 void e1000_init_function_pointers_80003es2lan(struct e1000_hw *hw); 43 44 STATIC s32 e1000_init_phy_params_80003es2lan(struct e1000_hw *hw); 45 STATIC s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw); 46 STATIC s32 e1000_init_mac_params_80003es2lan(struct e1000_hw *hw); 47 STATIC s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw); 48 STATIC void e1000_release_phy_80003es2lan(struct e1000_hw *hw); 49 STATIC s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw); 50 STATIC void e1000_release_nvm_80003es2lan(struct e1000_hw *hw); 51 STATIC s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw, 52 u32 offset, 53 u16 *data); 54 STATIC s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw, 55 u32 offset, 56 u16 data); 57 STATIC s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset, 58 u16 words, u16 *data); 59 STATIC s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw); 60 STATIC s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw); 61 STATIC s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw); 62 STATIC s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed, 63 u16 *duplex); 64 STATIC s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw); 65 STATIC s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw); 66 STATIC s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw); 67 STATIC void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw); 68 static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask); 69 static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex); 70 static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw); 71 static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw); 72 static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw); 73 static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask); 74 75 /* 76 * A table for the GG82563 cable length where the range is defined 77 * with a lower bound at "index" and the upper bound at 78 * "index + 5". 79 */ 80 static const u16 e1000_gg82563_cable_length_table[] = 81 { 0, 60, 115, 150, 150, 60, 115, 150, 180, 180, 0xFF }; 82 #define GG82563_CABLE_LENGTH_TABLE_SIZE \ 83 (sizeof(e1000_gg82563_cable_length_table) / \ 84 sizeof(e1000_gg82563_cable_length_table[0])) 85 86 /** 87 * e1000_init_phy_params_80003es2lan - Init ESB2 PHY func ptrs. 88 * @hw: pointer to the HW structure 89 * 90 * This is a function pointer entry point called by the api module. 91 **/ 92 STATIC s32 e1000_init_phy_params_80003es2lan(struct e1000_hw *hw) 93 { 94 struct e1000_phy_info *phy = &hw->phy; 95 struct e1000_functions *func = &hw->func; 96 s32 ret_val = E1000_SUCCESS; 97 98 DEBUGFUNC("e1000_init_phy_params_80003es2lan"); 99 100 if (hw->phy.media_type != e1000_media_type_copper) { 101 phy->type = e1000_phy_none; 102 goto out; 103 } 104 105 phy->addr = 1; 106 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 107 phy->reset_delay_us = 100; 108 phy->type = e1000_phy_gg82563; 109 110 func->acquire_phy = e1000_acquire_phy_80003es2lan; 111 func->check_polarity = e1000_check_polarity_m88; 112 func->check_reset_block = e1000_check_reset_block_generic; 113 func->commit_phy = e1000_phy_sw_reset_generic; 114 func->get_cfg_done = e1000_get_cfg_done_80003es2lan; 115 func->get_phy_info = e1000_get_phy_info_m88; 116 func->release_phy = e1000_release_phy_80003es2lan; 117 func->reset_phy = e1000_phy_hw_reset_generic; 118 func->set_d3_lplu_state = e1000_set_d3_lplu_state_generic; 119 120 func->force_speed_duplex = e1000_phy_force_speed_duplex_80003es2lan; 121 func->get_cable_length = e1000_get_cable_length_80003es2lan; 122 func->read_phy_reg = e1000_read_phy_reg_gg82563_80003es2lan; 123 func->write_phy_reg = e1000_write_phy_reg_gg82563_80003es2lan; 124 125 /* This can only be done after all function pointers are setup. */ 126 ret_val = e1000_get_phy_id(hw); 127 128 /* Verify phy id */ 129 if (phy->id != GG82563_E_PHY_ID) { 130 ret_val = -E1000_ERR_PHY; 131 goto out; 132 } 133 134 out: 135 return ret_val; 136 } 137 138 /** 139 * e1000_init_nvm_params_80003es2lan - Init ESB2 NVM func ptrs. 140 * @hw: pointer to the HW structure 141 * 142 * This is a function pointer entry point called by the api module. 143 **/ 144 STATIC s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw) 145 { 146 struct e1000_nvm_info *nvm = &hw->nvm; 147 struct e1000_functions *func = &hw->func; 148 u32 eecd = E1000_READ_REG(hw, E1000_EECD); 149 u16 size; 150 151 DEBUGFUNC("e1000_init_nvm_params_80003es2lan"); 152 153 nvm->opcode_bits = 8; 154 nvm->delay_usec = 1; 155 switch (nvm->override) { 156 case e1000_nvm_override_spi_large: 157 nvm->page_size = 32; 158 nvm->address_bits = 16; 159 break; 160 case e1000_nvm_override_spi_small: 161 nvm->page_size = 8; 162 nvm->address_bits = 8; 163 break; 164 default: 165 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8; 166 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8; 167 break; 168 } 169 170 nvm->type = e1000_nvm_eeprom_spi; 171 172 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> 173 E1000_EECD_SIZE_EX_SHIFT); 174 175 /* 176 * Added to a constant, "size" becomes the left-shift value 177 * for setting word_size. 178 */ 179 size += NVM_WORD_SIZE_BASE_SHIFT; 180 nvm->word_size = 1 << size; 181 182 /* Function Pointers */ 183 func->acquire_nvm = e1000_acquire_nvm_80003es2lan; 184 func->read_nvm = e1000_read_nvm_eerd; 185 func->release_nvm = e1000_release_nvm_80003es2lan; 186 func->update_nvm = e1000_update_nvm_checksum_generic; 187 func->valid_led_default = e1000_valid_led_default_generic; 188 func->validate_nvm = e1000_validate_nvm_checksum_generic; 189 func->write_nvm = e1000_write_nvm_80003es2lan; 190 191 return E1000_SUCCESS; 192 } 193 194 /** 195 * e1000_init_mac_params_80003es2lan - Init ESB2 MAC func ptrs. 196 * @hw: pointer to the HW structure 197 * 198 * This is a function pointer entry point called by the api module. 199 **/ 200 STATIC s32 e1000_init_mac_params_80003es2lan(struct e1000_hw *hw) 201 { 202 struct e1000_mac_info *mac = &hw->mac; 203 struct e1000_functions *func = &hw->func; 204 s32 ret_val = E1000_SUCCESS; 205 206 DEBUGFUNC("e1000_init_mac_params_80003es2lan"); 207 208 /* Set media type */ 209 switch (hw->device_id) { 210 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT: 211 hw->phy.media_type = e1000_media_type_internal_serdes; 212 break; 213 default: 214 hw->phy.media_type = e1000_media_type_copper; 215 break; 216 } 217 218 /* Set mta register count */ 219 mac->mta_reg_count = 128; 220 /* Set rar entry count */ 221 mac->rar_entry_count = E1000_RAR_ENTRIES; 222 /* Set if part includes ASF firmware */ 223 mac->asf_firmware_present = TRUE; 224 /* Set if manageability features are enabled. */ 225 mac->arc_subsystem_valid = 226 (E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK) 227 ? TRUE : FALSE; 228 229 /* Function pointers */ 230 231 /* bus type/speed/width */ 232 func->get_bus_info = e1000_get_bus_info_pcie_generic; 233 /* reset */ 234 func->reset_hw = e1000_reset_hw_80003es2lan; 235 /* hw initialization */ 236 func->init_hw = e1000_init_hw_80003es2lan; 237 /* link setup */ 238 func->setup_link = e1000_setup_link_generic; 239 /* physical interface link setup */ 240 func->setup_physical_interface = 241 (hw->phy.media_type == e1000_media_type_copper) 242 ? e1000_setup_copper_link_80003es2lan 243 : e1000_setup_fiber_serdes_link_generic; 244 /* check for link */ 245 switch (hw->phy.media_type) { 246 case e1000_media_type_copper: 247 func->check_for_link = e1000_check_for_copper_link_generic; 248 break; 249 case e1000_media_type_fiber: 250 func->check_for_link = e1000_check_for_fiber_link_generic; 251 break; 252 case e1000_media_type_internal_serdes: 253 func->check_for_link = e1000_check_for_serdes_link_generic; 254 break; 255 default: 256 ret_val = -E1000_ERR_CONFIG; 257 goto out; 258 break; 259 } 260 /* check management mode */ 261 func->check_mng_mode = e1000_check_mng_mode_generic; 262 /* multicast address update */ 263 func->update_mc_addr_list = e1000_update_mc_addr_list_generic; 264 /* writing VFTA */ 265 func->write_vfta = e1000_write_vfta_generic; 266 /* clearing VFTA */ 267 func->clear_vfta = e1000_clear_vfta_generic; 268 /* setting MTA */ 269 func->mta_set = e1000_mta_set_generic; 270 /* blink LED */ 271 func->blink_led = e1000_blink_led_generic; 272 /* setup LED */ 273 func->setup_led = e1000_setup_led_generic; 274 /* cleanup LED */ 275 func->cleanup_led = e1000_cleanup_led_generic; 276 /* turn on/off LED */ 277 func->led_on = e1000_led_on_generic; 278 func->led_off = e1000_led_off_generic; 279 /* remove device */ 280 func->remove_device = e1000_remove_device_generic; 281 /* clear hardware counters */ 282 func->clear_hw_cntrs = e1000_clear_hw_cntrs_80003es2lan; 283 /* link info */ 284 func->get_link_up_info = e1000_get_link_up_info_80003es2lan; 285 286 out: 287 return ret_val; 288 } 289 290 /** 291 * e1000_init_function_pointers_80003es2lan - Init ESB2 func ptrs. 292 * @hw: pointer to the HW structure 293 * 294 * The only function explicitly called by the api module to initialize 295 * all function pointers and parameters. 296 **/ 297 void e1000_init_function_pointers_80003es2lan(struct e1000_hw *hw) 298 { 299 DEBUGFUNC("e1000_init_function_pointers_80003es2lan"); 300 301 hw->func.init_mac_params = e1000_init_mac_params_80003es2lan; 302 hw->func.init_nvm_params = e1000_init_nvm_params_80003es2lan; 303 hw->func.init_phy_params = e1000_init_phy_params_80003es2lan; 304 } 305 306 /** 307 * e1000_acquire_phy_80003es2lan - Acquire rights to access PHY 308 * @hw: pointer to the HW structure 309 * 310 * A wrapper to acquire access rights to the correct PHY. This is a 311 * function pointer entry point called by the api module. 312 **/ 313 STATIC s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw) 314 { 315 u16 mask; 316 317 DEBUGFUNC("e1000_acquire_phy_80003es2lan"); 318 319 mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM; 320 321 return e1000_acquire_swfw_sync_80003es2lan(hw, mask); 322 } 323 324 /** 325 * e1000_release_phy_80003es2lan - Release rights to access PHY 326 * @hw: pointer to the HW structure 327 * 328 * A wrapper to release access rights to the correct PHY. This is a 329 * function pointer entry point called by the api module. 330 **/ 331 STATIC void e1000_release_phy_80003es2lan(struct e1000_hw *hw) 332 { 333 u16 mask; 334 335 DEBUGFUNC("e1000_release_phy_80003es2lan"); 336 337 mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM; 338 e1000_release_swfw_sync_80003es2lan(hw, mask); 339 } 340 341 /** 342 * e1000_acquire_nvm_80003es2lan - Acquire rights to access NVM 343 * @hw: pointer to the HW structure 344 * 345 * Acquire the semaphore to access the EEPROM. This is a function 346 * pointer entry point called by the api module. 347 **/ 348 STATIC s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw) 349 { 350 s32 ret_val; 351 352 DEBUGFUNC("e1000_acquire_nvm_80003es2lan"); 353 354 ret_val = e1000_acquire_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM); 355 if (ret_val) 356 goto out; 357 358 ret_val = e1000_acquire_nvm_generic(hw); 359 360 if (ret_val) 361 e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM); 362 363 out: 364 return ret_val; 365 } 366 367 /** 368 * e1000_release_nvm_80003es2lan - Relinquish rights to access NVM 369 * @hw: pointer to the HW structure 370 * 371 * Release the semaphore used to access the EEPROM. This is a 372 * function pointer entry point called by the api module. 373 **/ 374 STATIC void e1000_release_nvm_80003es2lan(struct e1000_hw *hw) 375 { 376 DEBUGFUNC("e1000_release_nvm_80003es2lan"); 377 378 e1000_release_nvm_generic(hw); 379 e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM); 380 } 381 382 /** 383 * e1000_acquire_swfw_sync_80003es2lan - Acquire SW/FW semaphore 384 * @hw: pointer to the HW structure 385 * @mask: specifies which semaphore to acquire 386 * 387 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask 388 * will also specify which port we're acquiring the lock for. 389 **/ 390 static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask) 391 { 392 u32 swfw_sync; 393 u32 swmask = mask; 394 u32 fwmask = mask << 16; 395 s32 ret_val = E1000_SUCCESS; 396 s32 i = 0, timeout = 200; 397 398 DEBUGFUNC("e1000_acquire_swfw_sync_80003es2lan"); 399 400 while (i < timeout) { 401 if (e1000_get_hw_semaphore_generic(hw)) { 402 ret_val = -E1000_ERR_SWFW_SYNC; 403 goto out; 404 } 405 406 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC); 407 if (!(swfw_sync & (fwmask | swmask))) 408 break; 409 410 /* 411 * Firmware currently using resource (fwmask) 412 * or other software thread using resource (swmask) 413 */ 414 e1000_put_hw_semaphore_generic(hw); 415 msec_delay_irq(5); 416 i++; 417 } 418 419 if (i == timeout) { 420 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n"); 421 ret_val = -E1000_ERR_SWFW_SYNC; 422 goto out; 423 } 424 425 swfw_sync |= swmask; 426 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync); 427 428 e1000_put_hw_semaphore_generic(hw); 429 430 out: 431 return ret_val; 432 } 433 434 /** 435 * e1000_release_swfw_sync_80003es2lan - Release SW/FW semaphore 436 * @hw: pointer to the HW structure 437 * @mask: specifies which semaphore to acquire 438 * 439 * Release the SW/FW semaphore used to access the PHY or NVM. The mask 440 * will also specify which port we're releasing the lock for. 441 **/ 442 static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask) 443 { 444 u32 swfw_sync; 445 446 DEBUGFUNC("e1000_release_swfw_sync_80003es2lan"); 447 448 while (e1000_get_hw_semaphore_generic(hw) != E1000_SUCCESS); 449 /* Empty */ 450 451 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC); 452 swfw_sync &= ~mask; 453 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync); 454 455 e1000_put_hw_semaphore_generic(hw); 456 } 457 458 /** 459 * e1000_read_phy_reg_gg82563_80003es2lan - Read GG82563 PHY register 460 * @hw: pointer to the HW structure 461 * @offset: offset of the register to read 462 * @data: pointer to the data returned from the operation 463 * 464 * Read the GG82563 PHY register. This is a function pointer entry 465 * point called by the api module. 466 **/ 467 STATIC s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw, 468 u32 offset, u16 *data) 469 { 470 s32 ret_val; 471 u32 page_select; 472 u16 temp; 473 474 DEBUGFUNC("e1000_read_phy_reg_gg82563_80003es2lan"); 475 476 /* Select Configuration Page */ 477 if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) { 478 page_select = GG82563_PHY_PAGE_SELECT; 479 } else { 480 /* 481 * Use Alternative Page Select register to access 482 * registers 30 and 31 483 */ 484 page_select = GG82563_PHY_PAGE_SELECT_ALT; 485 } 486 487 temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT); 488 ret_val = e1000_write_phy_reg_m88(hw, page_select, temp); 489 if (ret_val) 490 goto out; 491 492 /* 493 * The "ready" bit in the MDIC register may be incorrectly set 494 * before the device has completed the "Page Select" MDI 495 * transaction. So we wait 200us after each MDI command... 496 */ 497 usec_delay(200); 498 499 /* ...and verify the command was successful. */ 500 ret_val = e1000_read_phy_reg_m88(hw, page_select, &temp); 501 502 if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) { 503 ret_val = -E1000_ERR_PHY; 504 goto out; 505 } 506 507 usec_delay(200); 508 509 ret_val = e1000_read_phy_reg_m88(hw, 510 MAX_PHY_REG_ADDRESS & offset, 511 data); 512 513 usec_delay(200); 514 515 out: 516 return ret_val; 517 } 518 519 /** 520 * e1000_write_phy_reg_gg82563_80003es2lan - Write GG82563 PHY register 521 * @hw: pointer to the HW structure 522 * @offset: offset of the register to read 523 * @data: value to write to the register 524 * 525 * Write to the GG82563 PHY register. This is a function pointer entry 526 * point called by the api module. 527 **/ 528 STATIC s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw, 529 u32 offset, u16 data) 530 { 531 s32 ret_val; 532 u32 page_select; 533 u16 temp; 534 535 DEBUGFUNC("e1000_write_phy_reg_gg82563_80003es2lan"); 536 537 /* Select Configuration Page */ 538 if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) { 539 page_select = GG82563_PHY_PAGE_SELECT; 540 } else { 541 /* 542 * Use Alternative Page Select register to access 543 * registers 30 and 31 544 */ 545 page_select = GG82563_PHY_PAGE_SELECT_ALT; 546 } 547 548 temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT); 549 ret_val = e1000_write_phy_reg_m88(hw, page_select, temp); 550 if (ret_val) 551 goto out; 552 553 554 /* 555 * The "ready" bit in the MDIC register may be incorrectly set 556 * before the device has completed the "Page Select" MDI 557 * transaction. So we wait 200us after each MDI command... 558 */ 559 usec_delay(200); 560 561 /* ...and verify the command was successful. */ 562 ret_val = e1000_read_phy_reg_m88(hw, page_select, &temp); 563 564 if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) { 565 ret_val = -E1000_ERR_PHY; 566 goto out; 567 } 568 569 usec_delay(200); 570 571 ret_val = e1000_write_phy_reg_m88(hw, 572 MAX_PHY_REG_ADDRESS & offset, 573 data); 574 575 usec_delay(200); 576 577 out: 578 return ret_val; 579 } 580 581 /** 582 * e1000_write_nvm_80003es2lan - Write to ESB2 NVM 583 * @hw: pointer to the HW structure 584 * @offset: offset of the register to read 585 * @words: number of words to write 586 * @data: buffer of data to write to the NVM 587 * 588 * Write "words" of data to the ESB2 NVM. This is a function 589 * pointer entry point called by the api module. 590 **/ 591 STATIC s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset, 592 u16 words, u16 *data) 593 { 594 DEBUGFUNC("e1000_write_nvm_80003es2lan"); 595 596 return e1000_write_nvm_spi(hw, offset, words, data); 597 } 598 599 /** 600 * e1000_get_cfg_done_80003es2lan - Wait for configuration to complete 601 * @hw: pointer to the HW structure 602 * 603 * Wait a specific amount of time for manageability processes to complete. 604 * This is a function pointer entry point called by the phy module. 605 **/ 606 STATIC s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw) 607 { 608 s32 timeout = PHY_CFG_TIMEOUT; 609 s32 ret_val = E1000_SUCCESS; 610 u32 mask = E1000_NVM_CFG_DONE_PORT_0; 611 612 DEBUGFUNC("e1000_get_cfg_done_80003es2lan"); 613 614 if (hw->bus.func == 1) 615 mask = E1000_NVM_CFG_DONE_PORT_1; 616 617 while (timeout) { 618 if (E1000_READ_REG(hw, E1000_EEMNGCTL) & mask) 619 break; 620 msec_delay(1); 621 timeout--; 622 } 623 if (!timeout) { 624 DEBUGOUT("MNG configuration cycle has not completed.\n"); 625 ret_val = -E1000_ERR_RESET; 626 goto out; 627 } 628 629 out: 630 return ret_val; 631 } 632 633 /** 634 * e1000_phy_force_speed_duplex_80003es2lan - Force PHY speed and duplex 635 * @hw: pointer to the HW structure 636 * 637 * Force the speed and duplex settings onto the PHY. This is a 638 * function pointer entry point called by the phy module. 639 **/ 640 STATIC s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw) 641 { 642 s32 ret_val; 643 u16 phy_data; 644 bool link; 645 646 DEBUGFUNC("e1000_phy_force_speed_duplex_80003es2lan"); 647 648 /* 649 * Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI 650 * forced whenever speed and duplex are forced. 651 */ 652 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 653 if (ret_val) 654 goto out; 655 656 phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_AUTO; 657 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL, phy_data); 658 if (ret_val) 659 goto out; 660 661 DEBUGOUT1("GG82563 PSCR: %X\n", phy_data); 662 663 ret_val = e1000_read_phy_reg(hw, PHY_CONTROL, &phy_data); 664 if (ret_val) 665 goto out; 666 667 e1000_phy_force_speed_duplex_setup(hw, &phy_data); 668 669 /* Reset the phy to commit changes. */ 670 phy_data |= MII_CR_RESET; 671 672 ret_val = e1000_write_phy_reg(hw, PHY_CONTROL, phy_data); 673 if (ret_val) 674 goto out; 675 676 usec_delay(1); 677 678 if (hw->phy.autoneg_wait_to_complete) { 679 DEBUGOUT("Waiting for forced speed/duplex link " 680 "on GG82563 phy.\n"); 681 682 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 683 100000, &link); 684 if (ret_val) 685 goto out; 686 687 if (!link) { 688 /* 689 * We didn't get link. 690 * Reset the DSP and cross our fingers. 691 */ 692 ret_val = e1000_phy_reset_dsp_generic(hw); 693 if (ret_val) 694 goto out; 695 } 696 697 /* Try once more */ 698 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 699 100000, &link); 700 if (ret_val) 701 goto out; 702 } 703 704 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data); 705 if (ret_val) 706 goto out; 707 708 /* 709 * Resetting the phy means we need to verify the TX_CLK corresponds 710 * to the link speed. 10Mbps -> 2.5MHz, else 25MHz. 711 */ 712 phy_data &= ~GG82563_MSCR_TX_CLK_MASK; 713 if (hw->mac.forced_speed_duplex & E1000_ALL_10_SPEED) 714 phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5; 715 else 716 phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25; 717 718 /* 719 * In addition, we must re-enable CRS on Tx for both half and full 720 * duplex. 721 */ 722 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX; 723 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, phy_data); 724 725 out: 726 return ret_val; 727 } 728 729 /** 730 * e1000_get_cable_length_80003es2lan - Set approximate cable length 731 * @hw: pointer to the HW structure 732 * 733 * Find the approximate cable length as measured by the GG82563 PHY. 734 * This is a function pointer entry point called by the phy module. 735 **/ 736 STATIC s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw) 737 { 738 struct e1000_phy_info *phy = &hw->phy; 739 s32 ret_val; 740 u16 phy_data, index; 741 742 DEBUGFUNC("e1000_get_cable_length_80003es2lan"); 743 744 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_DSP_DISTANCE, &phy_data); 745 if (ret_val) 746 goto out; 747 748 index = phy_data & GG82563_DSPD_CABLE_LENGTH; 749 phy->min_cable_length = e1000_gg82563_cable_length_table[index]; 750 phy->max_cable_length = e1000_gg82563_cable_length_table[index+5]; 751 752 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; 753 754 out: 755 return ret_val; 756 } 757 758 /** 759 * e1000_get_link_up_info_80003es2lan - Report speed and duplex 760 * @hw: pointer to the HW structure 761 * @speed: pointer to speed buffer 762 * @duplex: pointer to duplex buffer 763 * 764 * Retrieve the current speed and duplex configuration. 765 * This is a function pointer entry point called by the api module. 766 **/ 767 STATIC s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed, 768 u16 *duplex) 769 { 770 s32 ret_val; 771 772 DEBUGFUNC("e1000_get_link_up_info_80003es2lan"); 773 774 if (hw->phy.media_type == e1000_media_type_copper) { 775 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, 776 speed, 777 duplex); 778 if (ret_val) 779 goto out; 780 if (*speed == SPEED_1000) 781 ret_val = e1000_cfg_kmrn_1000_80003es2lan(hw); 782 else 783 ret_val = e1000_cfg_kmrn_10_100_80003es2lan(hw, 784 *duplex); 785 } else { 786 ret_val = e1000_get_speed_and_duplex_fiber_serdes_generic(hw, 787 speed, 788 duplex); 789 } 790 791 out: 792 return ret_val; 793 } 794 795 /** 796 * e1000_reset_hw_80003es2lan - Reset the ESB2 controller 797 * @hw: pointer to the HW structure 798 * 799 * Perform a global reset to the ESB2 controller. 800 * This is a function pointer entry point called by the api module. 801 **/ 802 STATIC s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw) 803 { 804 u32 ctrl, icr; 805 s32 ret_val; 806 807 DEBUGFUNC("e1000_reset_hw_80003es2lan"); 808 809 /* 810 * Prevent the PCI-E bus from sticking if there is no TLP connection 811 * on the last TLP read/write transaction when MAC is reset. 812 */ 813 ret_val = e1000_disable_pcie_master_generic(hw); 814 if (ret_val) { 815 DEBUGOUT("PCI-E Master disable polling has failed.\n"); 816 } 817 818 DEBUGOUT("Masking off all interrupts\n"); 819 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 820 821 E1000_WRITE_REG(hw, E1000_RCTL, 0); 822 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); 823 E1000_WRITE_FLUSH(hw); 824 825 msec_delay(10); 826 827 ctrl = E1000_READ_REG(hw, E1000_CTRL); 828 829 DEBUGOUT("Issuing a global reset to MAC\n"); 830 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); 831 832 ret_val = e1000_get_auto_rd_done_generic(hw); 833 if (ret_val) 834 /* We don't want to continue accessing MAC registers. */ 835 goto out; 836 837 /* Clear any pending interrupt events. */ 838 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 839 icr = E1000_READ_REG(hw, E1000_ICR); 840 841 out: 842 return ret_val; 843 } 844 845 /** 846 * e1000_init_hw_80003es2lan - Initialize the ESB2 controller 847 * @hw: pointer to the HW structure 848 * 849 * Initialize the hw bits, LED, VFTA, MTA, link and hw counters. 850 * This is a function pointer entry point called by the api module. 851 **/ 852 STATIC s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw) 853 { 854 struct e1000_mac_info *mac = &hw->mac; 855 u32 reg_data; 856 s32 ret_val; 857 u16 i; 858 859 DEBUGFUNC("e1000_init_hw_80003es2lan"); 860 861 e1000_initialize_hw_bits_80003es2lan(hw); 862 863 /* Initialize identification LED */ 864 ret_val = e1000_id_led_init_generic(hw); 865 if (ret_val) { 866 DEBUGOUT("Error initializing identification LED\n"); 867 /* This is not fatal and we should not stop init due to this */ 868 } 869 870 /* Disabling VLAN filtering */ 871 DEBUGOUT("Initializing the IEEE VLAN\n"); 872 e1000_clear_vfta(hw); 873 874 /* Setup the receive address. */ 875 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count); 876 877 /* Zero out the Multicast HASH table */ 878 DEBUGOUT("Zeroing the MTA\n"); 879 for (i = 0; i < mac->mta_reg_count; i++) 880 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 881 882 /* Setup link and flow control */ 883 ret_val = e1000_setup_link(hw); 884 885 /* Set the transmit descriptor write-back policy */ 886 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(0)); 887 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | 888 E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC; 889 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg_data); 890 891 /* ...for both queues. */ 892 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(1)); 893 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | 894 E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC; 895 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg_data); 896 897 /* Enable retransmit on late collisions */ 898 reg_data = E1000_READ_REG(hw, E1000_TCTL); 899 reg_data |= E1000_TCTL_RTLC; 900 E1000_WRITE_REG(hw, E1000_TCTL, reg_data); 901 902 /* Configure Gigabit Carry Extend Padding */ 903 reg_data = E1000_READ_REG(hw, E1000_TCTL_EXT); 904 reg_data &= ~E1000_TCTL_EXT_GCEX_MASK; 905 reg_data |= DEFAULT_TCTL_EXT_GCEX_80003ES2LAN; 906 E1000_WRITE_REG(hw, E1000_TCTL_EXT, reg_data); 907 908 /* Configure Transmit Inter-Packet Gap */ 909 reg_data = E1000_READ_REG(hw, E1000_TIPG); 910 reg_data &= ~E1000_TIPG_IPGT_MASK; 911 reg_data |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN; 912 E1000_WRITE_REG(hw, E1000_TIPG, reg_data); 913 914 reg_data = E1000_READ_REG_ARRAY(hw, E1000_FFLT, 0x0001); 915 reg_data &= ~0x00100000; 916 E1000_WRITE_REG_ARRAY(hw, E1000_FFLT, 0x0001, reg_data); 917 918 /* 919 * Clear all of the statistics registers (clear on read). It is 920 * important that we do this after we have tried to establish link 921 * because the symbol error count will increment wildly if there 922 * is no link. 923 */ 924 e1000_clear_hw_cntrs_80003es2lan(hw); 925 926 return ret_val; 927 } 928 929 /** 930 * e1000_initialize_hw_bits_80003es2lan - Init hw bits of ESB2 931 * @hw: pointer to the HW structure 932 * 933 * Initializes required hardware-dependent bits needed for normal operation. 934 **/ 935 static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw) 936 { 937 u32 reg; 938 939 DEBUGFUNC("e1000_initialize_hw_bits_80003es2lan"); 940 941 if (hw->mac.disable_hw_init_bits) 942 goto out; 943 944 /* Transmit Descriptor Control 0 */ 945 reg = E1000_READ_REG(hw, E1000_TXDCTL(0)); 946 reg |= (1 << 22); 947 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg); 948 949 /* Transmit Descriptor Control 1 */ 950 reg = E1000_READ_REG(hw, E1000_TXDCTL(1)); 951 reg |= (1 << 22); 952 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg); 953 954 /* Transmit Arbitration Control 0 */ 955 reg = E1000_READ_REG(hw, E1000_TARC(0)); 956 reg &= ~(0xF << 27); /* 30:27 */ 957 if (hw->phy.media_type != e1000_media_type_copper) 958 reg &= ~(1 << 20); 959 E1000_WRITE_REG(hw, E1000_TARC(0), reg); 960 961 /* Transmit Arbitration Control 1 */ 962 reg = E1000_READ_REG(hw, E1000_TARC(1)); 963 if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR) 964 reg &= ~(1 << 28); 965 else 966 reg |= (1 << 28); 967 E1000_WRITE_REG(hw, E1000_TARC(1), reg); 968 969 out: 970 return; 971 } 972 973 /** 974 * e1000_copper_link_setup_gg82563_80003es2lan - Configure GG82563 Link 975 * @hw: pointer to the HW structure 976 * 977 * Setup some GG82563 PHY registers for obtaining link 978 **/ 979 static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw) 980 { 981 struct e1000_phy_info *phy = &hw->phy; 982 s32 ret_val; 983 u32 ctrl_ext; 984 u16 data; 985 986 DEBUGFUNC("e1000_copper_link_setup_gg82563_80003es2lan"); 987 988 if (!phy->reset_disable) { 989 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, 990 &data); 991 if (ret_val) 992 goto out; 993 994 data |= GG82563_MSCR_ASSERT_CRS_ON_TX; 995 /* Use 25MHz for both link down and 1000Base-T for Tx clock. */ 996 data |= GG82563_MSCR_TX_CLK_1000MBPS_25; 997 998 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, 999 data); 1000 if (ret_val) 1001 goto out; 1002 1003 /* 1004 * Options: 1005 * MDI/MDI-X = 0 (default) 1006 * 0 - Auto for all speeds 1007 * 1 - MDI mode 1008 * 2 - MDI-X mode 1009 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) 1010 */ 1011 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL, &data); 1012 if (ret_val) 1013 goto out; 1014 1015 data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK; 1016 1017 switch (phy->mdix) { 1018 case 1: 1019 data |= GG82563_PSCR_CROSSOVER_MODE_MDI; 1020 break; 1021 case 2: 1022 data |= GG82563_PSCR_CROSSOVER_MODE_MDIX; 1023 break; 1024 case 0: 1025 default: 1026 data |= GG82563_PSCR_CROSSOVER_MODE_AUTO; 1027 break; 1028 } 1029 1030 /* 1031 * Options: 1032 * disable_polarity_correction = 0 (default) 1033 * Automatic Correction for Reversed Cable Polarity 1034 * 0 - Disabled 1035 * 1 - Enabled 1036 */ 1037 data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE; 1038 if (phy->disable_polarity_correction) 1039 data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE; 1040 1041 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL, data); 1042 if (ret_val) 1043 goto out; 1044 1045 /* SW Reset the PHY so all changes take effect */ 1046 ret_val = e1000_phy_commit(hw); 1047 if (ret_val) { 1048 DEBUGOUT("Error Resetting the PHY\n"); 1049 goto out; 1050 } 1051 1052 } 1053 1054 /* Bypass RX and TX FIFO's */ 1055 ret_val = e1000_write_kmrn_reg(hw, 1056 E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL, 1057 E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS | 1058 E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS); 1059 if (ret_val) 1060 goto out; 1061 1062 ret_val = e1000_read_kmrn_reg(hw, 1063 E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE, 1064 &data); 1065 if (ret_val) 1066 goto out; 1067 data |= E1000_KMRNCTRLSTA_OPMODE_E_IDLE; 1068 ret_val = e1000_write_kmrn_reg(hw, 1069 E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE, 1070 data); 1071 if (ret_val) 1072 goto out; 1073 1074 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, &data); 1075 if (ret_val) 1076 goto out; 1077 1078 data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG; 1079 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, data); 1080 if (ret_val) 1081 goto out; 1082 1083 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 1084 ctrl_ext &= ~(E1000_CTRL_EXT_LINK_MODE_MASK); 1085 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 1086 1087 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL, &data); 1088 if (ret_val) 1089 goto out; 1090 1091 /* 1092 * Do not init these registers when the HW is in IAMT mode, since the 1093 * firmware will have already initialized them. We only initialize 1094 * them if the HW is not in IAMT mode. 1095 */ 1096 if (!(e1000_check_mng_mode(hw))) { 1097 /* Enable Electrical Idle on the PHY */ 1098 data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE; 1099 ret_val = e1000_write_phy_reg(hw, 1100 GG82563_PHY_PWR_MGMT_CTRL, 1101 data); 1102 if (ret_val) 1103 goto out; 1104 1105 ret_val = e1000_read_phy_reg(hw, 1106 GG82563_PHY_KMRN_MODE_CTRL, 1107 &data); 1108 if (ret_val) 1109 goto out; 1110 1111 data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 1112 ret_val = e1000_write_phy_reg(hw, 1113 GG82563_PHY_KMRN_MODE_CTRL, 1114 data); 1115 1116 if (ret_val) 1117 goto out; 1118 } 1119 1120 /* 1121 * Workaround: Disable padding in Kumeran interface in the MAC 1122 * and in the PHY to avoid CRC errors. 1123 */ 1124 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_INBAND_CTRL, &data); 1125 if (ret_val) 1126 goto out; 1127 1128 data |= GG82563_ICR_DIS_PADDING; 1129 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_INBAND_CTRL, data); 1130 if (ret_val) 1131 goto out; 1132 1133 out: 1134 return ret_val; 1135 } 1136 1137 /** 1138 * e1000_setup_copper_link_80003es2lan - Setup Copper Link for ESB2 1139 * @hw: pointer to the HW structure 1140 * 1141 * Essentially a wrapper for setting up all things "copper" related. 1142 * This is a function pointer entry point called by the mac module. 1143 **/ 1144 STATIC s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw) 1145 { 1146 u32 ctrl; 1147 s32 ret_val; 1148 u16 reg_data; 1149 1150 DEBUGFUNC("e1000_setup_copper_link_80003es2lan"); 1151 1152 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1153 ctrl |= E1000_CTRL_SLU; 1154 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1155 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1156 1157 /* 1158 * Set the mac to wait the maximum time between each 1159 * iteration and increase the max iterations when 1160 * polling the phy; this fixes erroneous timeouts at 10Mbps. 1161 */ 1162 ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF); 1163 if (ret_val) 1164 goto out; 1165 ret_val = e1000_read_kmrn_reg(hw, GG82563_REG(0x34, 9), ®_data); 1166 if (ret_val) 1167 goto out; 1168 reg_data |= 0x3F; 1169 ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 9), reg_data); 1170 if (ret_val) 1171 goto out; 1172 ret_val = e1000_read_kmrn_reg(hw, 1173 E1000_KMRNCTRLSTA_OFFSET_INB_CTRL, 1174 ®_data); 1175 if (ret_val) 1176 goto out; 1177 reg_data |= E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING; 1178 ret_val = e1000_write_kmrn_reg(hw, 1179 E1000_KMRNCTRLSTA_OFFSET_INB_CTRL, 1180 reg_data); 1181 if (ret_val) 1182 goto out; 1183 1184 ret_val = e1000_copper_link_setup_gg82563_80003es2lan(hw); 1185 if (ret_val) 1186 goto out; 1187 1188 ret_val = e1000_setup_copper_link_generic(hw); 1189 1190 out: 1191 return ret_val; 1192 } 1193 1194 /** 1195 * e1000_cfg_kmrn_10_100_80003es2lan - Apply "quirks" for 10/100 operation 1196 * @hw: pointer to the HW structure 1197 * @duplex: current duplex setting 1198 * 1199 * Configure the KMRN interface by applying last minute quirks for 1200 * 10/100 operation. 1201 **/ 1202 static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex) 1203 { 1204 s32 ret_val = E1000_SUCCESS; 1205 u32 tipg; 1206 u32 i = 0; 1207 u16 reg_data, reg_data2; 1208 1209 DEBUGFUNC("e1000_configure_kmrn_for_10_100"); 1210 1211 reg_data = E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT; 1212 ret_val = e1000_write_kmrn_reg(hw, 1213 E1000_KMRNCTRLSTA_OFFSET_HD_CTRL, 1214 reg_data); 1215 if (ret_val) 1216 goto out; 1217 1218 /* Configure Transmit Inter-Packet Gap */ 1219 tipg = E1000_READ_REG(hw, E1000_TIPG); 1220 tipg &= ~E1000_TIPG_IPGT_MASK; 1221 tipg |= DEFAULT_TIPG_IPGT_10_100_80003ES2LAN; 1222 E1000_WRITE_REG(hw, E1000_TIPG, tipg); 1223 1224 1225 do { 1226 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, 1227 ®_data); 1228 if (ret_val) 1229 goto out; 1230 1231 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, 1232 ®_data2); 1233 if (ret_val) 1234 goto out; 1235 i++; 1236 } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY)); 1237 1238 if (duplex == HALF_DUPLEX) 1239 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER; 1240 else 1241 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 1242 1243 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); 1244 1245 out: 1246 return ret_val; 1247 } 1248 1249 /** 1250 * e1000_cfg_kmrn_1000_80003es2lan - Apply "quirks" for gigabit operation 1251 * @hw: pointer to the HW structure 1252 * 1253 * Configure the KMRN interface by applying last minute quirks for 1254 * gigabit operation. 1255 **/ 1256 static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw) 1257 { 1258 s32 ret_val = E1000_SUCCESS; 1259 u16 reg_data, reg_data2; 1260 u32 tipg; 1261 u32 i = 0; 1262 1263 DEBUGFUNC("e1000_configure_kmrn_for_1000"); 1264 1265 reg_data = E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT; 1266 ret_val = e1000_write_kmrn_reg(hw, 1267 E1000_KMRNCTRLSTA_OFFSET_HD_CTRL, 1268 reg_data); 1269 if (ret_val) 1270 goto out; 1271 1272 /* Configure Transmit Inter-Packet Gap */ 1273 tipg = E1000_READ_REG(hw, E1000_TIPG); 1274 tipg &= ~E1000_TIPG_IPGT_MASK; 1275 tipg |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN; 1276 E1000_WRITE_REG(hw, E1000_TIPG, tipg); 1277 1278 1279 do { 1280 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, 1281 ®_data); 1282 if (ret_val) 1283 goto out; 1284 1285 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, 1286 ®_data2); 1287 if (ret_val) 1288 goto out; 1289 i++; 1290 } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY)); 1291 1292 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 1293 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); 1294 1295 out: 1296 return ret_val; 1297 } 1298 1299 /** 1300 * e1000_clear_hw_cntrs_80003es2lan - Clear device specific hardware counters 1301 * @hw: pointer to the HW structure 1302 * 1303 * Clears the hardware counters by reading the counter registers. 1304 **/ 1305 STATIC void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw) 1306 { 1307 volatile u32 temp; 1308 1309 DEBUGFUNC("e1000_clear_hw_cntrs_80003es2lan"); 1310 1311 e1000_clear_hw_cntrs_base_generic(hw); 1312 1313 temp = E1000_READ_REG(hw, E1000_PRC64); 1314 temp = E1000_READ_REG(hw, E1000_PRC127); 1315 temp = E1000_READ_REG(hw, E1000_PRC255); 1316 temp = E1000_READ_REG(hw, E1000_PRC511); 1317 temp = E1000_READ_REG(hw, E1000_PRC1023); 1318 temp = E1000_READ_REG(hw, E1000_PRC1522); 1319 temp = E1000_READ_REG(hw, E1000_PTC64); 1320 temp = E1000_READ_REG(hw, E1000_PTC127); 1321 temp = E1000_READ_REG(hw, E1000_PTC255); 1322 temp = E1000_READ_REG(hw, E1000_PTC511); 1323 temp = E1000_READ_REG(hw, E1000_PTC1023); 1324 temp = E1000_READ_REG(hw, E1000_PTC1522); 1325 1326 temp = E1000_READ_REG(hw, E1000_ALGNERRC); 1327 temp = E1000_READ_REG(hw, E1000_RXERRC); 1328 temp = E1000_READ_REG(hw, E1000_TNCRS); 1329 temp = E1000_READ_REG(hw, E1000_CEXTERR); 1330 temp = E1000_READ_REG(hw, E1000_TSCTC); 1331 temp = E1000_READ_REG(hw, E1000_TSCTFC); 1332 1333 temp = E1000_READ_REG(hw, E1000_MGTPRC); 1334 temp = E1000_READ_REG(hw, E1000_MGTPDC); 1335 temp = E1000_READ_REG(hw, E1000_MGTPTC); 1336 1337 temp = E1000_READ_REG(hw, E1000_IAC); 1338 temp = E1000_READ_REG(hw, E1000_ICRXOC); 1339 1340 temp = E1000_READ_REG(hw, E1000_ICRXPTC); 1341 temp = E1000_READ_REG(hw, E1000_ICRXATC); 1342 temp = E1000_READ_REG(hw, E1000_ICTXPTC); 1343 temp = E1000_READ_REG(hw, E1000_ICTXATC); 1344 temp = E1000_READ_REG(hw, E1000_ICTXQEC); 1345 temp = E1000_READ_REG(hw, E1000_ICTXQMTC); 1346 temp = E1000_READ_REG(hw, E1000_ICRXDMTC); 1347 }
Cache object: d1d77627cdea21e5ac0907b0e1e59281
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