1 /*******************************************************************************
2
3 Copyright (c) 2001-2007, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
15
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
19
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32 *******************************************************************************/
33 /* $FreeBSD$ */
34
35
36 /* e1000_82541
37 * e1000_82547
38 * e1000_82541_rev_2
39 * e1000_82547_rev_2
40 */
41
42 #include "e1000_api.h"
43 #include "e1000_82541.h"
44
45 void e1000_init_function_pointers_82541(struct e1000_hw *hw);
46
47 STATIC s32 e1000_init_phy_params_82541(struct e1000_hw *hw);
48 STATIC s32 e1000_init_nvm_params_82541(struct e1000_hw *hw);
49 STATIC s32 e1000_init_mac_params_82541(struct e1000_hw *hw);
50 STATIC s32 e1000_reset_hw_82541(struct e1000_hw *hw);
51 STATIC s32 e1000_init_hw_82541(struct e1000_hw *hw);
52 STATIC s32 e1000_get_link_up_info_82541(struct e1000_hw *hw, u16 *speed,
53 u16 *duplex);
54 STATIC s32 e1000_phy_hw_reset_82541(struct e1000_hw *hw);
55 STATIC s32 e1000_setup_copper_link_82541(struct e1000_hw *hw);
56 STATIC s32 e1000_check_for_link_82541(struct e1000_hw *hw);
57 STATIC s32 e1000_get_cable_length_igp_82541(struct e1000_hw *hw);
58 STATIC s32 e1000_set_d3_lplu_state_82541(struct e1000_hw *hw,
59 bool active);
60 STATIC s32 e1000_setup_led_82541(struct e1000_hw *hw);
61 STATIC s32 e1000_cleanup_led_82541(struct e1000_hw *hw);
62 STATIC void e1000_clear_hw_cntrs_82541(struct e1000_hw *hw);
63 static s32 e1000_config_dsp_after_link_change_82541(struct e1000_hw *hw,
64 bool link_up);
65 static s32 e1000_phy_init_script_82541(struct e1000_hw *hw);
66
67 static const u16 e1000_igp_cable_length_table[] =
68 { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
69 5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25,
70 25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40,
71 40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60,
72 60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90,
73 90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100,
74 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110,
75 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120};
76 #define IGP01E1000_AGC_LENGTH_TABLE_SIZE \
77 (sizeof(e1000_igp_cable_length_table) / \
78 sizeof(e1000_igp_cable_length_table[0]))
79
80 struct e1000_dev_spec_82541 {
81 e1000_dsp_config dsp_config;
82 e1000_ffe_config ffe_config;
83 u16 spd_default;
84 bool phy_init_script;
85 };
86
87 /**
88 * e1000_init_phy_params_82541 - Init PHY func ptrs.
89 * @hw: pointer to the HW structure
90 *
91 * This is a function pointer entry point called by the api module.
92 **/
93 STATIC s32 e1000_init_phy_params_82541(struct e1000_hw *hw)
94 {
95 struct e1000_phy_info *phy = &hw->phy;
96 struct e1000_functions *func = &hw->func;
97 s32 ret_val = E1000_SUCCESS;
98
99 DEBUGFUNC("e1000_init_phy_params_82541");
100
101 phy->addr = 1;
102 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
103 phy->reset_delay_us = 10000;
104 phy->type = e1000_phy_igp;
105
106 /* Function Pointers */
107 func->check_polarity = e1000_check_polarity_igp;
108 func->force_speed_duplex = e1000_phy_force_speed_duplex_igp;
109 func->get_cable_length = e1000_get_cable_length_igp_82541;
110 func->get_cfg_done = e1000_get_cfg_done_generic;
111 func->get_phy_info = e1000_get_phy_info_igp;
112 func->read_phy_reg = e1000_read_phy_reg_igp;
113 func->reset_phy = e1000_phy_hw_reset_82541;
114 func->set_d3_lplu_state = e1000_set_d3_lplu_state_82541;
115 func->write_phy_reg = e1000_write_phy_reg_igp;
116
117 ret_val = e1000_get_phy_id(hw);
118 if (ret_val)
119 goto out;
120
121 /* Verify phy id */
122 if (phy->id != IGP01E1000_I_PHY_ID) {
123 ret_val = -E1000_ERR_PHY;
124 goto out;
125 }
126
127 out:
128 return ret_val;
129 }
130
131 /**
132 * e1000_init_nvm_params_82541 - Init NVM func ptrs.
133 * @hw: pointer to the HW structure
134 *
135 * This is a function pointer entry point called by the api module.
136 **/
137 STATIC s32 e1000_init_nvm_params_82541(struct e1000_hw *hw)
138 {
139 struct e1000_nvm_info *nvm = &hw->nvm;
140 struct e1000_functions *func = &hw->func;
141 s32 ret_val = E1000_SUCCESS;
142 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
143 u16 size;
144
145 DEBUGFUNC("e1000_init_nvm_params_82541");
146
147 switch (nvm->override) {
148 case e1000_nvm_override_spi_large:
149 nvm->type = e1000_nvm_eeprom_spi;
150 eecd |= E1000_EECD_ADDR_BITS;
151 break;
152 case e1000_nvm_override_spi_small:
153 nvm->type = e1000_nvm_eeprom_spi;
154 eecd &= ~E1000_EECD_ADDR_BITS;
155 break;
156 case e1000_nvm_override_microwire_large:
157 nvm->type = e1000_nvm_eeprom_microwire;
158 eecd |= E1000_EECD_SIZE;
159 break;
160 case e1000_nvm_override_microwire_small:
161 nvm->type = e1000_nvm_eeprom_microwire;
162 eecd &= ~E1000_EECD_SIZE;
163 break;
164 default:
165 nvm->type = eecd & E1000_EECD_TYPE
166 ? e1000_nvm_eeprom_spi
167 : e1000_nvm_eeprom_microwire;
168 break;
169 }
170
171 if (nvm->type == e1000_nvm_eeprom_spi) {
172 nvm->address_bits = (eecd & E1000_EECD_ADDR_BITS)
173 ? 16 : 8;
174 nvm->delay_usec = 1;
175 nvm->opcode_bits = 8;
176 nvm->page_size = (eecd & E1000_EECD_ADDR_BITS)
177 ? 32 : 8;
178
179 /* Function Pointers */
180 func->acquire_nvm = e1000_acquire_nvm_generic;
181 func->read_nvm = e1000_read_nvm_spi;
182 func->release_nvm = e1000_release_nvm_generic;
183 func->update_nvm = e1000_update_nvm_checksum_generic;
184 func->valid_led_default = e1000_valid_led_default_generic;
185 func->validate_nvm = e1000_validate_nvm_checksum_generic;
186 func->write_nvm = e1000_write_nvm_spi;
187
188 /*
189 * nvm->word_size must be discovered after the pointers
190 * are set so we can verify the size from the nvm image
191 * itself. Temporarily set it to a dummy value so the
192 * read will work.
193 */
194 nvm->word_size = 64;
195 ret_val = e1000_read_nvm(hw, NVM_CFG, 1, &size);
196 if (ret_val)
197 goto out;
198 size = (size & NVM_SIZE_MASK) >> NVM_SIZE_SHIFT;
199 /*
200 * if size != 0, it can be added to a constant and become
201 * the left-shift value to set the word_size. Otherwise,
202 * word_size stays at 64.
203 */
204 if (size) {
205 size += NVM_WORD_SIZE_BASE_SHIFT_82541;
206 nvm->word_size = 1 << size;
207 }
208 } else {
209 nvm->address_bits = (eecd & E1000_EECD_ADDR_BITS)
210 ? 8 : 6;
211 nvm->delay_usec = 50;
212 nvm->opcode_bits = 3;
213 nvm->word_size = (eecd & E1000_EECD_ADDR_BITS)
214 ? 256 : 64;
215
216 /* Function Pointers */
217 func->acquire_nvm = e1000_acquire_nvm_generic;
218 func->read_nvm = e1000_read_nvm_microwire;
219 func->release_nvm = e1000_release_nvm_generic;
220 func->update_nvm = e1000_update_nvm_checksum_generic;
221 func->valid_led_default = e1000_valid_led_default_generic;
222 func->validate_nvm = e1000_validate_nvm_checksum_generic;
223 func->write_nvm = e1000_write_nvm_microwire;
224 }
225
226 out:
227 return ret_val;
228 }
229
230 /**
231 * e1000_init_mac_params_82541 - Init MAC func ptrs.
232 * @hw: pointer to the HW structure
233 *
234 * This is a function pointer entry point called by the api module.
235 **/
236 STATIC s32 e1000_init_mac_params_82541(struct e1000_hw *hw)
237 {
238 struct e1000_mac_info *mac = &hw->mac;
239 struct e1000_functions *func = &hw->func;
240 s32 ret_val;
241
242 DEBUGFUNC("e1000_init_mac_params_82541");
243
244 /* Set media type */
245 hw->phy.media_type = e1000_media_type_copper;
246 /* Set mta register count */
247 mac->mta_reg_count = 128;
248 /* Set rar entry count */
249 mac->rar_entry_count = E1000_RAR_ENTRIES;
250 /* Set if part includes ASF firmware */
251 mac->asf_firmware_present = TRUE;
252
253 /* Function Pointers */
254
255 /* bus type/speed/width */
256 func->get_bus_info = e1000_get_bus_info_pci_generic;
257 /* reset */
258 func->reset_hw = e1000_reset_hw_82541;
259 /* hw initialization */
260 func->init_hw = e1000_init_hw_82541;
261 /* link setup */
262 func->setup_link = e1000_setup_link_generic;
263 /* physical interface link setup */
264 func->setup_physical_interface = e1000_setup_copper_link_82541;
265 /* check for link */
266 func->check_for_link = e1000_check_for_link_82541;
267 /* link info */
268 func->get_link_up_info = e1000_get_link_up_info_82541;
269 /* multicast address update */
270 func->update_mc_addr_list = e1000_update_mc_addr_list_generic;
271 /* writing VFTA */
272 func->write_vfta = e1000_write_vfta_generic;
273 /* clearing VFTA */
274 func->clear_vfta = e1000_clear_vfta_generic;
275 /* setting MTA */
276 func->mta_set = e1000_mta_set_generic;
277 /* setup LED */
278 func->setup_led = e1000_setup_led_82541;
279 /* cleanup LED */
280 func->cleanup_led = e1000_cleanup_led_82541;
281 /* turn on/off LED */
282 func->led_on = e1000_led_on_generic;
283 func->led_off = e1000_led_off_generic;
284 /* remove device */
285 func->remove_device = e1000_remove_device_generic;
286 /* clear hardware counters */
287 func->clear_hw_cntrs = e1000_clear_hw_cntrs_82541;
288
289 hw->dev_spec_size = sizeof(struct e1000_dev_spec_82541);
290
291 /* Device-specific structure allocation */
292 ret_val = e1000_alloc_zeroed_dev_spec_struct(hw, hw->dev_spec_size);
293
294 return ret_val;
295 }
296
297 /**
298 * e1000_init_function_pointers_82541 - Init func ptrs.
299 * @hw: pointer to the HW structure
300 *
301 * The only function explicitly called by the api module to initialize
302 * all function pointers and parameters.
303 **/
304 void e1000_init_function_pointers_82541(struct e1000_hw *hw)
305 {
306 DEBUGFUNC("e1000_init_function_pointers_82541");
307
308 hw->func.init_mac_params = e1000_init_mac_params_82541;
309 hw->func.init_nvm_params = e1000_init_nvm_params_82541;
310 hw->func.init_phy_params = e1000_init_phy_params_82541;
311 }
312
313 /**
314 * e1000_reset_hw_82541 - Reset hardware
315 * @hw: pointer to the HW structure
316 *
317 * This resets the hardware into a known state. This is a
318 * function pointer entry point called by the api module.
319 **/
320 STATIC s32 e1000_reset_hw_82541(struct e1000_hw *hw)
321 {
322 u32 ledctl, ctrl, icr, manc;
323
324 DEBUGFUNC("e1000_reset_hw_82541");
325
326 DEBUGOUT("Masking off all interrupts\n");
327 E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF);
328
329 E1000_WRITE_REG(hw, E1000_RCTL, 0);
330 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
331 E1000_WRITE_FLUSH(hw);
332
333 /*
334 * Delay to allow any outstanding PCI transactions to complete
335 * before resetting the device.
336 */
337 msec_delay(10);
338
339 ctrl = E1000_READ_REG(hw, E1000_CTRL);
340
341 /* Must reset the Phy before resetting the MAC */
342 if ((hw->mac.type == e1000_82541) || (hw->mac.type == e1000_82547)) {
343 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl | E1000_CTRL_PHY_RST));
344 msec_delay(5);
345 }
346
347 DEBUGOUT("Issuing a global reset to 82541/82547 MAC\n");
348 switch (hw->mac.type) {
349 case e1000_82541:
350 case e1000_82541_rev_2:
351 /*
352 * These controllers can't ack the 64-bit write when
353 * issuing the reset, so we use IO-mapping as a
354 * workaround to issue the reset.
355 */
356 E1000_WRITE_REG_IO(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
357 break;
358 default:
359 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
360 break;
361 }
362
363 /* Wait for NVM reload */
364 msec_delay(20);
365
366 /* Disable HW ARPs on ASF enabled adapters */
367 manc = E1000_READ_REG(hw, E1000_MANC);
368 manc &= ~E1000_MANC_ARP_EN;
369 E1000_WRITE_REG(hw, E1000_MANC, manc);
370
371 if ((hw->mac.type == e1000_82541) || (hw->mac.type == e1000_82547)) {
372 e1000_phy_init_script_82541(hw);
373
374 /* Configure activity LED after Phy reset */
375 ledctl = E1000_READ_REG(hw, E1000_LEDCTL);
376 ledctl &= IGP_ACTIVITY_LED_MASK;
377 ledctl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
378 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl);
379 }
380
381 /* Once again, mask the interrupts */
382 DEBUGOUT("Masking off all interrupts\n");
383 E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF);
384
385 /* Clear any pending interrupt events. */
386 icr = E1000_READ_REG(hw, E1000_ICR);
387
388 return E1000_SUCCESS;
389 }
390
391 /**
392 * e1000_init_hw_82541 - Initialize hardware
393 * @hw: pointer to the HW structure
394 *
395 * This inits the hardware readying it for operation. This is a
396 * function pointer entry point called by the api module.
397 **/
398 STATIC s32 e1000_init_hw_82541(struct e1000_hw *hw)
399 {
400 struct e1000_mac_info *mac = &hw->mac;
401 u32 i, txdctl;
402 s32 ret_val;
403
404 DEBUGFUNC("e1000_init_hw_82541");
405
406 /* Initialize identification LED */
407 ret_val = e1000_id_led_init_generic(hw);
408 if (ret_val) {
409 DEBUGOUT("Error initializing identification LED\n");
410 /* This is not fatal and we should not stop init due to this */
411 }
412
413 /* Disabling VLAN filtering */
414 DEBUGOUT("Initializing the IEEE VLAN\n");
415 e1000_clear_vfta(hw);
416
417 /* Setup the receive address. */
418 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
419
420 /* Zero out the Multicast HASH table */
421 DEBUGOUT("Zeroing the MTA\n");
422 for (i = 0; i < mac->mta_reg_count; i++) {
423 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
424 /*
425 * Avoid back to back register writes by adding the register
426 * read (flush). This is to protect against some strange
427 * bridge configurations that may issue Memory Write Block
428 * (MWB) to our register space.
429 */
430 E1000_WRITE_FLUSH(hw);
431 }
432
433 /* Setup link and flow control */
434 ret_val = e1000_setup_link(hw);
435
436 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0));
437 txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
438 E1000_TXDCTL_FULL_TX_DESC_WB;
439 E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl);
440
441 /*
442 * Clear all of the statistics registers (clear on read). It is
443 * important that we do this after we have tried to establish link
444 * because the symbol error count will increment wildly if there
445 * is no link.
446 */
447 e1000_clear_hw_cntrs_82541(hw);
448
449 return ret_val;
450 }
451
452 /**
453 * e1000_get_link_up_info_82541 - Report speed and duplex
454 * @hw: pointer to the HW structure
455 * @speed: pointer to speed buffer
456 * @duplex: pointer to duplex buffer
457 *
458 * Retrieve the current speed and duplex configuration.
459 * This is a function pointer entry point called by the api module.
460 **/
461 STATIC s32 e1000_get_link_up_info_82541(struct e1000_hw *hw, u16 *speed,
462 u16 *duplex)
463 {
464 struct e1000_phy_info *phy = &hw->phy;
465 s32 ret_val;
466 u16 data;
467
468 DEBUGFUNC("e1000_get_link_up_info_82541");
469
470 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, duplex);
471 if (ret_val)
472 goto out;
473
474 if (!phy->speed_downgraded)
475 goto out;
476
477 /*
478 * IGP01 PHY may advertise full duplex operation after speed
479 * downgrade even if it is operating at half duplex.
480 * Here we set the duplex settings to match the duplex in the
481 * link partner's capabilities.
482 */
483 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &data);
484 if (ret_val)
485 goto out;
486
487 if (!(data & NWAY_ER_LP_NWAY_CAPS)) {
488 *duplex = HALF_DUPLEX;
489 } else {
490 ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY, &data);
491 if (ret_val)
492 goto out;
493
494 if (*speed == SPEED_100) {
495 if (!(data & NWAY_LPAR_100TX_FD_CAPS))
496 *duplex = HALF_DUPLEX;
497 } else if (*speed == SPEED_10) {
498 if (!(data & NWAY_LPAR_10T_FD_CAPS))
499 *duplex = HALF_DUPLEX;
500 }
501 }
502
503 out:
504 return ret_val;
505 }
506
507 /**
508 * e1000_phy_hw_reset_82541 - PHY hardware reset
509 * @hw: pointer to the HW structure
510 *
511 * Verify the reset block is not blocking us from resetting. Acquire
512 * semaphore (if necessary) and read/set/write the device control reset
513 * bit in the PHY. Wait the appropriate delay time for the device to
514 * reset and relase the semaphore (if necessary).
515 * This is a function pointer entry point called by the api module.
516 **/
517 STATIC s32 e1000_phy_hw_reset_82541(struct e1000_hw *hw)
518 {
519 s32 ret_val;
520 u32 ledctl;
521
522 DEBUGFUNC("e1000_phy_hw_reset_82541");
523
524 ret_val = e1000_phy_hw_reset_generic(hw);
525 if (ret_val)
526 goto out;
527
528 e1000_phy_init_script_82541(hw);
529
530 if ((hw->mac.type == e1000_82541) || (hw->mac.type == e1000_82547)) {
531 /* Configure activity LED after PHY reset */
532 ledctl = E1000_READ_REG(hw, E1000_LEDCTL);
533 ledctl &= IGP_ACTIVITY_LED_MASK;
534 ledctl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
535 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl);
536 }
537
538 out:
539 return ret_val;
540 }
541
542 /**
543 * e1000_setup_copper_link_82541 - Configure copper link settings
544 * @hw: pointer to the HW structure
545 *
546 * Calls the appropriate function to configure the link for auto-neg or forced
547 * speed and duplex. Then we check for link, once link is established calls
548 * to configure collision distance and flow control are called. If link is
549 * not established, we return -E1000_ERR_PHY (-2). This is a function
550 * pointer entry point called by the api module.
551 **/
552 STATIC s32 e1000_setup_copper_link_82541(struct e1000_hw *hw)
553 {
554 struct e1000_phy_info *phy = &hw->phy;
555 struct e1000_dev_spec_82541 *dev_spec;
556 s32 ret_val;
557 u32 ctrl, ledctl;
558
559 DEBUGFUNC("e1000_setup_copper_link_82541");
560
561 ctrl = E1000_READ_REG(hw, E1000_CTRL);
562 ctrl |= E1000_CTRL_SLU;
563 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
564 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
565
566 hw->phy.reset_disable = FALSE;
567
568 dev_spec = (struct e1000_dev_spec_82541 *)hw->dev_spec;
569
570 /* Earlier revs of the IGP phy require us to force MDI. */
571 if (hw->mac.type == e1000_82541 || hw->mac.type == e1000_82547) {
572 dev_spec->dsp_config = e1000_dsp_config_disabled;
573 phy->mdix = 1;
574 } else {
575 dev_spec->dsp_config = e1000_dsp_config_enabled;
576 }
577
578 ret_val = e1000_copper_link_setup_igp(hw);
579 if (ret_val)
580 goto out;
581
582 if (hw->mac.autoneg) {
583 if (dev_spec->ffe_config == e1000_ffe_config_active)
584 dev_spec->ffe_config = e1000_ffe_config_enabled;
585 }
586
587 /* Configure activity LED after Phy reset */
588 ledctl = E1000_READ_REG(hw, E1000_LEDCTL);
589 ledctl &= IGP_ACTIVITY_LED_MASK;
590 ledctl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
591 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl);
592
593 ret_val = e1000_setup_copper_link_generic(hw);
594
595 out:
596 return ret_val;
597 }
598
599 /**
600 * e1000_check_for_link_82541 - Check/Store link connection
601 * @hw: pointer to the HW structure
602 *
603 * This checks the link condition of the adapter and stores the
604 * results in the hw->mac structure. This is a function pointer entry
605 * point called by the api module.
606 **/
607 STATIC s32 e1000_check_for_link_82541(struct e1000_hw *hw)
608 {
609 struct e1000_mac_info *mac = &hw->mac;
610 s32 ret_val;
611 bool link;
612
613 DEBUGFUNC("e1000_check_for_link_82541");
614
615 /*
616 * We only want to go out to the PHY registers to see if Auto-Neg
617 * has completed and/or if our link status has changed. The
618 * get_link_status flag is set upon receiving a Link Status
619 * Change or Rx Sequence Error interrupt.
620 */
621 if (!mac->get_link_status) {
622 ret_val = E1000_SUCCESS;
623 goto out;
624 }
625
626 /*
627 * First we want to see if the MII Status Register reports
628 * link. If so, then we want to get the current speed/duplex
629 * of the PHY.
630 */
631 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
632 if (ret_val)
633 goto out;
634
635 if (!link) {
636 ret_val = e1000_config_dsp_after_link_change_82541(hw, FALSE);
637 goto out; /* No link detected */
638 }
639
640 mac->get_link_status = FALSE;
641
642 /*
643 * Check if there was DownShift, must be checked
644 * immediately after link-up
645 */
646 e1000_check_downshift_generic(hw);
647
648 /*
649 * If we are forcing speed/duplex, then we simply return since
650 * we have already determined whether we have link or not.
651 */
652 if (!mac->autoneg) {
653 ret_val = -E1000_ERR_CONFIG;
654 goto out;
655 }
656
657 ret_val = e1000_config_dsp_after_link_change_82541(hw, TRUE);
658
659 /*
660 * Auto-Neg is enabled. Auto Speed Detection takes care
661 * of MAC speed/duplex configuration. So we only need to
662 * configure Collision Distance in the MAC.
663 */
664 e1000_config_collision_dist_generic(hw);
665
666 /*
667 * Configure Flow Control now that Auto-Neg has completed.
668 * First, we need to restore the desired flow control
669 * settings because we may have had to re-autoneg with a
670 * different link partner.
671 */
672 ret_val = e1000_config_fc_after_link_up_generic(hw);
673 if (ret_val) {
674 DEBUGOUT("Error configuring flow control\n");
675 }
676
677 out:
678 return ret_val;
679 }
680
681 /**
682 * e1000_config_dsp_after_link_change_82541 - Config DSP after link
683 * @hw: pointer to the HW structure
684 * @link_up: boolean flag for link up status
685 *
686 * Return E1000_ERR_PHY when failing to read/write the PHY, else E1000_SUCCESS
687 * at any other case.
688 *
689 * 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a
690 * gigabit link is achieved to improve link quality.
691 * This is a function pointer entry point called by the api module.
692 **/
693 static s32 e1000_config_dsp_after_link_change_82541(struct e1000_hw *hw,
694 bool link_up)
695 {
696 struct e1000_phy_info *phy = &hw->phy;
697 struct e1000_dev_spec_82541 *dev_spec;
698 s32 ret_val;
699 u32 idle_errs = 0;
700 u16 phy_data, phy_saved_data, speed, duplex, i;
701 u16 ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_20;
702 u16 dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
703 {IGP01E1000_PHY_AGC_PARAM_A,
704 IGP01E1000_PHY_AGC_PARAM_B,
705 IGP01E1000_PHY_AGC_PARAM_C,
706 IGP01E1000_PHY_AGC_PARAM_D};
707
708 DEBUGFUNC("e1000_config_dsp_after_link_change_82541");
709
710 dev_spec = (struct e1000_dev_spec_82541 *)hw->dev_spec;
711
712 if (link_up) {
713 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
714 if (ret_val) {
715 DEBUGOUT("Error getting link speed and duplex\n");
716 goto out;
717 }
718
719 if (speed != SPEED_1000) {
720 ret_val = E1000_SUCCESS;
721 goto out;
722 }
723
724 ret_val = e1000_get_cable_length(hw);
725 if (ret_val)
726 goto out;
727
728 if ((dev_spec->dsp_config == e1000_dsp_config_enabled) &&
729 phy->min_cable_length >= 50) {
730
731 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
732 ret_val = e1000_read_phy_reg(hw,
733 dsp_reg_array[i],
734 &phy_data);
735 if (ret_val)
736 goto out;
737
738 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
739
740 ret_val = e1000_write_phy_reg(hw,
741 dsp_reg_array[i],
742 phy_data);
743 if (ret_val)
744 goto out;
745 }
746 dev_spec->dsp_config = e1000_dsp_config_activated;
747 }
748
749 if ((dev_spec->ffe_config != e1000_ffe_config_enabled) ||
750 (phy->min_cable_length >= 50)) {
751 ret_val = E1000_SUCCESS;
752 goto out;
753 }
754
755 /* clear previous idle error counts */
756 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
757 if (ret_val)
758 goto out;
759
760 for (i = 0; i < ffe_idle_err_timeout; i++) {
761 usec_delay(1000);
762 ret_val = e1000_read_phy_reg(hw,
763 PHY_1000T_STATUS,
764 &phy_data);
765 if (ret_val)
766 goto out;
767
768 idle_errs += (phy_data & SR_1000T_IDLE_ERROR_CNT);
769 if (idle_errs > SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) {
770 dev_spec->ffe_config = e1000_ffe_config_active;
771
772 ret_val = e1000_write_phy_reg(hw,
773 IGP01E1000_PHY_DSP_FFE,
774 IGP01E1000_PHY_DSP_FFE_CM_CP);
775 if (ret_val)
776 goto out;
777 break;
778 }
779
780 if (idle_errs)
781 ffe_idle_err_timeout =
782 FFE_IDLE_ERR_COUNT_TIMEOUT_100;
783 }
784 } else {
785 if (dev_spec->dsp_config == e1000_dsp_config_activated) {
786 /*
787 * Save off the current value of register 0x2F5B
788 * to be restored at the end of the routines.
789 */
790 ret_val = e1000_read_phy_reg(hw,
791 0x2F5B,
792 &phy_saved_data);
793 if (ret_val)
794 goto out;
795
796 /* Disable the PHY transmitter */
797 ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
798 if (ret_val)
799 goto out;
800
801 msec_delay_irq(20);
802
803 ret_val = e1000_write_phy_reg(hw,
804 0x0000,
805 IGP01E1000_IEEE_FORCE_GIG);
806 if (ret_val)
807 goto out;
808 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
809 ret_val = e1000_read_phy_reg(hw,
810 dsp_reg_array[i],
811 &phy_data);
812 if (ret_val)
813 goto out;
814
815 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
816 phy_data |= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS;
817
818 ret_val = e1000_write_phy_reg(hw,
819 dsp_reg_array[i],
820 phy_data);
821 if (ret_val)
822 goto out;
823 }
824
825 ret_val = e1000_write_phy_reg(hw,
826 0x0000,
827 IGP01E1000_IEEE_RESTART_AUTONEG);
828 if (ret_val)
829 goto out;
830
831 msec_delay_irq(20);
832
833 /* Now enable the transmitter */
834 ret_val = e1000_write_phy_reg(hw,
835 0x2F5B,
836 phy_saved_data);
837 if (ret_val)
838 goto out;
839
840 dev_spec->dsp_config = e1000_dsp_config_enabled;
841 }
842
843 if (dev_spec->ffe_config != e1000_ffe_config_active) {
844 ret_val = E1000_SUCCESS;
845 goto out;
846 }
847
848 /*
849 * Save off the current value of register 0x2F5B
850 * to be restored at the end of the routines.
851 */
852 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
853 if (ret_val)
854 goto out;
855
856 /* Disable the PHY transmitter */
857 ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
858 if (ret_val)
859 goto out;
860
861 msec_delay_irq(20);
862
863 ret_val = e1000_write_phy_reg(hw,
864 0x0000,
865 IGP01E1000_IEEE_FORCE_GIG);
866 if (ret_val)
867 goto out;
868
869 ret_val = e1000_write_phy_reg(hw,
870 IGP01E1000_PHY_DSP_FFE,
871 IGP01E1000_PHY_DSP_FFE_DEFAULT);
872 if (ret_val)
873 goto out;
874
875 ret_val = e1000_write_phy_reg(hw,
876 0x0000,
877 IGP01E1000_IEEE_RESTART_AUTONEG);
878 if (ret_val)
879 goto out;
880
881 msec_delay_irq(20);
882
883 /* Now enable the transmitter */
884 ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
885
886 if (ret_val)
887 goto out;
888
889 dev_spec->ffe_config = e1000_ffe_config_enabled;
890 }
891
892 out:
893 return ret_val;
894 }
895
896 /**
897 * e1000_get_cable_length_igp_82541 - Determine cable length for igp PHY
898 * @hw: pointer to the HW structure
899 *
900 * The automatic gain control (agc) normalizes the amplitude of the
901 * received signal, adjusting for the attenuation produced by the
902 * cable. By reading the AGC registers, which reperesent the
903 * cobination of course and fine gain value, the value can be put
904 * into a lookup table to obtain the approximate cable length
905 * for each channel. This is a function pointer entry point called by the
906 * api module.
907 **/
908 STATIC s32 e1000_get_cable_length_igp_82541(struct e1000_hw *hw)
909 {
910 struct e1000_phy_info *phy = &hw->phy;
911 s32 ret_val = E1000_SUCCESS;
912 u16 i, data;
913 u16 cur_agc_value, agc_value = 0;
914 u16 min_agc_value = IGP01E1000_AGC_LENGTH_TABLE_SIZE;
915 u16 agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
916 {IGP01E1000_PHY_AGC_A,
917 IGP01E1000_PHY_AGC_B,
918 IGP01E1000_PHY_AGC_C,
919 IGP01E1000_PHY_AGC_D};
920
921 DEBUGFUNC("e1000_get_cable_length_igp_82541");
922
923 /* Read the AGC registers for all channels */
924 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
925 ret_val = e1000_read_phy_reg(hw, agc_reg_array[i], &data);
926 if (ret_val)
927 goto out;
928
929 cur_agc_value = data >> IGP01E1000_AGC_LENGTH_SHIFT;
930
931 /* Bounds checking */
932 if ((cur_agc_value >= IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) ||
933 (cur_agc_value == 0)) {
934 ret_val = -E1000_ERR_PHY;
935 goto out;
936 }
937
938 agc_value += cur_agc_value;
939
940 if (min_agc_value > cur_agc_value)
941 min_agc_value = cur_agc_value;
942 }
943
944 /* Remove the minimal AGC result for length < 50m */
945 if (agc_value < IGP01E1000_PHY_CHANNEL_NUM * 50) {
946 agc_value -= min_agc_value;
947 /* Average the three remaining channels for the length. */
948 agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1);
949 } else {
950 /* Average the channels for the length. */
951 agc_value /= IGP01E1000_PHY_CHANNEL_NUM;
952 }
953
954 phy->min_cable_length = (e1000_igp_cable_length_table[agc_value] >
955 IGP01E1000_AGC_RANGE)
956 ? (e1000_igp_cable_length_table[agc_value] -
957 IGP01E1000_AGC_RANGE)
958 : 0;
959 phy->max_cable_length = e1000_igp_cable_length_table[agc_value] +
960 IGP01E1000_AGC_RANGE;
961
962 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
963
964 out:
965 return ret_val;
966 }
967
968 /**
969 * e1000_set_d3_lplu_state_82541 - Sets low power link up state for D3
970 * @hw: pointer to the HW structure
971 * @active: boolean used to enable/disable lplu
972 *
973 * Success returns 0, Failure returns 1
974 *
975 * The low power link up (lplu) state is set to the power management level D3
976 * and SmartSpeed is disabled when active is true, else clear lplu for D3
977 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
978 * is used during Dx states where the power conservation is most important.
979 * During driver activity, SmartSpeed should be enabled so performance is
980 * maintained. This is a function pointer entry point called by the
981 * api module.
982 **/
983 STATIC s32 e1000_set_d3_lplu_state_82541(struct e1000_hw *hw, bool active)
984 {
985 struct e1000_phy_info *phy = &hw->phy;
986 s32 ret_val;
987 u16 data;
988
989 DEBUGFUNC("e1000_set_d3_lplu_state_82541");
990
991 switch (hw->mac.type) {
992 case e1000_82541_rev_2:
993 case e1000_82547_rev_2:
994 break;
995 default:
996 ret_val = e1000_set_d3_lplu_state_generic(hw, active);
997 goto out;
998 break;
999 }
1000
1001 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &data);
1002 if (ret_val)
1003 goto out;
1004
1005 if (!active) {
1006 data &= ~IGP01E1000_GMII_FLEX_SPD;
1007 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, data);
1008 if (ret_val)
1009 goto out;
1010
1011 /*
1012 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
1013 * during Dx states where the power conservation is most
1014 * important. During driver activity we should enable
1015 * SmartSpeed, so performance is maintained.
1016 */
1017 if (phy->smart_speed == e1000_smart_speed_on) {
1018 ret_val = e1000_read_phy_reg(hw,
1019 IGP01E1000_PHY_PORT_CONFIG,
1020 &data);
1021 if (ret_val)
1022 goto out;
1023
1024 data |= IGP01E1000_PSCFR_SMART_SPEED;
1025 ret_val = e1000_write_phy_reg(hw,
1026 IGP01E1000_PHY_PORT_CONFIG,
1027 data);
1028 if (ret_val)
1029 goto out;
1030 } else if (phy->smart_speed == e1000_smart_speed_off) {
1031 ret_val = e1000_read_phy_reg(hw,
1032 IGP01E1000_PHY_PORT_CONFIG,
1033 &data);
1034 if (ret_val)
1035 goto out;
1036
1037 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1038 ret_val = e1000_write_phy_reg(hw,
1039 IGP01E1000_PHY_PORT_CONFIG,
1040 data);
1041 if (ret_val)
1042 goto out;
1043 }
1044 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1045 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1046 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1047 data |= IGP01E1000_GMII_FLEX_SPD;
1048 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, data);
1049 if (ret_val)
1050 goto out;
1051
1052 /* When LPLU is enabled, we should disable SmartSpeed */
1053 ret_val = e1000_read_phy_reg(hw,
1054 IGP01E1000_PHY_PORT_CONFIG,
1055 &data);
1056 if (ret_val)
1057 goto out;
1058
1059 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1060 ret_val = e1000_write_phy_reg(hw,
1061 IGP01E1000_PHY_PORT_CONFIG,
1062 data);
1063 }
1064
1065 out:
1066 return ret_val;
1067 }
1068
1069 /**
1070 * e1000_setup_led_82541 - Configures SW controllable LED
1071 * @hw: pointer to the HW structure
1072 *
1073 * This prepares the SW controllable LED for use and saves the current state
1074 * of the LED so it can be later restored. This is a function pointer entry
1075 * point called by the api module.
1076 **/
1077 STATIC s32 e1000_setup_led_82541(struct e1000_hw *hw)
1078 {
1079 struct e1000_dev_spec_82541 *dev_spec;
1080 s32 ret_val;
1081
1082 DEBUGFUNC("e1000_setup_led_82541");
1083
1084 dev_spec = (struct e1000_dev_spec_82541 *)hw->dev_spec;
1085
1086 ret_val = e1000_read_phy_reg(hw,
1087 IGP01E1000_GMII_FIFO,
1088 &dev_spec->spd_default);
1089 if (ret_val)
1090 goto out;
1091
1092 ret_val = e1000_write_phy_reg(hw,
1093 IGP01E1000_GMII_FIFO,
1094 (u16)(dev_spec->spd_default &
1095 ~IGP01E1000_GMII_SPD));
1096 if (ret_val)
1097 goto out;
1098
1099 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
1100
1101 out:
1102 return ret_val;
1103 }
1104
1105 /**
1106 * e1000_cleanup_led_82541 - Set LED config to default operation
1107 * @hw: pointer to the HW structure
1108 *
1109 * Remove the current LED configuration and set the LED configuration
1110 * to the default value, saved from the EEPROM. This is a function pointer
1111 * entry point called by the api module.
1112 **/
1113 STATIC s32 e1000_cleanup_led_82541(struct e1000_hw *hw)
1114 {
1115 struct e1000_dev_spec_82541 *dev_spec;
1116 s32 ret_val;
1117
1118 DEBUGFUNC("e1000_cleanup_led_82541");
1119
1120 dev_spec = (struct e1000_dev_spec_82541 *)hw->dev_spec;
1121
1122 ret_val = e1000_write_phy_reg(hw,
1123 IGP01E1000_GMII_FIFO,
1124 dev_spec->spd_default);
1125 if (ret_val)
1126 goto out;
1127
1128 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default);
1129
1130 out:
1131 return ret_val;
1132 }
1133
1134 /**
1135 * e1000_phy_init_script_82541 - Initialize GbE PHY
1136 * @hw: pointer to the HW structure
1137 *
1138 * Initializes the IGP PHY.
1139 **/
1140 static s32 e1000_phy_init_script_82541(struct e1000_hw *hw)
1141 {
1142 struct e1000_dev_spec_82541 *dev_spec;
1143 u32 ret_val;
1144 u16 phy_saved_data;
1145
1146 DEBUGFUNC("e1000_phy_init_script_82541");
1147
1148 dev_spec = (struct e1000_dev_spec_82541 *)hw->dev_spec;
1149
1150 if (!dev_spec->phy_init_script) {
1151 ret_val = E1000_SUCCESS;
1152 goto out;
1153 }
1154
1155 /* Delay after phy reset to enable NVM configuration to load */
1156 msec_delay(20);
1157
1158 /*
1159 * Save off the current value of register 0x2F5B to be restored at
1160 * the end of this routine.
1161 */
1162 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
1163
1164 /* Disabled the PHY transmitter */
1165 e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
1166
1167 msec_delay(20);
1168
1169 e1000_write_phy_reg(hw, 0x0000, 0x0140);
1170
1171 msec_delay(5);
1172
1173 switch (hw->mac.type) {
1174 case e1000_82541:
1175 case e1000_82547:
1176 e1000_write_phy_reg(hw, 0x1F95, 0x0001);
1177
1178 e1000_write_phy_reg(hw, 0x1F71, 0xBD21);
1179
1180 e1000_write_phy_reg(hw, 0x1F79, 0x0018);
1181
1182 e1000_write_phy_reg(hw, 0x1F30, 0x1600);
1183
1184 e1000_write_phy_reg(hw, 0x1F31, 0x0014);
1185
1186 e1000_write_phy_reg(hw, 0x1F32, 0x161C);
1187
1188 e1000_write_phy_reg(hw, 0x1F94, 0x0003);
1189
1190 e1000_write_phy_reg(hw, 0x1F96, 0x003F);
1191
1192 e1000_write_phy_reg(hw, 0x2010, 0x0008);
1193 break;
1194 case e1000_82541_rev_2:
1195 case e1000_82547_rev_2:
1196 e1000_write_phy_reg(hw, 0x1F73, 0x0099);
1197 break;
1198 default:
1199 break;
1200 }
1201
1202 e1000_write_phy_reg(hw, 0x0000, 0x3300);
1203
1204 msec_delay(20);
1205
1206 /* Now enable the transmitter */
1207 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
1208
1209 if (hw->mac.type == e1000_82547) {
1210 u16 fused, fine, coarse;
1211
1212 /* Move to analog registers page */
1213 e1000_read_phy_reg(hw,
1214 IGP01E1000_ANALOG_SPARE_FUSE_STATUS,
1215 &fused);
1216
1217 if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
1218 e1000_read_phy_reg(hw,
1219 IGP01E1000_ANALOG_FUSE_STATUS,
1220 &fused);
1221
1222 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
1223 coarse = fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
1224
1225 if (coarse > IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
1226 coarse -= IGP01E1000_ANALOG_FUSE_COARSE_10;
1227 fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
1228 } else if (coarse ==
1229 IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
1230 fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
1231
1232 fused = (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
1233 (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) |
1234 (coarse & IGP01E1000_ANALOG_FUSE_COARSE_MASK);
1235
1236 e1000_write_phy_reg(hw,
1237 IGP01E1000_ANALOG_FUSE_CONTROL,
1238 fused);
1239 e1000_write_phy_reg(hw,
1240 IGP01E1000_ANALOG_FUSE_BYPASS,
1241 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
1242 }
1243 }
1244
1245 out:
1246 return ret_val;
1247 }
1248
1249 /**
1250 * e1000_init_script_state_82541 - Enable/Disable PHY init script
1251 * @hw: pointer to the HW structure
1252 * @state: boolean value used to enable/disable PHY init script
1253 *
1254 * Allows the driver to enable/disable the PHY init script, if the PHY is an
1255 * IGP PHY. This is a function pointer entry point called by the api module.
1256 **/
1257 void e1000_init_script_state_82541(struct e1000_hw *hw, bool state)
1258 {
1259 struct e1000_dev_spec_82541 *dev_spec;
1260
1261 DEBUGFUNC("e1000_init_script_state_82541");
1262
1263 if (hw->phy.type != e1000_phy_igp) {
1264 DEBUGOUT("Initialization script not necessary.\n");
1265 goto out;
1266 }
1267
1268 dev_spec = (struct e1000_dev_spec_82541 *)hw->dev_spec;
1269
1270 if (!dev_spec) {
1271 DEBUGOUT("dev_spec pointer is set to NULL.\n");
1272 goto out;
1273 }
1274
1275 dev_spec->phy_init_script = state;
1276
1277 out:
1278 return;
1279 }
1280
1281 /**
1282 * e1000_clear_hw_cntrs_82541 - Clear device specific hardware counters
1283 * @hw: pointer to the HW structure
1284 *
1285 * Clears the hardware counters by reading the counter registers.
1286 **/
1287 STATIC void e1000_clear_hw_cntrs_82541(struct e1000_hw *hw)
1288 {
1289 volatile u32 temp;
1290
1291 DEBUGFUNC("e1000_clear_hw_cntrs_82541");
1292
1293 e1000_clear_hw_cntrs_base_generic(hw);
1294
1295 temp = E1000_READ_REG(hw, E1000_PRC64);
1296 temp = E1000_READ_REG(hw, E1000_PRC127);
1297 temp = E1000_READ_REG(hw, E1000_PRC255);
1298 temp = E1000_READ_REG(hw, E1000_PRC511);
1299 temp = E1000_READ_REG(hw, E1000_PRC1023);
1300 temp = E1000_READ_REG(hw, E1000_PRC1522);
1301 temp = E1000_READ_REG(hw, E1000_PTC64);
1302 temp = E1000_READ_REG(hw, E1000_PTC127);
1303 temp = E1000_READ_REG(hw, E1000_PTC255);
1304 temp = E1000_READ_REG(hw, E1000_PTC511);
1305 temp = E1000_READ_REG(hw, E1000_PTC1023);
1306 temp = E1000_READ_REG(hw, E1000_PTC1522);
1307
1308 temp = E1000_READ_REG(hw, E1000_ALGNERRC);
1309 temp = E1000_READ_REG(hw, E1000_RXERRC);
1310 temp = E1000_READ_REG(hw, E1000_TNCRS);
1311 temp = E1000_READ_REG(hw, E1000_CEXTERR);
1312 temp = E1000_READ_REG(hw, E1000_TSCTC);
1313 temp = E1000_READ_REG(hw, E1000_TSCTFC);
1314
1315 temp = E1000_READ_REG(hw, E1000_MGTPRC);
1316 temp = E1000_READ_REG(hw, E1000_MGTPDC);
1317 temp = E1000_READ_REG(hw, E1000_MGTPTC);
1318 }
Cache object: 5430917ab99fb752309accdc11d44837
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