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sys/dev/em/e1000_82571.c
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1 /******************************************************************************* 2 3 Copyright (c) 2001-2007, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 *******************************************************************************/ 33 /* $FreeBSD$ */ 34 35 36 /* e1000_82571 37 * e1000_82572 38 * e1000_82573 39 */ 40 41 #include "e1000_api.h" 42 #include "e1000_82571.h" 43 44 void e1000_init_function_pointers_82571(struct e1000_hw *hw); 45 46 STATIC s32 e1000_init_phy_params_82571(struct e1000_hw *hw); 47 STATIC s32 e1000_init_nvm_params_82571(struct e1000_hw *hw); 48 STATIC s32 e1000_init_mac_params_82571(struct e1000_hw *hw); 49 STATIC s32 e1000_acquire_nvm_82571(struct e1000_hw *hw); 50 STATIC void e1000_release_nvm_82571(struct e1000_hw *hw); 51 STATIC s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, 52 u16 words, u16 *data); 53 STATIC s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw); 54 STATIC s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw); 55 STATIC s32 e1000_get_cfg_done_82571(struct e1000_hw *hw); 56 STATIC s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, 57 bool active); 58 STATIC s32 e1000_reset_hw_82571(struct e1000_hw *hw); 59 STATIC s32 e1000_init_hw_82571(struct e1000_hw *hw); 60 STATIC void e1000_clear_vfta_82571(struct e1000_hw *hw); 61 STATIC void e1000_update_mc_addr_list_82571(struct e1000_hw *hw, 62 u8 *mc_addr_list, u32 mc_addr_count, 63 u32 rar_used_count, u32 rar_count); 64 STATIC s32 e1000_setup_link_82571(struct e1000_hw *hw); 65 STATIC s32 e1000_setup_copper_link_82571(struct e1000_hw *hw); 66 STATIC s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw); 67 STATIC s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data); 68 STATIC void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw); 69 static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw); 70 static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw); 71 static s32 e1000_get_phy_id_82571(struct e1000_hw *hw); 72 static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw); 73 static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw); 74 static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset, 75 u16 words, u16 *data); 76 STATIC s32 e1000_read_mac_addr_82571(struct e1000_hw *hw); 77 78 struct e1000_dev_spec_82571 { 79 bool laa_is_present; 80 }; 81 82 /** 83 * e1000_init_phy_params_82571 - Init PHY func ptrs. 84 * @hw: pointer to the HW structure 85 * 86 * This is a function pointer entry point called by the api module. 87 **/ 88 STATIC s32 e1000_init_phy_params_82571(struct e1000_hw *hw) 89 { 90 struct e1000_phy_info *phy = &hw->phy; 91 struct e1000_functions *func = &hw->func; 92 s32 ret_val = E1000_SUCCESS; 93 94 DEBUGFUNC("e1000_init_phy_params_82571"); 95 96 if (hw->phy.media_type != e1000_media_type_copper) { 97 phy->type = e1000_phy_none; 98 goto out; 99 } 100 101 phy->addr = 1; 102 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 103 phy->reset_delay_us = 100; 104 105 func->acquire_phy = e1000_get_hw_semaphore_82571; 106 func->check_polarity = e1000_check_polarity_igp; 107 func->check_reset_block = e1000_check_reset_block_generic; 108 func->release_phy = e1000_put_hw_semaphore_82571; 109 func->reset_phy = e1000_phy_hw_reset_generic; 110 func->set_d0_lplu_state = e1000_set_d0_lplu_state_82571; 111 func->set_d3_lplu_state = e1000_set_d3_lplu_state_generic; 112 113 switch (hw->mac.type) { 114 case e1000_82571: 115 case e1000_82572: 116 phy->type = e1000_phy_igp_2; 117 func->get_cfg_done = e1000_get_cfg_done_82571; 118 func->get_phy_info = e1000_get_phy_info_igp; 119 func->force_speed_duplex = e1000_phy_force_speed_duplex_igp; 120 func->get_cable_length = e1000_get_cable_length_igp_2; 121 func->read_phy_reg = e1000_read_phy_reg_igp; 122 func->write_phy_reg = e1000_write_phy_reg_igp; 123 124 /* This uses above function pointers */ 125 ret_val = e1000_get_phy_id_82571(hw); 126 127 /* Verify PHY ID */ 128 if (phy->id != IGP01E1000_I_PHY_ID) { 129 ret_val = -E1000_ERR_PHY; 130 goto out; 131 } 132 break; 133 case e1000_82573: 134 phy->type = e1000_phy_m88; 135 func->get_cfg_done = e1000_get_cfg_done_generic; 136 func->get_phy_info = e1000_get_phy_info_m88; 137 func->commit_phy = e1000_phy_sw_reset_generic; 138 func->force_speed_duplex = e1000_phy_force_speed_duplex_m88; 139 func->get_cable_length = e1000_get_cable_length_m88; 140 func->read_phy_reg = e1000_read_phy_reg_m88; 141 func->write_phy_reg = e1000_write_phy_reg_m88; 142 143 /* This uses above function pointers */ 144 ret_val = e1000_get_phy_id_82571(hw); 145 146 /* Verify PHY ID */ 147 if (phy->id != M88E1111_I_PHY_ID) { 148 ret_val = -E1000_ERR_PHY; 149 goto out; 150 } 151 break; 152 153 default: 154 ret_val = -E1000_ERR_PHY; 155 goto out; 156 break; 157 } 158 159 out: 160 return ret_val; 161 } 162 163 /** 164 * e1000_init_nvm_params_82571 - Init NVM func ptrs. 165 * @hw: pointer to the HW structure 166 * 167 * This is a function pointer entry point called by the api module. 168 **/ 169 STATIC s32 e1000_init_nvm_params_82571(struct e1000_hw *hw) 170 { 171 struct e1000_nvm_info *nvm = &hw->nvm; 172 struct e1000_functions *func = &hw->func; 173 u32 eecd = E1000_READ_REG(hw, E1000_EECD); 174 u16 size; 175 176 DEBUGFUNC("e1000_init_nvm_params_82571"); 177 178 nvm->opcode_bits = 8; 179 nvm->delay_usec = 1; 180 switch (nvm->override) { 181 case e1000_nvm_override_spi_large: 182 nvm->page_size = 32; 183 nvm->address_bits = 16; 184 break; 185 case e1000_nvm_override_spi_small: 186 nvm->page_size = 8; 187 nvm->address_bits = 8; 188 break; 189 default: 190 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8; 191 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8; 192 break; 193 } 194 195 switch (hw->mac.type) { 196 case e1000_82573: 197 if (((eecd >> 15) & 0x3) == 0x3) { 198 nvm->type = e1000_nvm_flash_hw; 199 nvm->word_size = 2048; 200 /* 201 * Autonomous Flash update bit must be cleared due 202 * to Flash update issue. 203 */ 204 eecd &= ~E1000_EECD_AUPDEN; 205 E1000_WRITE_REG(hw, E1000_EECD, eecd); 206 break; 207 } 208 /* Fall Through */ 209 default: 210 nvm->type = e1000_nvm_eeprom_spi; 211 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> 212 E1000_EECD_SIZE_EX_SHIFT); 213 /* 214 * Added to a constant, "size" becomes the left-shift value 215 * for setting word_size. 216 */ 217 size += NVM_WORD_SIZE_BASE_SHIFT; 218 nvm->word_size = 1 << size; 219 break; 220 } 221 222 /* Function Pointers */ 223 func->acquire_nvm = e1000_acquire_nvm_82571; 224 func->read_nvm = (hw->mac.type == e1000_82573) 225 ? e1000_read_nvm_eerd 226 : e1000_read_nvm_spi; 227 func->release_nvm = e1000_release_nvm_82571; 228 func->update_nvm = e1000_update_nvm_checksum_82571; 229 func->validate_nvm = e1000_validate_nvm_checksum_82571; 230 func->valid_led_default = e1000_valid_led_default_82571; 231 func->write_nvm = e1000_write_nvm_82571; 232 233 return E1000_SUCCESS; 234 } 235 236 /** 237 * e1000_init_mac_params_82571 - Init MAC func ptrs. 238 * @hw: pointer to the HW structure 239 * 240 * This is a function pointer entry point called by the api module. 241 **/ 242 STATIC s32 e1000_init_mac_params_82571(struct e1000_hw *hw) 243 { 244 struct e1000_mac_info *mac = &hw->mac; 245 struct e1000_functions *func = &hw->func; 246 s32 ret_val = E1000_SUCCESS; 247 248 DEBUGFUNC("e1000_init_mac_params_82571"); 249 250 /* Set media type */ 251 switch (hw->device_id) { 252 case E1000_DEV_ID_82571EB_FIBER: 253 case E1000_DEV_ID_82572EI_FIBER: 254 case E1000_DEV_ID_82571EB_QUAD_FIBER: 255 hw->phy.media_type = e1000_media_type_fiber; 256 break; 257 case E1000_DEV_ID_82571EB_SERDES: 258 case E1000_DEV_ID_82571EB_SERDES_DUAL: 259 case E1000_DEV_ID_82571EB_SERDES_QUAD: 260 case E1000_DEV_ID_82572EI_SERDES: 261 hw->phy.media_type = e1000_media_type_internal_serdes; 262 break; 263 default: 264 hw->phy.media_type = e1000_media_type_copper; 265 break; 266 } 267 268 /* Set mta register count */ 269 mac->mta_reg_count = 128; 270 /* Set rar entry count */ 271 mac->rar_entry_count = E1000_RAR_ENTRIES; 272 /* Set if part includes ASF firmware */ 273 mac->asf_firmware_present = TRUE; 274 /* Set if manageability features are enabled. */ 275 mac->arc_subsystem_valid = 276 (E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK) 277 ? TRUE : FALSE; 278 279 /* Function pointers */ 280 281 /* bus type/speed/width */ 282 func->get_bus_info = e1000_get_bus_info_pcie_generic; 283 /* reset */ 284 func->reset_hw = e1000_reset_hw_82571; 285 /* hw initialization */ 286 func->init_hw = e1000_init_hw_82571; 287 /* link setup */ 288 func->setup_link = e1000_setup_link_82571; 289 /* physical interface link setup */ 290 func->setup_physical_interface = 291 (hw->phy.media_type == e1000_media_type_copper) 292 ? e1000_setup_copper_link_82571 293 : e1000_setup_fiber_serdes_link_82571; 294 /* check for link */ 295 switch (hw->phy.media_type) { 296 case e1000_media_type_copper: 297 func->check_for_link = e1000_check_for_copper_link_generic; 298 break; 299 case e1000_media_type_fiber: 300 func->check_for_link = e1000_check_for_fiber_link_generic; 301 break; 302 case e1000_media_type_internal_serdes: 303 func->check_for_link = e1000_check_for_serdes_link_generic; 304 break; 305 default: 306 ret_val = -E1000_ERR_CONFIG; 307 goto out; 308 break; 309 } 310 /* check management mode */ 311 func->check_mng_mode = e1000_check_mng_mode_generic; 312 /* multicast address update */ 313 func->update_mc_addr_list = e1000_update_mc_addr_list_82571; 314 /* writing VFTA */ 315 func->write_vfta = e1000_write_vfta_generic; 316 /* clearing VFTA */ 317 func->clear_vfta = e1000_clear_vfta_82571; 318 /* setting MTA */ 319 func->mta_set = e1000_mta_set_generic; 320 /* read mac address */ 321 func->read_mac_addr = e1000_read_mac_addr_82571; 322 /* blink LED */ 323 func->blink_led = e1000_blink_led_generic; 324 /* setup LED */ 325 func->setup_led = e1000_setup_led_generic; 326 /* cleanup LED */ 327 func->cleanup_led = e1000_cleanup_led_generic; 328 /* turn on/off LED */ 329 func->led_on = e1000_led_on_generic; 330 func->led_off = e1000_led_off_generic; 331 /* remove device */ 332 func->remove_device = e1000_remove_device_generic; 333 /* clear hardware counters */ 334 func->clear_hw_cntrs = e1000_clear_hw_cntrs_82571; 335 /* link info */ 336 func->get_link_up_info = 337 (hw->phy.media_type == e1000_media_type_copper) 338 ? e1000_get_speed_and_duplex_copper_generic 339 : e1000_get_speed_and_duplex_fiber_serdes_generic; 340 341 hw->dev_spec_size = sizeof(struct e1000_dev_spec_82571); 342 343 /* Device-specific structure allocation */ 344 ret_val = e1000_alloc_zeroed_dev_spec_struct(hw, hw->dev_spec_size); 345 346 out: 347 return ret_val; 348 } 349 350 /** 351 * e1000_init_function_pointers_82571 - Init func ptrs. 352 * @hw: pointer to the HW structure 353 * 354 * The only function explicitly called by the api module to initialize 355 * all function pointers and parameters. 356 **/ 357 void e1000_init_function_pointers_82571(struct e1000_hw *hw) 358 { 359 DEBUGFUNC("e1000_init_function_pointers_82571"); 360 361 hw->func.init_mac_params = e1000_init_mac_params_82571; 362 hw->func.init_nvm_params = e1000_init_nvm_params_82571; 363 hw->func.init_phy_params = e1000_init_phy_params_82571; 364 } 365 366 /** 367 * e1000_get_phy_id_82571 - Retrieve the PHY ID and revision 368 * @hw: pointer to the HW structure 369 * 370 * Reads the PHY registers and stores the PHY ID and possibly the PHY 371 * revision in the hardware structure. 372 **/ 373 static s32 e1000_get_phy_id_82571(struct e1000_hw *hw) 374 { 375 struct e1000_phy_info *phy = &hw->phy; 376 s32 ret_val = E1000_SUCCESS; 377 378 DEBUGFUNC("e1000_get_phy_id_82571"); 379 380 switch (hw->mac.type) { 381 case e1000_82571: 382 case e1000_82572: 383 /* 384 * The 82571 firmware may still be configuring the PHY. 385 * In this case, we cannot access the PHY until the 386 * configuration is done. So we explicitly set the 387 * PHY ID. 388 */ 389 phy->id = IGP01E1000_I_PHY_ID; 390 break; 391 case e1000_82573: 392 ret_val = e1000_get_phy_id(hw); 393 break; 394 default: 395 ret_val = -E1000_ERR_PHY; 396 break; 397 } 398 399 return ret_val; 400 } 401 402 /** 403 * e1000_get_hw_semaphore_82571 - Acquire hardware semaphore 404 * @hw: pointer to the HW structure 405 * 406 * Acquire the HW semaphore to access the PHY or NVM 407 **/ 408 s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw) 409 { 410 u32 swsm; 411 s32 ret_val = E1000_SUCCESS; 412 s32 timeout = hw->nvm.word_size + 1; 413 s32 i = 0; 414 415 DEBUGFUNC("e1000_get_hw_semaphore_82571"); 416 417 /* Get the FW semaphore. */ 418 for (i = 0; i < timeout; i++) { 419 swsm = E1000_READ_REG(hw, E1000_SWSM); 420 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_SWESMBI); 421 422 /* Semaphore acquired if bit latched */ 423 if (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI) 424 break; 425 426 usec_delay(50); 427 } 428 429 if (i == timeout) { 430 /* Release semaphores */ 431 e1000_put_hw_semaphore_generic(hw); 432 DEBUGOUT("Driver can't access the NVM\n"); 433 ret_val = -E1000_ERR_NVM; 434 goto out; 435 } 436 437 out: 438 return ret_val; 439 } 440 441 /** 442 * e1000_put_hw_semaphore_82571 - Release hardware semaphore 443 * @hw: pointer to the HW structure 444 * 445 * Release hardware semaphore used to access the PHY or NVM 446 **/ 447 void e1000_put_hw_semaphore_82571(struct e1000_hw *hw) 448 { 449 u32 swsm; 450 451 DEBUGFUNC("e1000_put_hw_semaphore_82571"); 452 453 swsm = E1000_READ_REG(hw, E1000_SWSM); 454 455 swsm &= ~E1000_SWSM_SWESMBI; 456 457 E1000_WRITE_REG(hw, E1000_SWSM, swsm); 458 } 459 460 /** 461 * e1000_acquire_nvm_82571 - Request for access to the EEPROM 462 * @hw: pointer to the HW structure 463 * 464 * To gain access to the EEPROM, first we must obtain a hardware semaphore. 465 * Then for non-82573 hardware, set the EEPROM access request bit and wait 466 * for EEPROM access grant bit. If the access grant bit is not set, release 467 * hardware semaphore. 468 **/ 469 STATIC s32 e1000_acquire_nvm_82571(struct e1000_hw *hw) 470 { 471 s32 ret_val; 472 473 DEBUGFUNC("e1000_acquire_nvm_82571"); 474 475 ret_val = e1000_get_hw_semaphore_82571(hw); 476 if (ret_val) 477 goto out; 478 479 if (hw->mac.type != e1000_82573) 480 ret_val = e1000_acquire_nvm_generic(hw); 481 482 if (ret_val) 483 e1000_put_hw_semaphore_82571(hw); 484 485 out: 486 return ret_val; 487 } 488 489 /** 490 * e1000_release_nvm_82571 - Release exclusive access to EEPROM 491 * @hw: pointer to the HW structure 492 * 493 * Stop any current commands to the EEPROM and clear the EEPROM request bit. 494 **/ 495 STATIC void e1000_release_nvm_82571(struct e1000_hw *hw) 496 { 497 DEBUGFUNC("e1000_release_nvm_82571"); 498 499 e1000_release_nvm_generic(hw); 500 e1000_put_hw_semaphore_82571(hw); 501 } 502 503 /** 504 * e1000_write_nvm_82571 - Write to EEPROM using appropriate interface 505 * @hw: pointer to the HW structure 506 * @offset: offset within the EEPROM to be written to 507 * @words: number of words to write 508 * @data: 16 bit word(s) to be written to the EEPROM 509 * 510 * For non-82573 silicon, write data to EEPROM at offset using SPI interface. 511 * 512 * If e1000_update_nvm_checksum is not called after this function, the 513 * EEPROM will most likley contain an invalid checksum. 514 **/ 515 STATIC s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, u16 words, 516 u16 *data) 517 { 518 s32 ret_val = E1000_SUCCESS; 519 520 DEBUGFUNC("e1000_write_nvm_82571"); 521 522 switch (hw->mac.type) { 523 case e1000_82573: 524 ret_val = e1000_write_nvm_eewr_82571(hw, offset, words, data); 525 break; 526 case e1000_82571: 527 case e1000_82572: 528 ret_val = e1000_write_nvm_spi(hw, offset, words, data); 529 break; 530 default: 531 ret_val = -E1000_ERR_NVM; 532 break; 533 } 534 535 return ret_val; 536 } 537 538 /** 539 * e1000_update_nvm_checksum_82571 - Update EEPROM checksum 540 * @hw: pointer to the HW structure 541 * 542 * Updates the EEPROM checksum by reading/adding each word of the EEPROM 543 * up to the checksum. Then calculates the EEPROM checksum and writes the 544 * value to the EEPROM. 545 **/ 546 STATIC s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw) 547 { 548 u32 eecd; 549 s32 ret_val; 550 u16 i; 551 552 DEBUGFUNC("e1000_update_nvm_checksum_82571"); 553 554 ret_val = e1000_update_nvm_checksum_generic(hw); 555 if (ret_val) 556 goto out; 557 558 /* 559 * If our nvm is an EEPROM, then we're done 560 * otherwise, commit the checksum to the flash NVM. 561 */ 562 if (hw->nvm.type != e1000_nvm_flash_hw) 563 goto out; 564 565 /* Check for pending operations. */ 566 for (i = 0; i < E1000_FLASH_UPDATES; i++) { 567 msec_delay(1); 568 if ((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_FLUPD) == 0) 569 break; 570 } 571 572 if (i == E1000_FLASH_UPDATES) { 573 ret_val = -E1000_ERR_NVM; 574 goto out; 575 } 576 577 /* Reset the firmware if using STM opcode. */ 578 if ((E1000_READ_REG(hw, E1000_FLOP) & 0xFF00) == E1000_STM_OPCODE) { 579 /* 580 * The enabling of and the actual reset must be done 581 * in two write cycles. 582 */ 583 E1000_WRITE_REG(hw, E1000_HICR, E1000_HICR_FW_RESET_ENABLE); 584 E1000_WRITE_FLUSH(hw); 585 E1000_WRITE_REG(hw, E1000_HICR, E1000_HICR_FW_RESET); 586 } 587 588 /* Commit the write to flash */ 589 eecd = E1000_READ_REG(hw, E1000_EECD) | E1000_EECD_FLUPD; 590 E1000_WRITE_REG(hw, E1000_EECD, eecd); 591 592 for (i = 0; i < E1000_FLASH_UPDATES; i++) { 593 msec_delay(1); 594 if ((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_FLUPD) == 0) 595 break; 596 } 597 598 if (i == E1000_FLASH_UPDATES) { 599 ret_val = -E1000_ERR_NVM; 600 goto out; 601 } 602 603 out: 604 return ret_val; 605 } 606 607 /** 608 * e1000_validate_nvm_checksum_82571 - Validate EEPROM checksum 609 * @hw: pointer to the HW structure 610 * 611 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM 612 * and then verifies that the sum of the EEPROM is equal to 0xBABA. 613 **/ 614 STATIC s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw) 615 { 616 DEBUGFUNC("e1000_validate_nvm_checksum_82571"); 617 618 if (hw->nvm.type == e1000_nvm_flash_hw) 619 e1000_fix_nvm_checksum_82571(hw); 620 621 return e1000_validate_nvm_checksum_generic(hw); 622 } 623 624 /** 625 * e1000_write_nvm_eewr_82571 - Write to EEPROM for 82573 silicon 626 * @hw: pointer to the HW structure 627 * @offset: offset within the EEPROM to be written to 628 * @words: number of words to write 629 * @data: 16 bit word(s) to be written to the EEPROM 630 * 631 * After checking for invalid values, poll the EEPROM to ensure the previous 632 * command has completed before trying to write the next word. After write 633 * poll for completion. 634 * 635 * If e1000_update_nvm_checksum is not called after this function, the 636 * EEPROM will most likley contain an invalid checksum. 637 **/ 638 static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset, 639 u16 words, u16 *data) 640 { 641 struct e1000_nvm_info *nvm = &hw->nvm; 642 u32 i, eewr = 0; 643 s32 ret_val = 0; 644 645 DEBUGFUNC("e1000_write_nvm_eewr_82571"); 646 647 /* 648 * A check for invalid values: offset too large, too many words, 649 * and not enough words. 650 */ 651 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || 652 (words == 0)) { 653 DEBUGOUT("nvm parameter(s) out of bounds\n"); 654 ret_val = -E1000_ERR_NVM; 655 goto out; 656 } 657 658 for (i = 0; i < words; i++) { 659 eewr = (data[i] << E1000_NVM_RW_REG_DATA) | 660 ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) | 661 E1000_NVM_RW_REG_START; 662 663 ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE); 664 if (ret_val) 665 break; 666 667 E1000_WRITE_REG(hw, E1000_EEWR, eewr); 668 669 ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE); 670 if (ret_val) 671 break; 672 } 673 674 out: 675 return ret_val; 676 } 677 678 /** 679 * e1000_get_cfg_done_82571 - Poll for configuration done 680 * @hw: pointer to the HW structure 681 * 682 * Reads the management control register for the config done bit to be set. 683 **/ 684 STATIC s32 e1000_get_cfg_done_82571(struct e1000_hw *hw) 685 { 686 s32 timeout = PHY_CFG_TIMEOUT; 687 s32 ret_val = E1000_SUCCESS; 688 689 DEBUGFUNC("e1000_get_cfg_done_82571"); 690 691 while (timeout) { 692 if (E1000_READ_REG(hw, E1000_EEMNGCTL) & E1000_NVM_CFG_DONE_PORT_0) 693 break; 694 msec_delay(1); 695 timeout--; 696 } 697 if (!timeout) { 698 DEBUGOUT("MNG configuration cycle has not completed.\n"); 699 ret_val = -E1000_ERR_RESET; 700 goto out; 701 } 702 703 out: 704 return ret_val; 705 } 706 707 /** 708 * e1000_set_d0_lplu_state_82571 - Set Low Power Linkup D0 state 709 * @hw: pointer to the HW structure 710 * @active: TRUE to enable LPLU, FALSE to disable 711 * 712 * Sets the LPLU D0 state according to the active flag. When activating LPLU 713 * this function also disables smart speed and vice versa. LPLU will not be 714 * activated unless the device autonegotiation advertisement meets standards 715 * of either 10 or 10/100 or 10/100/1000 at all duplexes. This is a function 716 * pointer entry point only called by PHY setup routines. 717 **/ 718 STATIC s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active) 719 { 720 struct e1000_phy_info *phy = &hw->phy; 721 s32 ret_val; 722 u16 data; 723 724 DEBUGFUNC("e1000_set_d0_lplu_state_82571"); 725 726 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data); 727 if (ret_val) 728 goto out; 729 730 if (active) { 731 data |= IGP02E1000_PM_D0_LPLU; 732 ret_val = e1000_write_phy_reg(hw, 733 IGP02E1000_PHY_POWER_MGMT, 734 data); 735 if (ret_val) 736 goto out; 737 738 /* When LPLU is enabled, we should disable SmartSpeed */ 739 ret_val = e1000_read_phy_reg(hw, 740 IGP01E1000_PHY_PORT_CONFIG, 741 &data); 742 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 743 ret_val = e1000_write_phy_reg(hw, 744 IGP01E1000_PHY_PORT_CONFIG, 745 data); 746 if (ret_val) 747 goto out; 748 } else { 749 data &= ~IGP02E1000_PM_D0_LPLU; 750 ret_val = e1000_write_phy_reg(hw, 751 IGP02E1000_PHY_POWER_MGMT, 752 data); 753 /* 754 * LPLU and SmartSpeed are mutually exclusive. LPLU is used 755 * during Dx states where the power conservation is most 756 * important. During driver activity we should enable 757 * SmartSpeed, so performance is maintained. 758 */ 759 if (phy->smart_speed == e1000_smart_speed_on) { 760 ret_val = e1000_read_phy_reg(hw, 761 IGP01E1000_PHY_PORT_CONFIG, 762 &data); 763 if (ret_val) 764 goto out; 765 766 data |= IGP01E1000_PSCFR_SMART_SPEED; 767 ret_val = e1000_write_phy_reg(hw, 768 IGP01E1000_PHY_PORT_CONFIG, 769 data); 770 if (ret_val) 771 goto out; 772 } else if (phy->smart_speed == e1000_smart_speed_off) { 773 ret_val = e1000_read_phy_reg(hw, 774 IGP01E1000_PHY_PORT_CONFIG, 775 &data); 776 if (ret_val) 777 goto out; 778 779 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 780 ret_val = e1000_write_phy_reg(hw, 781 IGP01E1000_PHY_PORT_CONFIG, 782 data); 783 if (ret_val) 784 goto out; 785 } 786 } 787 788 out: 789 return ret_val; 790 } 791 792 /** 793 * e1000_reset_hw_82571 - Reset hardware 794 * @hw: pointer to the HW structure 795 * 796 * This resets the hardware into a known state. This is a 797 * function pointer entry point called by the api module. 798 **/ 799 STATIC s32 e1000_reset_hw_82571(struct e1000_hw *hw) 800 { 801 u32 ctrl, extcnf_ctrl, ctrl_ext, icr; 802 s32 ret_val; 803 u16 i = 0; 804 805 DEBUGFUNC("e1000_reset_hw_82571"); 806 807 /* 808 * Prevent the PCI-E bus from sticking if there is no TLP connection 809 * on the last TLP read/write transaction when MAC is reset. 810 */ 811 ret_val = e1000_disable_pcie_master_generic(hw); 812 if (ret_val) { 813 DEBUGOUT("PCI-E Master disable polling has failed.\n"); 814 } 815 816 DEBUGOUT("Masking off all interrupts\n"); 817 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 818 819 E1000_WRITE_REG(hw, E1000_RCTL, 0); 820 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); 821 E1000_WRITE_FLUSH(hw); 822 823 msec_delay(10); 824 825 /* 826 * Must acquire the MDIO ownership before MAC reset. 827 * Ownership defaults to firmware after a reset. 828 */ 829 if (hw->mac.type == e1000_82573) { 830 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); 831 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; 832 833 do { 834 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl); 835 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL); 836 837 if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP) 838 break; 839 840 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; 841 842 msec_delay(2); 843 i++; 844 } while (i < MDIO_OWNERSHIP_TIMEOUT); 845 } 846 847 ctrl = E1000_READ_REG(hw, E1000_CTRL); 848 849 DEBUGOUT("Issuing a global reset to MAC\n"); 850 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); 851 852 if (hw->nvm.type == e1000_nvm_flash_hw) { 853 usec_delay(10); 854 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 855 ctrl_ext |= E1000_CTRL_EXT_EE_RST; 856 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 857 E1000_WRITE_FLUSH(hw); 858 } 859 860 ret_val = e1000_get_auto_rd_done_generic(hw); 861 if (ret_val) 862 /* We don't want to continue accessing MAC registers. */ 863 goto out; 864 865 /* 866 * Phy configuration from NVM just starts after EECD_AUTO_RD is set. 867 * Need to wait for Phy configuration completion before accessing 868 * NVM and Phy. 869 */ 870 if (hw->mac.type == e1000_82573) 871 msec_delay(25); 872 873 /* Clear any pending interrupt events. */ 874 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 875 icr = E1000_READ_REG(hw, E1000_ICR); 876 877 e1000_check_alt_mac_addr_generic(hw); 878 879 out: 880 return ret_val; 881 } 882 883 /** 884 * e1000_init_hw_82571 - Initialize hardware 885 * @hw: pointer to the HW structure 886 * 887 * This inits the hardware readying it for operation. 888 **/ 889 STATIC s32 e1000_init_hw_82571(struct e1000_hw *hw) 890 { 891 struct e1000_mac_info *mac = &hw->mac; 892 u32 reg_data; 893 s32 ret_val; 894 u16 i, rar_count = mac->rar_entry_count; 895 896 DEBUGFUNC("e1000_init_hw_82571"); 897 898 e1000_initialize_hw_bits_82571(hw); 899 900 /* Initialize identification LED */ 901 ret_val = e1000_id_led_init_generic(hw); 902 if (ret_val) { 903 DEBUGOUT("Error initializing identification LED\n"); 904 /* This is not fatal and we should not stop init due to this */ 905 } 906 907 /* Disabling VLAN filtering */ 908 DEBUGOUT("Initializing the IEEE VLAN\n"); 909 e1000_clear_vfta(hw); 910 911 /* Setup the receive address. */ 912 /* 913 * If, however, a locally administered address was assigned to the 914 * 82571, we must reserve a RAR for it to work around an issue where 915 * resetting one port will reload the MAC on the other port. 916 */ 917 if (e1000_get_laa_state_82571(hw)) 918 rar_count--; 919 e1000_init_rx_addrs_generic(hw, rar_count); 920 921 /* Zero out the Multicast HASH table */ 922 DEBUGOUT("Zeroing the MTA\n"); 923 for (i = 0; i < mac->mta_reg_count; i++) 924 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 925 926 /* Setup link and flow control */ 927 ret_val = e1000_setup_link(hw); 928 929 /* Set the transmit descriptor write-back policy */ 930 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(0)); 931 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | 932 E1000_TXDCTL_FULL_TX_DESC_WB | 933 E1000_TXDCTL_COUNT_DESC; 934 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg_data); 935 936 /* ...for both queues. */ 937 if (mac->type != e1000_82573) { 938 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(1)); 939 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | 940 E1000_TXDCTL_FULL_TX_DESC_WB | 941 E1000_TXDCTL_COUNT_DESC; 942 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg_data); 943 } else { 944 e1000_enable_tx_pkt_filtering(hw); 945 reg_data = E1000_READ_REG(hw, E1000_GCR); 946 reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX; 947 E1000_WRITE_REG(hw, E1000_GCR, reg_data); 948 } 949 950 /* 951 * Clear all of the statistics registers (clear on read). It is 952 * important that we do this after we have tried to establish link 953 * because the symbol error count will increment wildly if there 954 * is no link. 955 */ 956 e1000_clear_hw_cntrs_82571(hw); 957 958 return ret_val; 959 } 960 961 /** 962 * e1000_initialize_hw_bits_82571 - Initialize hardware-dependent bits 963 * @hw: pointer to the HW structure 964 * 965 * Initializes required hardware-dependent bits needed for normal operation. 966 **/ 967 static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw) 968 { 969 u32 reg; 970 971 DEBUGFUNC("e1000_initialize_hw_bits_82571"); 972 973 if (hw->mac.disable_hw_init_bits) 974 goto out; 975 976 /* Transmit Descriptor Control 0 */ 977 reg = E1000_READ_REG(hw, E1000_TXDCTL(0)); 978 reg |= (1 << 22); 979 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg); 980 981 /* Transmit Descriptor Control 1 */ 982 reg = E1000_READ_REG(hw, E1000_TXDCTL(1)); 983 reg |= (1 << 22); 984 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg); 985 986 /* Transmit Arbitration Control 0 */ 987 reg = E1000_READ_REG(hw, E1000_TARC(0)); 988 reg &= ~(0xF << 27); /* 30:27 */ 989 switch (hw->mac.type) { 990 case e1000_82571: 991 case e1000_82572: 992 reg |= (1 << 23) | (1 << 24) | (1 << 25) | (1 << 26); 993 break; 994 default: 995 break; 996 } 997 E1000_WRITE_REG(hw, E1000_TARC(0), reg); 998 999 /* Transmit Arbitration Control 1 */ 1000 reg = E1000_READ_REG(hw, E1000_TARC(1)); 1001 switch (hw->mac.type) { 1002 case e1000_82571: 1003 case e1000_82572: 1004 reg &= ~((1 << 29) | (1 << 30)); 1005 reg |= (1 << 22) | (1 << 24) | (1 << 25) | (1 << 26); 1006 if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR) 1007 reg &= ~(1 << 28); 1008 else 1009 reg |= (1 << 28); 1010 E1000_WRITE_REG(hw, E1000_TARC(1), reg); 1011 break; 1012 default: 1013 break; 1014 } 1015 1016 /* Device Control */ 1017 if (hw->mac.type == e1000_82573) { 1018 reg = E1000_READ_REG(hw, E1000_CTRL); 1019 reg &= ~(1 << 29); 1020 E1000_WRITE_REG(hw, E1000_CTRL, reg); 1021 } 1022 1023 /* Extended Device Control */ 1024 if (hw->mac.type == e1000_82573) { 1025 reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 1026 reg &= ~(1 << 23); 1027 reg |= (1 << 22); 1028 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg); 1029 } 1030 1031 out: 1032 return; 1033 } 1034 1035 /** 1036 * e1000_clear_vfta_82571 - Clear VLAN filter table 1037 * @hw: pointer to the HW structure 1038 * 1039 * Clears the register array which contains the VLAN filter table by 1040 * setting all the values to 0. 1041 **/ 1042 STATIC void e1000_clear_vfta_82571(struct e1000_hw *hw) 1043 { 1044 u32 offset; 1045 u32 vfta_value = 0; 1046 u32 vfta_offset = 0; 1047 u32 vfta_bit_in_reg = 0; 1048 1049 DEBUGFUNC("e1000_clear_vfta_82571"); 1050 1051 if (hw->mac.type == e1000_82573) { 1052 if (hw->mng_cookie.vlan_id != 0) { 1053 /* 1054 * The VFTA is a 4096b bit-field, each identifying 1055 * a single VLAN ID. The following operations 1056 * determine which 32b entry (i.e. offset) into the 1057 * array we want to set the VLAN ID (i.e. bit) of 1058 * the manageability unit. 1059 */ 1060 vfta_offset = (hw->mng_cookie.vlan_id >> 1061 E1000_VFTA_ENTRY_SHIFT) & 1062 E1000_VFTA_ENTRY_MASK; 1063 vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id & 1064 E1000_VFTA_ENTRY_BIT_SHIFT_MASK); 1065 } 1066 } 1067 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { 1068 /* 1069 * If the offset we want to clear is the same offset of the 1070 * manageability VLAN ID, then clear all bits except that of 1071 * the manageability unit. 1072 */ 1073 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0; 1074 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, vfta_value); 1075 E1000_WRITE_FLUSH(hw); 1076 } 1077 } 1078 1079 /** 1080 * e1000_update_mc_addr_list_82571 - Update Multicast addresses 1081 * @hw: pointer to the HW structure 1082 * @mc_addr_list: array of multicast addresses to program 1083 * @mc_addr_count: number of multicast addresses to program 1084 * @rar_used_count: the first RAR register free to program 1085 * @rar_count: total number of supported Receive Address Registers 1086 * 1087 * Updates the Receive Address Registers and Multicast Table Array. 1088 * The caller must have a packed mc_addr_list of multicast addresses. 1089 * The parameter rar_count will usually be hw->mac.rar_entry_count 1090 * unless there are workarounds that change this. 1091 **/ 1092 STATIC void e1000_update_mc_addr_list_82571(struct e1000_hw *hw, 1093 u8 *mc_addr_list, u32 mc_addr_count, 1094 u32 rar_used_count, u32 rar_count) 1095 { 1096 DEBUGFUNC("e1000_update_mc_addr_list_82571"); 1097 1098 if (e1000_get_laa_state_82571(hw)) 1099 rar_count--; 1100 1101 e1000_update_mc_addr_list_generic(hw, mc_addr_list, mc_addr_count, 1102 rar_used_count, rar_count); 1103 } 1104 1105 /** 1106 * e1000_setup_link_82571 - Setup flow control and link settings 1107 * @hw: pointer to the HW structure 1108 * 1109 * Determines which flow control settings to use, then configures flow 1110 * control. Calls the appropriate media-specific link configuration 1111 * function. Assuming the adapter has a valid link partner, a valid link 1112 * should be established. Assumes the hardware has previously been reset 1113 * and the transmitter and receiver are not enabled. 1114 **/ 1115 STATIC s32 e1000_setup_link_82571(struct e1000_hw *hw) 1116 { 1117 DEBUGFUNC("e1000_setup_link_82571"); 1118 1119 /* 1120 * 82573 does not have a word in the NVM to determine 1121 * the default flow control setting, so we explicitly 1122 * set it to full. 1123 */ 1124 if (hw->mac.type == e1000_82573) 1125 hw->fc.type = e1000_fc_full; 1126 1127 return e1000_setup_link_generic(hw); 1128 } 1129 1130 /** 1131 * e1000_setup_copper_link_82571 - Configure copper link settings 1132 * @hw: pointer to the HW structure 1133 * 1134 * Configures the link for auto-neg or forced speed and duplex. Then we check 1135 * for link, once link is established calls to configure collision distance 1136 * and flow control are called. 1137 **/ 1138 STATIC s32 e1000_setup_copper_link_82571(struct e1000_hw *hw) 1139 { 1140 u32 ctrl, led_ctrl; 1141 s32 ret_val; 1142 1143 DEBUGFUNC("e1000_setup_copper_link_82571"); 1144 1145 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1146 ctrl |= E1000_CTRL_SLU; 1147 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1148 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1149 1150 switch (hw->phy.type) { 1151 case e1000_phy_m88: 1152 ret_val = e1000_copper_link_setup_m88(hw); 1153 break; 1154 case e1000_phy_igp_2: 1155 ret_val = e1000_copper_link_setup_igp(hw); 1156 /* Setup activity LED */ 1157 led_ctrl = E1000_READ_REG(hw, E1000_LEDCTL); 1158 led_ctrl &= IGP_ACTIVITY_LED_MASK; 1159 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 1160 E1000_WRITE_REG(hw, E1000_LEDCTL, led_ctrl); 1161 break; 1162 default: 1163 ret_val = -E1000_ERR_PHY; 1164 break; 1165 } 1166 1167 if (ret_val) 1168 goto out; 1169 1170 ret_val = e1000_setup_copper_link_generic(hw); 1171 1172 out: 1173 return ret_val; 1174 } 1175 1176 /** 1177 * e1000_setup_fiber_serdes_link_82571 - Setup link for fiber/serdes 1178 * @hw: pointer to the HW structure 1179 * 1180 * Configures collision distance and flow control for fiber and serdes links. 1181 * Upon successful setup, poll for link. 1182 **/ 1183 STATIC s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw) 1184 { 1185 DEBUGFUNC("e1000_setup_fiber_serdes_link_82571"); 1186 1187 switch (hw->mac.type) { 1188 case e1000_82571: 1189 case e1000_82572: 1190 /* 1191 * If SerDes loopback mode is entered, there is no form 1192 * of reset to take the adapter out of that mode. So we 1193 * have to explicitly take the adapter out of loopback 1194 * mode. This prevents drivers from twidling their thumbs 1195 * if another tool failed to take it out of loopback mode. 1196 */ 1197 E1000_WRITE_REG(hw, E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK); 1198 break; 1199 default: 1200 break; 1201 } 1202 1203 return e1000_setup_fiber_serdes_link_generic(hw); 1204 } 1205 1206 /** 1207 * e1000_valid_led_default_82571 - Verify a valid default LED config 1208 * @hw: pointer to the HW structure 1209 * @data: pointer to the NVM (EEPROM) 1210 * 1211 * Read the EEPROM for the current default LED configuration. If the 1212 * LED configuration is not valid, set to a valid LED configuration. 1213 **/ 1214 STATIC s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data) 1215 { 1216 s32 ret_val; 1217 1218 DEBUGFUNC("e1000_valid_led_default_82571"); 1219 1220 ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data); 1221 if (ret_val) { 1222 DEBUGOUT("NVM Read Error\n"); 1223 goto out; 1224 } 1225 1226 if (hw->mac.type == e1000_82573 && 1227 *data == ID_LED_RESERVED_F746) 1228 *data = ID_LED_DEFAULT_82573; 1229 else if (*data == ID_LED_RESERVED_0000 || 1230 *data == ID_LED_RESERVED_FFFF) 1231 *data = ID_LED_DEFAULT; 1232 out: 1233 return ret_val; 1234 } 1235 1236 /** 1237 * e1000_get_laa_state_82571 - Get locally administered address state 1238 * @hw: pointer to the HW structure 1239 * 1240 * Retrieve and return the current locally administed address state. 1241 **/ 1242 bool e1000_get_laa_state_82571(struct e1000_hw *hw) 1243 { 1244 struct e1000_dev_spec_82571 *dev_spec; 1245 bool state = FALSE; 1246 1247 DEBUGFUNC("e1000_get_laa_state_82571"); 1248 1249 if (hw->mac.type != e1000_82571) 1250 goto out; 1251 1252 dev_spec = (struct e1000_dev_spec_82571 *)hw->dev_spec; 1253 1254 state = dev_spec->laa_is_present; 1255 1256 out: 1257 return state; 1258 } 1259 1260 /** 1261 * e1000_set_laa_state_82571 - Set locally administered address state 1262 * @hw: pointer to the HW structure 1263 * @state: enable/disable locally administered address 1264 * 1265 * Enable/Disable the current locally administed address state. 1266 **/ 1267 void e1000_set_laa_state_82571(struct e1000_hw *hw, bool state) 1268 { 1269 struct e1000_dev_spec_82571 *dev_spec; 1270 1271 DEBUGFUNC("e1000_set_laa_state_82571"); 1272 1273 if (hw->mac.type != e1000_82571) 1274 goto out; 1275 1276 dev_spec = (struct e1000_dev_spec_82571 *)hw->dev_spec; 1277 1278 dev_spec->laa_is_present = state; 1279 1280 /* If workaround is activated... */ 1281 if (state) { 1282 /* 1283 * Hold a copy of the LAA in RAR[14] This is done so that 1284 * between the time RAR[0] gets clobbered and the time it 1285 * gets fixed, the actual LAA is in one of the RARs and no 1286 * incoming packets directed to this port are dropped. 1287 * Eventually the LAA will be in RAR[0] and RAR[14]. 1288 */ 1289 e1000_rar_set_generic(hw, hw->mac.addr, 1290 hw->mac.rar_entry_count - 1); 1291 } 1292 1293 out: 1294 return; 1295 } 1296 1297 /** 1298 * e1000_fix_nvm_checksum_82571 - Fix EEPROM checksum 1299 * @hw: pointer to the HW structure 1300 * 1301 * Verifies that the EEPROM has completed the update. After updating the 1302 * EEPROM, we need to check bit 15 in work 0x23 for the checksum fix. If 1303 * the checksum fix is not implemented, we need to set the bit and update 1304 * the checksum. Otherwise, if bit 15 is set and the checksum is incorrect, 1305 * we need to return bad checksum. 1306 **/ 1307 static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw) 1308 { 1309 struct e1000_nvm_info *nvm = &hw->nvm; 1310 s32 ret_val = E1000_SUCCESS; 1311 u16 data; 1312 1313 DEBUGFUNC("e1000_fix_nvm_checksum_82571"); 1314 1315 if (nvm->type != e1000_nvm_flash_hw) 1316 goto out; 1317 1318 /* 1319 * Check bit 4 of word 10h. If it is 0, firmware is done updating 1320 * 10h-12h. Checksum may need to be fixed. 1321 */ 1322 ret_val = e1000_read_nvm(hw, 0x10, 1, &data); 1323 if (ret_val) 1324 goto out; 1325 1326 if (!(data & 0x10)) { 1327 /* 1328 * Read 0x23 and check bit 15. This bit is a 1 1329 * when the checksum has already been fixed. If 1330 * the checksum is still wrong and this bit is a 1331 * 1, we need to return bad checksum. Otherwise, 1332 * we need to set this bit to a 1 and update the 1333 * checksum. 1334 */ 1335 ret_val = e1000_read_nvm(hw, 0x23, 1, &data); 1336 if (ret_val) 1337 goto out; 1338 1339 if (!(data & 0x8000)) { 1340 data |= 0x8000; 1341 ret_val = e1000_write_nvm(hw, 0x23, 1, &data); 1342 if (ret_val) 1343 goto out; 1344 ret_val = e1000_update_nvm_checksum(hw); 1345 } 1346 } 1347 1348 out: 1349 return ret_val; 1350 } 1351 1352 /** 1353 * e1000_read_mac_addr_82571 - Read device MAC address 1354 * @hw: pointer to the HW structure 1355 **/ 1356 STATIC s32 e1000_read_mac_addr_82571(struct e1000_hw *hw) 1357 { 1358 s32 ret_val = E1000_SUCCESS; 1359 1360 DEBUGFUNC("e1000_read_mac_addr_82571"); 1361 if (e1000_check_alt_mac_addr_generic(hw)) 1362 ret_val = e1000_read_mac_addr_generic(hw); 1363 1364 return ret_val; 1365 } 1366 1367 /** 1368 * e1000_clear_hw_cntrs_82571 - Clear device specific hardware counters 1369 * @hw: pointer to the HW structure 1370 * 1371 * Clears the hardware counters by reading the counter registers. 1372 **/ 1373 STATIC void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw) 1374 { 1375 volatile u32 temp; 1376 1377 DEBUGFUNC("e1000_clear_hw_cntrs_82571"); 1378 1379 e1000_clear_hw_cntrs_base_generic(hw); 1380 temp = E1000_READ_REG(hw, E1000_PRC64); 1381 temp = E1000_READ_REG(hw, E1000_PRC127); 1382 temp = E1000_READ_REG(hw, E1000_PRC255); 1383 temp = E1000_READ_REG(hw, E1000_PRC511); 1384 temp = E1000_READ_REG(hw, E1000_PRC1023); 1385 temp = E1000_READ_REG(hw, E1000_PRC1522); 1386 temp = E1000_READ_REG(hw, E1000_PTC64); 1387 temp = E1000_READ_REG(hw, E1000_PTC127); 1388 temp = E1000_READ_REG(hw, E1000_PTC255); 1389 temp = E1000_READ_REG(hw, E1000_PTC511); 1390 temp = E1000_READ_REG(hw, E1000_PTC1023); 1391 temp = E1000_READ_REG(hw, E1000_PTC1522); 1392 1393 temp = E1000_READ_REG(hw, E1000_ALGNERRC); 1394 temp = E1000_READ_REG(hw, E1000_RXERRC); 1395 temp = E1000_READ_REG(hw, E1000_TNCRS); 1396 temp = E1000_READ_REG(hw, E1000_CEXTERR); 1397 temp = E1000_READ_REG(hw, E1000_TSCTC); 1398 temp = E1000_READ_REG(hw, E1000_TSCTFC); 1399 1400 temp = E1000_READ_REG(hw, E1000_MGTPRC); 1401 temp = E1000_READ_REG(hw, E1000_MGTPDC); 1402 temp = E1000_READ_REG(hw, E1000_MGTPTC); 1403 1404 temp = E1000_READ_REG(hw, E1000_IAC); 1405 temp = E1000_READ_REG(hw, E1000_ICRXOC); 1406 1407 temp = E1000_READ_REG(hw, E1000_ICRXPTC); 1408 temp = E1000_READ_REG(hw, E1000_ICRXATC); 1409 temp = E1000_READ_REG(hw, E1000_ICTXPTC); 1410 temp = E1000_READ_REG(hw, E1000_ICTXATC); 1411 temp = E1000_READ_REG(hw, E1000_ICTXQEC); 1412 temp = E1000_READ_REG(hw, E1000_ICTXQMTC); 1413 temp = E1000_READ_REG(hw, E1000_ICRXDMTC); 1414 }
Cache object: 6434a8663b76297f3ebe408dc7927f52
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