Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/dev/em/e1000_hw.h
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1 /******************************************************************************* 2 3 Copyright (c) 2001-2007, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 *******************************************************************************/ 33 /* $FreeBSD$ */ 34 35 36 #ifndef _E1000_HW_H_ 37 #define _E1000_HW_H_ 38 39 #include "e1000_osdep.h" 40 #include "e1000_regs.h" 41 #include "e1000_defines.h" 42 43 struct e1000_hw; 44 45 #ifndef NO_82542_SUPPORT 46 #define E1000_DEV_ID_82542 0x1000 47 #endif 48 #define E1000_DEV_ID_82543GC_FIBER 0x1001 49 #define E1000_DEV_ID_82543GC_COPPER 0x1004 50 #define E1000_DEV_ID_82544EI_COPPER 0x1008 51 #define E1000_DEV_ID_82544EI_FIBER 0x1009 52 #define E1000_DEV_ID_82544GC_COPPER 0x100C 53 #define E1000_DEV_ID_82544GC_LOM 0x100D 54 #define E1000_DEV_ID_82540EM 0x100E 55 #define E1000_DEV_ID_82540EM_LOM 0x1015 56 #define E1000_DEV_ID_82540EP_LOM 0x1016 57 #define E1000_DEV_ID_82540EP 0x1017 58 #define E1000_DEV_ID_82540EP_LP 0x101E 59 #define E1000_DEV_ID_82545EM_COPPER 0x100F 60 #define E1000_DEV_ID_82545EM_FIBER 0x1011 61 #define E1000_DEV_ID_82545GM_COPPER 0x1026 62 #define E1000_DEV_ID_82545GM_FIBER 0x1027 63 #define E1000_DEV_ID_82545GM_SERDES 0x1028 64 #define E1000_DEV_ID_82546EB_COPPER 0x1010 65 #define E1000_DEV_ID_82546EB_FIBER 0x1012 66 #define E1000_DEV_ID_82546EB_QUAD_COPPER 0x101D 67 #define E1000_DEV_ID_82546GB_COPPER 0x1079 68 #define E1000_DEV_ID_82546GB_FIBER 0x107A 69 #define E1000_DEV_ID_82546GB_SERDES 0x107B 70 #define E1000_DEV_ID_82546GB_PCIE 0x108A 71 #define E1000_DEV_ID_82546GB_QUAD_COPPER 0x1099 72 #define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5 73 #define E1000_DEV_ID_82541EI 0x1013 74 #define E1000_DEV_ID_82541EI_MOBILE 0x1018 75 #define E1000_DEV_ID_82541ER_LOM 0x1014 76 #define E1000_DEV_ID_82541ER 0x1078 77 #define E1000_DEV_ID_82541GI 0x1076 78 #define E1000_DEV_ID_82541GI_LF 0x107C 79 #define E1000_DEV_ID_82541GI_MOBILE 0x1077 80 #define E1000_DEV_ID_82547EI 0x1019 81 #define E1000_DEV_ID_82547EI_MOBILE 0x101A 82 #define E1000_DEV_ID_82547GI 0x1075 83 #define E1000_DEV_ID_82571EB_COPPER 0x105E 84 #define E1000_DEV_ID_82571EB_FIBER 0x105F 85 #define E1000_DEV_ID_82571EB_SERDES 0x1060 86 #define E1000_DEV_ID_82571EB_SERDES_DUAL 0x10D9 87 #define E1000_DEV_ID_82571EB_SERDES_QUAD 0x10DA 88 #define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4 89 #define E1000_DEV_ID_82571PT_QUAD_COPPER 0x10D5 90 #define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5 91 #define E1000_DEV_ID_82571EB_QUAD_COPPER_LP 0x10BC 92 #define E1000_DEV_ID_82572EI_COPPER 0x107D 93 #define E1000_DEV_ID_82572EI_FIBER 0x107E 94 #define E1000_DEV_ID_82572EI_SERDES 0x107F 95 #define E1000_DEV_ID_82572EI 0x10B9 96 #define E1000_DEV_ID_82573E 0x108B 97 #define E1000_DEV_ID_82573E_IAMT 0x108C 98 #define E1000_DEV_ID_82573L 0x109A 99 #define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096 100 #define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098 101 #define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA 102 #define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB 103 #define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049 104 #define E1000_DEV_ID_ICH8_IGP_AMT 0x104A 105 #define E1000_DEV_ID_ICH8_IGP_C 0x104B 106 #define E1000_DEV_ID_ICH8_IFE 0x104C 107 #define E1000_DEV_ID_ICH8_IFE_GT 0x10C4 108 #define E1000_DEV_ID_ICH8_IFE_G 0x10C5 109 #define E1000_DEV_ID_ICH8_IGP_M 0x104D 110 #define E1000_DEV_ID_ICH9_IGP_AMT 0x10BD 111 #define E1000_DEV_ID_ICH9_IGP_C 0x294C 112 #define E1000_DEV_ID_ICH9_IFE 0x10C0 113 #define E1000_DEV_ID_ICH9_IFE_GT 0x10C3 114 #define E1000_DEV_ID_ICH9_IFE_G 0x10C2 115 #define E1000_DEV_ID_82575EB_COPPER 0x10A7 116 #define E1000_DEV_ID_82575EB_FIBER_SERDES 0x10A9 117 #define E1000_DEV_ID_82575GB_QUAD_COPPER 0x10D6 118 119 #define E1000_REVISION_0 0 120 #define E1000_REVISION_1 1 121 #define E1000_REVISION_2 2 122 #define E1000_REVISION_3 3 123 #define E1000_REVISION_4 4 124 125 #define E1000_FUNC_0 0 126 #define E1000_FUNC_1 1 127 128 typedef enum { 129 e1000_undefined = 0, 130 #ifndef NO_82542_SUPPORT 131 e1000_82542, 132 #endif 133 e1000_82543, 134 e1000_82544, 135 e1000_82540, 136 e1000_82545, 137 e1000_82545_rev_3, 138 e1000_82546, 139 e1000_82546_rev_3, 140 e1000_82541, 141 e1000_82541_rev_2, 142 e1000_82547, 143 e1000_82547_rev_2, 144 e1000_82571, 145 e1000_82572, 146 e1000_82573, 147 e1000_80003es2lan, 148 e1000_ich8lan, 149 e1000_ich9lan, 150 e1000_82575, 151 e1000_num_macs /* List is 1-based, so subtract 1 for true count. */ 152 } e1000_mac_type; 153 154 typedef enum { 155 e1000_media_type_unknown = 0, 156 e1000_media_type_copper = 1, 157 e1000_media_type_fiber = 2, 158 e1000_media_type_internal_serdes = 3, 159 e1000_num_media_types 160 } e1000_media_type; 161 162 typedef enum { 163 e1000_nvm_unknown = 0, 164 e1000_nvm_none, 165 e1000_nvm_eeprom_spi, 166 e1000_nvm_eeprom_microwire, 167 e1000_nvm_flash_hw, 168 e1000_nvm_flash_sw 169 } e1000_nvm_type; 170 171 typedef enum { 172 e1000_nvm_override_none = 0, 173 e1000_nvm_override_spi_small, 174 e1000_nvm_override_spi_large, 175 e1000_nvm_override_microwire_small, 176 e1000_nvm_override_microwire_large 177 } e1000_nvm_override; 178 179 typedef enum { 180 e1000_phy_unknown = 0, 181 e1000_phy_none, 182 e1000_phy_m88, 183 e1000_phy_igp, 184 e1000_phy_igp_2, 185 e1000_phy_gg82563, 186 e1000_phy_igp_3, 187 e1000_phy_ife, 188 } e1000_phy_type; 189 190 typedef enum { 191 e1000_bus_type_unknown = 0, 192 e1000_bus_type_pci, 193 e1000_bus_type_pcix, 194 e1000_bus_type_pci_express, 195 e1000_bus_type_reserved 196 } e1000_bus_type; 197 198 typedef enum { 199 e1000_bus_speed_unknown = 0, 200 e1000_bus_speed_33, 201 e1000_bus_speed_66, 202 e1000_bus_speed_100, 203 e1000_bus_speed_120, 204 e1000_bus_speed_133, 205 e1000_bus_speed_2500, 206 e1000_bus_speed_5000, 207 e1000_bus_speed_reserved 208 } e1000_bus_speed; 209 210 typedef enum { 211 e1000_bus_width_unknown = 0, 212 e1000_bus_width_pcie_x1, 213 e1000_bus_width_pcie_x2, 214 e1000_bus_width_pcie_x4 = 4, 215 e1000_bus_width_pcie_x8 = 8, 216 e1000_bus_width_32, 217 e1000_bus_width_64, 218 e1000_bus_width_reserved 219 } e1000_bus_width; 220 221 typedef enum { 222 e1000_1000t_rx_status_not_ok = 0, 223 e1000_1000t_rx_status_ok, 224 e1000_1000t_rx_status_undefined = 0xFF 225 } e1000_1000t_rx_status; 226 227 typedef enum { 228 e1000_rev_polarity_normal = 0, 229 e1000_rev_polarity_reversed, 230 e1000_rev_polarity_undefined = 0xFF 231 } e1000_rev_polarity; 232 233 typedef enum { 234 e1000_fc_none = 0, 235 e1000_fc_rx_pause, 236 e1000_fc_tx_pause, 237 e1000_fc_full, 238 e1000_fc_default = 0xFF 239 } e1000_fc_type; 240 241 typedef enum { 242 e1000_ffe_config_enabled = 0, 243 e1000_ffe_config_active, 244 e1000_ffe_config_blocked 245 } e1000_ffe_config; 246 247 typedef enum { 248 e1000_dsp_config_disabled = 0, 249 e1000_dsp_config_enabled, 250 e1000_dsp_config_activated, 251 e1000_dsp_config_undefined = 0xFF 252 } e1000_dsp_config; 253 254 /* Receive Descriptor */ 255 struct e1000_rx_desc { 256 u64 buffer_addr; /* Address of the descriptor's data buffer */ 257 u16 length; /* Length of data DMAed into data buffer */ 258 u16 csum; /* Packet checksum */ 259 u8 status; /* Descriptor status */ 260 u8 errors; /* Descriptor Errors */ 261 u16 special; 262 }; 263 264 /* Receive Descriptor - Extended */ 265 union e1000_rx_desc_extended { 266 struct { 267 u64 buffer_addr; 268 u64 reserved; 269 } read; 270 struct { 271 struct { 272 u32 mrq; /* Multiple Rx Queues */ 273 union { 274 u32 rss; /* RSS Hash */ 275 struct { 276 u16 ip_id; /* IP id */ 277 u16 csum; /* Packet Checksum */ 278 } csum_ip; 279 } hi_dword; 280 } lower; 281 struct { 282 u32 status_error; /* ext status/error */ 283 u16 length; 284 u16 vlan; /* VLAN tag */ 285 } upper; 286 } wb; /* writeback */ 287 }; 288 289 #define MAX_PS_BUFFERS 4 290 /* Receive Descriptor - Packet Split */ 291 union e1000_rx_desc_packet_split { 292 struct { 293 /* one buffer for protocol header(s), three data buffers */ 294 u64 buffer_addr[MAX_PS_BUFFERS]; 295 } read; 296 struct { 297 struct { 298 u32 mrq; /* Multiple Rx Queues */ 299 union { 300 u32 rss; /* RSS Hash */ 301 struct { 302 u16 ip_id; /* IP id */ 303 u16 csum; /* Packet Checksum */ 304 } csum_ip; 305 } hi_dword; 306 } lower; 307 struct { 308 u32 status_error; /* ext status/error */ 309 u16 length0; /* length of buffer 0 */ 310 u16 vlan; /* VLAN tag */ 311 } middle; 312 struct { 313 u16 header_status; 314 u16 length[3]; /* length of buffers 1-3 */ 315 } upper; 316 u64 reserved; 317 } wb; /* writeback */ 318 }; 319 320 /* Transmit Descriptor */ 321 struct e1000_tx_desc { 322 u64 buffer_addr; /* Address of the descriptor's data buffer */ 323 union { 324 u32 data; 325 struct { 326 u16 length; /* Data buffer length */ 327 u8 cso; /* Checksum offset */ 328 u8 cmd; /* Descriptor control */ 329 } flags; 330 } lower; 331 union { 332 u32 data; 333 struct { 334 u8 status; /* Descriptor status */ 335 u8 css; /* Checksum start */ 336 u16 special; 337 } fields; 338 } upper; 339 }; 340 341 /* Offload Context Descriptor */ 342 struct e1000_context_desc { 343 union { 344 u32 ip_config; 345 struct { 346 u8 ipcss; /* IP checksum start */ 347 u8 ipcso; /* IP checksum offset */ 348 u16 ipcse; /* IP checksum end */ 349 } ip_fields; 350 } lower_setup; 351 union { 352 u32 tcp_config; 353 struct { 354 u8 tucss; /* TCP checksum start */ 355 u8 tucso; /* TCP checksum offset */ 356 u16 tucse; /* TCP checksum end */ 357 } tcp_fields; 358 } upper_setup; 359 u32 cmd_and_length; 360 union { 361 u32 data; 362 struct { 363 u8 status; /* Descriptor status */ 364 u8 hdr_len; /* Header length */ 365 u16 mss; /* Maximum segment size */ 366 } fields; 367 } tcp_seg_setup; 368 }; 369 370 /* Offload data descriptor */ 371 struct e1000_data_desc { 372 u64 buffer_addr; /* Address of the descriptor's buffer address */ 373 union { 374 u32 data; 375 struct { 376 u16 length; /* Data buffer length */ 377 u8 typ_len_ext; 378 u8 cmd; 379 } flags; 380 } lower; 381 union { 382 u32 data; 383 struct { 384 u8 status; /* Descriptor status */ 385 u8 popts; /* Packet Options */ 386 u16 special; 387 } fields; 388 } upper; 389 }; 390 391 /* Statistics counters collected by the MAC */ 392 struct e1000_hw_stats { 393 u64 crcerrs; 394 u64 algnerrc; 395 u64 symerrs; 396 u64 rxerrc; 397 u64 mpc; 398 u64 scc; 399 u64 ecol; 400 u64 mcc; 401 u64 latecol; 402 u64 colc; 403 u64 dc; 404 u64 tncrs; 405 u64 sec; 406 u64 cexterr; 407 u64 rlec; 408 u64 xonrxc; 409 u64 xontxc; 410 u64 xoffrxc; 411 u64 xofftxc; 412 u64 fcruc; 413 u64 prc64; 414 u64 prc127; 415 u64 prc255; 416 u64 prc511; 417 u64 prc1023; 418 u64 prc1522; 419 u64 gprc; 420 u64 bprc; 421 u64 mprc; 422 u64 gptc; 423 u64 gorc; 424 u64 gotc; 425 u64 rnbc; 426 u64 ruc; 427 u64 rfc; 428 u64 roc; 429 u64 rjc; 430 u64 mgprc; 431 u64 mgpdc; 432 u64 mgptc; 433 u64 tor; 434 u64 tot; 435 u64 tpr; 436 u64 tpt; 437 u64 ptc64; 438 u64 ptc127; 439 u64 ptc255; 440 u64 ptc511; 441 u64 ptc1023; 442 u64 ptc1522; 443 u64 mptc; 444 u64 bptc; 445 u64 tsctc; 446 u64 tsctfc; 447 u64 iac; 448 u64 icrxptc; 449 u64 icrxatc; 450 u64 ictxptc; 451 u64 ictxatc; 452 u64 ictxqec; 453 u64 ictxqmtc; 454 u64 icrxdmtc; 455 u64 icrxoc; 456 u64 cbtmpc; 457 u64 htdpmc; 458 u64 cbrdpc; 459 u64 cbrmpc; 460 u64 rpthc; 461 u64 hgptc; 462 u64 htcbdpc; 463 u64 hgorc; 464 u64 hgotc; 465 u64 lenerrs; 466 u64 scvpc; 467 u64 hrmpc; 468 }; 469 470 struct e1000_phy_stats { 471 u32 idle_errors; 472 u32 receive_errors; 473 }; 474 475 struct e1000_host_mng_dhcp_cookie { 476 u32 signature; 477 u8 status; 478 u8 reserved0; 479 u16 vlan_id; 480 u32 reserved1; 481 u16 reserved2; 482 u8 reserved3; 483 u8 checksum; 484 }; 485 486 /* Host Interface "Rev 1" */ 487 struct e1000_host_command_header { 488 u8 command_id; 489 u8 command_length; 490 u8 command_options; 491 u8 checksum; 492 }; 493 494 #define E1000_HI_MAX_DATA_LENGTH 252 495 struct e1000_host_command_info { 496 struct e1000_host_command_header command_header; 497 u8 command_data[E1000_HI_MAX_DATA_LENGTH]; 498 }; 499 500 /* Host Interface "Rev 2" */ 501 struct e1000_host_mng_command_header { 502 u8 command_id; 503 u8 checksum; 504 u16 reserved1; 505 u16 reserved2; 506 u16 command_length; 507 }; 508 509 #define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8 510 struct e1000_host_mng_command_info { 511 struct e1000_host_mng_command_header command_header; 512 u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH]; 513 }; 514 515 #include "e1000_mac.h" 516 #include "e1000_phy.h" 517 #include "e1000_nvm.h" 518 #include "e1000_manage.h" 519 520 struct e1000_functions { 521 /* Function pointers for the MAC. */ 522 s32 (*init_mac_params)(struct e1000_hw *); 523 s32 (*blink_led)(struct e1000_hw *); 524 s32 (*check_for_link)(struct e1000_hw *); 525 bool (*check_mng_mode)(struct e1000_hw *hw); 526 s32 (*cleanup_led)(struct e1000_hw *); 527 void (*clear_hw_cntrs)(struct e1000_hw *); 528 void (*clear_vfta)(struct e1000_hw *); 529 s32 (*get_bus_info)(struct e1000_hw *); 530 s32 (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *); 531 s32 (*led_on)(struct e1000_hw *); 532 s32 (*led_off)(struct e1000_hw *); 533 void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32, u32, 534 u32); 535 void (*remove_device)(struct e1000_hw *); 536 s32 (*reset_hw)(struct e1000_hw *); 537 s32 (*init_hw)(struct e1000_hw *); 538 s32 (*setup_link)(struct e1000_hw *); 539 s32 (*setup_physical_interface)(struct e1000_hw *); 540 s32 (*setup_led)(struct e1000_hw *); 541 void (*write_vfta)(struct e1000_hw *, u32, u32); 542 void (*mta_set)(struct e1000_hw *, u32); 543 void (*config_collision_dist)(struct e1000_hw*); 544 void (*rar_set)(struct e1000_hw*, u8*, u32); 545 s32 (*read_mac_addr)(struct e1000_hw*); 546 s32 (*validate_mdi_setting)(struct e1000_hw*); 547 s32 (*mng_host_if_write)(struct e1000_hw*, u8*, u16, u16, u8*); 548 s32 (*mng_write_cmd_header)(struct e1000_hw *hw, 549 struct e1000_host_mng_command_header*); 550 s32 (*mng_enable_host_if)(struct e1000_hw*); 551 s32 (*wait_autoneg)(struct e1000_hw*); 552 553 /* Function pointers for the PHY. */ 554 s32 (*init_phy_params)(struct e1000_hw *); 555 s32 (*acquire_phy)(struct e1000_hw *); 556 s32 (*check_polarity)(struct e1000_hw *); 557 s32 (*check_reset_block)(struct e1000_hw *); 558 s32 (*commit_phy)(struct e1000_hw *); 559 s32 (*force_speed_duplex)(struct e1000_hw *); 560 s32 (*get_cfg_done)(struct e1000_hw *hw); 561 s32 (*get_cable_length)(struct e1000_hw *); 562 s32 (*get_phy_info)(struct e1000_hw *); 563 s32 (*read_phy_reg)(struct e1000_hw *, u32, u16 *); 564 void (*release_phy)(struct e1000_hw *); 565 s32 (*reset_phy)(struct e1000_hw *); 566 s32 (*set_d0_lplu_state)(struct e1000_hw *, bool); 567 s32 (*set_d3_lplu_state)(struct e1000_hw *, bool); 568 s32 (*write_phy_reg)(struct e1000_hw *, u32, u16); 569 570 /* Function pointers for the NVM. */ 571 s32 (*init_nvm_params)(struct e1000_hw *); 572 s32 (*acquire_nvm)(struct e1000_hw *); 573 s32 (*read_nvm)(struct e1000_hw *, u16, u16, u16 *); 574 void (*release_nvm)(struct e1000_hw *); 575 void (*reload_nvm)(struct e1000_hw *); 576 s32 (*update_nvm)(struct e1000_hw *); 577 s32 (*valid_led_default)(struct e1000_hw *, u16 *); 578 s32 (*validate_nvm)(struct e1000_hw *); 579 s32 (*write_nvm)(struct e1000_hw *, u16, u16, u16 *); 580 }; 581 582 struct e1000_mac_info { 583 u8 addr[6]; 584 u8 perm_addr[6]; 585 586 e1000_mac_type type; 587 588 u32 collision_delta; 589 u32 ledctl_default; 590 u32 ledctl_mode1; 591 u32 ledctl_mode2; 592 u32 mc_filter_type; 593 u32 tx_packet_delta; 594 u32 txcw; 595 596 u16 current_ifs_val; 597 u16 ifs_max_val; 598 u16 ifs_min_val; 599 u16 ifs_ratio; 600 u16 ifs_step_size; 601 u16 mta_reg_count; 602 u16 rar_entry_count; 603 604 u8 forced_speed_duplex; 605 606 bool adaptive_ifs; 607 bool arc_subsystem_valid; 608 bool asf_firmware_present; 609 bool autoneg; 610 bool autoneg_failed; 611 bool disable_av; 612 bool disable_hw_init_bits; 613 bool get_link_status; 614 bool ifs_params_forced; 615 bool in_ifs_mode; 616 bool report_tx_early; 617 bool serdes_has_link; 618 bool tx_pkt_filtering; 619 }; 620 621 struct e1000_phy_info { 622 e1000_phy_type type; 623 624 e1000_1000t_rx_status local_rx; 625 e1000_1000t_rx_status remote_rx; 626 e1000_ms_type ms_type; 627 e1000_ms_type original_ms_type; 628 e1000_rev_polarity cable_polarity; 629 e1000_smart_speed smart_speed; 630 631 u32 addr; 632 u32 id; 633 u32 reset_delay_us; /* in usec */ 634 u32 revision; 635 636 e1000_media_type media_type; 637 638 u16 autoneg_advertised; 639 u16 autoneg_mask; 640 u16 cable_length; 641 u16 max_cable_length; 642 u16 min_cable_length; 643 644 u8 mdix; 645 646 bool disable_polarity_correction; 647 bool is_mdix; 648 bool polarity_correction; 649 bool reset_disable; 650 bool speed_downgraded; 651 bool autoneg_wait_to_complete; 652 }; 653 654 struct e1000_nvm_info { 655 e1000_nvm_type type; 656 e1000_nvm_override override; 657 658 u32 flash_bank_size; 659 u32 flash_base_addr; 660 661 u16 word_size; 662 u16 delay_usec; 663 u16 address_bits; 664 u16 opcode_bits; 665 u16 page_size; 666 }; 667 668 struct e1000_bus_info { 669 e1000_bus_type type; 670 e1000_bus_speed speed; 671 e1000_bus_width width; 672 673 u32 snoop; 674 675 u16 func; 676 u16 pci_cmd_word; 677 }; 678 679 struct e1000_fc_info { 680 u32 high_water; /* Flow control high-water mark */ 681 u32 low_water; /* Flow control low-water mark */ 682 u16 pause_time; /* Flow control pause timer */ 683 bool send_xon; /* Flow control send XON */ 684 bool strict_ieee; /* Strict IEEE mode */ 685 e1000_fc_type type; /* Type of flow control */ 686 e1000_fc_type original_type; 687 }; 688 689 struct e1000_hw { 690 void *back; 691 void *dev_spec; 692 693 u8 *hw_addr; 694 u8 *flash_address; 695 unsigned long io_base; 696 697 struct e1000_functions func; 698 struct e1000_mac_info mac; 699 struct e1000_fc_info fc; 700 struct e1000_phy_info phy; 701 struct e1000_nvm_info nvm; 702 struct e1000_bus_info bus; 703 struct e1000_host_mng_dhcp_cookie mng_cookie; 704 705 u32 dev_spec_size; 706 707 u16 device_id; 708 u16 subsystem_vendor_id; 709 u16 subsystem_device_id; 710 u16 vendor_id; 711 712 u8 revision_id; 713 }; 714 715 /* These functions must be implemented by drivers */ 716 void e1000_pci_clear_mwi(struct e1000_hw *hw); 717 void e1000_pci_set_mwi(struct e1000_hw *hw); 718 s32 e1000_alloc_zeroed_dev_spec_struct(struct e1000_hw *hw, u32 size); 719 s32 e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value); 720 void e1000_free_dev_spec_struct(struct e1000_hw *hw); 721 void e1000_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value); 722 void e1000_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value); 723 724 #endif
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