FreeBSD/Linux Kernel Cross Reference
sys/dev/em/e1000_mac.c
1 /*******************************************************************************
2
3 Copyright (c) 2001-2007, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
15
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
19
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32 *******************************************************************************/
33 /* $FreeBSD$ */
34
35
36 #include "e1000_api.h"
37 #include "e1000_mac.h"
38
39 /**
40 * e1000_remove_device_generic - Free device specific structure
41 * @hw: pointer to the HW structure
42 *
43 * If a device specific structure was allocated, this function will
44 * free it.
45 **/
46 void e1000_remove_device_generic(struct e1000_hw *hw)
47 {
48 DEBUGFUNC("e1000_remove_device_generic");
49
50 /* Freeing the dev_spec member of e1000_hw structure */
51 e1000_free_dev_spec_struct(hw);
52 }
53
54 /**
55 * e1000_get_bus_info_pci_generic - Get PCI(x) bus information
56 * @hw: pointer to the HW structure
57 *
58 * Determines and stores the system bus information for a particular
59 * network interface. The following bus information is determined and stored:
60 * bus speed, bus width, type (PCI/PCIx), and PCI(-x) function.
61 **/
62 s32 e1000_get_bus_info_pci_generic(struct e1000_hw *hw)
63 {
64 struct e1000_bus_info *bus = &hw->bus;
65 u32 status = E1000_READ_REG(hw, E1000_STATUS);
66 s32 ret_val = E1000_SUCCESS;
67 u16 pci_header_type;
68
69 DEBUGFUNC("e1000_get_bus_info_pci_generic");
70
71 /* PCI or PCI-X? */
72 bus->type = (status & E1000_STATUS_PCIX_MODE)
73 ? e1000_bus_type_pcix
74 : e1000_bus_type_pci;
75
76 /* Bus speed */
77 if (bus->type == e1000_bus_type_pci) {
78 bus->speed = (status & E1000_STATUS_PCI66)
79 ? e1000_bus_speed_66
80 : e1000_bus_speed_33;
81 } else {
82 switch (status & E1000_STATUS_PCIX_SPEED) {
83 case E1000_STATUS_PCIX_SPEED_66:
84 bus->speed = e1000_bus_speed_66;
85 break;
86 case E1000_STATUS_PCIX_SPEED_100:
87 bus->speed = e1000_bus_speed_100;
88 break;
89 case E1000_STATUS_PCIX_SPEED_133:
90 bus->speed = e1000_bus_speed_133;
91 break;
92 default:
93 bus->speed = e1000_bus_speed_reserved;
94 break;
95 }
96 }
97
98 /* Bus width */
99 bus->width = (status & E1000_STATUS_BUS64)
100 ? e1000_bus_width_64
101 : e1000_bus_width_32;
102
103 /* Which PCI(-X) function? */
104 e1000_read_pci_cfg(hw, PCI_HEADER_TYPE_REGISTER, &pci_header_type);
105 if (pci_header_type & PCI_HEADER_TYPE_MULTIFUNC)
106 bus->func = (status & E1000_STATUS_FUNC_MASK)
107 >> E1000_STATUS_FUNC_SHIFT;
108 else
109 bus->func = 0;
110
111 return ret_val;
112 }
113
114 /**
115 * e1000_get_bus_info_pcie_generic - Get PCIe bus information
116 * @hw: pointer to the HW structure
117 *
118 * Determines and stores the system bus information for a particular
119 * network interface. The following bus information is determined and stored:
120 * bus speed, bus width, type (PCIe), and PCIe function.
121 **/
122 s32 e1000_get_bus_info_pcie_generic(struct e1000_hw *hw)
123 {
124 struct e1000_bus_info *bus = &hw->bus;
125 s32 ret_val;
126 u32 status;
127 u16 pcie_link_status, pci_header_type;
128
129 DEBUGFUNC("e1000_get_bus_info_pcie_generic");
130
131 bus->type = e1000_bus_type_pci_express;
132 bus->speed = e1000_bus_speed_2500;
133
134 ret_val = e1000_read_pcie_cap_reg(hw,
135 PCIE_LINK_STATUS,
136 &pcie_link_status);
137 if (ret_val)
138 bus->width = e1000_bus_width_unknown;
139 else
140 bus->width = (e1000_bus_width)((pcie_link_status &
141 PCIE_LINK_WIDTH_MASK) >>
142 PCIE_LINK_WIDTH_SHIFT);
143
144 e1000_read_pci_cfg(hw, PCI_HEADER_TYPE_REGISTER, &pci_header_type);
145 if (pci_header_type & PCI_HEADER_TYPE_MULTIFUNC) {
146 status = E1000_READ_REG(hw, E1000_STATUS);
147 bus->func = (status & E1000_STATUS_FUNC_MASK)
148 >> E1000_STATUS_FUNC_SHIFT;
149 } else {
150 bus->func = 0;
151 }
152
153 return E1000_SUCCESS;
154 }
155
156 /**
157 * e1000_clear_vfta_generic - Clear VLAN filter table
158 * @hw: pointer to the HW structure
159 *
160 * Clears the register array which contains the VLAN filter table by
161 * setting all the values to 0.
162 **/
163 void e1000_clear_vfta_generic(struct e1000_hw *hw)
164 {
165 u32 offset;
166
167 DEBUGFUNC("e1000_clear_vfta_generic");
168
169 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
170 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0);
171 E1000_WRITE_FLUSH(hw);
172 }
173 }
174
175 /**
176 * e1000_write_vfta_generic - Write value to VLAN filter table
177 * @hw: pointer to the HW structure
178 * @offset: register offset in VLAN filter table
179 * @value: register value written to VLAN filter table
180 *
181 * Writes value at the given offset in the register array which stores
182 * the VLAN filter table.
183 **/
184 void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value)
185 {
186 DEBUGFUNC("e1000_write_vfta_generic");
187
188 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value);
189 E1000_WRITE_FLUSH(hw);
190 }
191
192 /**
193 * e1000_init_rx_addrs_generic - Initialize receive address's
194 * @hw: pointer to the HW structure
195 * @rar_count: receive address registers
196 *
197 * Setups the receive address registers by setting the base receive address
198 * register to the devices MAC address and clearing all the other receive
199 * address registers to 0.
200 **/
201 void e1000_init_rx_addrs_generic(struct e1000_hw *hw, u16 rar_count)
202 {
203 u32 i;
204
205 DEBUGFUNC("e1000_init_rx_addrs_generic");
206
207 /* Setup the receive address */
208 DEBUGOUT("Programming MAC Address into RAR[0]\n");
209
210 e1000_rar_set_generic(hw, hw->mac.addr, 0);
211
212 /* Zero out the other (rar_entry_count - 1) receive addresses */
213 DEBUGOUT1("Clearing RAR[1-%u]\n", rar_count-1);
214 for (i = 1; i < rar_count; i++) {
215 E1000_WRITE_REG_ARRAY(hw, E1000_RA, (i << 1), 0);
216 E1000_WRITE_FLUSH(hw);
217 E1000_WRITE_REG_ARRAY(hw, E1000_RA, ((i << 1) + 1), 0);
218 E1000_WRITE_FLUSH(hw);
219 }
220 }
221
222 /**
223 * e1000_check_alt_mac_addr_generic - Check for alternate MAC addr
224 * @hw: pointer to the HW structure
225 *
226 * Checks the nvm for an alternate MAC address. An alternate MAC address
227 * can be setup by pre-boot software and must be treated like a permanent
228 * address and must override the actual permanent MAC address. If an
229 * alternate MAC address is fopund it is saved in the hw struct and
230 * prgrammed into RAR0 and the cuntion returns success, otherwise the
231 * fucntion returns an error.
232 **/
233 s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw)
234 {
235 u32 i;
236 s32 ret_val = E1000_SUCCESS;
237 u16 offset, nvm_alt_mac_addr_offset, nvm_data;
238 u8 alt_mac_addr[ETH_ADDR_LEN];
239
240 DEBUGFUNC("e1000_check_alt_mac_addr_generic");
241
242 ret_val = e1000_read_nvm(hw, NVM_ALT_MAC_ADDR_PTR, 1, &nvm_alt_mac_addr_offset);
243 if (ret_val) {
244 DEBUGOUT("NVM Read Error\n");
245 goto out;
246 }
247
248 if (nvm_alt_mac_addr_offset == 0xFFFF) {
249 ret_val = -(E1000_NOT_IMPLEMENTED);
250 goto out;
251 }
252
253 if (hw->bus.func == E1000_FUNC_1)
254 nvm_alt_mac_addr_offset += ETH_ADDR_LEN/sizeof(u16);
255
256 for (i = 0; i < ETH_ADDR_LEN; i += 2) {
257 offset = nvm_alt_mac_addr_offset + (i >> 1);
258 ret_val = e1000_read_nvm(hw, offset, 1, &nvm_data);
259 if (ret_val) {
260 DEBUGOUT("NVM Read Error\n");
261 goto out;
262 }
263
264 alt_mac_addr[i] = (u8)(nvm_data & 0xFF);
265 alt_mac_addr[i + 1] = (u8)(nvm_data >> 8);
266 }
267
268 /* if multicast bit is set, the alternate address will not be used */
269 if (alt_mac_addr[0] & 0x01) {
270 ret_val = -(E1000_NOT_IMPLEMENTED);
271 goto out;
272 }
273
274 for (i = 0; i < ETH_ADDR_LEN; i++)
275 hw->mac.addr[i] = hw->mac.perm_addr[i] = alt_mac_addr[i];
276
277 e1000_rar_set(hw, hw->mac.perm_addr, 0);
278
279 out:
280 return ret_val;
281 }
282
283 /**
284 * e1000_rar_set_generic - Set receive address register
285 * @hw: pointer to the HW structure
286 * @addr: pointer to the receive address
287 * @index: receive address array register
288 *
289 * Sets the receive address array register at index to the address passed
290 * in by addr.
291 **/
292 void e1000_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index)
293 {
294 u32 rar_low, rar_high;
295
296 DEBUGFUNC("e1000_rar_set_generic");
297
298 /*
299 * HW expects these in little endian so we reverse the byte order
300 * from network order (big endian) to little endian
301 */
302 rar_low = ((u32) addr[0] |
303 ((u32) addr[1] << 8) |
304 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
305
306 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
307
308 if (!hw->mac.disable_av)
309 rar_high |= E1000_RAH_AV;
310
311 E1000_WRITE_REG_ARRAY(hw, E1000_RA, (index << 1), rar_low);
312 E1000_WRITE_REG_ARRAY(hw, E1000_RA, ((index << 1) + 1), rar_high);
313 }
314
315 /**
316 * e1000_mta_set_generic - Set multicast filter table address
317 * @hw: pointer to the HW structure
318 * @hash_value: determines the MTA register and bit to set
319 *
320 * The multicast table address is a register array of 32-bit registers.
321 * The hash_value is used to determine what register the bit is in, the
322 * current value is read, the new bit is OR'd in and the new value is
323 * written back into the register.
324 **/
325 void e1000_mta_set_generic(struct e1000_hw *hw, u32 hash_value)
326 {
327 u32 hash_bit, hash_reg, mta;
328
329 DEBUGFUNC("e1000_mta_set_generic");
330 /*
331 * The MTA is a register array of 32-bit registers. It is
332 * treated like an array of (32*mta_reg_count) bits. We want to
333 * set bit BitArray[hash_value]. So we figure out what register
334 * the bit is in, read it, OR in the new bit, then write
335 * back the new value. The (hw->mac.mta_reg_count - 1) serves as a
336 * mask to bits 31:5 of the hash value which gives us the
337 * register we're modifying. The hash bit within that register
338 * is determined by the lower 5 bits of the hash value.
339 */
340 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1);
341 hash_bit = hash_value & 0x1F;
342
343 mta = E1000_READ_REG_ARRAY(hw, E1000_MTA, hash_reg);
344
345 mta |= (1 << hash_bit);
346
347 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, hash_reg, mta);
348 E1000_WRITE_FLUSH(hw);
349 }
350
351 /**
352 * e1000_update_mc_addr_list_generic - Update Multicast addresses
353 * @hw: pointer to the HW structure
354 * @mc_addr_list: array of multicast addresses to program
355 * @mc_addr_count: number of multicast addresses to program
356 * @rar_used_count: the first RAR register free to program
357 * @rar_count: total number of supported Receive Address Registers
358 *
359 * Updates the Receive Address Registers and Multicast Table Array.
360 * The caller must have a packed mc_addr_list of multicast addresses.
361 * The parameter rar_count will usually be hw->mac.rar_entry_count
362 * unless there are workarounds that change this.
363 **/
364 void e1000_update_mc_addr_list_generic(struct e1000_hw *hw,
365 u8 *mc_addr_list, u32 mc_addr_count,
366 u32 rar_used_count, u32 rar_count)
367 {
368 u32 hash_value;
369 u32 i;
370
371 DEBUGFUNC("e1000_update_mc_addr_list_generic");
372
373 /*
374 * Load the first set of multicast addresses into the exact
375 * filters (RAR). If there are not enough to fill the RAR
376 * array, clear the filters.
377 */
378 for (i = rar_used_count; i < rar_count; i++) {
379 if (mc_addr_count) {
380 e1000_rar_set(hw, mc_addr_list, i);
381 mc_addr_count--;
382 mc_addr_list += ETH_ADDR_LEN;
383 } else {
384 E1000_WRITE_REG_ARRAY(hw, E1000_RA, i << 1, 0);
385 E1000_WRITE_FLUSH(hw);
386 E1000_WRITE_REG_ARRAY(hw, E1000_RA, (i << 1) + 1, 0);
387 E1000_WRITE_FLUSH(hw);
388 }
389 }
390
391 /* Clear the old settings from the MTA */
392 DEBUGOUT("Clearing MTA\n");
393 for (i = 0; i < hw->mac.mta_reg_count; i++) {
394 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
395 E1000_WRITE_FLUSH(hw);
396 }
397
398 /* Load any remaining multicast addresses into the hash table. */
399 for (; mc_addr_count > 0; mc_addr_count--) {
400 hash_value = e1000_hash_mc_addr(hw, mc_addr_list);
401 DEBUGOUT1("Hash value = 0x%03X\n", hash_value);
402 e1000_mta_set(hw, hash_value);
403 mc_addr_list += ETH_ADDR_LEN;
404 }
405 }
406
407 /**
408 * e1000_hash_mc_addr_generic - Generate a multicast hash value
409 * @hw: pointer to the HW structure
410 * @mc_addr: pointer to a multicast address
411 *
412 * Generates a multicast address hash value which is used to determine
413 * the multicast filter table array address and new table value. See
414 * e1000_mta_set_generic()
415 **/
416 u32 e1000_hash_mc_addr_generic(struct e1000_hw *hw, u8 *mc_addr)
417 {
418 u32 hash_value, hash_mask;
419 u8 bit_shift = 0;
420
421 DEBUGFUNC("e1000_hash_mc_addr_generic");
422
423 /* Register count multiplied by bits per register */
424 hash_mask = (hw->mac.mta_reg_count * 32) - 1;
425
426 /*
427 * For a mc_filter_type of 0, bit_shift is the number of left-shifts
428 * where 0xFF would still fall within the hash mask.
429 */
430 while (hash_mask >> bit_shift != 0xFF)
431 bit_shift++;
432
433 /*
434 * The portion of the address that is used for the hash table
435 * is determined by the mc_filter_type setting.
436 * The algorithm is such that there is a total of 8 bits of shifting.
437 * The bit_shift for a mc_filter_type of 0 represents the number of
438 * left-shifts where the MSB of mc_addr[5] would still fall within
439 * the hash_mask. Case 0 does this exactly. Since there are a total
440 * of 8 bits of shifting, then mc_addr[4] will shift right the
441 * remaining number of bits. Thus 8 - bit_shift. The rest of the
442 * cases are a variation of this algorithm...essentially raising the
443 * number of bits to shift mc_addr[5] left, while still keeping the
444 * 8-bit shifting total.
445 *
446 * For example, given the following Destination MAC Address and an
447 * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask),
448 * we can see that the bit_shift for case 0 is 4. These are the hash
449 * values resulting from each mc_filter_type...
450 * [0] [1] [2] [3] [4] [5]
451 * 01 AA 00 12 34 56
452 * LSB MSB
453 *
454 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563
455 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6
456 * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163
457 * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634
458 */
459 switch (hw->mac.mc_filter_type) {
460 default:
461 case 0:
462 break;
463 case 1:
464 bit_shift += 1;
465 break;
466 case 2:
467 bit_shift += 2;
468 break;
469 case 3:
470 bit_shift += 4;
471 break;
472 }
473
474 hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) |
475 (((u16) mc_addr[5]) << bit_shift)));
476
477 return hash_value;
478 }
479
480 /**
481 * e1000_pcix_mmrbc_workaround_generic - Fix incorrect MMRBC value
482 * @hw: pointer to the HW structure
483 *
484 * In certain situations, a system BIOS may report that the PCIx maximum
485 * memory read byte count (MMRBC) value is higher than than the actual
486 * value. We check the PCIx command regsiter with the current PCIx status
487 * regsiter.
488 **/
489 void e1000_pcix_mmrbc_workaround_generic(struct e1000_hw *hw)
490 {
491 u16 cmd_mmrbc;
492 u16 pcix_cmd;
493 u16 pcix_stat_hi_word;
494 u16 stat_mmrbc;
495
496 DEBUGFUNC("e1000_pcix_mmrbc_workaround_generic");
497
498 /* Workaround for PCI-X issue when BIOS sets MMRBC incorrectly */
499 if (hw->bus.type != e1000_bus_type_pcix)
500 return;
501
502 e1000_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd);
503 e1000_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI, &pcix_stat_hi_word);
504 cmd_mmrbc = (pcix_cmd & PCIX_COMMAND_MMRBC_MASK) >>
505 PCIX_COMMAND_MMRBC_SHIFT;
506 stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>
507 PCIX_STATUS_HI_MMRBC_SHIFT;
508 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
509 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
510 if (cmd_mmrbc > stat_mmrbc) {
511 pcix_cmd &= ~PCIX_COMMAND_MMRBC_MASK;
512 pcix_cmd |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
513 e1000_write_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd);
514 }
515 }
516
517 /**
518 * e1000_clear_hw_cntrs_base_generic - Clear base hardware counters
519 * @hw: pointer to the HW structure
520 *
521 * Clears the base hardware counters by reading the counter registers.
522 **/
523 void e1000_clear_hw_cntrs_base_generic(struct e1000_hw *hw)
524 {
525 volatile u32 temp;
526
527 DEBUGFUNC("e1000_clear_hw_cntrs_base_generic");
528
529 temp = E1000_READ_REG(hw, E1000_CRCERRS);
530 temp = E1000_READ_REG(hw, E1000_SYMERRS);
531 temp = E1000_READ_REG(hw, E1000_MPC);
532 temp = E1000_READ_REG(hw, E1000_SCC);
533 temp = E1000_READ_REG(hw, E1000_ECOL);
534 temp = E1000_READ_REG(hw, E1000_MCC);
535 temp = E1000_READ_REG(hw, E1000_LATECOL);
536 temp = E1000_READ_REG(hw, E1000_COLC);
537 temp = E1000_READ_REG(hw, E1000_DC);
538 temp = E1000_READ_REG(hw, E1000_SEC);
539 temp = E1000_READ_REG(hw, E1000_RLEC);
540 temp = E1000_READ_REG(hw, E1000_XONRXC);
541 temp = E1000_READ_REG(hw, E1000_XONTXC);
542 temp = E1000_READ_REG(hw, E1000_XOFFRXC);
543 temp = E1000_READ_REG(hw, E1000_XOFFTXC);
544 temp = E1000_READ_REG(hw, E1000_FCRUC);
545 temp = E1000_READ_REG(hw, E1000_GPRC);
546 temp = E1000_READ_REG(hw, E1000_BPRC);
547 temp = E1000_READ_REG(hw, E1000_MPRC);
548 temp = E1000_READ_REG(hw, E1000_GPTC);
549 temp = E1000_READ_REG(hw, E1000_GORCL);
550 temp = E1000_READ_REG(hw, E1000_GORCH);
551 temp = E1000_READ_REG(hw, E1000_GOTCL);
552 temp = E1000_READ_REG(hw, E1000_GOTCH);
553 temp = E1000_READ_REG(hw, E1000_RNBC);
554 temp = E1000_READ_REG(hw, E1000_RUC);
555 temp = E1000_READ_REG(hw, E1000_RFC);
556 temp = E1000_READ_REG(hw, E1000_ROC);
557 temp = E1000_READ_REG(hw, E1000_RJC);
558 temp = E1000_READ_REG(hw, E1000_TORL);
559 temp = E1000_READ_REG(hw, E1000_TORH);
560 temp = E1000_READ_REG(hw, E1000_TOTL);
561 temp = E1000_READ_REG(hw, E1000_TOTH);
562 temp = E1000_READ_REG(hw, E1000_TPR);
563 temp = E1000_READ_REG(hw, E1000_TPT);
564 temp = E1000_READ_REG(hw, E1000_MPTC);
565 temp = E1000_READ_REG(hw, E1000_BPTC);
566 }
567
568 /**
569 * e1000_check_for_copper_link_generic - Check for link (Copper)
570 * @hw: pointer to the HW structure
571 *
572 * Checks to see of the link status of the hardware has changed. If a
573 * change in link status has been detected, then we read the PHY registers
574 * to get the current speed/duplex if link exists.
575 **/
576 s32 e1000_check_for_copper_link_generic(struct e1000_hw *hw)
577 {
578 struct e1000_mac_info *mac = &hw->mac;
579 s32 ret_val;
580 bool link;
581
582 DEBUGFUNC("e1000_check_for_copper_link");
583
584 /*
585 * We only want to go out to the PHY registers to see if Auto-Neg
586 * has completed and/or if our link status has changed. The
587 * get_link_status flag is set upon receiving a Link Status
588 * Change or Rx Sequence Error interrupt.
589 */
590 if (!mac->get_link_status) {
591 ret_val = E1000_SUCCESS;
592 goto out;
593 }
594
595 /*
596 * First we want to see if the MII Status Register reports
597 * link. If so, then we want to get the current speed/duplex
598 * of the PHY.
599 */
600 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
601 if (ret_val)
602 goto out;
603
604 if (!link)
605 goto out; /* No link detected */
606
607 mac->get_link_status = FALSE;
608
609 /*
610 * Check if there was DownShift, must be checked
611 * immediately after link-up
612 */
613 e1000_check_downshift_generic(hw);
614
615 /*
616 * If we are forcing speed/duplex, then we simply return since
617 * we have already determined whether we have link or not.
618 */
619 if (!mac->autoneg) {
620 ret_val = -E1000_ERR_CONFIG;
621 goto out;
622 }
623
624 /*
625 * Auto-Neg is enabled. Auto Speed Detection takes care
626 * of MAC speed/duplex configuration. So we only need to
627 * configure Collision Distance in the MAC.
628 */
629 e1000_config_collision_dist_generic(hw);
630
631 /*
632 * Configure Flow Control now that Auto-Neg has completed.
633 * First, we need to restore the desired flow control
634 * settings because we may have had to re-autoneg with a
635 * different link partner.
636 */
637 ret_val = e1000_config_fc_after_link_up_generic(hw);
638 if (ret_val) {
639 DEBUGOUT("Error configuring flow control\n");
640 }
641
642 out:
643 return ret_val;
644 }
645
646 /**
647 * e1000_check_for_fiber_link_generic - Check for link (Fiber)
648 * @hw: pointer to the HW structure
649 *
650 * Checks for link up on the hardware. If link is not up and we have
651 * a signal, then we need to force link up.
652 **/
653 s32 e1000_check_for_fiber_link_generic(struct e1000_hw *hw)
654 {
655 struct e1000_mac_info *mac = &hw->mac;
656 u32 rxcw;
657 u32 ctrl;
658 u32 status;
659 s32 ret_val = E1000_SUCCESS;
660
661 DEBUGFUNC("e1000_check_for_fiber_link_generic");
662
663 ctrl = E1000_READ_REG(hw, E1000_CTRL);
664 status = E1000_READ_REG(hw, E1000_STATUS);
665 rxcw = E1000_READ_REG(hw, E1000_RXCW);
666
667 /*
668 * If we don't have link (auto-negotiation failed or link partner
669 * cannot auto-negotiate), the cable is plugged in (we have signal),
670 * and our link partner is not trying to auto-negotiate with us (we
671 * are receiving idles or data), we need to force link up. We also
672 * need to give auto-negotiation time to complete, in case the cable
673 * was just plugged in. The autoneg_failed flag does this.
674 */
675 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
676 if ((ctrl & E1000_CTRL_SWDPIN1) && (!(status & E1000_STATUS_LU)) &&
677 (!(rxcw & E1000_RXCW_C))) {
678 if (mac->autoneg_failed == 0) {
679 mac->autoneg_failed = 1;
680 goto out;
681 }
682 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n");
683
684 /* Disable auto-negotiation in the TXCW register */
685 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE));
686
687 /* Force link-up and also force full-duplex. */
688 ctrl = E1000_READ_REG(hw, E1000_CTRL);
689 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
690 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
691
692 /* Configure Flow Control after forcing link up. */
693 ret_val = e1000_config_fc_after_link_up_generic(hw);
694 if (ret_val) {
695 DEBUGOUT("Error configuring flow control\n");
696 goto out;
697 }
698 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
699 /*
700 * If we are forcing link and we are receiving /C/ ordered
701 * sets, re-enable auto-negotiation in the TXCW register
702 * and disable forced link in the Device Control register
703 * in an attempt to auto-negotiate with our link partner.
704 */
705 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n");
706 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
707 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU));
708
709 mac->serdes_has_link = TRUE;
710 }
711
712 out:
713 return ret_val;
714 }
715
716 /**
717 * e1000_check_for_serdes_link_generic - Check for link (Serdes)
718 * @hw: pointer to the HW structure
719 *
720 * Checks for link up on the hardware. If link is not up and we have
721 * a signal, then we need to force link up.
722 **/
723 s32 e1000_check_for_serdes_link_generic(struct e1000_hw *hw)
724 {
725 struct e1000_mac_info *mac = &hw->mac;
726 u32 rxcw;
727 u32 ctrl;
728 u32 status;
729 s32 ret_val = E1000_SUCCESS;
730
731 DEBUGFUNC("e1000_check_for_serdes_link_generic");
732
733 ctrl = E1000_READ_REG(hw, E1000_CTRL);
734 status = E1000_READ_REG(hw, E1000_STATUS);
735 rxcw = E1000_READ_REG(hw, E1000_RXCW);
736
737 /*
738 * If we don't have link (auto-negotiation failed or link partner
739 * cannot auto-negotiate), and our link partner is not trying to
740 * auto-negotiate with us (we are receiving idles or data),
741 * we need to force link up. We also need to give auto-negotiation
742 * time to complete.
743 */
744 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
745 if ((!(status & E1000_STATUS_LU)) && (!(rxcw & E1000_RXCW_C))) {
746 if (mac->autoneg_failed == 0) {
747 mac->autoneg_failed = 1;
748 goto out;
749 }
750 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n");
751
752 /* Disable auto-negotiation in the TXCW register */
753 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE));
754
755 /* Force link-up and also force full-duplex. */
756 ctrl = E1000_READ_REG(hw, E1000_CTRL);
757 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
758 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
759
760 /* Configure Flow Control after forcing link up. */
761 ret_val = e1000_config_fc_after_link_up_generic(hw);
762 if (ret_val) {
763 DEBUGOUT("Error configuring flow control\n");
764 goto out;
765 }
766 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
767 /*
768 * If we are forcing link and we are receiving /C/ ordered
769 * sets, re-enable auto-negotiation in the TXCW register
770 * and disable forced link in the Device Control register
771 * in an attempt to auto-negotiate with our link partner.
772 */
773 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n");
774 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
775 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU));
776
777 mac->serdes_has_link = TRUE;
778 } else if (!(E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW))) {
779 /*
780 * If we force link for non-auto-negotiation switch, check
781 * link status based on MAC synchronization for internal
782 * serdes media type.
783 */
784 /* SYNCH bit and IV bit are sticky. */
785 usec_delay(10);
786 if (E1000_RXCW_SYNCH & E1000_READ_REG(hw, E1000_RXCW)) {
787 if (!(rxcw & E1000_RXCW_IV)) {
788 mac->serdes_has_link = TRUE;
789 DEBUGOUT("SERDES: Link is up.\n");
790 }
791 } else {
792 mac->serdes_has_link = FALSE;
793 DEBUGOUT("SERDES: Link is down.\n");
794 }
795 }
796
797 if (E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW)) {
798 status = E1000_READ_REG(hw, E1000_STATUS);
799 mac->serdes_has_link = (status & E1000_STATUS_LU)
800 ? TRUE
801 : FALSE;
802 }
803
804 out:
805 return ret_val;
806 }
807
808 /**
809 * e1000_setup_link_generic - Setup flow control and link settings
810 * @hw: pointer to the HW structure
811 *
812 * Determines which flow control settings to use, then configures flow
813 * control. Calls the appropriate media-specific link configuration
814 * function. Assuming the adapter has a valid link partner, a valid link
815 * should be established. Assumes the hardware has previously been reset
816 * and the transmitter and receiver are not enabled.
817 **/
818 s32 e1000_setup_link_generic(struct e1000_hw *hw)
819 {
820 struct e1000_functions *func = &hw->func;
821 s32 ret_val = E1000_SUCCESS;
822
823 DEBUGFUNC("e1000_setup_link_generic");
824
825 /*
826 * In the case of the phy reset being blocked, we already have a link.
827 * We do not need to set it up again.
828 */
829 if (e1000_check_reset_block(hw))
830 goto out;
831
832 ret_val = e1000_set_default_fc_generic(hw);
833 if (ret_val)
834 goto out;
835
836 /*
837 * We want to save off the original Flow Control configuration just
838 * in case we get disconnected and then reconnected into a different
839 * hub or switch with different Flow Control capabilities.
840 */
841 hw->fc.original_type = hw->fc.type;
842
843 DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc.type);
844
845 /* Call the necessary media_type subroutine to configure the link. */
846 ret_val = func->setup_physical_interface(hw);
847 if (ret_val)
848 goto out;
849
850 /*
851 * Initialize the flow control address, type, and PAUSE timer
852 * registers to their default values. This is done even if flow
853 * control is disabled, because it does not hurt anything to
854 * initialize these registers.
855 */
856 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n");
857 E1000_WRITE_REG(hw, E1000_FCT, FLOW_CONTROL_TYPE);
858 E1000_WRITE_REG(hw, E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH);
859 E1000_WRITE_REG(hw, E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW);
860
861 E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time);
862
863 ret_val = e1000_set_fc_watermarks_generic(hw);
864
865 out:
866 return ret_val;
867 }
868
869 /**
870 * e1000_setup_fiber_serdes_link_generic - Setup link for fiber/serdes
871 * @hw: pointer to the HW structure
872 *
873 * Configures collision distance and flow control for fiber and serdes
874 * links. Upon successful setup, poll for link.
875 **/
876 s32 e1000_setup_fiber_serdes_link_generic(struct e1000_hw *hw)
877 {
878 u32 ctrl;
879 s32 ret_val = E1000_SUCCESS;
880
881 DEBUGFUNC("e1000_setup_fiber_serdes_link_generic");
882
883 ctrl = E1000_READ_REG(hw, E1000_CTRL);
884
885 /* Take the link out of reset */
886 ctrl &= ~E1000_CTRL_LRST;
887
888 e1000_config_collision_dist_generic(hw);
889
890 ret_val = e1000_commit_fc_settings_generic(hw);
891 if (ret_val)
892 goto out;
893
894 /*
895 * Since auto-negotiation is enabled, take the link out of reset (the
896 * link will be in reset, because we previously reset the chip). This
897 * will restart auto-negotiation. If auto-negotiation is successful
898 * then the link-up status bit will be set and the flow control enable
899 * bits (RFCE and TFCE) will be set according to their negotiated value.
900 */
901 DEBUGOUT("Auto-negotiation enabled\n");
902
903 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
904 E1000_WRITE_FLUSH(hw);
905 msec_delay(1);
906
907 /*
908 * For these adapters, the SW defineable pin 1 is set when the optics
909 * detect a signal. If we have a signal, then poll for a "Link-Up"
910 * indication.
911 */
912 if (hw->phy.media_type == e1000_media_type_internal_serdes ||
913 (E1000_READ_REG(hw, E1000_CTRL) & E1000_CTRL_SWDPIN1)) {
914 ret_val = e1000_poll_fiber_serdes_link_generic(hw);
915 } else {
916 DEBUGOUT("No signal detected\n");
917 }
918
919 out:
920 return ret_val;
921 }
922
923 /**
924 * e1000_config_collision_dist_generic - Configure collision distance
925 * @hw: pointer to the HW structure
926 *
927 * Configures the collision distance to the default value and is used
928 * during link setup. Currently no func pointer exists and all
929 * implementations are handled in the generic version of this function.
930 **/
931 void e1000_config_collision_dist_generic(struct e1000_hw *hw)
932 {
933 u32 tctl;
934
935 DEBUGFUNC("e1000_config_collision_dist_generic");
936
937 tctl = E1000_READ_REG(hw, E1000_TCTL);
938
939 tctl &= ~E1000_TCTL_COLD;
940 tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT;
941
942 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
943 E1000_WRITE_FLUSH(hw);
944 }
945
946 /**
947 * e1000_poll_fiber_serdes_link_generic - Poll for link up
948 * @hw: pointer to the HW structure
949 *
950 * Polls for link up by reading the status register, if link fails to come
951 * up with auto-negotiation, then the link is forced if a signal is detected.
952 **/
953 s32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw)
954 {
955 struct e1000_mac_info *mac = &hw->mac;
956 u32 i, status;
957 s32 ret_val = E1000_SUCCESS;
958
959 DEBUGFUNC("e1000_poll_fiber_serdes_link_generic");
960
961 /*
962 * If we have a signal (the cable is plugged in, or assumed true for
963 * serdes media) then poll for a "Link-Up" indication in the Device
964 * Status Register. Time-out if a link isn't seen in 500 milliseconds
965 * seconds (Auto-negotiation should complete in less than 500
966 * milliseconds even if the other end is doing it in SW).
967 */
968 for (i = 0; i < FIBER_LINK_UP_LIMIT; i++) {
969 msec_delay(10);
970 status = E1000_READ_REG(hw, E1000_STATUS);
971 if (status & E1000_STATUS_LU)
972 break;
973 }
974 if (i == FIBER_LINK_UP_LIMIT) {
975 DEBUGOUT("Never got a valid link from auto-neg!!!\n");
976 mac->autoneg_failed = 1;
977 /*
978 * AutoNeg failed to achieve a link, so we'll call
979 * mac->check_for_link. This routine will force the
980 * link up if we detect a signal. This will allow us to
981 * communicate with non-autonegotiating link partners.
982 */
983 ret_val = e1000_check_for_link(hw);
984 if (ret_val) {
985 DEBUGOUT("Error while checking for link\n");
986 goto out;
987 }
988 mac->autoneg_failed = 0;
989 } else {
990 mac->autoneg_failed = 0;
991 DEBUGOUT("Valid Link Found\n");
992 }
993
994 out:
995 return ret_val;
996 }
997
998 /**
999 * e1000_commit_fc_settings_generic - Configure flow control
1000 * @hw: pointer to the HW structure
1001 *
1002 * Write the flow control settings to the Transmit Config Word Register (TXCW)
1003 * base on the flow control settings in e1000_mac_info.
1004 **/
1005 s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw)
1006 {
1007 struct e1000_mac_info *mac = &hw->mac;
1008 u32 txcw;
1009 s32 ret_val = E1000_SUCCESS;
1010
1011 DEBUGFUNC("e1000_commit_fc_settings_generic");
1012
1013 /*
1014 * Check for a software override of the flow control settings, and
1015 * setup the device accordingly. If auto-negotiation is enabled, then
1016 * software will have to set the "PAUSE" bits to the correct value in
1017 * the Transmit Config Word Register (TXCW) and re-start auto-
1018 * negotiation. However, if auto-negotiation is disabled, then
1019 * software will have to manually configure the two flow control enable
1020 * bits in the CTRL register.
1021 *
1022 * The possible values of the "fc" parameter are:
1023 * 0: Flow control is completely disabled
1024 * 1: Rx flow control is enabled (we can receive pause frames,
1025 * but not send pause frames).
1026 * 2: Tx flow control is enabled (we can send pause frames but we
1027 * do not support receiving pause frames).
1028 * 3: Both Rx and TX flow control (symmetric) are enabled.
1029 */
1030 switch (hw->fc.type) {
1031 case e1000_fc_none:
1032 /* Flow control completely disabled by a software over-ride. */
1033 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
1034 break;
1035 case e1000_fc_rx_pause:
1036 /*
1037 * RX Flow control is enabled and TX Flow control is disabled
1038 * by a software over-ride. Since there really isn't a way to
1039 * advertise that we are capable of RX Pause ONLY, we will
1040 * advertise that we support both symmetric and asymmetric RX
1041 * PAUSE. Later, we will disable the adapter's ability to send
1042 * PAUSE frames.
1043 */
1044 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
1045 break;
1046 case e1000_fc_tx_pause:
1047 /*
1048 * TX Flow control is enabled, and RX Flow control is disabled,
1049 * by a software over-ride.
1050 */
1051 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
1052 break;
1053 case e1000_fc_full:
1054 /*
1055 * Flow control (both RX and TX) is enabled by a software
1056 * over-ride.
1057 */
1058 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
1059 break;
1060 default:
1061 DEBUGOUT("Flow control param set incorrectly\n");
1062 ret_val = -E1000_ERR_CONFIG;
1063 goto out;
1064 break;
1065 }
1066
1067 E1000_WRITE_REG(hw, E1000_TXCW, txcw);
1068 mac->txcw = txcw;
1069
1070 out:
1071 return ret_val;
1072 }
1073
1074 /**
1075 * e1000_set_fc_watermarks_generic - Set flow control high/low watermarks
1076 * @hw: pointer to the HW structure
1077 *
1078 * Sets the flow control high/low threshold (watermark) registers. If
1079 * flow control XON frame transmission is enabled, then set XON frame
1080 * tansmission as well.
1081 **/
1082 s32 e1000_set_fc_watermarks_generic(struct e1000_hw *hw)
1083 {
1084 s32 ret_val = E1000_SUCCESS;
1085 u32 fcrtl = 0, fcrth = 0;
1086
1087 DEBUGFUNC("e1000_set_fc_watermarks_generic");
1088
1089 /*
1090 * Set the flow control receive threshold registers. Normally,
1091 * these registers will be set to a default threshold that may be
1092 * adjusted later by the driver's runtime code. However, if the
1093 * ability to transmit pause frames is not enabled, then these
1094 * registers will be set to 0.
1095 */
1096 if (hw->fc.type & e1000_fc_tx_pause) {
1097 /*
1098 * We need to set up the Receive Threshold high and low water
1099 * marks as well as (optionally) enabling the transmission of
1100 * XON frames.
1101 */
1102 fcrtl = hw->fc.low_water;
1103 if (hw->fc.send_xon)
1104 fcrtl |= E1000_FCRTL_XONE;
1105
1106 fcrth = hw->fc.high_water;
1107 }
1108 E1000_WRITE_REG(hw, E1000_FCRTL, fcrtl);
1109 E1000_WRITE_REG(hw, E1000_FCRTH, fcrth);
1110
1111 return ret_val;
1112 }
1113
1114 /**
1115 * e1000_set_default_fc_generic - Set flow control default values
1116 * @hw: pointer to the HW structure
1117 *
1118 * Read the EEPROM for the default values for flow control and store the
1119 * values.
1120 **/
1121 s32 e1000_set_default_fc_generic(struct e1000_hw *hw)
1122 {
1123 s32 ret_val = E1000_SUCCESS;
1124 u16 nvm_data;
1125
1126 DEBUGFUNC("e1000_set_default_fc_generic");
1127
1128 /*
1129 * Read and store word 0x0F of the EEPROM. This word contains bits
1130 * that determine the hardware's default PAUSE (flow control) mode,
1131 * a bit that determines whether the HW defaults to enabling or
1132 * disabling auto-negotiation, and the direction of the
1133 * SW defined pins. If there is no SW over-ride of the flow
1134 * control setting, then the variable hw->fc will
1135 * be initialized based on a value in the EEPROM.
1136 */
1137 ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &nvm_data);
1138
1139 if (ret_val) {
1140 DEBUGOUT("NVM Read Error\n");
1141 goto out;
1142 }
1143
1144 if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 0)
1145 hw->fc.type = e1000_fc_none;
1146 else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) ==
1147 NVM_WORD0F_ASM_DIR)
1148 hw->fc.type = e1000_fc_tx_pause;
1149 else
1150 hw->fc.type = e1000_fc_full;
1151
1152 out:
1153 return ret_val;
1154 }
1155
1156 /**
1157 * e1000_force_mac_fc_generic - Force the MAC's flow control settings
1158 * @hw: pointer to the HW structure
1159 *
1160 * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the
1161 * device control register to reflect the adapter settings. TFCE and RFCE
1162 * need to be explicitly set by software when a copper PHY is used because
1163 * autonegotiation is managed by the PHY rather than the MAC. Software must
1164 * also configure these bits when link is forced on a fiber connection.
1165 **/
1166 s32 e1000_force_mac_fc_generic(struct e1000_hw *hw)
1167 {
1168 u32 ctrl;
1169 s32 ret_val = E1000_SUCCESS;
1170
1171 DEBUGFUNC("e1000_force_mac_fc_generic");
1172
1173 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1174
1175 /*
1176 * Because we didn't get link via the internal auto-negotiation
1177 * mechanism (we either forced link or we got link via PHY
1178 * auto-neg), we have to manually enable/disable transmit an
1179 * receive flow control.
1180 *
1181 * The "Case" statement below enables/disable flow control
1182 * according to the "hw->fc.type" parameter.
1183 *
1184 * The possible values of the "fc" parameter are:
1185 * 0: Flow control is completely disabled
1186 * 1: Rx flow control is enabled (we can receive pause
1187 * frames but not send pause frames).
1188 * 2: Tx flow control is enabled (we can send pause frames
1189 * frames but we do not receive pause frames).
1190 * 3: Both Rx and TX flow control (symmetric) is enabled.
1191 * other: No other values should be possible at this point.
1192 */
1193 DEBUGOUT1("hw->fc.type = %u\n", hw->fc.type);
1194
1195 switch (hw->fc.type) {
1196 case e1000_fc_none:
1197 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
1198 break;
1199 case e1000_fc_rx_pause:
1200 ctrl &= (~E1000_CTRL_TFCE);
1201 ctrl |= E1000_CTRL_RFCE;
1202 break;
1203 case e1000_fc_tx_pause:
1204 ctrl &= (~E1000_CTRL_RFCE);
1205 ctrl |= E1000_CTRL_TFCE;
1206 break;
1207 case e1000_fc_full:
1208 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
1209 break;
1210 default:
1211 DEBUGOUT("Flow control param set incorrectly\n");
1212 ret_val = -E1000_ERR_CONFIG;
1213 goto out;
1214 }
1215
1216 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1217
1218 out:
1219 return ret_val;
1220 }
1221
1222 /**
1223 * e1000_config_fc_after_link_up_generic - Configures flow control after link
1224 * @hw: pointer to the HW structure
1225 *
1226 * Checks the status of auto-negotiation after link up to ensure that the
1227 * speed and duplex were not forced. If the link needed to be forced, then
1228 * flow control needs to be forced also. If auto-negotiation is enabled
1229 * and did not fail, then we configure flow control based on our link
1230 * partner.
1231 **/
1232 s32 e1000_config_fc_after_link_up_generic(struct e1000_hw *hw)
1233 {
1234 struct e1000_mac_info *mac = &hw->mac;
1235 s32 ret_val = E1000_SUCCESS;
1236 u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg;
1237 u16 speed, duplex;
1238
1239 DEBUGFUNC("e1000_config_fc_after_link_up_generic");
1240
1241 /*
1242 * Check for the case where we have fiber media and auto-neg failed
1243 * so we had to force link. In this case, we need to force the
1244 * configuration of the MAC to match the "fc" parameter.
1245 */
1246 if (mac->autoneg_failed) {
1247 if (hw->phy.media_type == e1000_media_type_fiber ||
1248 hw->phy.media_type == e1000_media_type_internal_serdes)
1249 ret_val = e1000_force_mac_fc_generic(hw);
1250 } else {
1251 if (hw->phy.media_type == e1000_media_type_copper)
1252 ret_val = e1000_force_mac_fc_generic(hw);
1253 }
1254
1255 if (ret_val) {
1256 DEBUGOUT("Error forcing flow control settings\n");
1257 goto out;
1258 }
1259
1260 /*
1261 * Check for the case where we have copper media and auto-neg is
1262 * enabled. In this case, we need to check and see if Auto-Neg
1263 * has completed, and if so, how the PHY and link partner has
1264 * flow control configured.
1265 */
1266 if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) {
1267 /*
1268 * Read the MII Status Register and check to see if AutoNeg
1269 * has completed. We read this twice because this reg has
1270 * some "sticky" (latched) bits.
1271 */
1272 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
1273 if (ret_val)
1274 goto out;
1275 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
1276 if (ret_val)
1277 goto out;
1278
1279 if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) {
1280 DEBUGOUT("Copper PHY and Auto Neg "
1281 "has not completed.\n");
1282 goto out;
1283 }
1284
1285 /*
1286 * The AutoNeg process has completed, so we now need to
1287 * read both the Auto Negotiation Advertisement
1288 * Register (Address 4) and the Auto_Negotiation Base
1289 * Page Ability Register (Address 5) to determine how
1290 * flow control was negotiated.
1291 */
1292 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV,
1293 &mii_nway_adv_reg);
1294 if (ret_val)
1295 goto out;
1296 ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY,
1297 &mii_nway_lp_ability_reg);
1298 if (ret_val)
1299 goto out;
1300
1301 /*
1302 * Two bits in the Auto Negotiation Advertisement Register
1303 * (Address 4) and two bits in the Auto Negotiation Base
1304 * Page Ability Register (Address 5) determine flow control
1305 * for both the PHY and the link partner. The following
1306 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
1307 * 1999, describes these PAUSE resolution bits and how flow
1308 * control is determined based upon these settings.
1309 * NOTE: DC = Don't Care
1310 *
1311 * LOCAL DEVICE | LINK PARTNER
1312 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
1313 *-------|---------|-------|---------|--------------------
1314 * 0 | 0 | DC | DC | e1000_fc_none
1315 * 0 | 1 | 0 | DC | e1000_fc_none
1316 * 0 | 1 | 1 | 0 | e1000_fc_none
1317 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1318 * 1 | 0 | 0 | DC | e1000_fc_none
1319 * 1 | DC | 1 | DC | e1000_fc_full
1320 * 1 | 1 | 0 | 0 | e1000_fc_none
1321 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1322 *
1323 * Are both PAUSE bits set to 1? If so, this implies
1324 * Symmetric Flow Control is enabled at both ends. The
1325 * ASM_DIR bits are irrelevant per the spec.
1326 *
1327 * For Symmetric Flow Control:
1328 *
1329 * LOCAL DEVICE | LINK PARTNER
1330 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1331 *-------|---------|-------|---------|--------------------
1332 * 1 | DC | 1 | DC | E1000_fc_full
1333 *
1334 */
1335 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1336 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
1337 /*
1338 * Now we need to check if the user selected RX ONLY
1339 * of pause frames. In this case, we had to advertise
1340 * FULL flow control because we could not advertise RX
1341 * ONLY. Hence, we must now check to see if we need to
1342 * turn OFF the TRANSMISSION of PAUSE frames.
1343 */
1344 if (hw->fc.original_type == e1000_fc_full) {
1345 hw->fc.type = e1000_fc_full;
1346 DEBUGOUT("Flow Control = FULL.\r\n");
1347 } else {
1348 hw->fc.type = e1000_fc_rx_pause;
1349 DEBUGOUT("Flow Control = "
1350 "RX PAUSE frames only.\r\n");
1351 }
1352 }
1353 /*
1354 * For receiving PAUSE frames ONLY.
1355 *
1356 * LOCAL DEVICE | LINK PARTNER
1357 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1358 *-------|---------|-------|---------|--------------------
1359 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1360 */
1361 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1362 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1363 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1364 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1365 hw->fc.type = e1000_fc_tx_pause;
1366 DEBUGOUT("Flow Control = TX PAUSE frames only.\r\n");
1367 }
1368 /*
1369 * For transmitting PAUSE frames ONLY.
1370 *
1371 * LOCAL DEVICE | LINK PARTNER
1372 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1373 *-------|---------|-------|---------|--------------------
1374 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1375 */
1376 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1377 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1378 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1379 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1380 hw->fc.type = e1000_fc_rx_pause;
1381 DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n");
1382 }
1383 /*
1384 * Per the IEEE spec, at this point flow control should be
1385 * disabled. However, we want to consider that we could
1386 * be connected to a legacy switch that doesn't advertise
1387 * desired flow control, but can be forced on the link
1388 * partner. So if we advertised no flow control, that is
1389 * what we will resolve to. If we advertised some kind of
1390 * receive capability (Rx Pause Only or Full Flow Control)
1391 * and the link partner advertised none, we will configure
1392 * ourselves to enable Rx Flow Control only. We can do
1393 * this safely for two reasons: If the link partner really
1394 * didn't want flow control enabled, and we enable Rx, no
1395 * harm done since we won't be receiving any PAUSE frames
1396 * anyway. If the intent on the link partner was to have
1397 * flow control enabled, then by us enabling RX only, we
1398 * can at least receive pause frames and process them.
1399 * This is a good idea because in most cases, since we are
1400 * predominantly a server NIC, more times than not we will
1401 * be asked to delay transmission of packets than asking
1402 * our link partner to pause transmission of frames.
1403 */
1404 else if ((hw->fc.original_type == e1000_fc_none ||
1405 hw->fc.original_type == e1000_fc_tx_pause) ||
1406 hw->fc.strict_ieee) {
1407 hw->fc.type = e1000_fc_none;
1408 DEBUGOUT("Flow Control = NONE.\r\n");
1409 } else {
1410 hw->fc.type = e1000_fc_rx_pause;
1411 DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n");
1412 }
1413
1414 /*
1415 * Now we need to do one last check... If we auto-
1416 * negotiated to HALF DUPLEX, flow control should not be
1417 * enabled per IEEE 802.3 spec.
1418 */
1419 ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
1420 if (ret_val) {
1421 DEBUGOUT("Error getting link speed and duplex\n");
1422 goto out;
1423 }
1424
1425 if (duplex == HALF_DUPLEX)
1426 hw->fc.type = e1000_fc_none;
1427
1428 /*
1429 * Now we call a subroutine to actually force the MAC
1430 * controller to use the correct flow control settings.
1431 */
1432 ret_val = e1000_force_mac_fc_generic(hw);
1433 if (ret_val) {
1434 DEBUGOUT("Error forcing flow control settings\n");
1435 goto out;
1436 }
1437 }
1438
1439 out:
1440 return ret_val;
1441 }
1442
1443 /**
1444 * e1000_get_speed_and_duplex_copper_generic - Retreive current speed/duplex
1445 * @hw: pointer to the HW structure
1446 * @speed: stores the current speed
1447 * @duplex: stores the current duplex
1448 *
1449 * Read the status register for the current speed/duplex and store the current
1450 * speed and duplex for copper connections.
1451 **/
1452 s32 e1000_get_speed_and_duplex_copper_generic(struct e1000_hw *hw, u16 *speed,
1453 u16 *duplex)
1454 {
1455 u32 status;
1456
1457 DEBUGFUNC("e1000_get_speed_and_duplex_copper_generic");
1458
1459 status = E1000_READ_REG(hw, E1000_STATUS);
1460 if (status & E1000_STATUS_SPEED_1000) {
1461 *speed = SPEED_1000;
1462 DEBUGOUT("1000 Mbs, ");
1463 } else if (status & E1000_STATUS_SPEED_100) {
1464 *speed = SPEED_100;
1465 DEBUGOUT("100 Mbs, ");
1466 } else {
1467 *speed = SPEED_10;
1468 DEBUGOUT("10 Mbs, ");
1469 }
1470
1471 if (status & E1000_STATUS_FD) {
1472 *duplex = FULL_DUPLEX;
1473 DEBUGOUT("Full Duplex\n");
1474 } else {
1475 *duplex = HALF_DUPLEX;
1476 DEBUGOUT("Half Duplex\n");
1477 }
1478
1479 return E1000_SUCCESS;
1480 }
1481
1482 /**
1483 * e1000_get_speed_and_duplex_fiber_generic - Retreive current speed/duplex
1484 * @hw: pointer to the HW structure
1485 * @speed: stores the current speed
1486 * @duplex: stores the current duplex
1487 *
1488 * Sets the speed and duplex to gigabit full duplex (the only possible option)
1489 * for fiber/serdes links.
1490 **/
1491 s32 e1000_get_speed_and_duplex_fiber_serdes_generic(struct e1000_hw *hw,
1492 u16 *speed, u16 *duplex)
1493 {
1494 DEBUGFUNC("e1000_get_speed_and_duplex_fiber_serdes_generic");
1495 UNREFERENCED_PARAMETER(hw);
1496
1497 *speed = SPEED_1000;
1498 *duplex = FULL_DUPLEX;
1499
1500 return E1000_SUCCESS;
1501 }
1502
1503 /**
1504 * e1000_get_hw_semaphore_generic - Acquire hardware semaphore
1505 * @hw: pointer to the HW structure
1506 *
1507 * Acquire the HW semaphore to access the PHY or NVM
1508 **/
1509 s32 e1000_get_hw_semaphore_generic(struct e1000_hw *hw)
1510 {
1511 u32 swsm;
1512 s32 ret_val = E1000_SUCCESS;
1513 s32 timeout = hw->nvm.word_size + 1;
1514 s32 i = 0;
1515
1516 DEBUGFUNC("e1000_get_hw_semaphore_generic");
1517
1518 /* Get the SW semaphore */
1519 while (i < timeout) {
1520 swsm = E1000_READ_REG(hw, E1000_SWSM);
1521 if (!(swsm & E1000_SWSM_SMBI))
1522 break;
1523
1524 usec_delay(50);
1525 i++;
1526 }
1527
1528 if (i == timeout) {
1529 DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
1530 ret_val = -E1000_ERR_NVM;
1531 goto out;
1532 }
1533
1534 /* Get the FW semaphore. */
1535 for (i = 0; i < timeout; i++) {
1536 swsm = E1000_READ_REG(hw, E1000_SWSM);
1537 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_SWESMBI);
1538
1539 /* Semaphore acquired if bit latched */
1540 if (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI)
1541 break;
1542
1543 usec_delay(50);
1544 }
1545
1546 if (i == timeout) {
1547 /* Release semaphores */
1548 e1000_put_hw_semaphore_generic(hw);
1549 DEBUGOUT("Driver can't access the NVM\n");
1550 ret_val = -E1000_ERR_NVM;
1551 goto out;
1552 }
1553
1554 out:
1555 return ret_val;
1556 }
1557
1558 /**
1559 * e1000_put_hw_semaphore_generic - Release hardware semaphore
1560 * @hw: pointer to the HW structure
1561 *
1562 * Release hardware semaphore used to access the PHY or NVM
1563 **/
1564 void e1000_put_hw_semaphore_generic(struct e1000_hw *hw)
1565 {
1566 u32 swsm;
1567
1568 DEBUGFUNC("e1000_put_hw_semaphore_generic");
1569
1570 swsm = E1000_READ_REG(hw, E1000_SWSM);
1571
1572 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
1573
1574 E1000_WRITE_REG(hw, E1000_SWSM, swsm);
1575 }
1576
1577 /**
1578 * e1000_get_auto_rd_done_generic - Check for auto read completion
1579 * @hw: pointer to the HW structure
1580 *
1581 * Check EEPROM for Auto Read done bit.
1582 **/
1583 s32 e1000_get_auto_rd_done_generic(struct e1000_hw *hw)
1584 {
1585 s32 i = 0;
1586 s32 ret_val = E1000_SUCCESS;
1587
1588 DEBUGFUNC("e1000_get_auto_rd_done_generic");
1589
1590 while (i < AUTO_READ_DONE_TIMEOUT) {
1591 if (E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_AUTO_RD)
1592 break;
1593 msec_delay(1);
1594 i++;
1595 }
1596
1597 if (i == AUTO_READ_DONE_TIMEOUT) {
1598 DEBUGOUT("Auto read by HW from NVM has not completed.\n");
1599 ret_val = -E1000_ERR_RESET;
1600 goto out;
1601 }
1602
1603 out:
1604 return ret_val;
1605 }
1606
1607 /**
1608 * e1000_valid_led_default_generic - Verify a valid default LED config
1609 * @hw: pointer to the HW structure
1610 * @data: pointer to the NVM (EEPROM)
1611 *
1612 * Read the EEPROM for the current default LED configuration. If the
1613 * LED configuration is not valid, set to a valid LED configuration.
1614 **/
1615 s32 e1000_valid_led_default_generic(struct e1000_hw *hw, u16 *data)
1616 {
1617 s32 ret_val;
1618
1619 DEBUGFUNC("e1000_valid_led_default_generic");
1620
1621 ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
1622 if (ret_val) {
1623 DEBUGOUT("NVM Read Error\n");
1624 goto out;
1625 }
1626
1627 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
1628 *data = ID_LED_DEFAULT;
1629
1630 out:
1631 return ret_val;
1632 }
1633
1634 /**
1635 * e1000_id_led_init_generic -
1636 * @hw: pointer to the HW structure
1637 *
1638 **/
1639 s32 e1000_id_led_init_generic(struct e1000_hw * hw)
1640 {
1641 struct e1000_mac_info *mac = &hw->mac;
1642 s32 ret_val;
1643 const u32 ledctl_mask = 0x000000FF;
1644 const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON;
1645 const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
1646 u16 data, i, temp;
1647 const u16 led_mask = 0x0F;
1648
1649 DEBUGFUNC("e1000_id_led_init_generic");
1650
1651 ret_val = hw->func.valid_led_default(hw, &data);
1652 if (ret_val)
1653 goto out;
1654
1655 mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL);
1656 mac->ledctl_mode1 = mac->ledctl_default;
1657 mac->ledctl_mode2 = mac->ledctl_default;
1658
1659 for (i = 0; i < 4; i++) {
1660 temp = (data >> (i << 2)) & led_mask;
1661 switch (temp) {
1662 case ID_LED_ON1_DEF2:
1663 case ID_LED_ON1_ON2:
1664 case ID_LED_ON1_OFF2:
1665 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
1666 mac->ledctl_mode1 |= ledctl_on << (i << 3);
1667 break;
1668 case ID_LED_OFF1_DEF2:
1669 case ID_LED_OFF1_ON2:
1670 case ID_LED_OFF1_OFF2:
1671 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
1672 mac->ledctl_mode1 |= ledctl_off << (i << 3);
1673 break;
1674 default:
1675 /* Do nothing */
1676 break;
1677 }
1678 switch (temp) {
1679 case ID_LED_DEF1_ON2:
1680 case ID_LED_ON1_ON2:
1681 case ID_LED_OFF1_ON2:
1682 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
1683 mac->ledctl_mode2 |= ledctl_on << (i << 3);
1684 break;
1685 case ID_LED_DEF1_OFF2:
1686 case ID_LED_ON1_OFF2:
1687 case ID_LED_OFF1_OFF2:
1688 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
1689 mac->ledctl_mode2 |= ledctl_off << (i << 3);
1690 break;
1691 default:
1692 /* Do nothing */
1693 break;
1694 }
1695 }
1696
1697 out:
1698 return ret_val;
1699 }
1700
1701 /**
1702 * e1000_setup_led_generic - Configures SW controllable LED
1703 * @hw: pointer to the HW structure
1704 *
1705 * This prepares the SW controllable LED for use and saves the current state
1706 * of the LED so it can be later restored.
1707 **/
1708 s32 e1000_setup_led_generic(struct e1000_hw *hw)
1709 {
1710 u32 ledctl;
1711 s32 ret_val = E1000_SUCCESS;
1712
1713 DEBUGFUNC("e1000_setup_led_generic");
1714
1715 if (hw->func.setup_led != e1000_setup_led_generic) {
1716 ret_val = -E1000_ERR_CONFIG;
1717 goto out;
1718 }
1719
1720 if (hw->phy.media_type == e1000_media_type_fiber) {
1721 ledctl = E1000_READ_REG(hw, E1000_LEDCTL);
1722 hw->mac.ledctl_default = ledctl;
1723 /* Turn off LED0 */
1724 ledctl &= ~(E1000_LEDCTL_LED0_IVRT |
1725 E1000_LEDCTL_LED0_BLINK |
1726 E1000_LEDCTL_LED0_MODE_MASK);
1727 ledctl |= (E1000_LEDCTL_MODE_LED_OFF <<
1728 E1000_LEDCTL_LED0_MODE_SHIFT);
1729 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl);
1730 } else if (hw->phy.media_type == e1000_media_type_copper) {
1731 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
1732 }
1733
1734 out:
1735 return ret_val;
1736 }
1737
1738 /**
1739 * e1000_cleanup_led_generic - Set LED config to default operation
1740 * @hw: pointer to the HW structure
1741 *
1742 * Remove the current LED configuration and set the LED configuration
1743 * to the default value, saved from the EEPROM.
1744 **/
1745 s32 e1000_cleanup_led_generic(struct e1000_hw *hw)
1746 {
1747 s32 ret_val = E1000_SUCCESS;
1748
1749 DEBUGFUNC("e1000_cleanup_led_generic");
1750
1751 if (hw->func.cleanup_led != e1000_cleanup_led_generic) {
1752 ret_val = -E1000_ERR_CONFIG;
1753 goto out;
1754 }
1755
1756 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default);
1757
1758 out:
1759 return ret_val;
1760 }
1761
1762 /**
1763 * e1000_blink_led_generic - Blink LED
1764 * @hw: pointer to the HW structure
1765 *
1766 * Blink the led's which are set to be on.
1767 **/
1768 s32 e1000_blink_led_generic(struct e1000_hw *hw)
1769 {
1770 u32 ledctl_blink = 0;
1771 u32 i;
1772
1773 DEBUGFUNC("e1000_blink_led_generic");
1774
1775 if (hw->phy.media_type == e1000_media_type_fiber) {
1776 /* always blink LED0 for PCI-E fiber */
1777 ledctl_blink = E1000_LEDCTL_LED0_BLINK |
1778 (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT);
1779 } else {
1780 /*
1781 * set the blink bit for each LED that's "on" (0x0E)
1782 * in ledctl_mode2
1783 */
1784 ledctl_blink = hw->mac.ledctl_mode2;
1785 for (i = 0; i < 4; i++)
1786 if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) ==
1787 E1000_LEDCTL_MODE_LED_ON)
1788 ledctl_blink |= (E1000_LEDCTL_LED0_BLINK <<
1789 (i * 8));
1790 }
1791
1792 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl_blink);
1793
1794 return E1000_SUCCESS;
1795 }
1796
1797 /**
1798 * e1000_led_on_generic - Turn LED on
1799 * @hw: pointer to the HW structure
1800 *
1801 * Turn LED on.
1802 **/
1803 s32 e1000_led_on_generic(struct e1000_hw *hw)
1804 {
1805 u32 ctrl;
1806
1807 DEBUGFUNC("e1000_led_on_generic");
1808
1809 switch (hw->phy.media_type) {
1810 case e1000_media_type_fiber:
1811 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1812 ctrl &= ~E1000_CTRL_SWDPIN0;
1813 ctrl |= E1000_CTRL_SWDPIO0;
1814 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1815 break;
1816 case e1000_media_type_copper:
1817 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2);
1818 break;
1819 default:
1820 break;
1821 }
1822
1823 return E1000_SUCCESS;
1824 }
1825
1826 /**
1827 * e1000_led_off_generic - Turn LED off
1828 * @hw: pointer to the HW structure
1829 *
1830 * Turn LED off.
1831 **/
1832 s32 e1000_led_off_generic(struct e1000_hw *hw)
1833 {
1834 u32 ctrl;
1835
1836 DEBUGFUNC("e1000_led_off_generic");
1837
1838 switch (hw->phy.media_type) {
1839 case e1000_media_type_fiber:
1840 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1841 ctrl |= E1000_CTRL_SWDPIN0;
1842 ctrl |= E1000_CTRL_SWDPIO0;
1843 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1844 break;
1845 case e1000_media_type_copper:
1846 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
1847 break;
1848 default:
1849 break;
1850 }
1851
1852 return E1000_SUCCESS;
1853 }
1854
1855 /**
1856 * e1000_set_pcie_no_snoop_generic - Set PCI-express capabilities
1857 * @hw: pointer to the HW structure
1858 * @no_snoop: bitmap of snoop events
1859 *
1860 * Set the PCI-express register to snoop for events enabled in 'no_snoop'.
1861 **/
1862 void e1000_set_pcie_no_snoop_generic(struct e1000_hw *hw, u32 no_snoop)
1863 {
1864 u32 gcr;
1865
1866 DEBUGFUNC("e1000_set_pcie_no_snoop_generic");
1867
1868 if (hw->bus.type != e1000_bus_type_pci_express)
1869 goto out;
1870
1871 if (no_snoop) {
1872 gcr = E1000_READ_REG(hw, E1000_GCR);
1873 gcr &= ~(PCIE_NO_SNOOP_ALL);
1874 gcr |= no_snoop;
1875 E1000_WRITE_REG(hw, E1000_GCR, gcr);
1876 }
1877 out:
1878 return;
1879 }
1880
1881 /**
1882 * e1000_disable_pcie_master_generic - Disables PCI-express master access
1883 * @hw: pointer to the HW structure
1884 *
1885 * Returns 0 (E1000_SUCCESS) if successful, else returns -10
1886 * (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not casued
1887 * the master requests to be disabled.
1888 *
1889 * Disables PCI-Express master access and verifies there are no pending
1890 * requests.
1891 **/
1892 s32 e1000_disable_pcie_master_generic(struct e1000_hw *hw)
1893 {
1894 u32 ctrl;
1895 s32 timeout = MASTER_DISABLE_TIMEOUT;
1896 s32 ret_val = E1000_SUCCESS;
1897
1898 DEBUGFUNC("e1000_disable_pcie_master_generic");
1899
1900 if (hw->bus.type != e1000_bus_type_pci_express)
1901 goto out;
1902
1903 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1904 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE;
1905 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1906
1907 while (timeout) {
1908 if (!(E1000_READ_REG(hw, E1000_STATUS) &
1909 E1000_STATUS_GIO_MASTER_ENABLE))
1910 break;
1911 usec_delay(100);
1912 timeout--;
1913 }
1914
1915 if (!timeout) {
1916 DEBUGOUT("Master requests are pending.\n");
1917 ret_val = -E1000_ERR_MASTER_REQUESTS_PENDING;
1918 goto out;
1919 }
1920
1921 out:
1922 return ret_val;
1923 }
1924
1925 /**
1926 * e1000_reset_adaptive_generic - Reset Adaptive Interframe Spacing
1927 * @hw: pointer to the HW structure
1928 *
1929 * Reset the Adaptive Interframe Spacing throttle to default values.
1930 **/
1931 void e1000_reset_adaptive_generic(struct e1000_hw *hw)
1932 {
1933 struct e1000_mac_info *mac = &hw->mac;
1934
1935 DEBUGFUNC("e1000_reset_adaptive_generic");
1936
1937 if (!mac->adaptive_ifs) {
1938 DEBUGOUT("Not in Adaptive IFS mode!\n");
1939 goto out;
1940 }
1941
1942 if (!mac->ifs_params_forced) {
1943 mac->current_ifs_val = 0;
1944 mac->ifs_min_val = IFS_MIN;
1945 mac->ifs_max_val = IFS_MAX;
1946 mac->ifs_step_size = IFS_STEP;
1947 mac->ifs_ratio = IFS_RATIO;
1948 }
1949
1950 mac->in_ifs_mode = FALSE;
1951 E1000_WRITE_REG(hw, E1000_AIT, 0);
1952 out:
1953 return;
1954 }
1955
1956 /**
1957 * e1000_update_adaptive_generic - Update Adaptive Interframe Spacing
1958 * @hw: pointer to the HW structure
1959 *
1960 * Update the Adaptive Interframe Spacing Throttle value based on the
1961 * time between transmitted packets and time between collisions.
1962 **/
1963 void e1000_update_adaptive_generic(struct e1000_hw *hw)
1964 {
1965 struct e1000_mac_info *mac = &hw->mac;
1966
1967 DEBUGFUNC("e1000_update_adaptive_generic");
1968
1969 if (!mac->adaptive_ifs) {
1970 DEBUGOUT("Not in Adaptive IFS mode!\n");
1971 goto out;
1972 }
1973
1974 if ((mac->collision_delta * mac->ifs_ratio) > mac->tx_packet_delta) {
1975 if (mac->tx_packet_delta > MIN_NUM_XMITS) {
1976 mac->in_ifs_mode = TRUE;
1977 if (mac->current_ifs_val < mac->ifs_max_val) {
1978 if (!mac->current_ifs_val)
1979 mac->current_ifs_val = mac->ifs_min_val;
1980 else
1981 mac->current_ifs_val +=
1982 mac->ifs_step_size;
1983 E1000_WRITE_REG(hw, E1000_AIT, mac->current_ifs_val);
1984 }
1985 }
1986 } else {
1987 if (mac->in_ifs_mode &&
1988 (mac->tx_packet_delta <= MIN_NUM_XMITS)) {
1989 mac->current_ifs_val = 0;
1990 mac->in_ifs_mode = FALSE;
1991 E1000_WRITE_REG(hw, E1000_AIT, 0);
1992 }
1993 }
1994 out:
1995 return;
1996 }
1997
1998 /**
1999 * e1000_validate_mdi_setting_generic - Verify MDI/MDIx settings
2000 * @hw: pointer to the HW structure
2001 *
2002 * Verify that when not using auto-negotitation that MDI/MDIx is correctly
2003 * set, which is forced to MDI mode only.
2004 **/
2005 s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw)
2006 {
2007 s32 ret_val = E1000_SUCCESS;
2008
2009 DEBUGFUNC("e1000_validate_mdi_setting_generic");
2010
2011 if (!hw->mac.autoneg && (hw->phy.mdix == 0 || hw->phy.mdix == 3)) {
2012 DEBUGOUT("Invalid MDI setting detected\n");
2013 hw->phy.mdix = 1;
2014 ret_val = -E1000_ERR_CONFIG;
2015 goto out;
2016 }
2017
2018 out:
2019 return ret_val;
2020 }
2021
2022 /**
2023 * e1000_write_8bit_ctrl_reg_generic - Write a 8bit CTRL register
2024 * @hw: pointer to the HW structure
2025 * @reg: 32bit register offset such as E1000_SCTL
2026 * @offset: register offset to write to
2027 * @data: data to write at register offset
2028 *
2029 * Writes an address/data control type register. There are several of these
2030 * and they all have the format address << 8 | data and bit 31 is polled for
2031 * completion.
2032 **/
2033 s32 e1000_write_8bit_ctrl_reg_generic(struct e1000_hw *hw, u32 reg,
2034 u32 offset, u8 data)
2035 {
2036 u32 i, regvalue = 0;
2037 s32 ret_val = E1000_SUCCESS;
2038
2039 DEBUGFUNC("e1000_write_8bit_ctrl_reg_generic");
2040
2041 /* Set up the address and data */
2042 regvalue = ((u32)data) | (offset << E1000_GEN_CTL_ADDRESS_SHIFT);
2043 E1000_WRITE_REG(hw, reg, regvalue);
2044
2045 /* Poll the ready bit to see if the MDI read completed */
2046 for (i = 0; i < E1000_GEN_POLL_TIMEOUT; i++) {
2047 usec_delay(5);
2048 regvalue = E1000_READ_REG(hw, reg);
2049 if (regvalue & E1000_GEN_CTL_READY)
2050 break;
2051 }
2052 if (!(regvalue & E1000_GEN_CTL_READY)) {
2053 DEBUGOUT1("Reg %08x did not indicate ready\n", reg);
2054 ret_val = -E1000_ERR_PHY;
2055 goto out;
2056 }
2057
2058 out:
2059 return ret_val;
2060 }
Cache object: 8efb207407fd85169e54f56c583d1727
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