FreeBSD/Linux Kernel Cross Reference
sys/dev/em/e1000_phy.c
1 /*******************************************************************************
2
3 Copyright (c) 2001-2007, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
15
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
19
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32 *******************************************************************************/
33 /* $FreeBSD$ */
34
35
36 #include "e1000_api.h"
37 #include "e1000_phy.h"
38
39 static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw);
40 STATIC void e1000_release_phy(struct e1000_hw *hw);
41 STATIC s32 e1000_acquire_phy(struct e1000_hw *hw);
42
43 /* Cable length tables */
44 static const u16 e1000_m88_cable_length_table[] =
45 { 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED };
46 #define M88E1000_CABLE_LENGTH_TABLE_SIZE \
47 (sizeof(e1000_m88_cable_length_table) / \
48 sizeof(e1000_m88_cable_length_table[0]))
49
50 static const u16 e1000_igp_2_cable_length_table[] =
51 { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21,
52 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41,
53 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61,
54 21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82,
55 40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104,
56 60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121,
57 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124,
58 104, 109, 114, 118, 121, 124};
59 #define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \
60 (sizeof(e1000_igp_2_cable_length_table) / \
61 sizeof(e1000_igp_2_cable_length_table[0]))
62
63 /**
64 * e1000_check_reset_block_generic - Check if PHY reset is blocked
65 * @hw: pointer to the HW structure
66 *
67 * Read the PHY management control register and check whether a PHY reset
68 * is blocked. If a reset is not blocked return E1000_SUCCESS, otherwise
69 * return E1000_BLK_PHY_RESET (12).
70 **/
71 s32 e1000_check_reset_block_generic(struct e1000_hw *hw)
72 {
73 u32 manc;
74
75 DEBUGFUNC("e1000_check_reset_block");
76
77 manc = E1000_READ_REG(hw, E1000_MANC);
78
79 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
80 E1000_BLK_PHY_RESET : E1000_SUCCESS;
81 }
82
83 /**
84 * e1000_get_phy_id - Retrieve the PHY ID and revision
85 * @hw: pointer to the HW structure
86 *
87 * Reads the PHY registers and stores the PHY ID and possibly the PHY
88 * revision in the hardware structure.
89 **/
90 s32 e1000_get_phy_id(struct e1000_hw *hw)
91 {
92 struct e1000_phy_info *phy = &hw->phy;
93 s32 ret_val = E1000_SUCCESS;
94 u16 phy_id;
95
96 DEBUGFUNC("e1000_get_phy_id");
97
98 ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id);
99 if (ret_val)
100 goto out;
101
102 phy->id = (u32)(phy_id << 16);
103 usec_delay(20);
104 ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id);
105 if (ret_val)
106 goto out;
107
108 phy->id |= (u32)(phy_id & PHY_REVISION_MASK);
109 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
110
111 out:
112 return ret_val;
113 }
114
115 /**
116 * e1000_phy_reset_dsp_generic - Reset PHY DSP
117 * @hw: pointer to the HW structure
118 *
119 * Reset the digital signal processor.
120 **/
121 s32 e1000_phy_reset_dsp_generic(struct e1000_hw *hw)
122 {
123 s32 ret_val;
124
125 DEBUGFUNC("e1000_phy_reset_dsp_generic");
126
127 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xC1);
128 if (ret_val)
129 goto out;
130
131 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0);
132
133 out:
134 return ret_val;
135 }
136
137 /**
138 * e1000_read_phy_reg_mdic - Read MDI control register
139 * @hw: pointer to the HW structure
140 * @offset: register offset to be read
141 * @data: pointer to the read data
142 *
143 * Reads the MDI control regsiter in the PHY at offset and stores the
144 * information read to data.
145 **/
146 STATIC s32 e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
147 {
148 struct e1000_phy_info *phy = &hw->phy;
149 u32 i, mdic = 0;
150 s32 ret_val = E1000_SUCCESS;
151
152 DEBUGFUNC("e1000_read_phy_reg_mdic");
153
154 if (offset > MAX_PHY_REG_ADDRESS) {
155 DEBUGOUT1("PHY Address %d is out of range\n", offset);
156 ret_val = -E1000_ERR_PARAM;
157 goto out;
158 }
159
160 /*
161 * Set up Op-code, Phy Address, and register offset in the MDI
162 * Control register. The MAC will take care of interfacing with the
163 * PHY to retrieve the desired data.
164 */
165 mdic = ((offset << E1000_MDIC_REG_SHIFT) |
166 (phy->addr << E1000_MDIC_PHY_SHIFT) |
167 (E1000_MDIC_OP_READ));
168
169 E1000_WRITE_REG(hw, E1000_MDIC, mdic);
170
171 /*
172 * Poll the ready bit to see if the MDI read completed
173 * Increasing the time out as testing showed failures with
174 * the lower time out
175 */
176 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
177 usec_delay(50);
178 mdic = E1000_READ_REG(hw, E1000_MDIC);
179 if (mdic & E1000_MDIC_READY)
180 break;
181 }
182 if (!(mdic & E1000_MDIC_READY)) {
183 DEBUGOUT("MDI Read did not complete\n");
184 ret_val = -E1000_ERR_PHY;
185 goto out;
186 }
187 if (mdic & E1000_MDIC_ERROR) {
188 DEBUGOUT("MDI Error\n");
189 ret_val = -E1000_ERR_PHY;
190 goto out;
191 }
192 *data = (u16) mdic;
193
194 out:
195 return ret_val;
196 }
197
198 /**
199 * e1000_write_phy_reg_mdic - Write MDI control register
200 * @hw: pointer to the HW structure
201 * @offset: register offset to write to
202 * @data: data to write to register at offset
203 *
204 * Writes data to MDI control register in the PHY at offset.
205 **/
206 STATIC s32 e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
207 {
208 struct e1000_phy_info *phy = &hw->phy;
209 u32 i, mdic = 0;
210 s32 ret_val = E1000_SUCCESS;
211
212 DEBUGFUNC("e1000_write_phy_reg_mdic");
213
214 if (offset > MAX_PHY_REG_ADDRESS) {
215 DEBUGOUT1("PHY Address %d is out of range\n", offset);
216 ret_val = -E1000_ERR_PARAM;
217 goto out;
218 }
219
220 /*
221 * Set up Op-code, Phy Address, and register offset in the MDI
222 * Control register. The MAC will take care of interfacing with the
223 * PHY to retrieve the desired data.
224 */
225 mdic = (((u32)data) |
226 (offset << E1000_MDIC_REG_SHIFT) |
227 (phy->addr << E1000_MDIC_PHY_SHIFT) |
228 (E1000_MDIC_OP_WRITE));
229
230 E1000_WRITE_REG(hw, E1000_MDIC, mdic);
231
232 /*
233 * Poll the ready bit to see if the MDI read completed
234 * Increasing the time out as testing showed failures with
235 * the lower time out
236 */
237 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
238 usec_delay(50);
239 mdic = E1000_READ_REG(hw, E1000_MDIC);
240 if (mdic & E1000_MDIC_READY)
241 break;
242 }
243 if (!(mdic & E1000_MDIC_READY)) {
244 DEBUGOUT("MDI Write did not complete\n");
245 ret_val = -E1000_ERR_PHY;
246 goto out;
247 }
248 if (mdic & E1000_MDIC_ERROR) {
249 DEBUGOUT("MDI Error\n");
250 ret_val = -E1000_ERR_PHY;
251 goto out;
252 }
253
254 out:
255 return ret_val;
256 }
257
258 /**
259 * e1000_read_phy_reg_m88 - Read m88 PHY register
260 * @hw: pointer to the HW structure
261 * @offset: register offset to be read
262 * @data: pointer to the read data
263 *
264 * Acquires semaphore, if necessary, then reads the PHY register at offset
265 * and storing the retrieved information in data. Release any acquired
266 * semaphores before exiting.
267 **/
268 s32 e1000_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data)
269 {
270 s32 ret_val;
271
272 DEBUGFUNC("e1000_read_phy_reg_m88");
273
274 ret_val = e1000_acquire_phy(hw);
275 if (ret_val)
276 goto out;
277
278 ret_val = e1000_read_phy_reg_mdic(hw,
279 MAX_PHY_REG_ADDRESS & offset,
280 data);
281
282 e1000_release_phy(hw);
283
284 out:
285 return ret_val;
286 }
287
288 /**
289 * e1000_write_phy_reg_m88 - Write m88 PHY register
290 * @hw: pointer to the HW structure
291 * @offset: register offset to write to
292 * @data: data to write at register offset
293 *
294 * Acquires semaphore, if necessary, then writes the data to PHY register
295 * at the offset. Release any acquired semaphores before exiting.
296 **/
297 s32 e1000_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data)
298 {
299 s32 ret_val;
300
301 DEBUGFUNC("e1000_write_phy_reg_m88");
302
303 ret_val = e1000_acquire_phy(hw);
304 if (ret_val)
305 goto out;
306
307 ret_val = e1000_write_phy_reg_mdic(hw,
308 MAX_PHY_REG_ADDRESS & offset,
309 data);
310
311 e1000_release_phy(hw);
312
313 out:
314 return ret_val;
315 }
316
317 /**
318 * e1000_read_phy_reg_igp - Read igp PHY register
319 * @hw: pointer to the HW structure
320 * @offset: register offset to be read
321 * @data: pointer to the read data
322 *
323 * Acquires semaphore, if necessary, then reads the PHY register at offset
324 * and storing the retrieved information in data. Release any acquired
325 * semaphores before exiting.
326 **/
327 s32 e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data)
328 {
329 s32 ret_val;
330
331 DEBUGFUNC("e1000_read_phy_reg_igp");
332
333 ret_val = e1000_acquire_phy(hw);
334 if (ret_val)
335 goto out;
336
337 if (offset > MAX_PHY_MULTI_PAGE_REG) {
338 ret_val = e1000_write_phy_reg_mdic(hw,
339 IGP01E1000_PHY_PAGE_SELECT,
340 (u16)offset);
341 if (ret_val) {
342 e1000_release_phy(hw);
343 goto out;
344 }
345 }
346
347 ret_val = e1000_read_phy_reg_mdic(hw,
348 MAX_PHY_REG_ADDRESS & offset,
349 data);
350
351 e1000_release_phy(hw);
352
353 out:
354 return ret_val;
355 }
356
357 /**
358 * e1000_write_phy_reg_igp - Write igp PHY register
359 * @hw: pointer to the HW structure
360 * @offset: register offset to write to
361 * @data: data to write at register offset
362 *
363 * Acquires semaphore, if necessary, then writes the data to PHY register
364 * at the offset. Release any acquired semaphores before exiting.
365 **/
366 s32 e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data)
367 {
368 s32 ret_val;
369
370 DEBUGFUNC("e1000_write_phy_reg_igp");
371
372 ret_val = e1000_acquire_phy(hw);
373 if (ret_val)
374 goto out;
375
376 if (offset > MAX_PHY_MULTI_PAGE_REG) {
377 ret_val = e1000_write_phy_reg_mdic(hw,
378 IGP01E1000_PHY_PAGE_SELECT,
379 (u16)offset);
380 if (ret_val) {
381 e1000_release_phy(hw);
382 goto out;
383 }
384 }
385
386 ret_val = e1000_write_phy_reg_mdic(hw,
387 MAX_PHY_REG_ADDRESS & offset,
388 data);
389
390 e1000_release_phy(hw);
391
392 out:
393 return ret_val;
394 }
395
396 /**
397 * e1000_read_kmrn_reg_generic - Read kumeran register
398 * @hw: pointer to the HW structure
399 * @offset: register offset to be read
400 * @data: pointer to the read data
401 *
402 * Acquires semaphore, if necessary. Then reads the PHY register at offset
403 * using the kumeran interface. The information retrieved is stored in data.
404 * Release any acquired semaphores before exiting.
405 **/
406 s32 e1000_read_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 *data)
407 {
408 u32 kmrnctrlsta;
409 s32 ret_val;
410
411 DEBUGFUNC("e1000_read_kmrn_reg_generic");
412
413 ret_val = e1000_acquire_phy(hw);
414 if (ret_val)
415 goto out;
416
417 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
418 E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
419 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
420
421 usec_delay(2);
422
423 kmrnctrlsta = E1000_READ_REG(hw, E1000_KMRNCTRLSTA);
424 *data = (u16)kmrnctrlsta;
425
426 e1000_release_phy(hw);
427
428 out:
429 return ret_val;
430 }
431
432 /**
433 * e1000_write_kmrn_reg_generic - Write kumeran register
434 * @hw: pointer to the HW structure
435 * @offset: register offset to write to
436 * @data: data to write at register offset
437 *
438 * Acquires semaphore, if necessary. Then write the data to PHY register
439 * at the offset using the kumeran interface. Release any acquired semaphores
440 * before exiting.
441 **/
442 s32 e1000_write_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 data)
443 {
444 u32 kmrnctrlsta;
445 s32 ret_val;
446
447 DEBUGFUNC("e1000_write_kmrn_reg_generic");
448
449 ret_val = e1000_acquire_phy(hw);
450 if (ret_val)
451 goto out;
452
453 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
454 E1000_KMRNCTRLSTA_OFFSET) | data;
455 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
456
457 usec_delay(2);
458 e1000_release_phy(hw);
459
460 out:
461 return ret_val;
462 }
463
464 /**
465 * e1000_copper_link_setup_m88 - Setup m88 PHY's for copper link
466 * @hw: pointer to the HW structure
467 *
468 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock
469 * and downshift values are set also.
470 **/
471 s32 e1000_copper_link_setup_m88(struct e1000_hw *hw)
472 {
473 struct e1000_phy_info *phy = &hw->phy;
474 s32 ret_val;
475 u16 phy_data;
476
477 DEBUGFUNC("e1000_copper_link_setup_m88");
478
479 if (phy->reset_disable) {
480 ret_val = E1000_SUCCESS;
481 goto out;
482 }
483
484 /* Enable CRS on TX. This must be set for half-duplex operation. */
485 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
486 if (ret_val)
487 goto out;
488
489 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
490
491 /*
492 * Options:
493 * MDI/MDI-X = 0 (default)
494 * 0 - Auto for all speeds
495 * 1 - MDI mode
496 * 2 - MDI-X mode
497 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
498 */
499 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
500
501 switch (phy->mdix) {
502 case 1:
503 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
504 break;
505 case 2:
506 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
507 break;
508 case 3:
509 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
510 break;
511 case 0:
512 default:
513 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
514 break;
515 }
516
517 /*
518 * Options:
519 * disable_polarity_correction = 0 (default)
520 * Automatic Correction for Reversed Cable Polarity
521 * 0 - Disabled
522 * 1 - Enabled
523 */
524 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
525 if (phy->disable_polarity_correction == 1)
526 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
527
528 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
529 if (ret_val)
530 goto out;
531
532 if (phy->revision < E1000_REVISION_4) {
533 /*
534 * Force TX_CLK in the Extended PHY Specific Control Register
535 * to 25MHz clock.
536 */
537 ret_val = e1000_read_phy_reg(hw,
538 M88E1000_EXT_PHY_SPEC_CTRL,
539 &phy_data);
540 if (ret_val)
541 goto out;
542
543 phy_data |= M88E1000_EPSCR_TX_CLK_25;
544
545 if ((phy->revision == E1000_REVISION_2) &&
546 (phy->id == M88E1111_I_PHY_ID)) {
547 /* 82573L PHY - set the downshift counter to 5x. */
548 phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK;
549 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
550 } else {
551 /* Configure Master and Slave downshift values */
552 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
553 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
554 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
555 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
556 }
557 ret_val = e1000_write_phy_reg(hw,
558 M88E1000_EXT_PHY_SPEC_CTRL,
559 phy_data);
560 if (ret_val)
561 goto out;
562 }
563
564 /* Commit the changes. */
565 ret_val = e1000_phy_commit(hw);
566 if (ret_val) {
567 DEBUGOUT("Error committing the PHY changes\n");
568 goto out;
569 }
570
571 out:
572 return ret_val;
573 }
574
575 /**
576 * e1000_copper_link_setup_igp - Setup igp PHY's for copper link
577 * @hw: pointer to the HW structure
578 *
579 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for
580 * igp PHY's.
581 **/
582 s32 e1000_copper_link_setup_igp(struct e1000_hw *hw)
583 {
584 struct e1000_phy_info *phy = &hw->phy;
585 s32 ret_val;
586 u16 data;
587
588 DEBUGFUNC("e1000_copper_link_setup_igp");
589
590 if (phy->reset_disable) {
591 ret_val = E1000_SUCCESS;
592 goto out;
593 }
594
595 ret_val = e1000_phy_hw_reset(hw);
596 if (ret_val) {
597 DEBUGOUT("Error resetting the PHY.\n");
598 goto out;
599 }
600
601 /* Wait 15ms for MAC to configure PHY from NVM settings. */
602 msec_delay(15);
603
604 /*
605 * The NVM settings will configure LPLU in D3 for
606 * non-IGP1 PHYs.
607 */
608 if (phy->type == e1000_phy_igp) {
609 /* disable lplu d3 during driver init */
610 ret_val = e1000_set_d3_lplu_state(hw, FALSE);
611 if (ret_val) {
612 DEBUGOUT("Error Disabling LPLU D3\n");
613 goto out;
614 }
615 }
616
617 /* disable lplu d0 during driver init */
618 ret_val = e1000_set_d0_lplu_state(hw, FALSE);
619 if (ret_val) {
620 DEBUGOUT("Error Disabling LPLU D0\n");
621 goto out;
622 }
623 /* Configure mdi-mdix settings */
624 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &data);
625 if (ret_val)
626 goto out;
627
628 data &= ~IGP01E1000_PSCR_AUTO_MDIX;
629
630 switch (phy->mdix) {
631 case 1:
632 data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
633 break;
634 case 2:
635 data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
636 break;
637 case 0:
638 default:
639 data |= IGP01E1000_PSCR_AUTO_MDIX;
640 break;
641 }
642 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, data);
643 if (ret_val)
644 goto out;
645
646 /* set auto-master slave resolution settings */
647 if (hw->mac.autoneg) {
648 /*
649 * when autonegotiation advertisement is only 1000Mbps then we
650 * should disable SmartSpeed and enable Auto MasterSlave
651 * resolution as hardware default.
652 */
653 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) {
654 /* Disable SmartSpeed */
655 ret_val = e1000_read_phy_reg(hw,
656 IGP01E1000_PHY_PORT_CONFIG,
657 &data);
658 if (ret_val)
659 goto out;
660
661 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
662 ret_val = e1000_write_phy_reg(hw,
663 IGP01E1000_PHY_PORT_CONFIG,
664 data);
665 if (ret_val)
666 goto out;
667
668 /* Set auto Master/Slave resolution process */
669 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &data);
670 if (ret_val)
671 goto out;
672
673 data &= ~CR_1000T_MS_ENABLE;
674 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, data);
675 if (ret_val)
676 goto out;
677 }
678
679 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &data);
680 if (ret_val)
681 goto out;
682
683 /* load defaults for future use */
684 phy->original_ms_type = (data & CR_1000T_MS_ENABLE) ?
685 ((data & CR_1000T_MS_VALUE) ?
686 e1000_ms_force_master :
687 e1000_ms_force_slave) :
688 e1000_ms_auto;
689
690 switch (phy->ms_type) {
691 case e1000_ms_force_master:
692 data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
693 break;
694 case e1000_ms_force_slave:
695 data |= CR_1000T_MS_ENABLE;
696 data &= ~(CR_1000T_MS_VALUE);
697 break;
698 case e1000_ms_auto:
699 data &= ~CR_1000T_MS_ENABLE;
700 default:
701 break;
702 }
703 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, data);
704 if (ret_val)
705 goto out;
706 }
707
708 out:
709 return ret_val;
710 }
711
712 /**
713 * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link
714 * @hw: pointer to the HW structure
715 *
716 * Performs initial bounds checking on autoneg advertisement parameter, then
717 * configure to advertise the full capability. Setup the PHY to autoneg
718 * and restart the negotiation process between the link partner. If
719 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting.
720 **/
721 s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
722 {
723 struct e1000_phy_info *phy = &hw->phy;
724 s32 ret_val;
725 u16 phy_ctrl;
726
727 DEBUGFUNC("e1000_copper_link_autoneg");
728
729 /*
730 * Perform some bounds checking on the autoneg advertisement
731 * parameter.
732 */
733 phy->autoneg_advertised &= phy->autoneg_mask;
734
735 /*
736 * If autoneg_advertised is zero, we assume it was not defaulted
737 * by the calling code so we set to advertise full capability.
738 */
739 if (phy->autoneg_advertised == 0)
740 phy->autoneg_advertised = phy->autoneg_mask;
741
742 DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
743 ret_val = e1000_phy_setup_autoneg(hw);
744 if (ret_val) {
745 DEBUGOUT("Error Setting up Auto-Negotiation\n");
746 goto out;
747 }
748 DEBUGOUT("Restarting Auto-Neg\n");
749
750 /*
751 * Restart auto-negotiation by setting the Auto Neg Enable bit and
752 * the Auto Neg Restart bit in the PHY control register.
753 */
754 ret_val = e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl);
755 if (ret_val)
756 goto out;
757
758 phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
759 ret_val = e1000_write_phy_reg(hw, PHY_CONTROL, phy_ctrl);
760 if (ret_val)
761 goto out;
762
763 /*
764 * Does the user want to wait for Auto-Neg to complete here, or
765 * check at a later time (for example, callback routine).
766 */
767 if (phy->autoneg_wait_to_complete) {
768 ret_val = e1000_wait_autoneg(hw);
769 if (ret_val) {
770 DEBUGOUT("Error while waiting for "
771 "autoneg to complete\n");
772 goto out;
773 }
774 }
775
776 hw->mac.get_link_status = TRUE;
777
778 out:
779 return ret_val;
780 }
781
782 /**
783 * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation
784 * @hw: pointer to the HW structure
785 *
786 * Reads the MII auto-neg advertisement register and/or the 1000T control
787 * register and if the PHY is already setup for auto-negotiation, then
788 * return successful. Otherwise, setup advertisement and flow control to
789 * the appropriate values for the wanted auto-negotiation.
790 **/
791 s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
792 {
793 struct e1000_phy_info *phy = &hw->phy;
794 s32 ret_val;
795 u16 mii_autoneg_adv_reg;
796 u16 mii_1000t_ctrl_reg = 0;
797
798 DEBUGFUNC("e1000_phy_setup_autoneg");
799
800 phy->autoneg_advertised &= phy->autoneg_mask;
801
802 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
803 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
804 if (ret_val)
805 goto out;
806
807 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
808 /* Read the MII 1000Base-T Control Register (Address 9). */
809 ret_val = e1000_read_phy_reg(hw,
810 PHY_1000T_CTRL,
811 &mii_1000t_ctrl_reg);
812 if (ret_val)
813 goto out;
814 }
815
816 /*
817 * Need to parse both autoneg_advertised and fc and set up
818 * the appropriate PHY registers. First we will parse for
819 * autoneg_advertised software override. Since we can advertise
820 * a plethora of combinations, we need to check each bit
821 * individually.
822 */
823
824 /*
825 * First we clear all the 10/100 mb speed bits in the Auto-Neg
826 * Advertisement Register (Address 4) and the 1000 mb speed bits in
827 * the 1000Base-T Control Register (Address 9).
828 */
829 mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS |
830 NWAY_AR_100TX_HD_CAPS |
831 NWAY_AR_10T_FD_CAPS |
832 NWAY_AR_10T_HD_CAPS);
833 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS);
834
835 DEBUGOUT1("autoneg_advertised %x\n", phy->autoneg_advertised);
836
837 /* Do we want to advertise 10 Mb Half Duplex? */
838 if (phy->autoneg_advertised & ADVERTISE_10_HALF) {
839 DEBUGOUT("Advertise 10mb Half duplex\n");
840 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
841 }
842
843 /* Do we want to advertise 10 Mb Full Duplex? */
844 if (phy->autoneg_advertised & ADVERTISE_10_FULL) {
845 DEBUGOUT("Advertise 10mb Full duplex\n");
846 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
847 }
848
849 /* Do we want to advertise 100 Mb Half Duplex? */
850 if (phy->autoneg_advertised & ADVERTISE_100_HALF) {
851 DEBUGOUT("Advertise 100mb Half duplex\n");
852 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
853 }
854
855 /* Do we want to advertise 100 Mb Full Duplex? */
856 if (phy->autoneg_advertised & ADVERTISE_100_FULL) {
857 DEBUGOUT("Advertise 100mb Full duplex\n");
858 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
859 }
860
861 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
862 if (phy->autoneg_advertised & ADVERTISE_1000_HALF) {
863 DEBUGOUT("Advertise 1000mb Half duplex request denied!\n");
864 }
865
866 /* Do we want to advertise 1000 Mb Full Duplex? */
867 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) {
868 DEBUGOUT("Advertise 1000mb Full duplex\n");
869 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
870 }
871
872 /*
873 * Check for a software override of the flow control settings, and
874 * setup the PHY advertisement registers accordingly. If
875 * auto-negotiation is enabled, then software will have to set the
876 * "PAUSE" bits to the correct value in the Auto-Negotiation
877 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-
878 * negotiation.
879 *
880 * The possible values of the "fc" parameter are:
881 * 0: Flow control is completely disabled
882 * 1: Rx flow control is enabled (we can receive pause frames
883 * but not send pause frames).
884 * 2: Tx flow control is enabled (we can send pause frames
885 * but we do not support receiving pause frames).
886 * 3: Both Rx and TX flow control (symmetric) are enabled.
887 * other: No software override. The flow control configuration
888 * in the EEPROM is used.
889 */
890 switch (hw->fc.type) {
891 case e1000_fc_none:
892 /*
893 * Flow control (RX & TX) is completely disabled by a
894 * software over-ride.
895 */
896 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
897 break;
898 case e1000_fc_rx_pause:
899 /*
900 * RX Flow control is enabled, and TX Flow control is
901 * disabled, by a software over-ride.
902 *
903 * Since there really isn't a way to advertise that we are
904 * capable of RX Pause ONLY, we will advertise that we
905 * support both symmetric and asymmetric RX PAUSE. Later
906 * (in e1000_config_fc_after_link_up) we will disable the
907 * hw's ability to send PAUSE frames.
908 */
909 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
910 break;
911 case e1000_fc_tx_pause:
912 /*
913 * TX Flow control is enabled, and RX Flow control is
914 * disabled, by a software over-ride.
915 */
916 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
917 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
918 break;
919 case e1000_fc_full:
920 /*
921 * Flow control (both RX and TX) is enabled by a software
922 * over-ride.
923 */
924 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
925 break;
926 default:
927 DEBUGOUT("Flow control param set incorrectly\n");
928 ret_val = -E1000_ERR_CONFIG;
929 goto out;
930 }
931
932 ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
933 if (ret_val)
934 goto out;
935
936 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
937
938 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
939 ret_val = e1000_write_phy_reg(hw,
940 PHY_1000T_CTRL,
941 mii_1000t_ctrl_reg);
942 if (ret_val)
943 goto out;
944 }
945
946 out:
947 return ret_val;
948 }
949
950 /**
951 * e1000_setup_copper_link_generic - Configure copper link settings
952 * @hw: pointer to the HW structure
953 *
954 * Calls the appropriate function to configure the link for auto-neg or forced
955 * speed and duplex. Then we check for link, once link is established calls
956 * to configure collision distance and flow control are called. If link is
957 * not established, we return -E1000_ERR_PHY (-2).
958 **/
959 s32 e1000_setup_copper_link_generic(struct e1000_hw *hw)
960 {
961 s32 ret_val;
962 bool link;
963
964 DEBUGFUNC("e1000_setup_copper_link_generic");
965
966 if (hw->mac.autoneg) {
967 /*
968 * Setup autoneg and flow control advertisement and perform
969 * autonegotiation.
970 */
971 ret_val = e1000_copper_link_autoneg(hw);
972 if (ret_val)
973 goto out;
974 } else {
975 /*
976 * PHY will be set to 10H, 10F, 100H or 100F
977 * depending on user settings.
978 */
979 DEBUGOUT("Forcing Speed and Duplex\n");
980 ret_val = e1000_phy_force_speed_duplex(hw);
981 if (ret_val) {
982 DEBUGOUT("Error Forcing Speed and Duplex\n");
983 goto out;
984 }
985 }
986
987 /*
988 * Check link status. Wait up to 100 microseconds for link to become
989 * valid.
990 */
991 ret_val = e1000_phy_has_link_generic(hw,
992 COPPER_LINK_UP_LIMIT,
993 10,
994 &link);
995 if (ret_val)
996 goto out;
997
998 if (link) {
999 DEBUGOUT("Valid link established!!!\n");
1000 e1000_config_collision_dist_generic(hw);
1001 ret_val = e1000_config_fc_after_link_up_generic(hw);
1002 } else {
1003 DEBUGOUT("Unable to establish link!!!\n");
1004 }
1005
1006 out:
1007 return ret_val;
1008 }
1009
1010 /**
1011 * e1000_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY
1012 * @hw: pointer to the HW structure
1013 *
1014 * Calls the PHY setup function to force speed and duplex. Clears the
1015 * auto-crossover to force MDI manually. Waits for link and returns
1016 * successful if link up is successful, else -E1000_ERR_PHY (-2).
1017 **/
1018 s32 e1000_phy_force_speed_duplex_igp(struct e1000_hw *hw)
1019 {
1020 struct e1000_phy_info *phy = &hw->phy;
1021 s32 ret_val;
1022 u16 phy_data;
1023 bool link;
1024
1025 DEBUGFUNC("e1000_phy_force_speed_duplex_igp");
1026
1027 ret_val = e1000_read_phy_reg(hw, PHY_CONTROL, &phy_data);
1028 if (ret_val)
1029 goto out;
1030
1031 e1000_phy_force_speed_duplex_setup(hw, &phy_data);
1032
1033 ret_val = e1000_write_phy_reg(hw, PHY_CONTROL, phy_data);
1034 if (ret_val)
1035 goto out;
1036
1037 /*
1038 * Clear Auto-Crossover to force MDI manually. IGP requires MDI
1039 * forced whenever speed and duplex are forced.
1040 */
1041 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1042 if (ret_val)
1043 goto out;
1044
1045 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1046 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1047
1048 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1049 if (ret_val)
1050 goto out;
1051
1052 DEBUGOUT1("IGP PSCR: %X\n", phy_data);
1053
1054 usec_delay(1);
1055
1056 if (phy->autoneg_wait_to_complete) {
1057 DEBUGOUT("Waiting for forced speed/duplex link on IGP phy.\n");
1058
1059 ret_val = e1000_phy_has_link_generic(hw,
1060 PHY_FORCE_LIMIT,
1061 100000,
1062 &link);
1063 if (ret_val)
1064 goto out;
1065
1066 if (!link) {
1067 DEBUGOUT("Link taking longer than expected.\n");
1068 }
1069
1070 /* Try once more */
1071 ret_val = e1000_phy_has_link_generic(hw,
1072 PHY_FORCE_LIMIT,
1073 100000,
1074 &link);
1075 if (ret_val)
1076 goto out;
1077 }
1078
1079 out:
1080 return ret_val;
1081 }
1082
1083 /**
1084 * e1000_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY
1085 * @hw: pointer to the HW structure
1086 *
1087 * Calls the PHY setup function to force speed and duplex. Clears the
1088 * auto-crossover to force MDI manually. Resets the PHY to commit the
1089 * changes. If time expires while waiting for link up, we reset the DSP.
1090 * After reset, TX_CLK and CRS on TX must be set. Return successful upon
1091 * successful completion, else return corresponding error code.
1092 **/
1093 s32 e1000_phy_force_speed_duplex_m88(struct e1000_hw *hw)
1094 {
1095 struct e1000_phy_info *phy = &hw->phy;
1096 s32 ret_val;
1097 u16 phy_data;
1098 bool link;
1099
1100 DEBUGFUNC("e1000_phy_force_speed_duplex_m88");
1101
1102 /*
1103 * Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
1104 * forced whenever speed and duplex are forced.
1105 */
1106 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1107 if (ret_val)
1108 goto out;
1109
1110 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1111 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1112 if (ret_val)
1113 goto out;
1114
1115 DEBUGOUT1("M88E1000 PSCR: %X\n", phy_data);
1116
1117 ret_val = e1000_read_phy_reg(hw, PHY_CONTROL, &phy_data);
1118 if (ret_val)
1119 goto out;
1120
1121 e1000_phy_force_speed_duplex_setup(hw, &phy_data);
1122
1123 /* Reset the phy to commit changes. */
1124 phy_data |= MII_CR_RESET;
1125
1126 ret_val = e1000_write_phy_reg(hw, PHY_CONTROL, phy_data);
1127 if (ret_val)
1128 goto out;
1129
1130 usec_delay(1);
1131
1132 if (phy->autoneg_wait_to_complete) {
1133 DEBUGOUT("Waiting for forced speed/duplex link on M88 phy.\n");
1134
1135 ret_val = e1000_phy_has_link_generic(hw,
1136 PHY_FORCE_LIMIT,
1137 100000,
1138 &link);
1139 if (ret_val)
1140 goto out;
1141
1142 if (!link) {
1143 /*
1144 * We didn't get link.
1145 * Reset the DSP and cross our fingers.
1146 */
1147 ret_val = e1000_write_phy_reg(hw,
1148 M88E1000_PHY_PAGE_SELECT,
1149 0x001d);
1150 if (ret_val)
1151 goto out;
1152 ret_val = e1000_phy_reset_dsp_generic(hw);
1153 if (ret_val)
1154 goto out;
1155 }
1156
1157 /* Try once more */
1158 ret_val = e1000_phy_has_link_generic(hw,
1159 PHY_FORCE_LIMIT,
1160 100000,
1161 &link);
1162 if (ret_val)
1163 goto out;
1164 }
1165
1166 ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1167 if (ret_val)
1168 goto out;
1169
1170 /*
1171 * Resetting the phy means we need to re-force TX_CLK in the
1172 * Extended PHY Specific Control Register to 25MHz clock from
1173 * the reset value of 2.5MHz.
1174 */
1175 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1176 ret_val = e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1177 if (ret_val)
1178 goto out;
1179
1180 /*
1181 * In addition, we must re-enable CRS on Tx for both half and full
1182 * duplex.
1183 */
1184 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1185 if (ret_val)
1186 goto out;
1187
1188 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1189 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1190
1191 out:
1192 return ret_val;
1193 }
1194
1195 /**
1196 * e1000_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex
1197 * @hw: pointer to the HW structure
1198 * @phy_ctrl: pointer to current value of PHY_CONTROL
1199 *
1200 * Forces speed and duplex on the PHY by doing the following: disable flow
1201 * control, force speed/duplex on the MAC, disable auto speed detection,
1202 * disable auto-negotiation, configure duplex, configure speed, configure
1203 * the collision distance, write configuration to CTRL register. The
1204 * caller must write to the PHY_CONTROL register for these settings to
1205 * take affect.
1206 **/
1207 void e1000_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl)
1208 {
1209 struct e1000_mac_info *mac = &hw->mac;
1210 u32 ctrl;
1211
1212 DEBUGFUNC("e1000_phy_force_speed_duplex_setup");
1213
1214 /* Turn off flow control when forcing speed/duplex */
1215 hw->fc.type = e1000_fc_none;
1216
1217 /* Force speed/duplex on the mac */
1218 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1219 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1220 ctrl &= ~E1000_CTRL_SPD_SEL;
1221
1222 /* Disable Auto Speed Detection */
1223 ctrl &= ~E1000_CTRL_ASDE;
1224
1225 /* Disable autoneg on the phy */
1226 *phy_ctrl &= ~MII_CR_AUTO_NEG_EN;
1227
1228 /* Forcing Full or Half Duplex? */
1229 if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) {
1230 ctrl &= ~E1000_CTRL_FD;
1231 *phy_ctrl &= ~MII_CR_FULL_DUPLEX;
1232 DEBUGOUT("Half Duplex\n");
1233 } else {
1234 ctrl |= E1000_CTRL_FD;
1235 *phy_ctrl |= MII_CR_FULL_DUPLEX;
1236 DEBUGOUT("Full Duplex\n");
1237 }
1238
1239 /* Forcing 10mb or 100mb? */
1240 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) {
1241 ctrl |= E1000_CTRL_SPD_100;
1242 *phy_ctrl |= MII_CR_SPEED_100;
1243 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
1244 DEBUGOUT("Forcing 100mb\n");
1245 } else {
1246 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1247 *phy_ctrl |= MII_CR_SPEED_10;
1248 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
1249 DEBUGOUT("Forcing 10mb\n");
1250 }
1251
1252 e1000_config_collision_dist_generic(hw);
1253
1254 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1255 }
1256
1257 /**
1258 * e1000_set_d3_lplu_state_generic - Sets low power link up state for D3
1259 * @hw: pointer to the HW structure
1260 * @active: boolean used to enable/disable lplu
1261 *
1262 * Success returns 0, Failure returns 1
1263 *
1264 * The low power link up (lplu) state is set to the power management level D3
1265 * and SmartSpeed is disabled when active is true, else clear lplu for D3
1266 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
1267 * is used during Dx states where the power conservation is most important.
1268 * During driver activity, SmartSpeed should be enabled so performance is
1269 * maintained.
1270 **/
1271 s32 e1000_set_d3_lplu_state_generic(struct e1000_hw *hw, bool active)
1272 {
1273 struct e1000_phy_info *phy = &hw->phy;
1274 s32 ret_val;
1275 u16 data;
1276
1277 DEBUGFUNC("e1000_set_d3_lplu_state_generic");
1278
1279 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
1280 if (ret_val)
1281 goto out;
1282
1283 if (!active) {
1284 data &= ~IGP02E1000_PM_D3_LPLU;
1285 ret_val = e1000_write_phy_reg(hw,
1286 IGP02E1000_PHY_POWER_MGMT,
1287 data);
1288 if (ret_val)
1289 goto out;
1290 /*
1291 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
1292 * during Dx states where the power conservation is most
1293 * important. During driver activity we should enable
1294 * SmartSpeed, so performance is maintained.
1295 */
1296 if (phy->smart_speed == e1000_smart_speed_on) {
1297 ret_val = e1000_read_phy_reg(hw,
1298 IGP01E1000_PHY_PORT_CONFIG,
1299 &data);
1300 if (ret_val)
1301 goto out;
1302
1303 data |= IGP01E1000_PSCFR_SMART_SPEED;
1304 ret_val = e1000_write_phy_reg(hw,
1305 IGP01E1000_PHY_PORT_CONFIG,
1306 data);
1307 if (ret_val)
1308 goto out;
1309 } else if (phy->smart_speed == e1000_smart_speed_off) {
1310 ret_val = e1000_read_phy_reg(hw,
1311 IGP01E1000_PHY_PORT_CONFIG,
1312 &data);
1313 if (ret_val)
1314 goto out;
1315
1316 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1317 ret_val = e1000_write_phy_reg(hw,
1318 IGP01E1000_PHY_PORT_CONFIG,
1319 data);
1320 if (ret_val)
1321 goto out;
1322 }
1323 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1324 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1325 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1326 data |= IGP02E1000_PM_D3_LPLU;
1327 ret_val = e1000_write_phy_reg(hw,
1328 IGP02E1000_PHY_POWER_MGMT,
1329 data);
1330 if (ret_val)
1331 goto out;
1332
1333 /* When LPLU is enabled, we should disable SmartSpeed */
1334 ret_val = e1000_read_phy_reg(hw,
1335 IGP01E1000_PHY_PORT_CONFIG,
1336 &data);
1337 if (ret_val)
1338 goto out;
1339
1340 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1341 ret_val = e1000_write_phy_reg(hw,
1342 IGP01E1000_PHY_PORT_CONFIG,
1343 data);
1344 }
1345
1346 out:
1347 return ret_val;
1348 }
1349
1350 /**
1351 * e1000_check_downshift_generic - Checks whether a downshift in speed occured
1352 * @hw: pointer to the HW structure
1353 *
1354 * Success returns 0, Failure returns 1
1355 *
1356 * A downshift is detected by querying the PHY link health.
1357 **/
1358 s32 e1000_check_downshift_generic(struct e1000_hw *hw)
1359 {
1360 struct e1000_phy_info *phy = &hw->phy;
1361 s32 ret_val;
1362 u16 phy_data, offset, mask;
1363
1364 DEBUGFUNC("e1000_check_downshift_generic");
1365
1366 switch (phy->type) {
1367 case e1000_phy_m88:
1368 case e1000_phy_gg82563:
1369 offset = M88E1000_PHY_SPEC_STATUS;
1370 mask = M88E1000_PSSR_DOWNSHIFT;
1371 break;
1372 case e1000_phy_igp_2:
1373 case e1000_phy_igp:
1374 case e1000_phy_igp_3:
1375 offset = IGP01E1000_PHY_LINK_HEALTH;
1376 mask = IGP01E1000_PLHR_SS_DOWNGRADE;
1377 break;
1378 default:
1379 /* speed downshift not supported */
1380 phy->speed_downgraded = FALSE;
1381 ret_val = E1000_SUCCESS;
1382 goto out;
1383 }
1384
1385 ret_val = e1000_read_phy_reg(hw, offset, &phy_data);
1386
1387 if (!ret_val)
1388 phy->speed_downgraded = (phy_data & mask) ? TRUE : FALSE;
1389
1390 out:
1391 return ret_val;
1392 }
1393
1394 /**
1395 * e1000_check_polarity_m88 - Checks the polarity.
1396 * @hw: pointer to the HW structure
1397 *
1398 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1399 *
1400 * Polarity is determined based on the PHY specific status register.
1401 **/
1402 s32 e1000_check_polarity_m88(struct e1000_hw *hw)
1403 {
1404 struct e1000_phy_info *phy = &hw->phy;
1405 s32 ret_val;
1406 u16 data;
1407
1408 DEBUGFUNC("e1000_check_polarity_m88");
1409
1410 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &data);
1411
1412 if (!ret_val)
1413 phy->cable_polarity = (data & M88E1000_PSSR_REV_POLARITY)
1414 ? e1000_rev_polarity_reversed
1415 : e1000_rev_polarity_normal;
1416
1417 return ret_val;
1418 }
1419
1420 /**
1421 * e1000_check_polarity_igp - Checks the polarity.
1422 * @hw: pointer to the HW structure
1423 *
1424 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1425 *
1426 * Polarity is determined based on the PHY port status register, and the
1427 * current speed (since there is no polarity at 100Mbps).
1428 **/
1429 s32 e1000_check_polarity_igp(struct e1000_hw *hw)
1430 {
1431 struct e1000_phy_info *phy = &hw->phy;
1432 s32 ret_val;
1433 u16 data, offset, mask;
1434
1435 DEBUGFUNC("e1000_check_polarity_igp");
1436
1437 /*
1438 * Polarity is determined based on the speed of
1439 * our connection.
1440 */
1441 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);
1442 if (ret_val)
1443 goto out;
1444
1445 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
1446 IGP01E1000_PSSR_SPEED_1000MBPS) {
1447 offset = IGP01E1000_PHY_PCS_INIT_REG;
1448 mask = IGP01E1000_PHY_POLARITY_MASK;
1449 } else {
1450 /*
1451 * This really only applies to 10Mbps since
1452 * there is no polarity for 100Mbps (always 0).
1453 */
1454 offset = IGP01E1000_PHY_PORT_STATUS;
1455 mask = IGP01E1000_PSSR_POLARITY_REVERSED;
1456 }
1457
1458 ret_val = e1000_read_phy_reg(hw, offset, &data);
1459
1460 if (!ret_val)
1461 phy->cable_polarity = (data & mask)
1462 ? e1000_rev_polarity_reversed
1463 : e1000_rev_polarity_normal;
1464
1465 out:
1466 return ret_val;
1467 }
1468
1469 /**
1470 * e1000_wait_autoneg_generic - Wait for auto-neg compeletion
1471 * @hw: pointer to the HW structure
1472 *
1473 * Waits for auto-negotiation to complete or for the auto-negotiation time
1474 * limit to expire, which ever happens first.
1475 **/
1476 s32 e1000_wait_autoneg_generic(struct e1000_hw *hw)
1477 {
1478 s32 ret_val = E1000_SUCCESS;
1479 u16 i, phy_status;
1480
1481 DEBUGFUNC("e1000_wait_autoneg_generic");
1482
1483 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */
1484 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) {
1485 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_status);
1486 if (ret_val)
1487 break;
1488 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_status);
1489 if (ret_val)
1490 break;
1491 if (phy_status & MII_SR_AUTONEG_COMPLETE)
1492 break;
1493 msec_delay(100);
1494 }
1495
1496 /*
1497 * PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation
1498 * has completed.
1499 */
1500 return ret_val;
1501 }
1502
1503 /**
1504 * e1000_phy_has_link_generic - Polls PHY for link
1505 * @hw: pointer to the HW structure
1506 * @iterations: number of times to poll for link
1507 * @usec_interval: delay between polling attempts
1508 * @success: pointer to whether polling was successful or not
1509 *
1510 * Polls the PHY status register for link, 'iterations' number of times.
1511 **/
1512 s32 e1000_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
1513 u32 usec_interval, bool *success)
1514 {
1515 s32 ret_val = E1000_SUCCESS;
1516 u16 i, phy_status;
1517
1518 DEBUGFUNC("e1000_phy_has_link_generic");
1519
1520 for (i = 0; i < iterations; i++) {
1521 /*
1522 * Some PHYs require the PHY_STATUS register to be read
1523 * twice due to the link bit being sticky. No harm doing
1524 * it across the board.
1525 */
1526 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_status);
1527 if (ret_val)
1528 break;
1529 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_status);
1530 if (ret_val)
1531 break;
1532 if (phy_status & MII_SR_LINK_STATUS)
1533 break;
1534 if (usec_interval >= 1000)
1535 msec_delay_irq(usec_interval/1000);
1536 else
1537 usec_delay(usec_interval);
1538 }
1539
1540 *success = (i < iterations) ? TRUE : FALSE;
1541
1542 return ret_val;
1543 }
1544
1545 /**
1546 * e1000_get_cable_length_m88 - Determine cable length for m88 PHY
1547 * @hw: pointer to the HW structure
1548 *
1549 * Reads the PHY specific status register to retrieve the cable length
1550 * information. The cable length is determined by averaging the minimum and
1551 * maximum values to get the "average" cable length. The m88 PHY has four
1552 * possible cable length values, which are:
1553 * Register Value Cable Length
1554 * 0 < 50 meters
1555 * 1 50 - 80 meters
1556 * 2 80 - 110 meters
1557 * 3 110 - 140 meters
1558 * 4 > 140 meters
1559 **/
1560 s32 e1000_get_cable_length_m88(struct e1000_hw *hw)
1561 {
1562 struct e1000_phy_info *phy = &hw->phy;
1563 s32 ret_val;
1564 u16 phy_data, index;
1565
1566 DEBUGFUNC("e1000_get_cable_length_m88");
1567
1568 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1569 if (ret_val)
1570 goto out;
1571
1572 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
1573 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
1574 phy->min_cable_length = e1000_m88_cable_length_table[index];
1575 phy->max_cable_length = e1000_m88_cable_length_table[index+1];
1576
1577 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
1578
1579 out:
1580 return ret_val;
1581 }
1582
1583 /**
1584 * e1000_get_cable_length_igp_2 - Determine cable length for igp2 PHY
1585 * @hw: pointer to the HW structure
1586 *
1587 * The automatic gain control (agc) normalizes the amplitude of the
1588 * received signal, adjusting for the attenuation produced by the
1589 * cable. By reading the AGC registers, which reperesent the
1590 * cobination of course and fine gain value, the value can be put
1591 * into a lookup table to obtain the approximate cable length
1592 * for each channel.
1593 **/
1594 s32 e1000_get_cable_length_igp_2(struct e1000_hw *hw)
1595 {
1596 struct e1000_phy_info *phy = &hw->phy;
1597 s32 ret_val = E1000_SUCCESS;
1598 u16 phy_data, i, agc_value = 0;
1599 u16 cur_agc_index, max_agc_index = 0;
1600 u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1;
1601 u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] =
1602 {IGP02E1000_PHY_AGC_A,
1603 IGP02E1000_PHY_AGC_B,
1604 IGP02E1000_PHY_AGC_C,
1605 IGP02E1000_PHY_AGC_D};
1606
1607 DEBUGFUNC("e1000_get_cable_length_igp_2");
1608
1609 /* Read the AGC registers for all channels */
1610 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
1611 ret_val = e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data);
1612 if (ret_val)
1613 goto out;
1614
1615 /*
1616 * Getting bits 15:9, which represent the combination of
1617 * course and fine gain values. The result is a number
1618 * that can be put into the lookup table to obtain the
1619 * approximate cable length.
1620 */
1621 cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
1622 IGP02E1000_AGC_LENGTH_MASK;
1623
1624 /* Array index bound check. */
1625 if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) ||
1626 (cur_agc_index == 0)) {
1627 ret_val = -E1000_ERR_PHY;
1628 goto out;
1629 }
1630
1631 /* Remove min & max AGC values from calculation. */
1632 if (e1000_igp_2_cable_length_table[min_agc_index] >
1633 e1000_igp_2_cable_length_table[cur_agc_index])
1634 min_agc_index = cur_agc_index;
1635 if (e1000_igp_2_cable_length_table[max_agc_index] <
1636 e1000_igp_2_cable_length_table[cur_agc_index])
1637 max_agc_index = cur_agc_index;
1638
1639 agc_value += e1000_igp_2_cable_length_table[cur_agc_index];
1640 }
1641
1642 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] +
1643 e1000_igp_2_cable_length_table[max_agc_index]);
1644 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
1645
1646 /* Calculate cable length with the error range of +/- 10 meters. */
1647 phy->min_cable_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
1648 (agc_value - IGP02E1000_AGC_RANGE) : 0;
1649 phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE;
1650
1651 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
1652
1653 out:
1654 return ret_val;
1655 }
1656
1657 /**
1658 * e1000_get_phy_info_m88 - Retrieve PHY information
1659 * @hw: pointer to the HW structure
1660 *
1661 * Valid for only copper links. Read the PHY status register (sticky read)
1662 * to verify that link is up. Read the PHY special control register to
1663 * determine the polarity and 10base-T extended distance. Read the PHY
1664 * special status register to determine MDI/MDIx and current speed. If
1665 * speed is 1000, then determine cable length, local and remote receiver.
1666 **/
1667 s32 e1000_get_phy_info_m88(struct e1000_hw *hw)
1668 {
1669 struct e1000_phy_info *phy = &hw->phy;
1670 s32 ret_val;
1671 u16 phy_data;
1672 bool link;
1673
1674 DEBUGFUNC("e1000_get_phy_info_m88");
1675
1676 if (hw->phy.media_type != e1000_media_type_copper) {
1677 DEBUGOUT("Phy info is only valid for copper media\n");
1678 ret_val = -E1000_ERR_CONFIG;
1679 goto out;
1680 }
1681
1682 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
1683 if (ret_val)
1684 goto out;
1685
1686 if (!link) {
1687 DEBUGOUT("Phy info is only valid if link is up\n");
1688 ret_val = -E1000_ERR_CONFIG;
1689 goto out;
1690 }
1691
1692 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1693 if (ret_val)
1694 goto out;
1695
1696 phy->polarity_correction = (phy_data & M88E1000_PSCR_POLARITY_REVERSAL)
1697 ? TRUE
1698 : FALSE;
1699
1700 ret_val = e1000_check_polarity_m88(hw);
1701 if (ret_val)
1702 goto out;
1703
1704 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1705 if (ret_val)
1706 goto out;
1707
1708 phy->is_mdix = (phy_data & M88E1000_PSSR_MDIX) ? TRUE : FALSE;
1709
1710 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
1711 ret_val = e1000_get_cable_length(hw);
1712 if (ret_val)
1713 goto out;
1714
1715 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
1716 if (ret_val)
1717 goto out;
1718
1719 phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS)
1720 ? e1000_1000t_rx_status_ok
1721 : e1000_1000t_rx_status_not_ok;
1722
1723 phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS)
1724 ? e1000_1000t_rx_status_ok
1725 : e1000_1000t_rx_status_not_ok;
1726 } else {
1727 /* Set values to "undefined" */
1728 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
1729 phy->local_rx = e1000_1000t_rx_status_undefined;
1730 phy->remote_rx = e1000_1000t_rx_status_undefined;
1731 }
1732
1733 out:
1734 return ret_val;
1735 }
1736
1737 /**
1738 * e1000_get_phy_info_igp - Retrieve igp PHY information
1739 * @hw: pointer to the HW structure
1740 *
1741 * Read PHY status to determine if link is up. If link is up, then
1742 * set/determine 10base-T extended distance and polarity correction. Read
1743 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
1744 * determine on the cable length, local and remote receiver.
1745 **/
1746 s32 e1000_get_phy_info_igp(struct e1000_hw *hw)
1747 {
1748 struct e1000_phy_info *phy = &hw->phy;
1749 s32 ret_val;
1750 u16 data;
1751 bool link;
1752
1753 DEBUGFUNC("e1000_get_phy_info_igp");
1754
1755 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
1756 if (ret_val)
1757 goto out;
1758
1759 if (!link) {
1760 DEBUGOUT("Phy info is only valid if link is up\n");
1761 ret_val = -E1000_ERR_CONFIG;
1762 goto out;
1763 }
1764
1765 phy->polarity_correction = TRUE;
1766
1767 ret_val = e1000_check_polarity_igp(hw);
1768 if (ret_val)
1769 goto out;
1770
1771 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);
1772 if (ret_val)
1773 goto out;
1774
1775 phy->is_mdix = (data & IGP01E1000_PSSR_MDIX) ? TRUE : FALSE;
1776
1777 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
1778 IGP01E1000_PSSR_SPEED_1000MBPS) {
1779 ret_val = e1000_get_cable_length(hw);
1780 if (ret_val)
1781 goto out;
1782
1783 ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &data);
1784 if (ret_val)
1785 goto out;
1786
1787 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
1788 ? e1000_1000t_rx_status_ok
1789 : e1000_1000t_rx_status_not_ok;
1790
1791 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
1792 ? e1000_1000t_rx_status_ok
1793 : e1000_1000t_rx_status_not_ok;
1794 } else {
1795 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
1796 phy->local_rx = e1000_1000t_rx_status_undefined;
1797 phy->remote_rx = e1000_1000t_rx_status_undefined;
1798 }
1799
1800 out:
1801 return ret_val;
1802 }
1803
1804 /**
1805 * e1000_phy_sw_reset_generic - PHY software reset
1806 * @hw: pointer to the HW structure
1807 *
1808 * Does a software reset of the PHY by reading the PHY control register and
1809 * setting/write the control register reset bit to the PHY.
1810 **/
1811 s32 e1000_phy_sw_reset_generic(struct e1000_hw *hw)
1812 {
1813 s32 ret_val;
1814 u16 phy_ctrl;
1815
1816 DEBUGFUNC("e1000_phy_sw_reset_generic");
1817
1818 ret_val = e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl);
1819 if (ret_val)
1820 goto out;
1821
1822 phy_ctrl |= MII_CR_RESET;
1823 ret_val = e1000_write_phy_reg(hw, PHY_CONTROL, phy_ctrl);
1824 if (ret_val)
1825 goto out;
1826
1827 usec_delay(1);
1828
1829 out:
1830 return ret_val;
1831 }
1832
1833 /**
1834 * e1000_phy_hw_reset_generic - PHY hardware reset
1835 * @hw: pointer to the HW structure
1836 *
1837 * Verify the reset block is not blocking us from resetting. Acquire
1838 * semaphore (if necessary) and read/set/write the device control reset
1839 * bit in the PHY. Wait the appropriate delay time for the device to
1840 * reset and relase the semaphore (if necessary).
1841 **/
1842 s32 e1000_phy_hw_reset_generic(struct e1000_hw *hw)
1843 {
1844 struct e1000_phy_info *phy = &hw->phy;
1845 s32 ret_val;
1846 u32 ctrl;
1847
1848 DEBUGFUNC("e1000_phy_hw_reset_generic");
1849
1850 ret_val = e1000_check_reset_block(hw);
1851 if (ret_val) {
1852 ret_val = E1000_SUCCESS;
1853 goto out;
1854 }
1855
1856 ret_val = e1000_acquire_phy(hw);
1857 if (ret_val)
1858 goto out;
1859
1860 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1861 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PHY_RST);
1862 E1000_WRITE_FLUSH(hw);
1863
1864 usec_delay(phy->reset_delay_us);
1865
1866 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1867 E1000_WRITE_FLUSH(hw);
1868
1869 usec_delay(150);
1870
1871 e1000_release_phy(hw);
1872
1873 ret_val = e1000_get_phy_cfg_done(hw);
1874
1875 out:
1876 return ret_val;
1877 }
1878
1879 /**
1880 * e1000_get_cfg_done_generic - Generic configuration done
1881 * @hw: pointer to the HW structure
1882 *
1883 * Generic function to wait 10 milli-seconds for configuration to complete
1884 * and return success.
1885 **/
1886 s32 e1000_get_cfg_done_generic(struct e1000_hw *hw)
1887 {
1888 DEBUGFUNC("e1000_get_cfg_done_generic");
1889 UNREFERENCED_PARAMETER(hw);
1890
1891 msec_delay_irq(10);
1892
1893 return E1000_SUCCESS;
1894 }
1895
1896 /* Internal function pointers */
1897
1898 /**
1899 * e1000_get_phy_cfg_done - Generic PHY configuration done
1900 * @hw: pointer to the HW structure
1901 *
1902 * Return success if silicon family did not implement a family specific
1903 * get_cfg_done function.
1904 **/
1905 s32 e1000_get_phy_cfg_done(struct e1000_hw *hw)
1906 {
1907 if (hw->func.get_cfg_done)
1908 return hw->func.get_cfg_done(hw);
1909
1910 return E1000_SUCCESS;
1911 }
1912
1913 /**
1914 * e1000_release_phy - Generic release PHY
1915 * @hw: pointer to the HW structure
1916 *
1917 * Return if silicon family does not require a semaphore when accessing the
1918 * PHY.
1919 **/
1920 void e1000_release_phy(struct e1000_hw *hw)
1921 {
1922 if (hw->func.release_phy)
1923 hw->func.release_phy(hw);
1924 }
1925
1926 /**
1927 * e1000_acquire_phy - Generic acquire PHY
1928 * @hw: pointer to the HW structure
1929 *
1930 * Return success if silicon family does not require a semaphore when
1931 * accessing the PHY.
1932 **/
1933 s32 e1000_acquire_phy(struct e1000_hw *hw)
1934 {
1935 if (hw->func.acquire_phy)
1936 return hw->func.acquire_phy(hw);
1937
1938 return E1000_SUCCESS;
1939 }
1940
1941 /**
1942 * e1000_phy_force_speed_duplex - Generic force PHY speed/duplex
1943 * @hw: pointer to the HW structure
1944 *
1945 * When the silicon family has not implemented a forced speed/duplex
1946 * function for the PHY, simply return E1000_SUCCESS.
1947 **/
1948 s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw)
1949 {
1950 if (hw->func.force_speed_duplex)
1951 return hw->func.force_speed_duplex(hw);
1952
1953 return E1000_SUCCESS;
1954 }
1955
1956 /**
1957 * e1000_phy_init_script_igp3 - Inits the IGP3 PHY
1958 * @hw: pointer to the HW structure
1959 *
1960 * Initializes a Intel Gigabit PHY3 when an EEPROM is not present.
1961 **/
1962 s32 e1000_phy_init_script_igp3(struct e1000_hw *hw)
1963 {
1964 DEBUGOUT("Running IGP 3 PHY init script\n");
1965
1966 /* PHY init IGP 3 */
1967 /* Enable rise/fall, 10-mode work in class-A */
1968 e1000_write_phy_reg(hw, 0x2F5B, 0x9018);
1969 /* Remove all caps from Replica path filter */
1970 e1000_write_phy_reg(hw, 0x2F52, 0x0000);
1971 /* Bias trimming for ADC, AFE and Driver (Default) */
1972 e1000_write_phy_reg(hw, 0x2FB1, 0x8B24);
1973 /* Increase Hybrid poly bias */
1974 e1000_write_phy_reg(hw, 0x2FB2, 0xF8F0);
1975 /* Add 4% to TX amplitude in Giga mode */
1976 e1000_write_phy_reg(hw, 0x2010, 0x10B0);
1977 /* Disable trimming (TTT) */
1978 e1000_write_phy_reg(hw, 0x2011, 0x0000);
1979 /* Poly DC correction to 94.6% + 2% for all channels */
1980 e1000_write_phy_reg(hw, 0x20DD, 0x249A);
1981 /* ABS DC correction to 95.9% */
1982 e1000_write_phy_reg(hw, 0x20DE, 0x00D3);
1983 /* BG temp curve trim */
1984 e1000_write_phy_reg(hw, 0x28B4, 0x04CE);
1985 /* Increasing ADC OPAMP stage 1 currents to max */
1986 e1000_write_phy_reg(hw, 0x2F70, 0x29E4);
1987 /* Force 1000 ( required for enabling PHY regs configuration) */
1988 e1000_write_phy_reg(hw, 0x0000, 0x0140);
1989 /* Set upd_freq to 6 */
1990 e1000_write_phy_reg(hw, 0x1F30, 0x1606);
1991 /* Disable NPDFE */
1992 e1000_write_phy_reg(hw, 0x1F31, 0xB814);
1993 /* Disable adaptive fixed FFE (Default) */
1994 e1000_write_phy_reg(hw, 0x1F35, 0x002A);
1995 /* Enable FFE hysteresis */
1996 e1000_write_phy_reg(hw, 0x1F3E, 0x0067);
1997 /* Fixed FFE for short cable lengths */
1998 e1000_write_phy_reg(hw, 0x1F54, 0x0065);
1999 /* Fixed FFE for medium cable lengths */
2000 e1000_write_phy_reg(hw, 0x1F55, 0x002A);
2001 /* Fixed FFE for long cable lengths */
2002 e1000_write_phy_reg(hw, 0x1F56, 0x002A);
2003 /* Enable Adaptive Clip Threshold */
2004 e1000_write_phy_reg(hw, 0x1F72, 0x3FB0);
2005 /* AHT reset limit to 1 */
2006 e1000_write_phy_reg(hw, 0x1F76, 0xC0FF);
2007 /* Set AHT master delay to 127 msec */
2008 e1000_write_phy_reg(hw, 0x1F77, 0x1DEC);
2009 /* Set scan bits for AHT */
2010 e1000_write_phy_reg(hw, 0x1F78, 0xF9EF);
2011 /* Set AHT Preset bits */
2012 e1000_write_phy_reg(hw, 0x1F79, 0x0210);
2013 /* Change integ_factor of channel A to 3 */
2014 e1000_write_phy_reg(hw, 0x1895, 0x0003);
2015 /* Change prop_factor of channels BCD to 8 */
2016 e1000_write_phy_reg(hw, 0x1796, 0x0008);
2017 /* Change cg_icount + enable integbp for channels BCD */
2018 e1000_write_phy_reg(hw, 0x1798, 0xD008);
2019 /*
2020 * Change cg_icount + enable integbp + change prop_factor_master
2021 * to 8 for channel A
2022 */
2023 e1000_write_phy_reg(hw, 0x1898, 0xD918);
2024 /* Disable AHT in Slave mode on channel A */
2025 e1000_write_phy_reg(hw, 0x187A, 0x0800);
2026 /*
2027 * Enable LPLU and disable AN to 1000 in non-D0a states,
2028 * Enable SPD+B2B
2029 */
2030 e1000_write_phy_reg(hw, 0x0019, 0x008D);
2031 /* Enable restart AN on an1000_dis change */
2032 e1000_write_phy_reg(hw, 0x001B, 0x2080);
2033 /* Enable wh_fifo read clock in 10/100 modes */
2034 e1000_write_phy_reg(hw, 0x0014, 0x0045);
2035 /* Restart AN, Speed selection is 1000 */
2036 e1000_write_phy_reg(hw, 0x0000, 0x1340);
2037
2038 return E1000_SUCCESS;
2039 }
2040
2041 /**
2042 * e1000_get_phy_type_from_id - Get PHY type from id
2043 * @phy_id: phy_id read from the phy
2044 *
2045 * Returns the phy type from the id.
2046 **/
2047 e1000_phy_type e1000_get_phy_type_from_id(u32 phy_id)
2048 {
2049 e1000_phy_type phy_type = e1000_phy_unknown;
2050
2051 switch (phy_id) {
2052 case M88E1000_I_PHY_ID:
2053 case M88E1000_E_PHY_ID:
2054 case M88E1111_I_PHY_ID:
2055 case M88E1011_I_PHY_ID:
2056 phy_type = e1000_phy_m88;
2057 break;
2058 case IGP01E1000_I_PHY_ID: /* IGP 1 & 2 share this */
2059 phy_type = e1000_phy_igp_2;
2060 break;
2061 case GG82563_E_PHY_ID:
2062 phy_type = e1000_phy_gg82563;
2063 break;
2064 case IGP03E1000_E_PHY_ID:
2065 phy_type = e1000_phy_igp_3;
2066 break;
2067 case IFE_E_PHY_ID:
2068 case IFE_PLUS_E_PHY_ID:
2069 case IFE_C_E_PHY_ID:
2070 phy_type = e1000_phy_ife;
2071 break;
2072 default:
2073 phy_type = e1000_phy_unknown;
2074 break;
2075 }
2076 return phy_type;
2077 }
2078
2079
Cache object: 85e1455c2fe99dc9a0644b8b19c7b6ae
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