Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/dev/em/e1000_phy.h
Version:
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1 /******************************************************************************* 2 3 Copyright (c) 2001-2007, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 *******************************************************************************/ 33 /* $FreeBSD$ */ 34 35 36 #ifndef _E1000_PHY_H_ 37 #define _E1000_PHY_H_ 38 39 typedef enum { 40 e1000_ms_hw_default = 0, 41 e1000_ms_force_master, 42 e1000_ms_force_slave, 43 e1000_ms_auto 44 } e1000_ms_type; 45 46 typedef enum { 47 e1000_smart_speed_default = 0, 48 e1000_smart_speed_on, 49 e1000_smart_speed_off 50 } e1000_smart_speed; 51 52 s32 e1000_check_downshift_generic(struct e1000_hw *hw); 53 s32 e1000_check_polarity_m88(struct e1000_hw *hw); 54 s32 e1000_check_polarity_igp(struct e1000_hw *hw); 55 s32 e1000_check_reset_block_generic(struct e1000_hw *hw); 56 s32 e1000_copper_link_autoneg(struct e1000_hw *hw); 57 s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw); 58 s32 e1000_copper_link_setup_igp(struct e1000_hw *hw); 59 s32 e1000_copper_link_setup_m88(struct e1000_hw *hw); 60 s32 e1000_phy_force_speed_duplex_igp(struct e1000_hw *hw); 61 s32 e1000_phy_force_speed_duplex_m88(struct e1000_hw *hw); 62 s32 e1000_get_cable_length_m88(struct e1000_hw *hw); 63 s32 e1000_get_cable_length_igp_2(struct e1000_hw *hw); 64 s32 e1000_get_cfg_done_generic(struct e1000_hw *hw); 65 s32 e1000_get_phy_id(struct e1000_hw *hw); 66 s32 e1000_get_phy_info_igp(struct e1000_hw *hw); 67 s32 e1000_get_phy_info_m88(struct e1000_hw *hw); 68 s32 e1000_phy_sw_reset_generic(struct e1000_hw *hw); 69 void e1000_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl); 70 s32 e1000_phy_hw_reset_generic(struct e1000_hw *hw); 71 s32 e1000_phy_reset_dsp_generic(struct e1000_hw *hw); 72 s32 e1000_phy_setup_autoneg(struct e1000_hw *hw); 73 s32 e1000_read_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 *data); 74 s32 e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data); 75 s32 e1000_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data); 76 s32 e1000_set_d3_lplu_state_generic(struct e1000_hw *hw, bool active); 77 s32 e1000_setup_copper_link_generic(struct e1000_hw *hw); 78 s32 e1000_wait_autoneg_generic(struct e1000_hw *hw); 79 s32 e1000_write_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 data); 80 s32 e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data); 81 s32 e1000_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data); 82 s32 e1000_phy_reset_dsp(struct e1000_hw *hw); 83 s32 e1000_phy_has_link_generic(struct e1000_hw *hw, u32 iterations, 84 u32 usec_interval, bool *success); 85 s32 e1000_phy_init_script_igp3(struct e1000_hw *hw); 86 e1000_phy_type e1000_get_phy_type_from_id(u32 phy_id); 87 #define E1000_MAX_PHY_ADDR 4 88 89 /* IGP01E1000 Specific Registers */ 90 #define IGP01E1000_PHY_PORT_CONFIG 0x10 /* Port Config */ 91 #define IGP01E1000_PHY_PORT_STATUS 0x11 /* Status */ 92 #define IGP01E1000_PHY_PORT_CTRL 0x12 /* Control */ 93 #define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health */ 94 #define IGP01E1000_GMII_FIFO 0x14 /* GMII FIFO */ 95 #define IGP01E1000_PHY_CHANNEL_QUALITY 0x15 /* PHY Channel Quality */ 96 #define IGP02E1000_PHY_POWER_MGMT 0x19 /* Power Management */ 97 #define IGP01E1000_PHY_PAGE_SELECT 0x1F /* Page Select */ 98 #define BM_PHY_PAGE_SELECT 22 /* Page Select for IGP 4 */ 99 #define IGP_PAGE_SHIFT 5 100 #define PHY_REG_MASK 0x1F 101 102 #define BM_WUC_PAGE 800 103 #define BM_WUC_ADDRESS_OPCODE 0x11 104 #define BM_WUC_DATA_OPCODE 0x12 105 #define BM_WUC_ENABLE_PAGE 769 106 #define BM_WUC_ENABLE_REG 17 107 #define BM_WUC_ENABLE_BIT (1 << 2) 108 #define BM_WUC_HOST_WU_BIT (1 << 4) 109 110 #define IGP01E1000_PHY_PCS_INIT_REG 0x00B4 111 #define IGP01E1000_PHY_POLARITY_MASK 0x0078 112 113 #define IGP01E1000_PSCR_AUTO_MDIX 0x1000 114 #define IGP01E1000_PSCR_FORCE_MDI_MDIX 0x2000 /* 0=MDI, 1=MDIX */ 115 116 #define IGP01E1000_PSCFR_SMART_SPEED 0x0080 117 118 /* Enable flexible speed on link-up */ 119 #define IGP01E1000_GMII_FLEX_SPD 0x0010 120 #define IGP01E1000_GMII_SPD 0x0020 /* Enable SPD */ 121 122 #define IGP02E1000_PM_SPD 0x0001 /* Smart Power Down */ 123 #define IGP02E1000_PM_D0_LPLU 0x0002 /* For D0a states */ 124 #define IGP02E1000_PM_D3_LPLU 0x0004 /* For all other states */ 125 126 #define IGP01E1000_PLHR_SS_DOWNGRADE 0x8000 127 128 #define IGP01E1000_PSSR_POLARITY_REVERSED 0x0002 129 #define IGP01E1000_PSSR_MDIX 0x0008 130 #define IGP01E1000_PSSR_SPEED_MASK 0xC000 131 #define IGP01E1000_PSSR_SPEED_1000MBPS 0xC000 132 133 #define IGP02E1000_PHY_CHANNEL_NUM 4 134 #define IGP02E1000_PHY_AGC_A 0x11B1 135 #define IGP02E1000_PHY_AGC_B 0x12B1 136 #define IGP02E1000_PHY_AGC_C 0x14B1 137 #define IGP02E1000_PHY_AGC_D 0x18B1 138 139 #define IGP02E1000_AGC_LENGTH_SHIFT 9 /* Course - 15:13, Fine - 12:9 */ 140 #define IGP02E1000_AGC_LENGTH_MASK 0x7F 141 #define IGP02E1000_AGC_RANGE 15 142 143 #define IGP03E1000_PHY_MISC_CTRL 0x1B 144 #define IGP03E1000_PHY_MISC_DUPLEX_MANUAL_SET 0x1000 /* Manually Set Duplex */ 145 146 #define E1000_CABLE_LENGTH_UNDEFINED 0xFF 147 148 #define E1000_KMRNCTRLSTA_OFFSET 0x001F0000 149 #define E1000_KMRNCTRLSTA_OFFSET_SHIFT 16 150 #define E1000_KMRNCTRLSTA_REN 0x00200000 151 #define E1000_KMRNCTRLSTA_DIAG_OFFSET 0x3 /* Kumeran Diagnostic */ 152 #define E1000_KMRNCTRLSTA_DIAG_NELPBK 0x1000 /* Nearend Loopback mode */ 153 154 #define IFE_PHY_EXTENDED_STATUS_CONTROL 0x10 155 #define IFE_PHY_SPECIAL_CONTROL 0x11 /* 100BaseTx PHY Special Control */ 156 #define IFE_PHY_SPECIAL_CONTROL_LED 0x1B /* PHY Special and LED Control */ 157 #define IFE_PHY_MDIX_CONTROL 0x1C /* MDI/MDI-X Control */ 158 159 /* IFE PHY Extended Status Control */ 160 #define IFE_PESC_POLARITY_REVERSED 0x0100 161 162 /* IFE PHY Special Control */ 163 #define IFE_PSC_AUTO_POLARITY_DISABLE 0x0010 164 #define IFE_PSC_FORCE_POLARITY 0x0020 165 #define IFE_PSC_DISABLE_DYNAMIC_POWER_DOWN 0x0100 166 167 /* IFE PHY Special Control and LED Control */ 168 #define IFE_PSCL_PROBE_MODE 0x0020 169 #define IFE_PSCL_PROBE_LEDS_OFF 0x0006 /* Force LEDs 0 and 2 off */ 170 #define IFE_PSCL_PROBE_LEDS_ON 0x0007 /* Force LEDs 0 and 2 on */ 171 172 /* IFE PHY MDIX Control */ 173 #define IFE_PMC_MDIX_STATUS 0x0020 /* 1=MDI-X, 0=MDI */ 174 #define IFE_PMC_FORCE_MDIX 0x0040 /* 1=force MDI-X, 0=force MDI */ 175 #define IFE_PMC_AUTO_MDIX 0x0080 /* 1=enable auto MDI/MDI-X, 0=disable */ 176 177 #endif
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