Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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sys/dev/em/if_em.c
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1 /************************************************************************** 2 3 Copyright (c) 2001-2006, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ***************************************************************************/ 33 34 /*$FreeBSD: releng/6.2/sys/dev/em/if_em.c 164143 2006-11-10 09:30:27Z jfv $*/ 35 36 #ifdef HAVE_KERNEL_OPTION_HEADERS 37 #include "opt_device_polling.h" 38 #endif 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/bus.h> 43 #include <sys/endian.h> 44 #include <sys/kernel.h> 45 #include <sys/kthread.h> 46 #include <sys/malloc.h> 47 #include <sys/mbuf.h> 48 #include <sys/module.h> 49 #include <sys/rman.h> 50 #include <sys/socket.h> 51 #include <sys/sockio.h> 52 #include <sys/sysctl.h> 53 #include <sys/taskqueue.h> 54 55 #include <machine/bus.h> 56 #include <machine/resource.h> 57 58 #include <net/bpf.h> 59 #include <net/ethernet.h> 60 #include <net/if.h> 61 #include <net/if_arp.h> 62 #include <net/if_dl.h> 63 #include <net/if_media.h> 64 65 #include <net/if_types.h> 66 #include <net/if_vlan_var.h> 67 68 #include <netinet/in_systm.h> 69 #include <netinet/in.h> 70 #include <netinet/if_ether.h> 71 #include <netinet/ip.h> 72 #include <netinet/tcp.h> 73 #include <netinet/udp.h> 74 75 #include <machine/in_cksum.h> 76 77 #include <dev/pci/pcivar.h> 78 #include <dev/pci/pcireg.h> 79 #include <dev/em/if_em_hw.h> 80 #include <dev/em/if_em.h> 81 82 /********************************************************************* 83 * Set this to one to display debug statistics 84 *********************************************************************/ 85 int em_display_debug_stats = 0; 86 87 /********************************************************************* 88 * Driver version 89 *********************************************************************/ 90 char em_driver_version[] = "Version - 6.2.9"; 91 92 93 /********************************************************************* 94 * PCI Device ID Table 95 * 96 * Used by probe to select devices to load on 97 * Last field stores an index into em_strings 98 * Last entry must be all 0s 99 * 100 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, String Index } 101 *********************************************************************/ 102 103 static em_vendor_info_t em_vendor_info_array[] = 104 { 105 /* Intel(R) PRO/1000 Network Connection */ 106 { 0x8086, E1000_DEV_ID_82540EM, PCI_ANY_ID, PCI_ANY_ID, 0}, 107 { 0x8086, E1000_DEV_ID_82540EM_LOM, PCI_ANY_ID, PCI_ANY_ID, 0}, 108 { 0x8086, E1000_DEV_ID_82540EP, PCI_ANY_ID, PCI_ANY_ID, 0}, 109 { 0x8086, E1000_DEV_ID_82540EP_LOM, PCI_ANY_ID, PCI_ANY_ID, 0}, 110 { 0x8086, E1000_DEV_ID_82540EP_LP, PCI_ANY_ID, PCI_ANY_ID, 0}, 111 112 { 0x8086, E1000_DEV_ID_82541EI, PCI_ANY_ID, PCI_ANY_ID, 0}, 113 { 0x8086, E1000_DEV_ID_82541ER, PCI_ANY_ID, PCI_ANY_ID, 0}, 114 { 0x8086, E1000_DEV_ID_82541ER_LOM, PCI_ANY_ID, PCI_ANY_ID, 0}, 115 { 0x8086, E1000_DEV_ID_82541EI_MOBILE, PCI_ANY_ID, PCI_ANY_ID, 0}, 116 { 0x8086, E1000_DEV_ID_82541GI, PCI_ANY_ID, PCI_ANY_ID, 0}, 117 { 0x8086, E1000_DEV_ID_82541GI_LF, PCI_ANY_ID, PCI_ANY_ID, 0}, 118 { 0x8086, E1000_DEV_ID_82541GI_MOBILE, PCI_ANY_ID, PCI_ANY_ID, 0}, 119 120 { 0x8086, E1000_DEV_ID_82542, PCI_ANY_ID, PCI_ANY_ID, 0}, 121 122 { 0x8086, E1000_DEV_ID_82543GC_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 123 { 0x8086, E1000_DEV_ID_82543GC_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 124 125 { 0x8086, E1000_DEV_ID_82544EI_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 126 { 0x8086, E1000_DEV_ID_82544EI_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 127 { 0x8086, E1000_DEV_ID_82544GC_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 128 { 0x8086, E1000_DEV_ID_82544GC_LOM, PCI_ANY_ID, PCI_ANY_ID, 0}, 129 130 { 0x8086, E1000_DEV_ID_82545EM_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 131 { 0x8086, E1000_DEV_ID_82545EM_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 132 { 0x8086, E1000_DEV_ID_82545GM_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 133 { 0x8086, E1000_DEV_ID_82545GM_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 134 { 0x8086, E1000_DEV_ID_82545GM_SERDES, PCI_ANY_ID, PCI_ANY_ID, 0}, 135 136 { 0x8086, E1000_DEV_ID_82546EB_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 137 { 0x8086, E1000_DEV_ID_82546EB_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 138 { 0x8086, E1000_DEV_ID_82546EB_QUAD_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 139 { 0x8086, E1000_DEV_ID_82546GB_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 140 { 0x8086, E1000_DEV_ID_82546GB_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 141 { 0x8086, E1000_DEV_ID_82546GB_SERDES, PCI_ANY_ID, PCI_ANY_ID, 0}, 142 { 0x8086, E1000_DEV_ID_82546GB_PCIE, PCI_ANY_ID, PCI_ANY_ID, 0}, 143 { 0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 144 { 0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3, 145 PCI_ANY_ID, PCI_ANY_ID, 0}, 146 147 { 0x8086, E1000_DEV_ID_82547EI, PCI_ANY_ID, PCI_ANY_ID, 0}, 148 { 0x8086, E1000_DEV_ID_82547EI_MOBILE, PCI_ANY_ID, PCI_ANY_ID, 0}, 149 { 0x8086, E1000_DEV_ID_82547GI, PCI_ANY_ID, PCI_ANY_ID, 0}, 150 151 { 0x8086, E1000_DEV_ID_82571EB_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 152 { 0x8086, E1000_DEV_ID_82571EB_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 153 { 0x8086, E1000_DEV_ID_82571EB_SERDES, PCI_ANY_ID, PCI_ANY_ID, 0}, 154 { 0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER, 155 PCI_ANY_ID, PCI_ANY_ID, 0}, 156 { 0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE, 157 PCI_ANY_ID, PCI_ANY_ID, 0}, 158 159 { 0x8086, E1000_DEV_ID_82572EI_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 160 { 0x8086, E1000_DEV_ID_82572EI_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 161 { 0x8086, E1000_DEV_ID_82572EI_SERDES, PCI_ANY_ID, PCI_ANY_ID, 0}, 162 { 0x8086, E1000_DEV_ID_82572EI, PCI_ANY_ID, PCI_ANY_ID, 0}, 163 164 { 0x8086, E1000_DEV_ID_82573E, PCI_ANY_ID, PCI_ANY_ID, 0}, 165 { 0x8086, E1000_DEV_ID_82573E_IAMT, PCI_ANY_ID, PCI_ANY_ID, 0}, 166 { 0x8086, E1000_DEV_ID_82573L, PCI_ANY_ID, PCI_ANY_ID, 0}, 167 { 0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_SPT, 168 PCI_ANY_ID, PCI_ANY_ID, 0}, 169 { 0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_SPT, 170 PCI_ANY_ID, PCI_ANY_ID, 0}, 171 { 0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_DPT, 172 PCI_ANY_ID, PCI_ANY_ID, 0}, 173 { 0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_DPT, 174 PCI_ANY_ID, PCI_ANY_ID, 0}, 175 { 0x8086, E1000_DEV_ID_ICH8_IGP_M_AMT, PCI_ANY_ID, PCI_ANY_ID, 0}, 176 { 0x8086, E1000_DEV_ID_ICH8_IGP_AMT, PCI_ANY_ID, PCI_ANY_ID, 0}, 177 { 0x8086, E1000_DEV_ID_ICH8_IGP_C, PCI_ANY_ID, PCI_ANY_ID, 0}, 178 { 0x8086, E1000_DEV_ID_ICH8_IFE, PCI_ANY_ID, PCI_ANY_ID, 0}, 179 { 0x8086, E1000_DEV_ID_ICH8_IFE_GT, PCI_ANY_ID, PCI_ANY_ID, 0}, 180 { 0x8086, E1000_DEV_ID_ICH8_IFE_G, PCI_ANY_ID, PCI_ANY_ID, 0}, 181 { 0x8086, E1000_DEV_ID_ICH8_IGP_M, PCI_ANY_ID, PCI_ANY_ID, 0}, 182 183 /* required last entry */ 184 { 0, 0, 0, 0, 0} 185 }; 186 187 /********************************************************************* 188 * Table of branding strings for all supported NICs. 189 *********************************************************************/ 190 191 static char *em_strings[] = { 192 "Intel(R) PRO/1000 Network Connection" 193 }; 194 195 /********************************************************************* 196 * Function prototypes 197 *********************************************************************/ 198 static int em_probe(device_t); 199 static int em_attach(device_t); 200 static int em_detach(device_t); 201 static int em_shutdown(device_t); 202 static int em_suspend(device_t); 203 static int em_resume(device_t); 204 static void em_start(struct ifnet *); 205 static void em_start_locked(struct ifnet *ifp); 206 static int em_ioctl(struct ifnet *, u_long, caddr_t); 207 static void em_watchdog(struct adapter *); 208 static void em_init(void *); 209 static void em_init_locked(struct adapter *); 210 static void em_stop(void *); 211 static void em_media_status(struct ifnet *, struct ifmediareq *); 212 static int em_media_change(struct ifnet *); 213 static void em_identify_hardware(struct adapter *); 214 static int em_allocate_pci_resources(struct adapter *); 215 static int em_allocate_intr(struct adapter *); 216 static void em_free_intr(struct adapter *); 217 static void em_free_pci_resources(struct adapter *); 218 static void em_local_timer(void *); 219 static int em_hardware_init(struct adapter *); 220 static void em_setup_interface(device_t, struct adapter *); 221 static void em_setup_transmit_structures(struct adapter *); 222 static void em_initialize_transmit_unit(struct adapter *); 223 static int em_setup_receive_structures(struct adapter *); 224 static void em_initialize_receive_unit(struct adapter *); 225 static void em_enable_intr(struct adapter *); 226 static void em_disable_intr(struct adapter *); 227 static void em_free_transmit_structures(struct adapter *); 228 static void em_free_receive_structures(struct adapter *); 229 static void em_update_stats_counters(struct adapter *); 230 static void em_txeof(struct adapter *); 231 static int em_allocate_receive_structures(struct adapter *); 232 static int em_allocate_transmit_structures(struct adapter *); 233 static int em_rxeof(struct adapter *, int); 234 #ifndef __NO_STRICT_ALIGNMENT 235 static int em_fixup_rx(struct adapter *); 236 #endif 237 static void em_receive_checksum(struct adapter *, struct em_rx_desc *, 238 struct mbuf *); 239 static void em_transmit_checksum_setup(struct adapter *, struct mbuf *, 240 uint32_t *, uint32_t *); 241 #ifdef EM_TSO 242 static boolean_t em_tso_setup(struct adapter *, struct mbuf *, u_int32_t *, 243 uint32_t *); 244 #endif 245 static void em_set_promisc(struct adapter *); 246 static void em_disable_promisc(struct adapter *); 247 static void em_set_multi(struct adapter *); 248 static void em_print_hw_stats(struct adapter *); 249 static void em_update_link_status(struct adapter *); 250 static int em_get_buf(int i, struct adapter *, struct mbuf *); 251 static void em_enable_vlans(struct adapter *); 252 static void em_disable_vlans(struct adapter *); 253 static int em_encap(struct adapter *, struct mbuf **); 254 static void em_smartspeed(struct adapter *); 255 static int em_82547_fifo_workaround(struct adapter *, int); 256 static void em_82547_update_fifo_head(struct adapter *, int); 257 static int em_82547_tx_fifo_reset(struct adapter *); 258 static void em_82547_move_tail(void *); 259 static int em_dma_malloc(struct adapter *, bus_size_t, 260 struct em_dma_alloc *, int); 261 static void em_dma_free(struct adapter *, struct em_dma_alloc *); 262 static void em_print_debug_info(struct adapter *); 263 static int em_is_valid_ether_addr(uint8_t *); 264 static int em_sysctl_stats(SYSCTL_HANDLER_ARGS); 265 static int em_sysctl_debug_info(SYSCTL_HANDLER_ARGS); 266 static uint32_t em_fill_descriptors (bus_addr_t address, uint32_t length, 267 PDESC_ARRAY desc_array); 268 static int em_sysctl_int_delay(SYSCTL_HANDLER_ARGS); 269 static void em_add_int_delay_sysctl(struct adapter *, const char *, 270 const char *, struct em_int_delay_info *, int, int); 271 static void em_add_rx_process_limit(struct adapter *, const char *, 272 const char *, int *, int); 273 #ifdef EM_FAST_INTR 274 static void em_intr_fast(void *); 275 static void em_handle_rxtx(void *context, int pending); 276 static void em_handle_link(void *context, int pending); 277 #else /* Legacy Interrupt Handling */ 278 static void em_intr(void *); 279 #ifdef DEVICE_POLLING 280 static poll_handler_t em_poll; 281 #endif /* DEVICE_POLLING */ 282 #endif /* EM_FAST_INTR */ 283 284 /********************************************************************* 285 * FreeBSD Device Interface Entry Points 286 *********************************************************************/ 287 288 static device_method_t em_methods[] = { 289 /* Device interface */ 290 DEVMETHOD(device_probe, em_probe), 291 DEVMETHOD(device_attach, em_attach), 292 DEVMETHOD(device_detach, em_detach), 293 DEVMETHOD(device_shutdown, em_shutdown), 294 DEVMETHOD(device_suspend, em_suspend), 295 DEVMETHOD(device_resume, em_resume), 296 {0, 0} 297 }; 298 299 static driver_t em_driver = { 300 "em", em_methods, sizeof(struct adapter), 301 }; 302 303 static devclass_t em_devclass; 304 DRIVER_MODULE(em, pci, em_driver, em_devclass, 0, 0); 305 MODULE_DEPEND(em, pci, 1, 1, 1); 306 MODULE_DEPEND(em, ether, 1, 1, 1); 307 308 /********************************************************************* 309 * Tunable default values. 310 *********************************************************************/ 311 312 #define E1000_TICKS_TO_USECS(ticks) ((1024 * (ticks) + 500) / 1000) 313 #define E1000_USECS_TO_TICKS(usecs) ((1000 * (usecs) + 512) / 1024) 314 #define M_TSO_LEN 66 /* mbuf with just hdr and TSO pkthdr */ 315 316 static int em_tx_int_delay_dflt = E1000_TICKS_TO_USECS(EM_TIDV); 317 static int em_rx_int_delay_dflt = E1000_TICKS_TO_USECS(EM_RDTR); 318 static int em_tx_abs_int_delay_dflt = E1000_TICKS_TO_USECS(EM_TADV); 319 static int em_rx_abs_int_delay_dflt = E1000_TICKS_TO_USECS(EM_RADV); 320 static int em_rxd = EM_DEFAULT_RXD; 321 static int em_txd = EM_DEFAULT_TXD; 322 static int em_smart_pwr_down = FALSE; 323 324 TUNABLE_INT("hw.em.tx_int_delay", &em_tx_int_delay_dflt); 325 TUNABLE_INT("hw.em.rx_int_delay", &em_rx_int_delay_dflt); 326 TUNABLE_INT("hw.em.tx_abs_int_delay", &em_tx_abs_int_delay_dflt); 327 TUNABLE_INT("hw.em.rx_abs_int_delay", &em_rx_abs_int_delay_dflt); 328 TUNABLE_INT("hw.em.rxd", &em_rxd); 329 TUNABLE_INT("hw.em.txd", &em_txd); 330 TUNABLE_INT("hw.em.smart_pwr_down", &em_smart_pwr_down); 331 332 /* How many packets rxeof tries to clean at a time */ 333 static int em_rx_process_limit = 100; 334 TUNABLE_INT("hw.em.rx_process_limit", &em_rx_process_limit); 335 336 /********************************************************************* 337 * Device identification routine 338 * 339 * em_probe determines if the driver should be loaded on 340 * adapter based on PCI vendor/device id of the adapter. 341 * 342 * return BUS_PROBE_DEFAULT on success, positive on failure 343 *********************************************************************/ 344 345 static int 346 em_probe(device_t dev) 347 { 348 char adapter_name[60]; 349 uint16_t pci_vendor_id = 0; 350 uint16_t pci_device_id = 0; 351 uint16_t pci_subvendor_id = 0; 352 uint16_t pci_subdevice_id = 0; 353 em_vendor_info_t *ent; 354 355 INIT_DEBUGOUT("em_probe: begin"); 356 357 pci_vendor_id = pci_get_vendor(dev); 358 if (pci_vendor_id != EM_VENDOR_ID) 359 return (ENXIO); 360 361 pci_device_id = pci_get_device(dev); 362 pci_subvendor_id = pci_get_subvendor(dev); 363 pci_subdevice_id = pci_get_subdevice(dev); 364 365 ent = em_vendor_info_array; 366 while (ent->vendor_id != 0) { 367 if ((pci_vendor_id == ent->vendor_id) && 368 (pci_device_id == ent->device_id) && 369 370 ((pci_subvendor_id == ent->subvendor_id) || 371 (ent->subvendor_id == PCI_ANY_ID)) && 372 373 ((pci_subdevice_id == ent->subdevice_id) || 374 (ent->subdevice_id == PCI_ANY_ID))) { 375 sprintf(adapter_name, "%s %s", 376 em_strings[ent->index], 377 em_driver_version); 378 device_set_desc_copy(dev, adapter_name); 379 return (BUS_PROBE_DEFAULT); 380 } 381 ent++; 382 } 383 384 return (ENXIO); 385 } 386 387 /********************************************************************* 388 * Device initialization routine 389 * 390 * The attach entry point is called when the driver is being loaded. 391 * This routine identifies the type of hardware, allocates all resources 392 * and initializes the hardware. 393 * 394 * return 0 on success, positive on failure 395 *********************************************************************/ 396 397 static int 398 em_attach(device_t dev) 399 { 400 struct adapter *adapter; 401 int tsize, rsize; 402 int error = 0; 403 404 INIT_DEBUGOUT("em_attach: begin"); 405 406 adapter = device_get_softc(dev); 407 adapter->dev = adapter->osdep.dev = dev; 408 EM_LOCK_INIT(adapter, device_get_nameunit(dev)); 409 410 /* SYSCTL stuff */ 411 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 412 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 413 OID_AUTO, "debug_info", CTLTYPE_INT|CTLFLAG_RW, adapter, 0, 414 em_sysctl_debug_info, "I", "Debug Information"); 415 416 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 417 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 418 OID_AUTO, "stats", CTLTYPE_INT|CTLFLAG_RW, adapter, 0, 419 em_sysctl_stats, "I", "Statistics"); 420 421 callout_init_mtx(&adapter->timer, &adapter->mtx, 0); 422 callout_init_mtx(&adapter->tx_fifo_timer, &adapter->mtx, 0); 423 424 /* Determine hardware revision */ 425 em_identify_hardware(adapter); 426 427 /* Set up some sysctls for the tunable interrupt delays */ 428 em_add_int_delay_sysctl(adapter, "rx_int_delay", 429 "receive interrupt delay in usecs", &adapter->rx_int_delay, 430 E1000_REG_OFFSET(&adapter->hw, RDTR), em_rx_int_delay_dflt); 431 em_add_int_delay_sysctl(adapter, "tx_int_delay", 432 "transmit interrupt delay in usecs", &adapter->tx_int_delay, 433 E1000_REG_OFFSET(&adapter->hw, TIDV), em_tx_int_delay_dflt); 434 if (adapter->hw.mac_type >= em_82540) { 435 em_add_int_delay_sysctl(adapter, "rx_abs_int_delay", 436 "receive interrupt delay limit in usecs", 437 &adapter->rx_abs_int_delay, 438 E1000_REG_OFFSET(&adapter->hw, RADV), 439 em_rx_abs_int_delay_dflt); 440 em_add_int_delay_sysctl(adapter, "tx_abs_int_delay", 441 "transmit interrupt delay limit in usecs", 442 &adapter->tx_abs_int_delay, 443 E1000_REG_OFFSET(&adapter->hw, TADV), 444 em_tx_abs_int_delay_dflt); 445 } 446 447 /* Sysctls for limiting the amount of work done in the taskqueue */ 448 em_add_rx_process_limit(adapter, "rx_processing_limit", 449 "max number of rx packets to process", &adapter->rx_process_limit, 450 em_rx_process_limit); 451 452 /* 453 * Validate number of transmit and receive descriptors. It 454 * must not exceed hardware maximum, and must be multiple 455 * of EM_DBA_ALIGN. 456 */ 457 if (((em_txd * sizeof(struct em_tx_desc)) % EM_DBA_ALIGN) != 0 || 458 (adapter->hw.mac_type >= em_82544 && em_txd > EM_MAX_TXD) || 459 (adapter->hw.mac_type < em_82544 && em_txd > EM_MAX_TXD_82543) || 460 (em_txd < EM_MIN_TXD)) { 461 device_printf(dev, "Using %d TX descriptors instead of %d!\n", 462 EM_DEFAULT_TXD, em_txd); 463 adapter->num_tx_desc = EM_DEFAULT_TXD; 464 } else 465 adapter->num_tx_desc = em_txd; 466 if (((em_rxd * sizeof(struct em_rx_desc)) % EM_DBA_ALIGN) != 0 || 467 (adapter->hw.mac_type >= em_82544 && em_rxd > EM_MAX_RXD) || 468 (adapter->hw.mac_type < em_82544 && em_rxd > EM_MAX_RXD_82543) || 469 (em_rxd < EM_MIN_RXD)) { 470 device_printf(dev, "Using %d RX descriptors instead of %d!\n", 471 EM_DEFAULT_RXD, em_rxd); 472 adapter->num_rx_desc = EM_DEFAULT_RXD; 473 } else 474 adapter->num_rx_desc = em_rxd; 475 476 adapter->hw.autoneg = DO_AUTO_NEG; 477 adapter->hw.wait_autoneg_complete = WAIT_FOR_AUTO_NEG_DEFAULT; 478 adapter->hw.autoneg_advertised = AUTONEG_ADV_DEFAULT; 479 adapter->hw.tbi_compatibility_en = TRUE; 480 adapter->rx_buffer_len = EM_RXBUFFER_2048; 481 482 adapter->hw.phy_init_script = 1; 483 adapter->hw.phy_reset_disable = FALSE; 484 485 #ifndef EM_MASTER_SLAVE 486 adapter->hw.master_slave = em_ms_hw_default; 487 #else 488 adapter->hw.master_slave = EM_MASTER_SLAVE; 489 #endif 490 /* 491 * Set the max frame size assuming standard ethernet 492 * sized frames. 493 */ 494 adapter->hw.max_frame_size = 495 ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN; 496 497 adapter->hw.min_frame_size = 498 MINIMUM_ETHERNET_PACKET_SIZE + ETHER_CRC_LEN; 499 500 /* 501 * This controls when hardware reports transmit completion 502 * status. 503 */ 504 adapter->hw.report_tx_early = 1; 505 if (em_allocate_pci_resources(adapter)) { 506 device_printf(dev, "Allocation of PCI resources failed\n"); 507 error = ENXIO; 508 goto err_pci; 509 } 510 511 /* Initialize eeprom parameters */ 512 em_init_eeprom_params(&adapter->hw); 513 514 tsize = roundup2(adapter->num_tx_desc * sizeof(struct em_tx_desc), 515 EM_DBA_ALIGN); 516 517 /* Allocate Transmit Descriptor ring */ 518 if (em_dma_malloc(adapter, tsize, &adapter->txdma, BUS_DMA_NOWAIT)) { 519 device_printf(dev, "Unable to allocate tx_desc memory\n"); 520 error = ENOMEM; 521 goto err_tx_desc; 522 } 523 adapter->tx_desc_base = (struct em_tx_desc *)adapter->txdma.dma_vaddr; 524 525 rsize = roundup2(adapter->num_rx_desc * sizeof(struct em_rx_desc), 526 EM_DBA_ALIGN); 527 528 /* Allocate Receive Descriptor ring */ 529 if (em_dma_malloc(adapter, rsize, &adapter->rxdma, BUS_DMA_NOWAIT)) { 530 device_printf(dev, "Unable to allocate rx_desc memory\n"); 531 error = ENOMEM; 532 goto err_rx_desc; 533 } 534 adapter->rx_desc_base = (struct em_rx_desc *)adapter->rxdma.dma_vaddr; 535 536 /* Initialize the hardware */ 537 if (em_hardware_init(adapter)) { 538 device_printf(dev, "Unable to initialize the hardware\n"); 539 error = EIO; 540 goto err_hw_init; 541 } 542 543 /* Copy the permanent MAC address out of the EEPROM */ 544 if (em_read_mac_addr(&adapter->hw) < 0) { 545 device_printf(dev, "EEPROM read error while reading MAC" 546 " address\n"); 547 error = EIO; 548 goto err_hw_init; 549 } 550 551 if (!em_is_valid_ether_addr(adapter->hw.mac_addr)) { 552 device_printf(dev, "Invalid MAC address\n"); 553 error = EIO; 554 goto err_hw_init; 555 } 556 557 /* Allocate transmit descriptors and buffers */ 558 if (em_allocate_transmit_structures(adapter)) { 559 device_printf(dev, "Could not setup transmit structures\n"); 560 error = ENOMEM; 561 goto err_tx_struct; 562 } 563 564 /* Allocate receive descriptors and buffers */ 565 if (em_allocate_receive_structures(adapter)) { 566 device_printf(dev, "Could not setup receive structures\n"); 567 error = ENOMEM; 568 goto err_rx_struct; 569 } 570 571 /* Setup OS specific network interface */ 572 em_setup_interface(dev, adapter); 573 574 em_allocate_intr(adapter); 575 576 /* Initialize statistics */ 577 em_clear_hw_cntrs(&adapter->hw); 578 em_update_stats_counters(adapter); 579 adapter->hw.get_link_status = 1; 580 em_update_link_status(adapter); 581 582 /* Indicate SOL/IDER usage */ 583 if (em_check_phy_reset_block(&adapter->hw)) 584 device_printf(dev, 585 "PHY reset is blocked due to SOL/IDER session.\n"); 586 587 /* Identify 82544 on PCIX */ 588 em_get_bus_info(&adapter->hw); 589 if (adapter->hw.bus_type == em_bus_type_pcix && 590 adapter->hw.mac_type == em_82544) 591 adapter->pcix_82544 = TRUE; 592 else 593 adapter->pcix_82544 = FALSE; 594 595 INIT_DEBUGOUT("em_attach: end"); 596 597 return (0); 598 599 err_rx_struct: 600 em_free_transmit_structures(adapter); 601 err_hw_init: 602 err_tx_struct: 603 em_dma_free(adapter, &adapter->rxdma); 604 err_rx_desc: 605 em_dma_free(adapter, &adapter->txdma); 606 err_tx_desc: 607 err_pci: 608 em_free_intr(adapter); 609 em_free_pci_resources(adapter); 610 EM_LOCK_DESTROY(adapter); 611 612 return (error); 613 } 614 615 /********************************************************************* 616 * Device removal routine 617 * 618 * The detach entry point is called when the driver is being removed. 619 * This routine stops the adapter and deallocates all the resources 620 * that were allocated for driver operation. 621 * 622 * return 0 on success, positive on failure 623 *********************************************************************/ 624 625 static int 626 em_detach(device_t dev) 627 { 628 struct adapter *adapter = device_get_softc(dev); 629 struct ifnet *ifp = adapter->ifp; 630 631 INIT_DEBUGOUT("em_detach: begin"); 632 633 #ifdef DEVICE_POLLING 634 if (ifp->if_capenable & IFCAP_POLLING) 635 ether_poll_deregister(ifp); 636 #endif 637 638 em_free_intr(adapter); 639 EM_LOCK(adapter); 640 adapter->in_detach = 1; 641 em_stop(adapter); 642 em_phy_hw_reset(&adapter->hw); 643 EM_UNLOCK(adapter); 644 ether_ifdetach(adapter->ifp); 645 646 callout_drain(&adapter->timer); 647 callout_drain(&adapter->tx_fifo_timer); 648 649 em_free_pci_resources(adapter); 650 bus_generic_detach(dev); 651 if_free(ifp); 652 653 em_free_transmit_structures(adapter); 654 em_free_receive_structures(adapter); 655 656 /* Free Transmit Descriptor ring */ 657 if (adapter->tx_desc_base) { 658 em_dma_free(adapter, &adapter->txdma); 659 adapter->tx_desc_base = NULL; 660 } 661 662 /* Free Receive Descriptor ring */ 663 if (adapter->rx_desc_base) { 664 em_dma_free(adapter, &adapter->rxdma); 665 adapter->rx_desc_base = NULL; 666 } 667 668 EM_LOCK_DESTROY(adapter); 669 670 return (0); 671 } 672 673 /********************************************************************* 674 * 675 * Shutdown entry point 676 * 677 **********************************************************************/ 678 679 static int 680 em_shutdown(device_t dev) 681 { 682 struct adapter *adapter = device_get_softc(dev); 683 EM_LOCK(adapter); 684 em_stop(adapter); 685 EM_UNLOCK(adapter); 686 return (0); 687 } 688 689 /* 690 * Suspend/resume device methods. 691 */ 692 static int 693 em_suspend(device_t dev) 694 { 695 struct adapter *adapter = device_get_softc(dev); 696 697 EM_LOCK(adapter); 698 em_stop(adapter); 699 EM_UNLOCK(adapter); 700 701 return bus_generic_suspend(dev); 702 } 703 704 static int 705 em_resume(device_t dev) 706 { 707 struct adapter *adapter = device_get_softc(dev); 708 struct ifnet *ifp = adapter->ifp; 709 710 EM_LOCK(adapter); 711 em_init_locked(adapter); 712 if ((ifp->if_flags & IFF_UP) && 713 (ifp->if_drv_flags & IFF_DRV_RUNNING)) 714 em_start_locked(ifp); 715 EM_UNLOCK(adapter); 716 717 return bus_generic_resume(dev); 718 } 719 720 721 /********************************************************************* 722 * Transmit entry point 723 * 724 * em_start is called by the stack to initiate a transmit. 725 * The driver will remain in this routine as long as there are 726 * packets to transmit and transmit resources are available. 727 * In case resources are not available stack is notified and 728 * the packet is requeued. 729 **********************************************************************/ 730 731 static void 732 em_start_locked(struct ifnet *ifp) 733 { 734 struct adapter *adapter = ifp->if_softc; 735 struct mbuf *m_head; 736 737 EM_LOCK_ASSERT(adapter); 738 739 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING|IFF_DRV_OACTIVE)) != 740 IFF_DRV_RUNNING) 741 return; 742 if (!adapter->link_active) 743 return; 744 745 while (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 746 747 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 748 if (m_head == NULL) 749 break; 750 /* 751 * em_encap() can modify our pointer, and or make it NULL on 752 * failure. In that event, we can't requeue. 753 */ 754 if (em_encap(adapter, &m_head)) { 755 if (m_head == NULL) 756 break; 757 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 758 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 759 break; 760 } 761 762 /* Send a copy of the frame to the BPF listener */ 763 BPF_MTAP(ifp, m_head); 764 765 /* Set timeout in case hardware has problems transmitting. */ 766 adapter->watchdog_timer = EM_TX_TIMEOUT; 767 } 768 } 769 770 static void 771 em_start(struct ifnet *ifp) 772 { 773 struct adapter *adapter = ifp->if_softc; 774 775 EM_LOCK(adapter); 776 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 777 em_start_locked(ifp); 778 EM_UNLOCK(adapter); 779 } 780 781 /********************************************************************* 782 * Ioctl entry point 783 * 784 * em_ioctl is called when the user wants to configure the 785 * interface. 786 * 787 * return 0 on success, positive on failure 788 **********************************************************************/ 789 790 static int 791 em_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 792 { 793 struct adapter *adapter = ifp->if_softc; 794 struct ifreq *ifr = (struct ifreq *)data; 795 struct ifaddr *ifa = (struct ifaddr *)data; 796 int error = 0; 797 798 if (adapter->in_detach) 799 return (error); 800 801 switch (command) { 802 case SIOCSIFADDR: 803 case SIOCGIFADDR: 804 if (ifa->ifa_addr->sa_family == AF_INET) { 805 /* 806 * XXX 807 * Since resetting hardware takes a very long time 808 * and results in link renegotiation we only 809 * initialize the hardware only when it is absolutely 810 * required. 811 */ 812 ifp->if_flags |= IFF_UP; 813 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 814 EM_LOCK(adapter); 815 em_init_locked(adapter); 816 EM_UNLOCK(adapter); 817 } 818 arp_ifinit(ifp, ifa); 819 } else 820 error = ether_ioctl(ifp, command, data); 821 break; 822 case SIOCSIFMTU: 823 { 824 int max_frame_size; 825 uint16_t eeprom_data = 0; 826 827 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFMTU (Set Interface MTU)"); 828 829 EM_LOCK(adapter); 830 switch (adapter->hw.mac_type) { 831 case em_82573: 832 /* 833 * 82573 only supports jumbo frames 834 * if ASPM is disabled. 835 */ 836 em_read_eeprom(&adapter->hw, 837 EEPROM_INIT_3GIO_3, 1, &eeprom_data); 838 if (eeprom_data & EEPROM_WORD1A_ASPM_MASK) { 839 max_frame_size = ETHER_MAX_LEN; 840 break; 841 } 842 /* Allow Jumbo frames - fall thru */ 843 case em_82571: 844 case em_82572: 845 case em_80003es2lan: /* Limit Jumbo Frame size */ 846 max_frame_size = 9234; 847 break; 848 case em_ich8lan: 849 /* ICH8 does not support jumbo frames */ 850 max_frame_size = ETHER_MAX_LEN; 851 break; 852 default: 853 max_frame_size = MAX_JUMBO_FRAME_SIZE; 854 } 855 if (ifr->ifr_mtu > max_frame_size - ETHER_HDR_LEN - 856 ETHER_CRC_LEN) { 857 EM_UNLOCK(adapter); 858 error = EINVAL; 859 break; 860 } 861 862 ifp->if_mtu = ifr->ifr_mtu; 863 adapter->hw.max_frame_size = 864 ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; 865 em_init_locked(adapter); 866 EM_UNLOCK(adapter); 867 break; 868 } 869 case SIOCSIFFLAGS: 870 IOCTL_DEBUGOUT("ioctl rcv'd:\ 871 SIOCSIFFLAGS (Set Interface Flags)"); 872 EM_LOCK(adapter); 873 if (ifp->if_flags & IFF_UP) { 874 if ((ifp->if_drv_flags & IFF_DRV_RUNNING)) { 875 if ((ifp->if_flags ^ adapter->if_flags) & 876 IFF_PROMISC) { 877 em_disable_promisc(adapter); 878 em_set_promisc(adapter); 879 } 880 } else 881 em_init_locked(adapter); 882 } else { 883 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 884 em_stop(adapter); 885 } 886 } 887 adapter->if_flags = ifp->if_flags; 888 EM_UNLOCK(adapter); 889 break; 890 case SIOCADDMULTI: 891 case SIOCDELMULTI: 892 IOCTL_DEBUGOUT("ioctl rcv'd: SIOC(ADD|DEL)MULTI"); 893 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 894 EM_LOCK(adapter); 895 em_disable_intr(adapter); 896 em_set_multi(adapter); 897 if (adapter->hw.mac_type == em_82542_rev2_0) { 898 em_initialize_receive_unit(adapter); 899 } 900 #ifdef DEVICE_POLLING 901 if (!(ifp->if_capenable & IFCAP_POLLING)) 902 #endif 903 em_enable_intr(adapter); 904 EM_UNLOCK(adapter); 905 } 906 break; 907 case SIOCSIFMEDIA: 908 /* Check SOL/IDER usage */ 909 if (em_check_phy_reset_block(&adapter->hw)) { 910 device_printf(adapter->dev, "Media change is" 911 "blocked due to SOL/IDER session.\n"); 912 break; 913 } 914 case SIOCGIFMEDIA: 915 IOCTL_DEBUGOUT("ioctl rcv'd: \ 916 SIOCxIFMEDIA (Get/Set Interface Media)"); 917 error = ifmedia_ioctl(ifp, ifr, &adapter->media, command); 918 break; 919 case SIOCSIFCAP: 920 { 921 int mask, reinit; 922 923 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFCAP (Set Capabilities)"); 924 reinit = 0; 925 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 926 #ifdef DEVICE_POLLING 927 if (mask & IFCAP_POLLING) { 928 if (ifr->ifr_reqcap & IFCAP_POLLING) { 929 error = ether_poll_register(em_poll, ifp); 930 if (error) 931 return (error); 932 EM_LOCK(adapter); 933 em_disable_intr(adapter); 934 ifp->if_capenable |= IFCAP_POLLING; 935 EM_UNLOCK(adapter); 936 } else { 937 error = ether_poll_deregister(ifp); 938 /* Enable interrupt even in error case */ 939 EM_LOCK(adapter); 940 em_enable_intr(adapter); 941 ifp->if_capenable &= ~IFCAP_POLLING; 942 EM_UNLOCK(adapter); 943 } 944 } 945 #endif 946 if (mask & IFCAP_HWCSUM) { 947 ifp->if_capenable ^= IFCAP_HWCSUM; 948 reinit = 1; 949 } 950 if (mask & IFCAP_VLAN_HWTAGGING) { 951 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 952 reinit = 1; 953 } 954 if (reinit && (ifp->if_drv_flags & IFF_DRV_RUNNING)) 955 em_init(adapter); 956 break; 957 } 958 default: 959 error = ether_ioctl(ifp, command, data); 960 break; 961 } 962 963 return (error); 964 } 965 966 /********************************************************************* 967 * Watchdog timer: 968 * 969 * This routine is called from the local timer every second. 970 * As long as transmit descriptors are being cleaned the value 971 * is non-zero and we do nothing. Reaching 0 indicates a tx hang 972 * and we then reset the device. 973 * 974 **********************************************************************/ 975 976 static void 977 em_watchdog(struct adapter *adapter) 978 { 979 980 EM_LOCK_ASSERT(adapter); 981 982 /* 983 ** The timer is set to 5 every time start queues a packet. 984 ** Then txeof keeps resetting to 5 as long as it cleans at 985 ** least one descriptor. 986 ** Finally, anytime all descriptors are clean the timer is 987 ** set to 0. 988 */ 989 if (adapter->watchdog_timer == 0 || --adapter->watchdog_timer) 990 return; 991 992 /* If we are in this routine because of pause frames, then 993 * don't reset the hardware. 994 */ 995 if (E1000_READ_REG(&adapter->hw, STATUS) & E1000_STATUS_TXOFF) { 996 adapter->watchdog_timer = EM_TX_TIMEOUT; 997 return; 998 } 999 1000 if (em_check_for_link(&adapter->hw) == 0) 1001 device_printf(adapter->dev, "watchdog timeout -- resetting\n"); 1002 1003 adapter->ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1004 adapter->watchdog_events++; 1005 1006 em_init_locked(adapter); 1007 } 1008 1009 /********************************************************************* 1010 * Init entry point 1011 * 1012 * This routine is used in two ways. It is used by the stack as 1013 * init entry point in network interface structure. It is also used 1014 * by the driver as a hw/sw initialization routine to get to a 1015 * consistent state. 1016 * 1017 * return 0 on success, positive on failure 1018 **********************************************************************/ 1019 1020 static void 1021 em_init_locked(struct adapter *adapter) 1022 { 1023 struct ifnet *ifp = adapter->ifp; 1024 device_t dev = adapter->dev; 1025 uint32_t pba; 1026 1027 INIT_DEBUGOUT("em_init: begin"); 1028 1029 EM_LOCK_ASSERT(adapter); 1030 1031 em_stop(adapter); 1032 1033 /* 1034 * Packet Buffer Allocation (PBA) 1035 * Writing PBA sets the receive portion of the buffer 1036 * the remainder is used for the transmit buffer. 1037 * 1038 * Devices before the 82547 had a Packet Buffer of 64K. 1039 * Default allocation: PBA=48K for Rx, leaving 16K for Tx. 1040 * After the 82547 the buffer was reduced to 40K. 1041 * Default allocation: PBA=30K for Rx, leaving 10K for Tx. 1042 * Note: default does not leave enough room for Jumbo Frame >10k. 1043 */ 1044 switch (adapter->hw.mac_type) { 1045 case em_82547: 1046 case em_82547_rev_2: /* 82547: Total Packet Buffer is 40K */ 1047 if (adapter->hw.max_frame_size > EM_RXBUFFER_8192) 1048 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */ 1049 else 1050 pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */ 1051 adapter->tx_fifo_head = 0; 1052 adapter->tx_head_addr = pba << EM_TX_HEAD_ADDR_SHIFT; 1053 adapter->tx_fifo_size = 1054 (E1000_PBA_40K - pba) << EM_PBA_BYTES_SHIFT; 1055 break; 1056 /* Total Packet Buffer on these is 48K */ 1057 case em_82571: 1058 case em_82572: 1059 case em_80003es2lan: 1060 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */ 1061 break; 1062 case em_82573: /* 82573: Total Packet Buffer is 32K */ 1063 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */ 1064 break; 1065 case em_ich8lan: 1066 pba = E1000_PBA_8K; 1067 break; 1068 default: 1069 /* Devices before 82547 had a Packet Buffer of 64K. */ 1070 if(adapter->hw.max_frame_size > EM_RXBUFFER_8192) 1071 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 1072 else 1073 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 1074 } 1075 1076 INIT_DEBUGOUT1("em_init: pba=%dK",pba); 1077 E1000_WRITE_REG(&adapter->hw, PBA, pba); 1078 1079 /* Get the latest mac address, User can use a LAA */ 1080 bcopy(IF_LLADDR(adapter->ifp), adapter->hw.mac_addr, 1081 ETHER_ADDR_LEN); 1082 1083 /* Initialize the hardware */ 1084 if (em_hardware_init(adapter)) { 1085 device_printf(dev, "Unable to initialize the hardware\n"); 1086 return; 1087 } 1088 em_update_link_status(adapter); 1089 1090 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) 1091 em_enable_vlans(adapter); 1092 1093 /* Set hardware offload abilities */ 1094 ifp->if_hwassist = 0; 1095 if (adapter->hw.mac_type >= em_82543) { 1096 if (ifp->if_capenable & IFCAP_TXCSUM) 1097 ifp->if_hwassist |= EM_CHECKSUM_FEATURES; 1098 #ifdef EM_TSO 1099 if (ifp->if_capenable & IFCAP_TSO) 1100 ifp->if_hwassist |= EM_TCPSEG_FEATURES; 1101 #endif 1102 } 1103 1104 /* Prepare transmit descriptors and buffers */ 1105 em_setup_transmit_structures(adapter); 1106 em_initialize_transmit_unit(adapter); 1107 1108 /* Setup Multicast table */ 1109 em_set_multi(adapter); 1110 1111 /* Prepare receive descriptors and buffers */ 1112 if (em_setup_receive_structures(adapter)) { 1113 device_printf(dev, "Could not setup receive structures\n"); 1114 em_stop(adapter); 1115 return; 1116 } 1117 em_initialize_receive_unit(adapter); 1118 1119 /* Don't lose promiscuous settings */ 1120 em_set_promisc(adapter); 1121 1122 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1123 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1124 1125 callout_reset(&adapter->timer, hz, em_local_timer, adapter); 1126 em_clear_hw_cntrs(&adapter->hw); 1127 1128 #ifdef DEVICE_POLLING 1129 /* 1130 * Only enable interrupts if we are not polling, make sure 1131 * they are off otherwise. 1132 */ 1133 if (ifp->if_capenable & IFCAP_POLLING) 1134 em_disable_intr(adapter); 1135 else 1136 #endif /* DEVICE_POLLING */ 1137 em_enable_intr(adapter); 1138 1139 /* Don't reset the phy next time init gets called */ 1140 adapter->hw.phy_reset_disable = TRUE; 1141 } 1142 1143 static void 1144 em_init(void *arg) 1145 { 1146 struct adapter *adapter = arg; 1147 1148 EM_LOCK(adapter); 1149 em_init_locked(adapter); 1150 EM_UNLOCK(adapter); 1151 } 1152 1153 1154 #ifdef DEVICE_POLLING 1155 /********************************************************************* 1156 * 1157 * Legacy polling routine 1158 * 1159 *********************************************************************/ 1160 static void 1161 em_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1162 { 1163 struct adapter *adapter = ifp->if_softc; 1164 uint32_t reg_icr; 1165 1166 EM_LOCK(adapter); 1167 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 1168 EM_UNLOCK(adapter); 1169 return; 1170 } 1171 1172 if (cmd == POLL_AND_CHECK_STATUS) { 1173 reg_icr = E1000_READ_REG(&adapter->hw, ICR); 1174 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 1175 callout_stop(&adapter->timer); 1176 adapter->hw.get_link_status = 1; 1177 em_check_for_link(&adapter->hw); 1178 em_update_link_status(adapter); 1179 callout_reset(&adapter->timer, hz, 1180 em_local_timer, adapter); 1181 } 1182 } 1183 em_rxeof(adapter, count); 1184 em_txeof(adapter); 1185 1186 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1187 em_start_locked(ifp); 1188 EM_UNLOCK(adapter); 1189 } 1190 #endif /* DEVICE_POLLING */ 1191 1192 #ifndef EM_FAST_INTR 1193 /********************************************************************* 1194 * 1195 * Legacy Interrupt Service routine 1196 * 1197 *********************************************************************/ 1198 #define EM_MAX_INTR 10 1199 1200 static void 1201 em_intr(void *arg) 1202 { 1203 struct adapter *adapter = arg; 1204 struct ifnet *ifp; 1205 uint32_t reg_icr; 1206 1207 EM_LOCK(adapter); 1208 ifp = adapter->ifp; 1209 1210 #ifdef DEVICE_POLLING 1211 if (ifp->if_capenable & IFCAP_POLLING) { 1212 EM_UNLOCK(adapter); 1213 return; 1214 } 1215 #endif /* DEVICE_POLLING */ 1216 1217 reg_icr = E1000_READ_REG(&adapter->hw, ICR); 1218 1219 if ((reg_icr == 0) || (adapter->hw.mac_type >= em_82571 && 1220 (reg_icr & E1000_ICR_INT_ASSERTED) == 0) || 1221 /* 1222 * XXX: some laptops trigger several spurious interrupts 1223 * on em(4) when in the resume cycle. The ICR register 1224 * reports all-ones value in this case. Processing such 1225 * interrupts would lead to a freeze. I don't know why. 1226 */ 1227 (reg_icr == 0xffffffff)) 1228 goto leaving; 1229 1230 for (int i = 0;i < EM_MAX_INTR; ++i) { 1231 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1232 em_rxeof(adapter, adapter->rx_process_limit); 1233 em_txeof(adapter); 1234 } 1235 /* Link status change */ 1236 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 1237 callout_stop(&adapter->timer); 1238 adapter->hw.get_link_status = 1; 1239 em_check_for_link(&adapter->hw); 1240 em_update_link_status(adapter); 1241 callout_reset(&adapter->timer, hz, 1242 em_local_timer, adapter); 1243 } 1244 1245 if (reg_icr & E1000_ICR_RXO) 1246 adapter->rx_overruns++; 1247 } 1248 1249 leaving: 1250 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 1251 !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1252 em_start_locked(ifp); 1253 EM_UNLOCK(adapter); 1254 } 1255 1256 #else /* EM_FAST_INTR */ 1257 1258 static void 1259 em_handle_link(void *context, int pending) 1260 { 1261 struct adapter *adapter = context; 1262 struct ifnet *ifp; 1263 1264 ifp = adapter->ifp; 1265 1266 EM_LOCK(adapter); 1267 1268 callout_stop(&adapter->timer); 1269 adapter->hw.get_link_status = 1; 1270 em_check_for_link(&adapter->hw); 1271 em_update_link_status(adapter); 1272 callout_reset(&adapter->timer, hz, em_local_timer, adapter); 1273 EM_UNLOCK(adapter); 1274 } 1275 1276 static void 1277 em_handle_rxtx(void *context, int pending) 1278 { 1279 struct adapter *adapter = context; 1280 struct ifnet *ifp; 1281 1282 NET_LOCK_GIANT(); 1283 ifp = adapter->ifp; 1284 1285 /* 1286 * TODO: 1287 * It should be possible to run the tx clean loop without the lock. 1288 */ 1289 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1290 if (em_rxeof(adapter, adapter->rx_process_limit) != 0) 1291 taskqueue_enqueue(adapter->tq, &adapter->rxtx_task); 1292 EM_LOCK(adapter); 1293 em_txeof(adapter); 1294 1295 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1296 em_start_locked(ifp); 1297 EM_UNLOCK(adapter); 1298 } 1299 1300 em_enable_intr(adapter); 1301 NET_UNLOCK_GIANT(); 1302 } 1303 1304 /********************************************************************* 1305 * 1306 * Fast Interrupt Service routine 1307 * 1308 *********************************************************************/ 1309 static void 1310 em_intr_fast(void *arg) 1311 { 1312 struct adapter *adapter = arg; 1313 struct ifnet *ifp; 1314 uint32_t reg_icr; 1315 1316 ifp = adapter->ifp; 1317 1318 reg_icr = E1000_READ_REG(&adapter->hw, ICR); 1319 1320 /* Hot eject? */ 1321 if (reg_icr == 0xffffffff) 1322 return; 1323 1324 /* Definitely not our interrupt. */ 1325 if (reg_icr == 0x0) 1326 return; 1327 1328 /* 1329 * Starting with the 82571 chip, bit 31 should be used to 1330 * determine whether the interrupt belongs to us. 1331 */ 1332 if (adapter->hw.mac_type >= em_82571 && 1333 (reg_icr & E1000_ICR_INT_ASSERTED) == 0) 1334 return; 1335 1336 /* 1337 * Mask interrupts until the taskqueue is finished running. This is 1338 * cheap, just assume that it is needed. This also works around the 1339 * MSI message reordering errata on certain systems. 1340 */ 1341 em_disable_intr(adapter); 1342 taskqueue_enqueue(adapter->tq, &adapter->rxtx_task); 1343 1344 /* Link status change */ 1345 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) 1346 taskqueue_enqueue(taskqueue_fast, &adapter->link_task); 1347 1348 if (reg_icr & E1000_ICR_RXO) 1349 adapter->rx_overruns++; 1350 } 1351 #endif /* EM_FAST_INTR */ 1352 1353 /********************************************************************* 1354 * 1355 * Media Ioctl callback 1356 * 1357 * This routine is called whenever the user queries the status of 1358 * the interface using ifconfig. 1359 * 1360 **********************************************************************/ 1361 static void 1362 em_media_status(struct ifnet *ifp, struct ifmediareq *ifmr) 1363 { 1364 struct adapter *adapter = ifp->if_softc; 1365 u_char fiber_type = IFM_1000_SX; 1366 1367 INIT_DEBUGOUT("em_media_status: begin"); 1368 1369 EM_LOCK(adapter); 1370 em_check_for_link(&adapter->hw); 1371 em_update_link_status(adapter); 1372 1373 ifmr->ifm_status = IFM_AVALID; 1374 ifmr->ifm_active = IFM_ETHER; 1375 1376 if (!adapter->link_active) { 1377 EM_UNLOCK(adapter); 1378 return; 1379 } 1380 1381 ifmr->ifm_status |= IFM_ACTIVE; 1382 1383 if ((adapter->hw.media_type == em_media_type_fiber) || 1384 (adapter->hw.media_type == em_media_type_internal_serdes)) { 1385 if (adapter->hw.mac_type == em_82545) 1386 fiber_type = IFM_1000_LX; 1387 ifmr->ifm_active |= fiber_type | IFM_FDX; 1388 } else { 1389 switch (adapter->link_speed) { 1390 case 10: 1391 ifmr->ifm_active |= IFM_10_T; 1392 break; 1393 case 100: 1394 ifmr->ifm_active |= IFM_100_TX; 1395 break; 1396 case 1000: 1397 ifmr->ifm_active |= IFM_1000_T; 1398 break; 1399 } 1400 if (adapter->link_duplex == FULL_DUPLEX) 1401 ifmr->ifm_active |= IFM_FDX; 1402 else 1403 ifmr->ifm_active |= IFM_HDX; 1404 } 1405 EM_UNLOCK(adapter); 1406 } 1407 1408 /********************************************************************* 1409 * 1410 * Media Ioctl callback 1411 * 1412 * This routine is called when the user changes speed/duplex using 1413 * media/mediopt option with ifconfig. 1414 * 1415 **********************************************************************/ 1416 static int 1417 em_media_change(struct ifnet *ifp) 1418 { 1419 struct adapter *adapter = ifp->if_softc; 1420 struct ifmedia *ifm = &adapter->media; 1421 1422 INIT_DEBUGOUT("em_media_change: begin"); 1423 1424 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1425 return (EINVAL); 1426 1427 EM_LOCK(adapter); 1428 switch (IFM_SUBTYPE(ifm->ifm_media)) { 1429 case IFM_AUTO: 1430 adapter->hw.autoneg = DO_AUTO_NEG; 1431 adapter->hw.autoneg_advertised = AUTONEG_ADV_DEFAULT; 1432 break; 1433 case IFM_1000_LX: 1434 case IFM_1000_SX: 1435 case IFM_1000_T: 1436 adapter->hw.autoneg = DO_AUTO_NEG; 1437 adapter->hw.autoneg_advertised = ADVERTISE_1000_FULL; 1438 break; 1439 case IFM_100_TX: 1440 adapter->hw.autoneg = FALSE; 1441 adapter->hw.autoneg_advertised = 0; 1442 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1443 adapter->hw.forced_speed_duplex = em_100_full; 1444 else 1445 adapter->hw.forced_speed_duplex = em_100_half; 1446 break; 1447 case IFM_10_T: 1448 adapter->hw.autoneg = FALSE; 1449 adapter->hw.autoneg_advertised = 0; 1450 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1451 adapter->hw.forced_speed_duplex = em_10_full; 1452 else 1453 adapter->hw.forced_speed_duplex = em_10_half; 1454 break; 1455 default: 1456 device_printf(adapter->dev, "Unsupported media type\n"); 1457 } 1458 1459 /* As the speed/duplex settings my have changed we need to 1460 * reset the PHY. 1461 */ 1462 adapter->hw.phy_reset_disable = FALSE; 1463 1464 em_init_locked(adapter); 1465 EM_UNLOCK(adapter); 1466 1467 return (0); 1468 } 1469 1470 /********************************************************************* 1471 * 1472 * This routine maps the mbufs to tx descriptors. 1473 * 1474 * return 0 on success, positive on failure 1475 **********************************************************************/ 1476 static int 1477 em_encap(struct adapter *adapter, struct mbuf **m_headp) 1478 { 1479 struct ifnet *ifp = adapter->ifp; 1480 bus_dma_segment_t segs[EM_MAX_SCATTER]; 1481 bus_dmamap_t map; 1482 struct em_buffer *tx_buffer, *tx_buffer_mapped; 1483 struct em_tx_desc *current_tx_desc; 1484 struct mbuf *m_head; 1485 struct m_tag *mtag; 1486 uint32_t txd_upper, txd_lower, txd_used, txd_saved; 1487 int nsegs, i, j, first, last = 0; 1488 int error, do_tso, tso_desc = 0; 1489 1490 m_head = *m_headp; 1491 current_tx_desc = NULL; 1492 txd_upper = txd_lower = txd_used = txd_saved = 0; 1493 1494 #ifdef EM_TSO 1495 do_tso = ((m_head->m_pkthdr.csum_flags & CSUM_TSO) != 0); 1496 #else 1497 do_tso = 0; 1498 #endif 1499 1500 /* 1501 * Force a cleanup if number of TX descriptors 1502 * available hits the threshold 1503 */ 1504 if (adapter->num_tx_desc_avail <= EM_TX_CLEANUP_THRESHOLD) { 1505 em_txeof(adapter); 1506 /* Now do we at least have a minimal? */ 1507 if (adapter->num_tx_desc_avail <= EM_TX_OP_THRESHOLD) { 1508 adapter->no_tx_desc_avail1++; 1509 return (ENOBUFS); 1510 } 1511 } 1512 1513 /* Find out if we are in vlan mode. */ 1514 mtag = VLAN_OUTPUT_TAG(ifp, m_head); 1515 1516 /* 1517 * When operating in promiscuous mode, hardware encapsulation for 1518 * packets is disabled. This means we have to add the vlan 1519 * encapsulation in the driver, since it will have come down from the 1520 * VLAN layer with a tag instead of a VLAN header. 1521 */ 1522 if (mtag != NULL && adapter->em_insert_vlan_header) { 1523 struct ether_vlan_header *evl; 1524 struct ether_header eh; 1525 1526 m_head = m_pullup(m_head, sizeof(eh)); 1527 if (m_head == NULL) { 1528 *m_headp = NULL; 1529 return (ENOBUFS); 1530 } 1531 eh = *mtod(m_head, struct ether_header *); 1532 M_PREPEND(m_head, sizeof(*evl), M_DONTWAIT); 1533 if (m_head == NULL) { 1534 *m_headp = NULL; 1535 return (ENOBUFS); 1536 } 1537 m_head = m_pullup(m_head, sizeof(*evl)); 1538 if (m_head == NULL) { 1539 *m_headp = NULL; 1540 return (ENOBUFS); 1541 } 1542 evl = mtod(m_head, struct ether_vlan_header *); 1543 bcopy(&eh, evl, sizeof(*evl)); 1544 evl->evl_proto = evl->evl_encap_proto; 1545 evl->evl_encap_proto = htons(ETHERTYPE_VLAN); 1546 evl->evl_tag = htons(VLAN_TAG_VALUE(mtag)); 1547 m_tag_delete(m_head, mtag); 1548 mtag = NULL; 1549 *m_headp = m_head; 1550 } 1551 1552 /* 1553 * TSO workaround: 1554 * If an mbuf is only header we need 1555 * to pull 4 bytes of data into it. 1556 */ 1557 if (do_tso && (m_head->m_len <= M_TSO_LEN)) { 1558 m_head = m_pullup(m_head, M_TSO_LEN + 4); 1559 *m_headp = m_head; 1560 if (m_head == NULL) 1561 return (ENOBUFS); 1562 } 1563 1564 /* 1565 * Capture the first descriptor index, 1566 * this descriptor will have the index 1567 * of the EOP which is the only one that 1568 * now gets a DONE bit writeback. 1569 */ 1570 first = adapter->next_avail_tx_desc; 1571 1572 /* 1573 * Map the packet for DMA. 1574 */ 1575 tx_buffer = &adapter->tx_buffer_area[first]; 1576 tx_buffer_mapped = tx_buffer; 1577 map = tx_buffer->map; 1578 error = bus_dmamap_load_mbuf_sg(adapter->txtag, tx_buffer->map, 1579 *m_headp, segs, &nsegs, BUS_DMA_NOWAIT); 1580 if (error == EFBIG) { 1581 struct mbuf *m; 1582 1583 m = m_defrag(*m_headp, M_DONTWAIT); 1584 if (m == NULL) { 1585 adapter->mbuf_alloc_failed++; 1586 m_freem(*m_headp); 1587 *m_headp = NULL; 1588 return (ENOBUFS); 1589 } 1590 *m_headp = m; 1591 m_head = *m_headp; 1592 1593 /* Try it again */ 1594 error = bus_dmamap_load_mbuf_sg(adapter->txtag, tx_buffer->map, 1595 *m_headp, segs, &nsegs, BUS_DMA_NOWAIT); 1596 1597 if (error == ENOMEM) { 1598 adapter->no_tx_dma_setup++; 1599 return (error); 1600 } else if (error != 0) { 1601 adapter->no_tx_dma_setup++; 1602 m_freem(*m_headp); 1603 *m_headp = NULL; 1604 return (error); 1605 } 1606 } else if (error == ENOMEM) { 1607 adapter->no_tx_dma_setup++; 1608 return (error); 1609 } else if (error != 0) { 1610 adapter->no_tx_dma_setup++; 1611 m_freem(*m_headp); 1612 *m_headp = NULL; 1613 return (error); 1614 } 1615 1616 /* 1617 * TSO Hardware workaround, if this packet is not 1618 * TSO, and is only a single descriptor long, and 1619 * it follows a TSO burst, then we need to add a 1620 * sentinel descriptor to prevent premature writeback. 1621 */ 1622 if ((do_tso == 0) && (adapter->tx_tso == TRUE)) { 1623 if (nsegs == 1) 1624 tso_desc = TRUE; 1625 adapter->tx_tso = FALSE; 1626 } 1627 1628 if (nsegs > (adapter->num_tx_desc_avail - 2)) { 1629 adapter->no_tx_desc_avail2++; 1630 error = ENOBUFS; 1631 goto encap_fail; 1632 } 1633 1634 /* Do hardware assists */ 1635 if (ifp->if_hwassist > 0) { 1636 #ifdef EM_TSO 1637 if (em_tso_setup(adapter, m_head, &txd_upper, &txd_lower)) { 1638 /* we need to make a final sentinel transmit desc */ 1639 tso_desc = TRUE; 1640 } else 1641 #endif 1642 em_transmit_checksum_setup(adapter, m_head, 1643 &txd_upper, &txd_lower); 1644 } 1645 1646 i = adapter->next_avail_tx_desc; 1647 if (adapter->pcix_82544) 1648 txd_saved = i; 1649 1650 /* Set up our transmit descriptors */ 1651 for (j = 0; j < nsegs; j++) { 1652 bus_size_t seg_len; 1653 bus_addr_t seg_addr; 1654 /* If adapter is 82544 and on PCIX bus */ 1655 if(adapter->pcix_82544) { 1656 DESC_ARRAY desc_array; 1657 uint32_t array_elements, counter; 1658 /* 1659 * Check the Address and Length combination and 1660 * split the data accordingly 1661 */ 1662 array_elements = em_fill_descriptors(segs[j].ds_addr, 1663 segs[j].ds_len, &desc_array); 1664 for (counter = 0; counter < array_elements; counter++) { 1665 if (txd_used == adapter->num_tx_desc_avail) { 1666 adapter->next_avail_tx_desc = txd_saved; 1667 adapter->no_tx_desc_avail2++; 1668 error = ENOBUFS; 1669 goto encap_fail; 1670 } 1671 tx_buffer = &adapter->tx_buffer_area[i]; 1672 current_tx_desc = &adapter->tx_desc_base[i]; 1673 current_tx_desc->buffer_addr = htole64( 1674 desc_array.descriptor[counter].address); 1675 current_tx_desc->lower.data = htole32( 1676 (adapter->txd_cmd | txd_lower | (uint16_t) 1677 desc_array.descriptor[counter].length)); 1678 current_tx_desc->upper.data = 1679 htole32((txd_upper)); 1680 last = i; 1681 if (++i == adapter->num_tx_desc) 1682 i = 0; 1683 tx_buffer->m_head = NULL; 1684 tx_buffer->next_eop = -1; 1685 txd_used++; 1686 } 1687 } else { 1688 tx_buffer = &adapter->tx_buffer_area[i]; 1689 current_tx_desc = &adapter->tx_desc_base[i]; 1690 seg_addr = htole64(segs[j].ds_addr); 1691 seg_len = segs[j].ds_len; 1692 /* 1693 ** TSO Workaround: 1694 ** If this is the last descriptor, we want to 1695 ** split it so we have a small final sentinel 1696 */ 1697 if (tso_desc && (j == (nsegs -1)) && (seg_len > 8)) { 1698 seg_len -= 4; 1699 current_tx_desc->buffer_addr = seg_addr; 1700 current_tx_desc->lower.data = htole32( 1701 adapter->txd_cmd | txd_lower | seg_len); 1702 current_tx_desc->upper.data = 1703 htole32(txd_upper); 1704 if (++i == adapter->num_tx_desc) 1705 i = 0; 1706 /* Now make the sentinel */ 1707 ++txd_used; /* using an extra txd */ 1708 current_tx_desc = &adapter->tx_desc_base[i]; 1709 tx_buffer = &adapter->tx_buffer_area[i]; 1710 current_tx_desc->buffer_addr = 1711 seg_addr + seg_len; 1712 current_tx_desc->lower.data = htole32( 1713 adapter->txd_cmd | txd_lower | 4); 1714 current_tx_desc->upper.data = 1715 htole32(txd_upper); 1716 last = i; 1717 if (++i == adapter->num_tx_desc) 1718 i = 0; 1719 } else { 1720 current_tx_desc->buffer_addr = seg_addr; 1721 current_tx_desc->lower.data = htole32( 1722 adapter->txd_cmd | txd_lower | seg_len); 1723 current_tx_desc->upper.data = 1724 htole32(txd_upper); 1725 last = i; 1726 if (++i == adapter->num_tx_desc) 1727 i = 0; 1728 } 1729 tx_buffer->m_head = NULL; 1730 tx_buffer->next_eop = -1; 1731 } 1732 } 1733 1734 adapter->next_avail_tx_desc = i; 1735 if (adapter->pcix_82544) 1736 adapter->num_tx_desc_avail -= txd_used; 1737 else { 1738 adapter->num_tx_desc_avail -= nsegs; 1739 if (tso_desc) /* TSO used an extra for sentinel */ 1740 adapter->num_tx_desc_avail -= txd_used; 1741 } 1742 1743 if (mtag != NULL) { 1744 /* Set the vlan id. */ 1745 current_tx_desc->upper.fields.special = 1746 htole16(VLAN_TAG_VALUE(mtag)); 1747 /* Tell hardware to add tag */ 1748 current_tx_desc->lower.data |= 1749 htole32(E1000_TXD_CMD_VLE); 1750 } 1751 1752 tx_buffer->m_head = m_head; 1753 tx_buffer_mapped->map = tx_buffer->map; 1754 tx_buffer->map = map; 1755 bus_dmamap_sync(adapter->txtag, map, BUS_DMASYNC_PREWRITE); 1756 1757 /* 1758 * Last Descriptor of Packet 1759 * needs End Of Packet (EOP) 1760 * and Report Status (RS) 1761 */ 1762 current_tx_desc->lower.data |= 1763 htole32(E1000_TXD_CMD_EOP | E1000_TXD_CMD_RS); 1764 /* 1765 * Keep track in the first buffer which 1766 * descriptor will be written back 1767 */ 1768 tx_buffer = &adapter->tx_buffer_area[first]; 1769 tx_buffer->next_eop = last; 1770 1771 /* 1772 * Advance the Transmit Descriptor Tail (Tdt), this tells the E1000 1773 * that this frame is available to transmit. 1774 */ 1775 bus_dmamap_sync(adapter->txdma.dma_tag, adapter->txdma.dma_map, 1776 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1777 if (adapter->hw.mac_type == em_82547 && 1778 adapter->link_duplex == HALF_DUPLEX) 1779 em_82547_move_tail(adapter); 1780 else { 1781 E1000_WRITE_REG(&adapter->hw, TDT, i); 1782 if (adapter->hw.mac_type == em_82547) 1783 em_82547_update_fifo_head(adapter, 1784 m_head->m_pkthdr.len); 1785 } 1786 1787 return (0); 1788 1789 encap_fail: 1790 bus_dmamap_unload(adapter->txtag, tx_buffer->map); 1791 return (error); 1792 } 1793 1794 /********************************************************************* 1795 * 1796 * 82547 workaround to avoid controller hang in half-duplex environment. 1797 * The workaround is to avoid queuing a large packet that would span 1798 * the internal Tx FIFO ring boundary. We need to reset the FIFO pointers 1799 * in this case. We do that only when FIFO is quiescent. 1800 * 1801 **********************************************************************/ 1802 static void 1803 em_82547_move_tail(void *arg) 1804 { 1805 struct adapter *adapter = arg; 1806 uint16_t hw_tdt; 1807 uint16_t sw_tdt; 1808 struct em_tx_desc *tx_desc; 1809 uint16_t length = 0; 1810 boolean_t eop = 0; 1811 1812 EM_LOCK_ASSERT(adapter); 1813 1814 hw_tdt = E1000_READ_REG(&adapter->hw, TDT); 1815 sw_tdt = adapter->next_avail_tx_desc; 1816 1817 while (hw_tdt != sw_tdt) { 1818 tx_desc = &adapter->tx_desc_base[hw_tdt]; 1819 length += tx_desc->lower.flags.length; 1820 eop = tx_desc->lower.data & E1000_TXD_CMD_EOP; 1821 if (++hw_tdt == adapter->num_tx_desc) 1822 hw_tdt = 0; 1823 1824 if (eop) { 1825 if (em_82547_fifo_workaround(adapter, length)) { 1826 adapter->tx_fifo_wrk_cnt++; 1827 callout_reset(&adapter->tx_fifo_timer, 1, 1828 em_82547_move_tail, adapter); 1829 break; 1830 } 1831 E1000_WRITE_REG(&adapter->hw, TDT, hw_tdt); 1832 em_82547_update_fifo_head(adapter, length); 1833 length = 0; 1834 } 1835 } 1836 } 1837 1838 static int 1839 em_82547_fifo_workaround(struct adapter *adapter, int len) 1840 { 1841 int fifo_space, fifo_pkt_len; 1842 1843 fifo_pkt_len = roundup2(len + EM_FIFO_HDR, EM_FIFO_HDR); 1844 1845 if (adapter->link_duplex == HALF_DUPLEX) { 1846 fifo_space = adapter->tx_fifo_size - adapter->tx_fifo_head; 1847 1848 if (fifo_pkt_len >= (EM_82547_PKT_THRESH + fifo_space)) { 1849 if (em_82547_tx_fifo_reset(adapter)) 1850 return (0); 1851 else 1852 return (1); 1853 } 1854 } 1855 1856 return (0); 1857 } 1858 1859 static void 1860 em_82547_update_fifo_head(struct adapter *adapter, int len) 1861 { 1862 int fifo_pkt_len = roundup2(len + EM_FIFO_HDR, EM_FIFO_HDR); 1863 1864 /* tx_fifo_head is always 16 byte aligned */ 1865 adapter->tx_fifo_head += fifo_pkt_len; 1866 if (adapter->tx_fifo_head >= adapter->tx_fifo_size) { 1867 adapter->tx_fifo_head -= adapter->tx_fifo_size; 1868 } 1869 } 1870 1871 1872 static int 1873 em_82547_tx_fifo_reset(struct adapter *adapter) 1874 { 1875 uint32_t tctl; 1876 1877 if ((E1000_READ_REG(&adapter->hw, TDT) == 1878 E1000_READ_REG(&adapter->hw, TDH)) && 1879 (E1000_READ_REG(&adapter->hw, TDFT) == 1880 E1000_READ_REG(&adapter->hw, TDFH)) && 1881 (E1000_READ_REG(&adapter->hw, TDFTS) == 1882 E1000_READ_REG(&adapter->hw, TDFHS)) && 1883 (E1000_READ_REG(&adapter->hw, TDFPC) == 0)) { 1884 /* Disable TX unit */ 1885 tctl = E1000_READ_REG(&adapter->hw, TCTL); 1886 E1000_WRITE_REG(&adapter->hw, TCTL, tctl & ~E1000_TCTL_EN); 1887 1888 /* Reset FIFO pointers */ 1889 E1000_WRITE_REG(&adapter->hw, TDFT, adapter->tx_head_addr); 1890 E1000_WRITE_REG(&adapter->hw, TDFH, adapter->tx_head_addr); 1891 E1000_WRITE_REG(&adapter->hw, TDFTS, adapter->tx_head_addr); 1892 E1000_WRITE_REG(&adapter->hw, TDFHS, adapter->tx_head_addr); 1893 1894 /* Re-enable TX unit */ 1895 E1000_WRITE_REG(&adapter->hw, TCTL, tctl); 1896 E1000_WRITE_FLUSH(&adapter->hw); 1897 1898 adapter->tx_fifo_head = 0; 1899 adapter->tx_fifo_reset_cnt++; 1900 1901 return (TRUE); 1902 } 1903 else { 1904 return (FALSE); 1905 } 1906 } 1907 1908 static void 1909 em_set_promisc(struct adapter *adapter) 1910 { 1911 struct ifnet *ifp = adapter->ifp; 1912 uint32_t reg_rctl; 1913 1914 reg_rctl = E1000_READ_REG(&adapter->hw, RCTL); 1915 1916 if (ifp->if_flags & IFF_PROMISC) { 1917 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 1918 E1000_WRITE_REG(&adapter->hw, RCTL, reg_rctl); 1919 /* Disable VLAN stripping in promiscous mode 1920 * This enables bridging of vlan tagged frames to occur 1921 * and also allows vlan tags to be seen in tcpdump 1922 */ 1923 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) 1924 em_disable_vlans(adapter); 1925 adapter->em_insert_vlan_header = 1; 1926 } else if (ifp->if_flags & IFF_ALLMULTI) { 1927 reg_rctl |= E1000_RCTL_MPE; 1928 reg_rctl &= ~E1000_RCTL_UPE; 1929 E1000_WRITE_REG(&adapter->hw, RCTL, reg_rctl); 1930 adapter->em_insert_vlan_header = 0; 1931 } else 1932 adapter->em_insert_vlan_header = 0; 1933 } 1934 1935 static void 1936 em_disable_promisc(struct adapter *adapter) 1937 { 1938 struct ifnet *ifp = adapter->ifp; 1939 uint32_t reg_rctl; 1940 1941 reg_rctl = E1000_READ_REG(&adapter->hw, RCTL); 1942 1943 reg_rctl &= (~E1000_RCTL_UPE); 1944 reg_rctl &= (~E1000_RCTL_MPE); 1945 E1000_WRITE_REG(&adapter->hw, RCTL, reg_rctl); 1946 1947 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) 1948 em_enable_vlans(adapter); 1949 adapter->em_insert_vlan_header = 0; 1950 } 1951 1952 1953 /********************************************************************* 1954 * Multicast Update 1955 * 1956 * This routine is called whenever multicast address list is updated. 1957 * 1958 **********************************************************************/ 1959 1960 static void 1961 em_set_multi(struct adapter *adapter) 1962 { 1963 struct ifnet *ifp = adapter->ifp; 1964 struct ifmultiaddr *ifma; 1965 uint32_t reg_rctl = 0; 1966 uint8_t mta[MAX_NUM_MULTICAST_ADDRESSES * ETH_LENGTH_OF_ADDRESS]; 1967 int mcnt = 0; 1968 1969 IOCTL_DEBUGOUT("em_set_multi: begin"); 1970 1971 if (adapter->hw.mac_type == em_82542_rev2_0) { 1972 reg_rctl = E1000_READ_REG(&adapter->hw, RCTL); 1973 if (adapter->hw.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1974 em_pci_clear_mwi(&adapter->hw); 1975 reg_rctl |= E1000_RCTL_RST; 1976 E1000_WRITE_REG(&adapter->hw, RCTL, reg_rctl); 1977 msec_delay(5); 1978 } 1979 1980 IF_ADDR_LOCK(ifp); 1981 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1982 if (ifma->ifma_addr->sa_family != AF_LINK) 1983 continue; 1984 1985 if (mcnt == MAX_NUM_MULTICAST_ADDRESSES) 1986 break; 1987 1988 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1989 &mta[mcnt*ETH_LENGTH_OF_ADDRESS], ETH_LENGTH_OF_ADDRESS); 1990 mcnt++; 1991 } 1992 IF_ADDR_UNLOCK(ifp); 1993 1994 if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES) { 1995 reg_rctl = E1000_READ_REG(&adapter->hw, RCTL); 1996 reg_rctl |= E1000_RCTL_MPE; 1997 E1000_WRITE_REG(&adapter->hw, RCTL, reg_rctl); 1998 } else 1999 em_mc_addr_list_update(&adapter->hw, mta, mcnt, 0, 1); 2000 2001 if (adapter->hw.mac_type == em_82542_rev2_0) { 2002 reg_rctl = E1000_READ_REG(&adapter->hw, RCTL); 2003 reg_rctl &= ~E1000_RCTL_RST; 2004 E1000_WRITE_REG(&adapter->hw, RCTL, reg_rctl); 2005 msec_delay(5); 2006 if (adapter->hw.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 2007 em_pci_set_mwi(&adapter->hw); 2008 } 2009 } 2010 2011 2012 /********************************************************************* 2013 * Timer routine 2014 * 2015 * This routine checks for link status and updates statistics. 2016 * 2017 **********************************************************************/ 2018 2019 static void 2020 em_local_timer(void *arg) 2021 { 2022 struct adapter *adapter = arg; 2023 struct ifnet *ifp = adapter->ifp; 2024 2025 EM_LOCK_ASSERT(adapter); 2026 2027 em_check_for_link(&adapter->hw); 2028 em_update_link_status(adapter); 2029 em_update_stats_counters(adapter); 2030 if (em_display_debug_stats && ifp->if_drv_flags & IFF_DRV_RUNNING) 2031 em_print_hw_stats(adapter); 2032 em_smartspeed(adapter); 2033 /* 2034 * Each second we check the watchdog to 2035 * protect against hardware hangs. 2036 */ 2037 em_watchdog(adapter); 2038 2039 callout_reset(&adapter->timer, hz, em_local_timer, adapter); 2040 2041 } 2042 2043 static void 2044 em_update_link_status(struct adapter *adapter) 2045 { 2046 struct ifnet *ifp = adapter->ifp; 2047 device_t dev = adapter->dev; 2048 2049 if (E1000_READ_REG(&adapter->hw, STATUS) & E1000_STATUS_LU) { 2050 if (adapter->link_active == 0) { 2051 em_get_speed_and_duplex(&adapter->hw, 2052 &adapter->link_speed, &adapter->link_duplex); 2053 /* Check if we may set SPEED_MODE bit on PCI-E */ 2054 if ((adapter->link_speed == SPEED_1000) && 2055 ((adapter->hw.mac_type == em_82571) || 2056 (adapter->hw.mac_type == em_82572))) { 2057 int tarc0; 2058 2059 tarc0 = E1000_READ_REG(&adapter->hw, TARC0); 2060 tarc0 |= SPEED_MODE_BIT; 2061 E1000_WRITE_REG(&adapter->hw, TARC0, tarc0); 2062 } 2063 if (bootverbose) 2064 device_printf(dev, "Link is up %d Mbps %s\n", 2065 adapter->link_speed, 2066 ((adapter->link_duplex == FULL_DUPLEX) ? 2067 "Full Duplex" : "Half Duplex")); 2068 adapter->link_active = 1; 2069 adapter->smartspeed = 0; 2070 ifp->if_baudrate = adapter->link_speed * 1000000; 2071 if_link_state_change(ifp, LINK_STATE_UP); 2072 } 2073 } else { 2074 if (adapter->link_active == 1) { 2075 ifp->if_baudrate = adapter->link_speed = 0; 2076 adapter->link_duplex = 0; 2077 if (bootverbose) 2078 device_printf(dev, "Link is Down\n"); 2079 adapter->link_active = 0; 2080 if_link_state_change(ifp, LINK_STATE_DOWN); 2081 } 2082 } 2083 } 2084 2085 /********************************************************************* 2086 * 2087 * This routine disables all traffic on the adapter by issuing a 2088 * global reset on the MAC and deallocates TX/RX buffers. 2089 * 2090 **********************************************************************/ 2091 2092 static void 2093 em_stop(void *arg) 2094 { 2095 struct adapter *adapter = arg; 2096 struct ifnet *ifp = adapter->ifp; 2097 2098 EM_LOCK_ASSERT(adapter); 2099 2100 INIT_DEBUGOUT("em_stop: begin"); 2101 2102 em_disable_intr(adapter); 2103 callout_stop(&adapter->timer); 2104 callout_stop(&adapter->tx_fifo_timer); 2105 2106 /* Tell the stack that the interface is no longer active */ 2107 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2108 em_reset_hw(&adapter->hw); 2109 } 2110 2111 2112 /********************************************************************* 2113 * 2114 * Determine hardware revision. 2115 * 2116 **********************************************************************/ 2117 static void 2118 em_identify_hardware(struct adapter *adapter) 2119 { 2120 device_t dev = adapter->dev; 2121 2122 /* Make sure our PCI config space has the necessary stuff set */ 2123 adapter->hw.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2); 2124 if ((adapter->hw.pci_cmd_word & PCIM_CMD_BUSMASTEREN) == 0 && 2125 (adapter->hw.pci_cmd_word & PCIM_CMD_MEMEN)) { 2126 device_printf(dev, "Memory Access and/or Bus Master bits " 2127 "were not set!\n"); 2128 adapter->hw.pci_cmd_word |= 2129 (PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN); 2130 pci_write_config(dev, PCIR_COMMAND, 2131 adapter->hw.pci_cmd_word, 2); 2132 } 2133 2134 /* Save off the information about this board */ 2135 adapter->hw.vendor_id = pci_get_vendor(dev); 2136 adapter->hw.device_id = pci_get_device(dev); 2137 adapter->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1); 2138 adapter->hw.subsystem_vendor_id = 2139 pci_read_config(dev, PCIR_SUBVEND_0, 2); 2140 adapter->hw.subsystem_id = pci_read_config(dev, PCIR_SUBDEV_0, 2); 2141 2142 /* Identify the MAC */ 2143 if (em_set_mac_type(&adapter->hw)) 2144 device_printf(dev, "Unknown MAC Type\n"); 2145 2146 if (adapter->hw.mac_type == em_82541 || 2147 adapter->hw.mac_type == em_82541_rev_2 || 2148 adapter->hw.mac_type == em_82547 || 2149 adapter->hw.mac_type == em_82547_rev_2) 2150 adapter->hw.phy_init_script = TRUE; 2151 } 2152 2153 static int 2154 em_allocate_pci_resources(struct adapter *adapter) 2155 { 2156 device_t dev = adapter->dev; 2157 int val, rid; 2158 2159 rid = PCIR_BAR(0); 2160 adapter->res_memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 2161 &rid, RF_ACTIVE); 2162 if (adapter->res_memory == NULL) { 2163 device_printf(dev, "Unable to allocate bus resource: memory\n"); 2164 return (ENXIO); 2165 } 2166 adapter->osdep.mem_bus_space_tag = 2167 rman_get_bustag(adapter->res_memory); 2168 adapter->osdep.mem_bus_space_handle = 2169 rman_get_bushandle(adapter->res_memory); 2170 adapter->hw.hw_addr = (uint8_t *)&adapter->osdep.mem_bus_space_handle; 2171 2172 if (adapter->hw.mac_type > em_82543) { 2173 /* Figure our where our IO BAR is ? */ 2174 for (rid = PCIR_BAR(0); rid < PCIR_CIS;) { 2175 val = pci_read_config(dev, rid, 4); 2176 if (EM_BAR_TYPE(val) == EM_BAR_TYPE_IO) { 2177 adapter->io_rid = rid; 2178 break; 2179 } 2180 rid += 4; 2181 /* check for 64bit BAR */ 2182 if (EM_BAR_MEM_TYPE(val) == EM_BAR_MEM_TYPE_64BIT) 2183 rid += 4; 2184 } 2185 if (rid >= PCIR_CIS) { 2186 device_printf(dev, "Unable to locate IO BAR\n"); 2187 return (ENXIO); 2188 } 2189 adapter->res_ioport = bus_alloc_resource_any(dev, 2190 SYS_RES_IOPORT, &adapter->io_rid, RF_ACTIVE); 2191 if (adapter->res_ioport == NULL) { 2192 device_printf(dev, "Unable to allocate bus resource: " 2193 "ioport\n"); 2194 return (ENXIO); 2195 } 2196 adapter->hw.io_base = 0; 2197 adapter->osdep.io_bus_space_tag = 2198 rman_get_bustag(adapter->res_ioport); 2199 adapter->osdep.io_bus_space_handle = 2200 rman_get_bushandle(adapter->res_ioport); 2201 } 2202 2203 /* For ICH8 we need to find the flash memory. */ 2204 if (adapter->hw.mac_type == em_ich8lan) { 2205 rid = EM_FLASH; 2206 adapter->flash_mem = bus_alloc_resource_any(dev, 2207 SYS_RES_MEMORY, &rid, RF_ACTIVE); 2208 adapter->osdep.flash_bus_space_tag = 2209 rman_get_bustag(adapter->flash_mem); 2210 adapter->osdep.flash_bus_space_handle = 2211 rman_get_bushandle(adapter->flash_mem); 2212 } 2213 2214 rid = 0x0; 2215 adapter->res_interrupt = bus_alloc_resource_any(dev, 2216 SYS_RES_IRQ, &rid, RF_SHAREABLE | RF_ACTIVE); 2217 if (adapter->res_interrupt == NULL) { 2218 device_printf(dev, "Unable to allocate bus resource: " 2219 "interrupt\n"); 2220 return (ENXIO); 2221 } 2222 2223 adapter->hw.back = &adapter->osdep; 2224 2225 return (0); 2226 } 2227 2228 /********************************************************************* 2229 * 2230 * Setup the appropriate Interrupt handlers. 2231 * 2232 **********************************************************************/ 2233 int 2234 em_allocate_intr(struct adapter *adapter) 2235 { 2236 device_t dev = adapter->dev; 2237 int error; 2238 2239 /* Manually turn off all interrupts */ 2240 E1000_WRITE_REG(&adapter->hw, IMC, 0xffffffff); 2241 2242 #ifndef EM_FAST_INTR 2243 /* We do Legacy setup */ 2244 if (adapter->int_handler_tag == NULL && 2245 (error = bus_setup_intr(dev, adapter->res_interrupt, 2246 INTR_TYPE_NET | INTR_MPSAFE, em_intr, adapter, 2247 &adapter->int_handler_tag)) != 0) { 2248 device_printf(dev, "Failed to register interrupt handler"); 2249 return (error); 2250 } 2251 2252 #else /* EM_FAST_INTR */ 2253 /* 2254 * Try allocating a fast interrupt and the associated deferred 2255 * processing contexts. 2256 */ 2257 TASK_INIT(&adapter->rxtx_task, 0, em_handle_rxtx, adapter); 2258 TASK_INIT(&adapter->link_task, 0, em_handle_link, adapter); 2259 adapter->tq = taskqueue_create_fast("em_taskq", M_NOWAIT, 2260 taskqueue_thread_enqueue, &adapter->tq); 2261 taskqueue_start_threads(&adapter->tq, 1, PI_NET, "%s taskq", 2262 device_get_nameunit(adapter->dev)); 2263 if ((error = bus_setup_intr(dev, adapter->res_interrupt, 2264 INTR_TYPE_NET | INTR_FAST, em_intr_fast, adapter, 2265 &adapter->int_handler_tag)) != 0) { 2266 device_printf(dev, "Failed to register fast interrupt " 2267 "handler: %d\n", error); 2268 taskqueue_free(adapter->tq); 2269 adapter->tq = NULL; 2270 return (error); 2271 } 2272 #endif /* EM_FAST_INTR */ 2273 2274 em_enable_intr(adapter); 2275 return (0); 2276 } 2277 2278 static void 2279 em_free_intr(struct adapter *adapter) 2280 { 2281 device_t dev = adapter->dev; 2282 2283 if (adapter->res_interrupt != NULL) { 2284 bus_teardown_intr(dev, adapter->res_interrupt, 2285 adapter->int_handler_tag); 2286 adapter->int_handler_tag = NULL; 2287 } 2288 #ifdef EM_FAST_INTR 2289 if (adapter->tq != NULL) { 2290 taskqueue_drain(adapter->tq, &adapter->rxtx_task); 2291 taskqueue_drain(taskqueue_fast, &adapter->link_task); 2292 taskqueue_free(adapter->tq); 2293 adapter->tq = NULL; 2294 } 2295 #endif 2296 } 2297 2298 static void 2299 em_free_pci_resources(struct adapter *adapter) 2300 { 2301 device_t dev = adapter->dev; 2302 2303 if (adapter->res_interrupt != NULL) 2304 bus_release_resource(dev, SYS_RES_IRQ, 2305 0, adapter->res_interrupt); 2306 2307 if (adapter->res_memory != NULL) 2308 bus_release_resource(dev, SYS_RES_MEMORY, 2309 PCIR_BAR(0), adapter->res_memory); 2310 2311 if (adapter->flash_mem != NULL) 2312 bus_release_resource(dev, SYS_RES_MEMORY, 2313 EM_FLASH, adapter->flash_mem); 2314 2315 if (adapter->res_ioport != NULL) 2316 bus_release_resource(dev, SYS_RES_IOPORT, 2317 adapter->io_rid, adapter->res_ioport); 2318 } 2319 2320 /********************************************************************* 2321 * 2322 * Initialize the hardware to a configuration as specified by the 2323 * adapter structure. The controller is reset, the EEPROM is 2324 * verified, the MAC address is set, then the shared initialization 2325 * routines are called. 2326 * 2327 **********************************************************************/ 2328 static int 2329 em_hardware_init(struct adapter *adapter) 2330 { 2331 device_t dev = adapter->dev; 2332 uint16_t rx_buffer_size; 2333 2334 INIT_DEBUGOUT("em_hardware_init: begin"); 2335 /* Issue a global reset */ 2336 em_reset_hw(&adapter->hw); 2337 2338 /* When hardware is reset, fifo_head is also reset */ 2339 adapter->tx_fifo_head = 0; 2340 2341 /* Make sure we have a good EEPROM before we read from it */ 2342 if (em_validate_eeprom_checksum(&adapter->hw) < 0) { 2343 device_printf(dev, "The EEPROM Checksum Is Not Valid\n"); 2344 return (EIO); 2345 } 2346 2347 if (em_read_part_num(&adapter->hw, &(adapter->part_num)) < 0) { 2348 device_printf(dev, "EEPROM read error " 2349 "reading part number\n"); 2350 return (EIO); 2351 } 2352 2353 /* Set up smart power down as default off on newer adapters. */ 2354 if (!em_smart_pwr_down && (adapter->hw.mac_type == em_82571 || 2355 adapter->hw.mac_type == em_82572)) { 2356 uint16_t phy_tmp = 0; 2357 2358 /* Speed up time to link by disabling smart power down. */ 2359 em_read_phy_reg(&adapter->hw, 2360 IGP02E1000_PHY_POWER_MGMT, &phy_tmp); 2361 phy_tmp &= ~IGP02E1000_PM_SPD; 2362 em_write_phy_reg(&adapter->hw, 2363 IGP02E1000_PHY_POWER_MGMT, phy_tmp); 2364 } 2365 2366 /* 2367 * These parameters control the automatic generation (Tx) and 2368 * response (Rx) to Ethernet PAUSE frames. 2369 * - High water mark should allow for at least two frames to be 2370 * received after sending an XOFF. 2371 * - Low water mark works best when it is very near the high water mark. 2372 * This allows the receiver to restart by sending XON when it has 2373 * drained a bit. Here we use an arbitary value of 1500 which will 2374 * restart after one full frame is pulled from the buffer. There 2375 * could be several smaller frames in the buffer and if so they will 2376 * not trigger the XON until their total number reduces the buffer 2377 * by 1500. 2378 * - The pause time is fairly large at 1000 x 512ns = 512 usec. 2379 */ 2380 rx_buffer_size = ((E1000_READ_REG(&adapter->hw, PBA) & 0xffff) << 10 ); 2381 2382 adapter->hw.fc_high_water = rx_buffer_size - 2383 roundup2(adapter->hw.max_frame_size, 1024); 2384 adapter->hw.fc_low_water = adapter->hw.fc_high_water - 1500; 2385 if (adapter->hw.mac_type == em_80003es2lan) 2386 adapter->hw.fc_pause_time = 0xFFFF; 2387 else 2388 adapter->hw.fc_pause_time = 0x1000; 2389 adapter->hw.fc_send_xon = TRUE; 2390 adapter->hw.fc = E1000_FC_FULL; 2391 2392 if (em_init_hw(&adapter->hw) < 0) { 2393 device_printf(dev, "Hardware Initialization Failed"); 2394 return (EIO); 2395 } 2396 2397 em_check_for_link(&adapter->hw); 2398 2399 return (0); 2400 } 2401 2402 /********************************************************************* 2403 * 2404 * Setup networking device structure and register an interface. 2405 * 2406 **********************************************************************/ 2407 static void 2408 em_setup_interface(device_t dev, struct adapter *adapter) 2409 { 2410 struct ifnet *ifp; 2411 u_char fiber_type = IFM_1000_SX; /* default type */ 2412 2413 INIT_DEBUGOUT("em_setup_interface: begin"); 2414 2415 ifp = adapter->ifp = if_alloc(IFT_ETHER); 2416 if (ifp == NULL) 2417 panic("%s: can not if_alloc()", device_get_nameunit(dev)); 2418 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 2419 ifp->if_mtu = ETHERMTU; 2420 ifp->if_init = em_init; 2421 ifp->if_softc = adapter; 2422 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2423 ifp->if_ioctl = em_ioctl; 2424 ifp->if_start = em_start; 2425 ifp->if_timer = 0; /* Disable net layer watchdog */ 2426 ifp->if_watchdog = NULL; 2427 IFQ_SET_MAXLEN(&ifp->if_snd, adapter->num_tx_desc - 1); 2428 ifp->if_snd.ifq_drv_maxlen = adapter->num_tx_desc - 1; 2429 IFQ_SET_READY(&ifp->if_snd); 2430 2431 ether_ifattach(ifp, adapter->hw.mac_addr); 2432 2433 ifp->if_capabilities = ifp->if_capenable = 0; 2434 2435 if (adapter->hw.mac_type >= em_82543) { 2436 ifp->if_capabilities |= IFCAP_HWCSUM; 2437 ifp->if_capenable |= IFCAP_HWCSUM; 2438 } 2439 2440 #ifdef EM_TSO 2441 /* Enable TSO if available */ 2442 if ((adapter->hw.mac_type > em_82544) && 2443 (adapter->hw.mac_type != em_82547)) { 2444 ifp->if_capabilities |= IFCAP_TSO; 2445 ifp->if_capenable |= IFCAP_TSO; 2446 } 2447 #endif 2448 2449 /* 2450 * Tell the upper layer(s) we support long frames. 2451 */ 2452 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 2453 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU; 2454 ifp->if_capenable |= IFCAP_VLAN_MTU; 2455 2456 #ifdef DEVICE_POLLING 2457 ifp->if_capabilities |= IFCAP_POLLING; 2458 #endif 2459 2460 /* 2461 * Specify the media types supported by this adapter and register 2462 * callbacks to update media and link information 2463 */ 2464 ifmedia_init(&adapter->media, IFM_IMASK, 2465 em_media_change, em_media_status); 2466 if ((adapter->hw.media_type == em_media_type_fiber) || 2467 (adapter->hw.media_type == em_media_type_internal_serdes)) { 2468 if (adapter->hw.mac_type == em_82545) 2469 fiber_type = IFM_1000_LX; 2470 ifmedia_add(&adapter->media, IFM_ETHER | fiber_type | IFM_FDX, 2471 0, NULL); 2472 ifmedia_add(&adapter->media, IFM_ETHER | fiber_type, 0, NULL); 2473 } else { 2474 ifmedia_add(&adapter->media, IFM_ETHER | IFM_10_T, 0, NULL); 2475 ifmedia_add(&adapter->media, IFM_ETHER | IFM_10_T | IFM_FDX, 2476 0, NULL); 2477 ifmedia_add(&adapter->media, IFM_ETHER | IFM_100_TX, 2478 0, NULL); 2479 ifmedia_add(&adapter->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 2480 0, NULL); 2481 if (adapter->hw.phy_type != em_phy_ife) { 2482 ifmedia_add(&adapter->media, 2483 IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 2484 ifmedia_add(&adapter->media, 2485 IFM_ETHER | IFM_1000_T, 0, NULL); 2486 } 2487 } 2488 ifmedia_add(&adapter->media, IFM_ETHER | IFM_AUTO, 0, NULL); 2489 ifmedia_set(&adapter->media, IFM_ETHER | IFM_AUTO); 2490 } 2491 2492 2493 /********************************************************************* 2494 * 2495 * Workaround for SmartSpeed on 82541 and 82547 controllers 2496 * 2497 **********************************************************************/ 2498 static void 2499 em_smartspeed(struct adapter *adapter) 2500 { 2501 uint16_t phy_tmp; 2502 2503 if (adapter->link_active || (adapter->hw.phy_type != em_phy_igp) || 2504 adapter->hw.autoneg == 0 || 2505 (adapter->hw.autoneg_advertised & ADVERTISE_1000_FULL) == 0) 2506 return; 2507 2508 if (adapter->smartspeed == 0) { 2509 /* If Master/Slave config fault is asserted twice, 2510 * we assume back-to-back */ 2511 em_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp); 2512 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT)) 2513 return; 2514 em_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp); 2515 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) { 2516 em_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_tmp); 2517 if(phy_tmp & CR_1000T_MS_ENABLE) { 2518 phy_tmp &= ~CR_1000T_MS_ENABLE; 2519 em_write_phy_reg(&adapter->hw, PHY_1000T_CTRL, 2520 phy_tmp); 2521 adapter->smartspeed++; 2522 if(adapter->hw.autoneg && 2523 !em_phy_setup_autoneg(&adapter->hw) && 2524 !em_read_phy_reg(&adapter->hw, PHY_CTRL, 2525 &phy_tmp)) { 2526 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2527 MII_CR_RESTART_AUTO_NEG); 2528 em_write_phy_reg(&adapter->hw, PHY_CTRL, 2529 phy_tmp); 2530 } 2531 } 2532 } 2533 return; 2534 } else if(adapter->smartspeed == EM_SMARTSPEED_DOWNSHIFT) { 2535 /* If still no link, perhaps using 2/3 pair cable */ 2536 em_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_tmp); 2537 phy_tmp |= CR_1000T_MS_ENABLE; 2538 em_write_phy_reg(&adapter->hw, PHY_1000T_CTRL, phy_tmp); 2539 if(adapter->hw.autoneg && 2540 !em_phy_setup_autoneg(&adapter->hw) && 2541 !em_read_phy_reg(&adapter->hw, PHY_CTRL, &phy_tmp)) { 2542 phy_tmp |= (MII_CR_AUTO_NEG_EN | 2543 MII_CR_RESTART_AUTO_NEG); 2544 em_write_phy_reg(&adapter->hw, PHY_CTRL, phy_tmp); 2545 } 2546 } 2547 /* Restart process after EM_SMARTSPEED_MAX iterations */ 2548 if(adapter->smartspeed++ == EM_SMARTSPEED_MAX) 2549 adapter->smartspeed = 0; 2550 } 2551 2552 2553 /* 2554 * Manage DMA'able memory. 2555 */ 2556 static void 2557 em_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 2558 { 2559 if (error) 2560 return; 2561 *(bus_addr_t *) arg = segs[0].ds_addr; 2562 } 2563 2564 static int 2565 em_dma_malloc(struct adapter *adapter, bus_size_t size, 2566 struct em_dma_alloc *dma, int mapflags) 2567 { 2568 int error; 2569 2570 error = bus_dma_tag_create(NULL, /* parent */ 2571 EM_DBA_ALIGN, 0, /* alignment, bounds */ 2572 BUS_SPACE_MAXADDR, /* lowaddr */ 2573 BUS_SPACE_MAXADDR, /* highaddr */ 2574 NULL, NULL, /* filter, filterarg */ 2575 size, /* maxsize */ 2576 1, /* nsegments */ 2577 size, /* maxsegsize */ 2578 0, /* flags */ 2579 NULL, /* lockfunc */ 2580 NULL, /* lockarg */ 2581 &dma->dma_tag); 2582 if (error) { 2583 device_printf(adapter->dev, 2584 "%s: bus_dma_tag_create failed: %d\n", 2585 __func__, error); 2586 goto fail_0; 2587 } 2588 2589 error = bus_dmamem_alloc(dma->dma_tag, (void**) &dma->dma_vaddr, 2590 BUS_DMA_NOWAIT, &dma->dma_map); 2591 if (error) { 2592 device_printf(adapter->dev, 2593 "%s: bus_dmamem_alloc(%ju) failed: %d\n", 2594 __func__, (uintmax_t)size, error); 2595 goto fail_2; 2596 } 2597 2598 dma->dma_paddr = 0; 2599 error = bus_dmamap_load(dma->dma_tag, dma->dma_map, dma->dma_vaddr, 2600 size, em_dmamap_cb, &dma->dma_paddr, mapflags | BUS_DMA_NOWAIT); 2601 if (error || dma->dma_paddr == 0) { 2602 device_printf(adapter->dev, 2603 "%s: bus_dmamap_load failed: %d\n", 2604 __func__, error); 2605 goto fail_3; 2606 } 2607 2608 return (0); 2609 2610 fail_3: 2611 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 2612 fail_2: 2613 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 2614 bus_dma_tag_destroy(dma->dma_tag); 2615 fail_0: 2616 dma->dma_map = NULL; 2617 dma->dma_tag = NULL; 2618 2619 return (error); 2620 } 2621 2622 static void 2623 em_dma_free(struct adapter *adapter, struct em_dma_alloc *dma) 2624 { 2625 if (dma->dma_tag == NULL) 2626 return; 2627 if (dma->dma_map != NULL) { 2628 bus_dmamap_sync(dma->dma_tag, dma->dma_map, 2629 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2630 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 2631 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 2632 dma->dma_map = NULL; 2633 } 2634 bus_dma_tag_destroy(dma->dma_tag); 2635 dma->dma_tag = NULL; 2636 } 2637 2638 2639 /********************************************************************* 2640 * 2641 * Allocate memory for tx_buffer structures. The tx_buffer stores all 2642 * the information needed to transmit a packet on the wire. 2643 * 2644 **********************************************************************/ 2645 static int 2646 em_allocate_transmit_structures(struct adapter *adapter) 2647 { 2648 device_t dev = adapter->dev; 2649 struct em_buffer *tx_buffer; 2650 int error, i; 2651 2652 /* 2653 * Create DMA tags for tx descriptors 2654 */ 2655 if ((error = bus_dma_tag_create(NULL, /* parent */ 2656 1, 0, /* alignment, bounds */ 2657 BUS_SPACE_MAXADDR, /* lowaddr */ 2658 BUS_SPACE_MAXADDR, /* highaddr */ 2659 NULL, NULL, /* filter, filterarg */ 2660 EM_TSO_SIZE, /* maxsize */ 2661 EM_MAX_SCATTER, /* nsegments */ 2662 PAGE_SIZE, /* maxsegsize */ 2663 0, /* flags */ 2664 NULL, /* lockfunc */ 2665 NULL, /* lockarg */ 2666 &adapter->txtag)) != 0) { 2667 device_printf(dev, "Unable to allocate TX DMA tag\n"); 2668 goto fail; 2669 } 2670 2671 adapter->tx_buffer_area = malloc(sizeof(struct em_buffer) * 2672 adapter->num_tx_desc, M_DEVBUF, M_NOWAIT | M_ZERO); 2673 if (adapter->tx_buffer_area == NULL) { 2674 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 2675 error = ENOMEM; 2676 goto fail; 2677 } 2678 2679 /* Create the descriptor buffer dma maps */ 2680 tx_buffer = adapter->tx_buffer_area; 2681 for (i = 0; i < adapter->num_tx_desc; i++) { 2682 error = bus_dmamap_create(adapter->txtag, 0, &tx_buffer->map); 2683 if (error != 0) { 2684 device_printf(dev, "Unable to create TX DMA map\n"); 2685 goto fail; 2686 } 2687 tx_buffer++; 2688 } 2689 2690 return (0); 2691 2692 fail: 2693 em_free_transmit_structures(adapter); 2694 return (error); 2695 } 2696 2697 /********************************************************************* 2698 * 2699 * Initialize transmit structures. 2700 * 2701 **********************************************************************/ 2702 static void 2703 em_setup_transmit_structures(struct adapter *adapter) 2704 { 2705 struct em_buffer *tx_buffer; 2706 int i; 2707 2708 /* Clear the old ring contents */ 2709 bzero(adapter->tx_desc_base, 2710 (sizeof(struct em_tx_desc)) * adapter->num_tx_desc); 2711 2712 adapter->next_avail_tx_desc = 0; 2713 adapter->next_tx_to_clean = 0; 2714 2715 /* Free any existing tx buffers. */ 2716 tx_buffer = adapter->tx_buffer_area; 2717 for (i = 0; i < adapter->num_tx_desc; i++, tx_buffer++) { 2718 if (tx_buffer->m_head != NULL) { 2719 bus_dmamap_sync(adapter->txtag, tx_buffer->map, 2720 BUS_DMASYNC_POSTWRITE); 2721 bus_dmamap_unload(adapter->txtag, tx_buffer->map); 2722 m_freem(tx_buffer->m_head); 2723 tx_buffer->m_head = NULL; 2724 } 2725 } 2726 2727 /* Set number of descriptors available */ 2728 adapter->num_tx_desc_avail = adapter->num_tx_desc; 2729 2730 /* Set checksum context */ 2731 adapter->active_checksum_context = OFFLOAD_NONE; 2732 bus_dmamap_sync(adapter->txdma.dma_tag, adapter->txdma.dma_map, 2733 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2734 } 2735 2736 /********************************************************************* 2737 * 2738 * Enable transmit unit. 2739 * 2740 **********************************************************************/ 2741 static void 2742 em_initialize_transmit_unit(struct adapter *adapter) 2743 { 2744 uint32_t reg_tctl, reg_tipg = 0; 2745 uint64_t bus_addr; 2746 2747 INIT_DEBUGOUT("em_initialize_transmit_unit: begin"); 2748 /* Setup the Base and Length of the Tx Descriptor Ring */ 2749 bus_addr = adapter->txdma.dma_paddr; 2750 E1000_WRITE_REG(&adapter->hw, TDLEN, 2751 adapter->num_tx_desc * sizeof(struct em_tx_desc)); 2752 E1000_WRITE_REG(&adapter->hw, TDBAH, (uint32_t)(bus_addr >> 32)); 2753 E1000_WRITE_REG(&adapter->hw, TDBAL, (uint32_t)bus_addr); 2754 2755 /* Setup the HW Tx Head and Tail descriptor pointers */ 2756 E1000_WRITE_REG(&adapter->hw, TDT, 0); 2757 E1000_WRITE_REG(&adapter->hw, TDH, 0); 2758 2759 HW_DEBUGOUT2("Base = %x, Length = %x\n", 2760 E1000_READ_REG(&adapter->hw, TDBAL), 2761 E1000_READ_REG(&adapter->hw, TDLEN)); 2762 2763 /* Set the default values for the Tx Inter Packet Gap timer */ 2764 switch (adapter->hw.mac_type) { 2765 case em_82542_rev2_0: 2766 case em_82542_rev2_1: 2767 reg_tipg = DEFAULT_82542_TIPG_IPGT; 2768 reg_tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 2769 reg_tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 2770 break; 2771 case em_80003es2lan: 2772 reg_tipg = DEFAULT_82543_TIPG_IPGR1; 2773 reg_tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 << 2774 E1000_TIPG_IPGR2_SHIFT; 2775 break; 2776 default: 2777 if ((adapter->hw.media_type == em_media_type_fiber) || 2778 (adapter->hw.media_type == em_media_type_internal_serdes)) 2779 reg_tipg = DEFAULT_82543_TIPG_IPGT_FIBER; 2780 else 2781 reg_tipg = DEFAULT_82543_TIPG_IPGT_COPPER; 2782 reg_tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 2783 reg_tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 2784 } 2785 2786 E1000_WRITE_REG(&adapter->hw, TIPG, reg_tipg); 2787 E1000_WRITE_REG(&adapter->hw, TIDV, adapter->tx_int_delay.value); 2788 if(adapter->hw.mac_type >= em_82540) 2789 E1000_WRITE_REG(&adapter->hw, TADV, 2790 adapter->tx_abs_int_delay.value); 2791 2792 /* Program the Transmit Control Register */ 2793 reg_tctl = E1000_TCTL_PSP | E1000_TCTL_EN | 2794 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 2795 if (adapter->hw.mac_type >= em_82571) 2796 reg_tctl |= E1000_TCTL_MULR; 2797 if (adapter->link_duplex == FULL_DUPLEX) { 2798 reg_tctl |= E1000_FDX_COLLISION_DISTANCE << E1000_COLD_SHIFT; 2799 } else { 2800 reg_tctl |= E1000_HDX_COLLISION_DISTANCE << E1000_COLD_SHIFT; 2801 } 2802 /* This write will effectively turn on the transmit unit. */ 2803 E1000_WRITE_REG(&adapter->hw, TCTL, reg_tctl); 2804 2805 /* Setup Transmit Descriptor Base Settings */ 2806 adapter->txd_cmd = E1000_TXD_CMD_IFCS; 2807 2808 if (adapter->tx_int_delay.value > 0) 2809 adapter->txd_cmd |= E1000_TXD_CMD_IDE; 2810 } 2811 2812 /********************************************************************* 2813 * 2814 * Free all transmit related data structures. 2815 * 2816 **********************************************************************/ 2817 static void 2818 em_free_transmit_structures(struct adapter *adapter) 2819 { 2820 struct em_buffer *tx_buffer; 2821 int i; 2822 2823 INIT_DEBUGOUT("free_transmit_structures: begin"); 2824 2825 if (adapter->tx_buffer_area != NULL) { 2826 tx_buffer = adapter->tx_buffer_area; 2827 for (i = 0; i < adapter->num_tx_desc; i++, tx_buffer++) { 2828 if (tx_buffer->m_head != NULL) { 2829 bus_dmamap_sync(adapter->txtag, tx_buffer->map, 2830 BUS_DMASYNC_POSTWRITE); 2831 bus_dmamap_unload(adapter->txtag, 2832 tx_buffer->map); 2833 m_freem(tx_buffer->m_head); 2834 tx_buffer->m_head = NULL; 2835 } else if (tx_buffer->map != NULL) 2836 bus_dmamap_unload(adapter->txtag, 2837 tx_buffer->map); 2838 if (tx_buffer->map != NULL) { 2839 bus_dmamap_destroy(adapter->txtag, 2840 tx_buffer->map); 2841 tx_buffer->map = NULL; 2842 } 2843 } 2844 } 2845 if (adapter->tx_buffer_area != NULL) { 2846 free(adapter->tx_buffer_area, M_DEVBUF); 2847 adapter->tx_buffer_area = NULL; 2848 } 2849 if (adapter->txtag != NULL) { 2850 bus_dma_tag_destroy(adapter->txtag); 2851 adapter->txtag = NULL; 2852 } 2853 } 2854 2855 /********************************************************************* 2856 * 2857 * The offload context needs to be set when we transfer the first 2858 * packet of a particular protocol (TCP/UDP). We change the 2859 * context only if the protocol type changes. 2860 * 2861 **********************************************************************/ 2862 static void 2863 em_transmit_checksum_setup(struct adapter *adapter, struct mbuf *mp, 2864 uint32_t *txd_upper, uint32_t *txd_lower) 2865 { 2866 struct em_context_desc *TXD; 2867 struct em_buffer *tx_buffer; 2868 int curr_txd; 2869 2870 if (mp->m_pkthdr.csum_flags) { 2871 2872 if (mp->m_pkthdr.csum_flags & CSUM_TCP) { 2873 *txd_upper = E1000_TXD_POPTS_TXSM << 8; 2874 *txd_lower = E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D; 2875 if (adapter->active_checksum_context == OFFLOAD_TCP_IP) 2876 return; 2877 else 2878 adapter->active_checksum_context = 2879 OFFLOAD_TCP_IP; 2880 } else if (mp->m_pkthdr.csum_flags & CSUM_UDP) { 2881 *txd_upper = E1000_TXD_POPTS_TXSM << 8; 2882 *txd_lower = E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D; 2883 if (adapter->active_checksum_context == OFFLOAD_UDP_IP) 2884 return; 2885 else 2886 adapter->active_checksum_context = 2887 OFFLOAD_UDP_IP; 2888 } else { 2889 *txd_upper = 0; 2890 *txd_lower = 0; 2891 return; 2892 } 2893 } else { 2894 *txd_upper = 0; 2895 *txd_lower = 0; 2896 return; 2897 } 2898 2899 /* If we reach this point, the checksum offload context 2900 * needs to be reset. 2901 */ 2902 curr_txd = adapter->next_avail_tx_desc; 2903 tx_buffer = &adapter->tx_buffer_area[curr_txd]; 2904 TXD = (struct em_context_desc *) &adapter->tx_desc_base[curr_txd]; 2905 2906 TXD->lower_setup.ip_fields.ipcss = ETHER_HDR_LEN; 2907 TXD->lower_setup.ip_fields.ipcso = 2908 ETHER_HDR_LEN + offsetof(struct ip, ip_sum); 2909 TXD->lower_setup.ip_fields.ipcse = 2910 htole16(ETHER_HDR_LEN + sizeof(struct ip) - 1); 2911 2912 TXD->upper_setup.tcp_fields.tucss = 2913 ETHER_HDR_LEN + sizeof(struct ip); 2914 TXD->upper_setup.tcp_fields.tucse = htole16(0); 2915 2916 if (adapter->active_checksum_context == OFFLOAD_TCP_IP) { 2917 TXD->upper_setup.tcp_fields.tucso = 2918 ETHER_HDR_LEN + sizeof(struct ip) + 2919 offsetof(struct tcphdr, th_sum); 2920 } else if (adapter->active_checksum_context == OFFLOAD_UDP_IP) { 2921 TXD->upper_setup.tcp_fields.tucso = 2922 ETHER_HDR_LEN + sizeof(struct ip) + 2923 offsetof(struct udphdr, uh_sum); 2924 } 2925 2926 TXD->tcp_seg_setup.data = htole32(0); 2927 TXD->cmd_and_length = htole32(adapter->txd_cmd | E1000_TXD_CMD_DEXT); 2928 2929 tx_buffer->m_head = NULL; 2930 tx_buffer->next_eop = -1; 2931 2932 if (++curr_txd == adapter->num_tx_desc) 2933 curr_txd = 0; 2934 2935 adapter->num_tx_desc_avail--; 2936 adapter->next_avail_tx_desc = curr_txd; 2937 } 2938 2939 #ifdef EM_TSO 2940 /********************************************************************** 2941 * 2942 * Setup work for hardware segmentation offload (TSO) 2943 * 2944 **********************************************************************/ 2945 static boolean_t 2946 em_tso_setup(struct adapter *adapter, 2947 struct mbuf *mp, 2948 u_int32_t *txd_upper, 2949 u_int32_t *txd_lower) 2950 { 2951 struct em_context_desc *TXD; 2952 struct em_buffer *tx_buffer; 2953 struct ip *ip; 2954 struct tcphdr *th; 2955 int curr_txd, hdr_len, ip_hlen, tcp_hlen; 2956 2957 if (((mp->m_pkthdr.csum_flags & CSUM_TSO) == 0) || 2958 (mp->m_pkthdr.len <= E1000_TX_BUFFER_SIZE)) { 2959 return FALSE; 2960 } 2961 2962 *txd_lower = (E1000_TXD_CMD_DEXT | 2963 E1000_TXD_DTYP_D | 2964 E1000_TXD_CMD_TSE); 2965 2966 *txd_upper = (E1000_TXD_POPTS_IXSM | 2967 E1000_TXD_POPTS_TXSM) << 8; 2968 2969 curr_txd = adapter->next_avail_tx_desc; 2970 tx_buffer = &adapter->tx_buffer_area[curr_txd]; 2971 TXD = (struct em_context_desc *) &adapter->tx_desc_base[curr_txd]; 2972 2973 mp->m_data += sizeof(struct ether_header); 2974 ip = mtod(mp, struct ip *); 2975 ip->ip_len = 0; 2976 ip->ip_sum = 0; 2977 ip_hlen = ip->ip_hl << 2 ; 2978 th = (struct tcphdr *)((caddr_t)ip + ip_hlen); 2979 tcp_hlen = th->th_off << 2; 2980 2981 hdr_len = ETHER_HDR_LEN + ip_hlen + tcp_hlen; 2982 th->th_sum = in_pseudo(ip->ip_src.s_addr, 2983 ip->ip_dst.s_addr, 2984 htons(IPPROTO_TCP)); 2985 2986 mp->m_data -= sizeof(struct ether_header); 2987 TXD->lower_setup.ip_fields.ipcss = ETHER_HDR_LEN; 2988 TXD->lower_setup.ip_fields.ipcso = 2989 ETHER_HDR_LEN + offsetof(struct ip, ip_sum); 2990 TXD->lower_setup.ip_fields.ipcse = 2991 htole16(ETHER_HDR_LEN + ip_hlen - 1); 2992 2993 TXD->upper_setup.tcp_fields.tucss = 2994 ETHER_HDR_LEN + ip_hlen; 2995 TXD->upper_setup.tcp_fields.tucse = 0; 2996 TXD->upper_setup.tcp_fields.tucso = 2997 ETHER_HDR_LEN + ip_hlen + 2998 offsetof(struct tcphdr, th_sum); 2999 TXD->tcp_seg_setup.fields.mss = htole16(mp->m_pkthdr.tso_segsz); 3000 TXD->tcp_seg_setup.fields.hdr_len = hdr_len; 3001 TXD->cmd_and_length = htole32(adapter->txd_cmd | 3002 E1000_TXD_CMD_DEXT | 3003 E1000_TXD_CMD_TSE | 3004 E1000_TXD_CMD_IP | E1000_TXD_CMD_TCP | 3005 (mp->m_pkthdr.len - (hdr_len))); 3006 3007 tx_buffer->m_head = NULL; 3008 tx_buffer->next_eop = -1; 3009 3010 if (++curr_txd == adapter->num_tx_desc) 3011 curr_txd = 0; 3012 3013 adapter->num_tx_desc_avail--; 3014 adapter->next_avail_tx_desc = curr_txd; 3015 adapter->tx_tso = TRUE; 3016 3017 return TRUE; 3018 } 3019 #endif /* EM_TSO */ 3020 3021 /********************************************************************** 3022 * 3023 * Examine each tx_buffer in the used queue. If the hardware is done 3024 * processing the packet then free associated resources. The 3025 * tx_buffer is put back on the free queue. 3026 * 3027 **********************************************************************/ 3028 static void 3029 em_txeof(struct adapter *adapter) 3030 { 3031 int first, last, done, num_avail; 3032 struct em_buffer *tx_buffer; 3033 struct em_tx_desc *tx_desc, *eop_desc; 3034 struct ifnet *ifp = adapter->ifp; 3035 3036 EM_LOCK_ASSERT(adapter); 3037 3038 if (adapter->num_tx_desc_avail == adapter->num_tx_desc) 3039 return; 3040 3041 num_avail = adapter->num_tx_desc_avail; 3042 first = adapter->next_tx_to_clean; 3043 tx_desc = &adapter->tx_desc_base[first]; 3044 tx_buffer = &adapter->tx_buffer_area[first]; 3045 last = tx_buffer->next_eop; 3046 eop_desc = &adapter->tx_desc_base[last]; 3047 3048 /* 3049 * What this does is get the index of the 3050 * first descriptor AFTER the EOP of the 3051 * first packet, that way we can do the 3052 * simple comparison on the inner while loop. 3053 */ 3054 if (++last == adapter->num_tx_desc) last = 0; 3055 done = last; 3056 3057 bus_dmamap_sync(adapter->txdma.dma_tag, adapter->txdma.dma_map, 3058 BUS_DMASYNC_POSTREAD); 3059 3060 while (eop_desc->upper.fields.status & E1000_TXD_STAT_DD) { 3061 /* We clean the range of the packet */ 3062 while (first != done) { 3063 tx_desc->upper.data = 0; 3064 tx_desc->lower.data = 0; 3065 num_avail++; 3066 3067 if (tx_buffer->m_head) { 3068 ifp->if_opackets++; 3069 bus_dmamap_sync(adapter->txtag, 3070 tx_buffer->map, 3071 BUS_DMASYNC_POSTWRITE); 3072 bus_dmamap_unload(adapter->txtag, 3073 tx_buffer->map); 3074 3075 m_freem(tx_buffer->m_head); 3076 tx_buffer->m_head = NULL; 3077 } 3078 tx_buffer->next_eop = -1; 3079 3080 if (++first == adapter->num_tx_desc) 3081 first = 0; 3082 3083 tx_buffer = &adapter->tx_buffer_area[first]; 3084 tx_desc = &adapter->tx_desc_base[first]; 3085 } 3086 /* See if we can continue to the next packet */ 3087 last = tx_buffer->next_eop; 3088 if (last != -1) { 3089 eop_desc = &adapter->tx_desc_base[last]; 3090 /* Get new done point */ 3091 if (++last == adapter->num_tx_desc) last = 0; 3092 done = last; 3093 } else 3094 break; 3095 } 3096 bus_dmamap_sync(adapter->txdma.dma_tag, adapter->txdma.dma_map, 3097 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3098 3099 adapter->next_tx_to_clean = first; 3100 3101 /* 3102 * If we have enough room, clear IFF_DRV_OACTIVE to tell the stack 3103 * that it is OK to send packets. 3104 * If there are no pending descriptors, clear the timeout. Otherwise, 3105 * if some descriptors have been freed, restart the timeout. 3106 */ 3107 if (num_avail > EM_TX_CLEANUP_THRESHOLD) { 3108 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3109 /* All clean, turn off the timer */ 3110 if (num_avail == adapter->num_tx_desc) 3111 adapter->watchdog_timer = 0; 3112 /* Some cleaned, reset the timer */ 3113 else if (num_avail != adapter->num_tx_desc_avail) 3114 adapter->watchdog_timer = EM_TX_TIMEOUT; 3115 } 3116 adapter->num_tx_desc_avail = num_avail; 3117 return; 3118 } 3119 3120 /********************************************************************* 3121 * 3122 * Get a buffer from system mbuf buffer pool. 3123 * 3124 **********************************************************************/ 3125 static int 3126 em_get_buf(int i, struct adapter *adapter, struct mbuf *mp) 3127 { 3128 struct ifnet *ifp = adapter->ifp; 3129 bus_dma_segment_t segs[1]; 3130 struct em_buffer *rx_buffer; 3131 int error, nsegs; 3132 3133 if (mp == NULL) { 3134 mp = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 3135 if (mp == NULL) { 3136 adapter->mbuf_cluster_failed++; 3137 return (ENOBUFS); 3138 } 3139 mp->m_len = mp->m_pkthdr.len = MCLBYTES; 3140 } else { 3141 mp->m_len = mp->m_pkthdr.len = MCLBYTES; 3142 mp->m_data = mp->m_ext.ext_buf; 3143 mp->m_next = NULL; 3144 } 3145 3146 if (ifp->if_mtu <= ETHERMTU) 3147 m_adj(mp, ETHER_ALIGN); 3148 3149 rx_buffer = &adapter->rx_buffer_area[i]; 3150 3151 /* 3152 * Using memory from the mbuf cluster pool, invoke the 3153 * bus_dma machinery to arrange the memory mapping. 3154 */ 3155 error = bus_dmamap_load_mbuf_sg(adapter->rxtag, rx_buffer->map, 3156 mp, segs, &nsegs, 0); 3157 if (error != 0) { 3158 m_free(mp); 3159 return (error); 3160 } 3161 /* If nsegs is wrong then the stack is corrupt. */ 3162 KASSERT(nsegs == 1, ("Too many segments returned!")); 3163 rx_buffer->m_head = mp; 3164 adapter->rx_desc_base[i].buffer_addr = htole64(segs[0].ds_addr); 3165 bus_dmamap_sync(adapter->rxtag, rx_buffer->map, BUS_DMASYNC_PREREAD); 3166 3167 return (0); 3168 } 3169 3170 /********************************************************************* 3171 * 3172 * Allocate memory for rx_buffer structures. Since we use one 3173 * rx_buffer per received packet, the maximum number of rx_buffer's 3174 * that we'll need is equal to the number of receive descriptors 3175 * that we've allocated. 3176 * 3177 **********************************************************************/ 3178 static int 3179 em_allocate_receive_structures(struct adapter *adapter) 3180 { 3181 device_t dev = adapter->dev; 3182 struct em_buffer *rx_buffer; 3183 int i, error; 3184 3185 adapter->rx_buffer_area = malloc(sizeof(struct em_buffer) * 3186 adapter->num_rx_desc, M_DEVBUF, M_NOWAIT); 3187 if (adapter->rx_buffer_area == NULL) { 3188 device_printf(dev, "Unable to allocate rx_buffer memory\n"); 3189 return (ENOMEM); 3190 } 3191 3192 bzero(adapter->rx_buffer_area, 3193 sizeof(struct em_buffer) * adapter->num_rx_desc); 3194 3195 error = bus_dma_tag_create(NULL, /* parent */ 3196 1, 0, /* alignment, bounds */ 3197 BUS_SPACE_MAXADDR, /* lowaddr */ 3198 BUS_SPACE_MAXADDR, /* highaddr */ 3199 NULL, NULL, /* filter, filterarg */ 3200 MCLBYTES, /* maxsize */ 3201 1, /* nsegments */ 3202 MCLBYTES, /* maxsegsize */ 3203 0, /* flags */ 3204 NULL, /* lockfunc */ 3205 NULL, /* lockarg */ 3206 &adapter->rxtag); 3207 if (error) { 3208 device_printf(dev, "%s: bus_dma_tag_create failed %d\n", 3209 __func__, error); 3210 goto fail; 3211 } 3212 3213 rx_buffer = adapter->rx_buffer_area; 3214 for (i = 0; i < adapter->num_rx_desc; i++, rx_buffer++) { 3215 error = bus_dmamap_create(adapter->rxtag, BUS_DMA_NOWAIT, 3216 &rx_buffer->map); 3217 if (error) { 3218 device_printf(dev, "%s: bus_dmamap_create failed: %d\n", 3219 __func__, error); 3220 goto fail; 3221 } 3222 } 3223 3224 return (0); 3225 3226 fail: 3227 em_free_receive_structures(adapter); 3228 return (error); 3229 } 3230 3231 /********************************************************************* 3232 * 3233 * Allocate and initialize receive structures. 3234 * 3235 **********************************************************************/ 3236 static int 3237 em_setup_receive_structures(struct adapter *adapter) 3238 { 3239 struct em_buffer *rx_buffer; 3240 int i, error; 3241 3242 bzero(adapter->rx_desc_base, 3243 (sizeof(struct em_rx_desc)) * adapter->num_rx_desc); 3244 3245 /* Free current RX buffers. */ 3246 rx_buffer = adapter->rx_buffer_area; 3247 for (i = 0; i < adapter->num_rx_desc; i++, rx_buffer++) { 3248 if (rx_buffer->m_head != NULL) { 3249 bus_dmamap_sync(adapter->rxtag, rx_buffer->map, 3250 BUS_DMASYNC_POSTREAD); 3251 bus_dmamap_unload(adapter->rxtag, rx_buffer->map); 3252 m_freem(rx_buffer->m_head); 3253 rx_buffer->m_head = NULL; 3254 } 3255 } 3256 3257 /* Allocate new ones. */ 3258 for (i = 0; i < adapter->num_rx_desc; i++) { 3259 error = em_get_buf(i, adapter, NULL); 3260 if (error) 3261 return (error); 3262 } 3263 3264 /* Setup our descriptor pointers */ 3265 adapter->next_rx_desc_to_check = 0; 3266 bus_dmamap_sync(adapter->rxdma.dma_tag, adapter->rxdma.dma_map, 3267 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3268 3269 return (0); 3270 } 3271 3272 /********************************************************************* 3273 * 3274 * Enable receive unit. 3275 * 3276 **********************************************************************/ 3277 static void 3278 em_initialize_receive_unit(struct adapter *adapter) 3279 { 3280 struct ifnet *ifp = adapter->ifp; 3281 uint64_t bus_addr; 3282 uint32_t reg_rctl; 3283 uint32_t reg_rxcsum; 3284 3285 INIT_DEBUGOUT("em_initialize_receive_unit: begin"); 3286 3287 /* 3288 * Make sure receives are disabled while setting 3289 * up the descriptor ring 3290 */ 3291 E1000_WRITE_REG(&adapter->hw, RCTL, 0); 3292 3293 if(adapter->hw.mac_type >= em_82540) { 3294 E1000_WRITE_REG(&adapter->hw, RADV, 3295 adapter->rx_abs_int_delay.value); 3296 /* 3297 * Set the interrupt throttling rate. Value is calculated 3298 * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) 3299 */ 3300 #define MAX_INTS_PER_SEC 8000 3301 #define DEFAULT_ITR 1000000000/(MAX_INTS_PER_SEC * 256) 3302 E1000_WRITE_REG(&adapter->hw, ITR, DEFAULT_ITR); 3303 } 3304 3305 /* Setup the Base and Length of the Rx Descriptor Ring */ 3306 bus_addr = adapter->rxdma.dma_paddr; 3307 E1000_WRITE_REG(&adapter->hw, RDLEN, adapter->num_rx_desc * 3308 sizeof(struct em_rx_desc)); 3309 E1000_WRITE_REG(&adapter->hw, RDBAH, (uint32_t)(bus_addr >> 32)); 3310 E1000_WRITE_REG(&adapter->hw, RDBAL, (uint32_t)bus_addr); 3311 3312 /* Setup the Receive Control Register */ 3313 reg_rctl = E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO | 3314 E1000_RCTL_RDMTS_HALF | 3315 (adapter->hw.mc_filter_type << E1000_RCTL_MO_SHIFT); 3316 3317 if (adapter->hw.tbi_compatibility_on == TRUE) 3318 reg_rctl |= E1000_RCTL_SBP; 3319 3320 3321 switch (adapter->rx_buffer_len) { 3322 default: 3323 case EM_RXBUFFER_2048: 3324 reg_rctl |= E1000_RCTL_SZ_2048; 3325 break; 3326 case EM_RXBUFFER_4096: 3327 reg_rctl |= E1000_RCTL_SZ_4096 | 3328 E1000_RCTL_BSEX | E1000_RCTL_LPE; 3329 break; 3330 case EM_RXBUFFER_8192: 3331 reg_rctl |= E1000_RCTL_SZ_8192 | 3332 E1000_RCTL_BSEX | E1000_RCTL_LPE; 3333 break; 3334 case EM_RXBUFFER_16384: 3335 reg_rctl |= E1000_RCTL_SZ_16384 | 3336 E1000_RCTL_BSEX | E1000_RCTL_LPE; 3337 break; 3338 } 3339 3340 if (ifp->if_mtu > ETHERMTU) 3341 reg_rctl |= E1000_RCTL_LPE; 3342 3343 /* Enable 82543 Receive Checksum Offload for TCP and UDP */ 3344 if ((adapter->hw.mac_type >= em_82543) && 3345 (ifp->if_capenable & IFCAP_RXCSUM)) { 3346 reg_rxcsum = E1000_READ_REG(&adapter->hw, RXCSUM); 3347 reg_rxcsum |= (E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL); 3348 E1000_WRITE_REG(&adapter->hw, RXCSUM, reg_rxcsum); 3349 } 3350 3351 /* Enable Receives */ 3352 E1000_WRITE_REG(&adapter->hw, RCTL, reg_rctl); 3353 /* 3354 * Setup the HW Rx Head and 3355 * Tail Descriptor Pointers 3356 */ 3357 E1000_WRITE_REG(&adapter->hw, RDH, 0); 3358 E1000_WRITE_REG(&adapter->hw, RDT, adapter->num_rx_desc - 1); 3359 3360 return; 3361 } 3362 3363 /********************************************************************* 3364 * 3365 * Free receive related data structures. 3366 * 3367 **********************************************************************/ 3368 static void 3369 em_free_receive_structures(struct adapter *adapter) 3370 { 3371 struct em_buffer *rx_buffer; 3372 int i; 3373 3374 INIT_DEBUGOUT("free_receive_structures: begin"); 3375 3376 if (adapter->rx_buffer_area != NULL) { 3377 rx_buffer = adapter->rx_buffer_area; 3378 for (i = 0; i < adapter->num_rx_desc; i++, rx_buffer++) { 3379 if (rx_buffer->m_head != NULL) { 3380 bus_dmamap_sync(adapter->rxtag, rx_buffer->map, 3381 BUS_DMASYNC_POSTREAD); 3382 bus_dmamap_unload(adapter->rxtag, 3383 rx_buffer->map); 3384 m_freem(rx_buffer->m_head); 3385 rx_buffer->m_head = NULL; 3386 } else if (rx_buffer->map != NULL) 3387 bus_dmamap_unload(adapter->rxtag, 3388 rx_buffer->map); 3389 if (rx_buffer->map != NULL) { 3390 bus_dmamap_destroy(adapter->rxtag, 3391 rx_buffer->map); 3392 rx_buffer->map = NULL; 3393 } 3394 } 3395 } 3396 if (adapter->rx_buffer_area != NULL) { 3397 free(adapter->rx_buffer_area, M_DEVBUF); 3398 adapter->rx_buffer_area = NULL; 3399 } 3400 if (adapter->rxtag != NULL) { 3401 bus_dma_tag_destroy(adapter->rxtag); 3402 adapter->rxtag = NULL; 3403 } 3404 } 3405 3406 /********************************************************************* 3407 * 3408 * This routine executes in interrupt context. It replenishes 3409 * the mbufs in the descriptor and sends data which has been 3410 * dma'ed into host memory to upper layer. 3411 * 3412 * We loop at most count times if count is > 0, or until done if 3413 * count < 0. 3414 * 3415 *********************************************************************/ 3416 static int 3417 em_rxeof(struct adapter *adapter, int count) 3418 { 3419 struct ifnet *ifp; 3420 struct mbuf *mp; 3421 uint8_t accept_frame = 0; 3422 uint8_t eop = 0; 3423 uint16_t len, desc_len, prev_len_adj; 3424 int i; 3425 3426 /* Pointer to the receive descriptor being examined. */ 3427 struct em_rx_desc *current_desc; 3428 uint8_t status; 3429 3430 ifp = adapter->ifp; 3431 i = adapter->next_rx_desc_to_check; 3432 current_desc = &adapter->rx_desc_base[i]; 3433 bus_dmamap_sync(adapter->rxdma.dma_tag, adapter->rxdma.dma_map, 3434 BUS_DMASYNC_POSTREAD); 3435 3436 if (!((current_desc->status) & E1000_RXD_STAT_DD)) 3437 return (0); 3438 3439 while ((current_desc->status & E1000_RXD_STAT_DD) && 3440 (count != 0) && 3441 (ifp->if_drv_flags & IFF_DRV_RUNNING)) { 3442 struct mbuf *m = NULL; 3443 3444 mp = adapter->rx_buffer_area[i].m_head; 3445 /* 3446 * Can't defer bus_dmamap_sync(9) because TBI_ACCEPT 3447 * needs to access the last received byte in the mbuf. 3448 */ 3449 bus_dmamap_sync(adapter->rxtag, adapter->rx_buffer_area[i].map, 3450 BUS_DMASYNC_POSTREAD); 3451 3452 accept_frame = 1; 3453 prev_len_adj = 0; 3454 desc_len = le16toh(current_desc->length); 3455 status = current_desc->status; 3456 if (status & E1000_RXD_STAT_EOP) { 3457 count--; 3458 eop = 1; 3459 if (desc_len < ETHER_CRC_LEN) { 3460 len = 0; 3461 prev_len_adj = ETHER_CRC_LEN - desc_len; 3462 } else 3463 len = desc_len - ETHER_CRC_LEN; 3464 } else { 3465 eop = 0; 3466 len = desc_len; 3467 } 3468 3469 if (current_desc->errors & E1000_RXD_ERR_FRAME_ERR_MASK) { 3470 uint8_t last_byte; 3471 uint32_t pkt_len = desc_len; 3472 3473 if (adapter->fmp != NULL) 3474 pkt_len += adapter->fmp->m_pkthdr.len; 3475 3476 last_byte = *(mtod(mp, caddr_t) + desc_len - 1); 3477 if (TBI_ACCEPT(&adapter->hw, status, 3478 current_desc->errors, pkt_len, last_byte)) { 3479 em_tbi_adjust_stats(&adapter->hw, 3480 &adapter->stats, pkt_len, 3481 adapter->hw.mac_addr); 3482 if (len > 0) 3483 len--; 3484 } else 3485 accept_frame = 0; 3486 } 3487 3488 if (accept_frame) { 3489 if (em_get_buf(i, adapter, NULL) == ENOBUFS) { 3490 adapter->dropped_pkts++; 3491 em_get_buf(i, adapter, mp); 3492 if (adapter->fmp != NULL) 3493 m_freem(adapter->fmp); 3494 adapter->fmp = NULL; 3495 adapter->lmp = NULL; 3496 break; 3497 } 3498 3499 /* Assign correct length to the current fragment */ 3500 mp->m_len = len; 3501 3502 if (adapter->fmp == NULL) { 3503 mp->m_pkthdr.len = len; 3504 adapter->fmp = mp; /* Store the first mbuf */ 3505 adapter->lmp = mp; 3506 } else { 3507 /* Chain mbuf's together */ 3508 mp->m_flags &= ~M_PKTHDR; 3509 /* 3510 * Adjust length of previous mbuf in chain if 3511 * we received less than 4 bytes in the last 3512 * descriptor. 3513 */ 3514 if (prev_len_adj > 0) { 3515 adapter->lmp->m_len -= prev_len_adj; 3516 adapter->fmp->m_pkthdr.len -= 3517 prev_len_adj; 3518 } 3519 adapter->lmp->m_next = mp; 3520 adapter->lmp = adapter->lmp->m_next; 3521 adapter->fmp->m_pkthdr.len += len; 3522 } 3523 3524 if (eop) { 3525 adapter->fmp->m_pkthdr.rcvif = ifp; 3526 ifp->if_ipackets++; 3527 em_receive_checksum(adapter, current_desc, 3528 adapter->fmp); 3529 #ifndef __NO_STRICT_ALIGNMENT 3530 if (adapter->hw.max_frame_size > 3531 (MCLBYTES - ETHER_ALIGN) && 3532 em_fixup_rx(adapter) != 0) 3533 goto skip; 3534 #endif 3535 if (status & E1000_RXD_STAT_VP) 3536 VLAN_INPUT_TAG_NEW(ifp, adapter->fmp, 3537 (le16toh(current_desc->special) & 3538 E1000_RXD_SPC_VLAN_MASK)); 3539 #ifndef __NO_STRICT_ALIGNMENT 3540 skip: 3541 #endif 3542 m = adapter->fmp; 3543 adapter->fmp = NULL; 3544 adapter->lmp = NULL; 3545 } 3546 } else { 3547 adapter->dropped_pkts++; 3548 em_get_buf(i, adapter, mp); 3549 if (adapter->fmp != NULL) 3550 m_freem(adapter->fmp); 3551 adapter->fmp = NULL; 3552 adapter->lmp = NULL; 3553 } 3554 3555 /* Zero out the receive descriptors status. */ 3556 current_desc->status = 0; 3557 bus_dmamap_sync(adapter->rxdma.dma_tag, adapter->rxdma.dma_map, 3558 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3559 3560 /* Advance our pointers to the next descriptor. */ 3561 if (++i == adapter->num_rx_desc) 3562 i = 0; 3563 if (m != NULL) { 3564 adapter->next_rx_desc_to_check = i; 3565 #ifndef EM_FAST_INTR 3566 EM_UNLOCK(adapter); 3567 (*ifp->if_input)(ifp, m); 3568 EM_LOCK(adapter); 3569 #else 3570 /* Already running unlocked */ 3571 (*ifp->if_input)(ifp, m); 3572 #endif 3573 i = adapter->next_rx_desc_to_check; 3574 } 3575 current_desc = &adapter->rx_desc_base[i]; 3576 } 3577 adapter->next_rx_desc_to_check = i; 3578 3579 /* Advance the E1000's Receive Queue #0 "Tail Pointer". */ 3580 if (--i < 0) 3581 i = adapter->num_rx_desc - 1; 3582 E1000_WRITE_REG(&adapter->hw, RDT, i); 3583 if (!((current_desc->status) & E1000_RXD_STAT_DD)) 3584 return (0); 3585 3586 return (1); 3587 } 3588 3589 #ifndef __NO_STRICT_ALIGNMENT 3590 /* 3591 * When jumbo frames are enabled we should realign entire payload on 3592 * architecures with strict alignment. This is serious design mistake of 8254x 3593 * as it nullifies DMA operations. 8254x just allows RX buffer size to be 3594 * 2048/4096/8192/16384. What we really want is 2048 - ETHER_ALIGN to align its 3595 * payload. On architecures without strict alignment restrictions 8254x still 3596 * performs unaligned memory access which would reduce the performance too. 3597 * To avoid copying over an entire frame to align, we allocate a new mbuf and 3598 * copy ethernet header to the new mbuf. The new mbuf is prepended into the 3599 * existing mbuf chain. 3600 * 3601 * Be aware, best performance of the 8254x is achived only when jumbo frame is 3602 * not used at all on architectures with strict alignment. 3603 */ 3604 static int 3605 em_fixup_rx(struct adapter *adapter) 3606 { 3607 struct mbuf *m, *n; 3608 int error; 3609 3610 error = 0; 3611 m = adapter->fmp; 3612 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) { 3613 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len); 3614 m->m_data += ETHER_HDR_LEN; 3615 } else { 3616 MGETHDR(n, M_DONTWAIT, MT_DATA); 3617 if (n != NULL) { 3618 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 3619 m->m_data += ETHER_HDR_LEN; 3620 m->m_len -= ETHER_HDR_LEN; 3621 n->m_len = ETHER_HDR_LEN; 3622 M_MOVE_PKTHDR(n, m); 3623 n->m_next = m; 3624 adapter->fmp = n; 3625 } else { 3626 adapter->dropped_pkts++; 3627 m_freem(adapter->fmp); 3628 adapter->fmp = NULL; 3629 error = ENOMEM; 3630 } 3631 } 3632 3633 return (error); 3634 } 3635 #endif 3636 3637 /********************************************************************* 3638 * 3639 * Verify that the hardware indicated that the checksum is valid. 3640 * Inform the stack about the status of checksum so that stack 3641 * doesn't spend time verifying the checksum. 3642 * 3643 *********************************************************************/ 3644 static void 3645 em_receive_checksum(struct adapter *adapter, 3646 struct em_rx_desc *rx_desc, struct mbuf *mp) 3647 { 3648 /* 82543 or newer only */ 3649 if ((adapter->hw.mac_type < em_82543) || 3650 /* Ignore Checksum bit is set */ 3651 (rx_desc->status & E1000_RXD_STAT_IXSM)) { 3652 mp->m_pkthdr.csum_flags = 0; 3653 return; 3654 } 3655 3656 if (rx_desc->status & E1000_RXD_STAT_IPCS) { 3657 /* Did it pass? */ 3658 if (!(rx_desc->errors & E1000_RXD_ERR_IPE)) { 3659 /* IP Checksum Good */ 3660 mp->m_pkthdr.csum_flags = CSUM_IP_CHECKED; 3661 mp->m_pkthdr.csum_flags |= CSUM_IP_VALID; 3662 3663 } else { 3664 mp->m_pkthdr.csum_flags = 0; 3665 } 3666 } 3667 3668 if (rx_desc->status & E1000_RXD_STAT_TCPCS) { 3669 /* Did it pass? */ 3670 if (!(rx_desc->errors & E1000_RXD_ERR_TCPE)) { 3671 mp->m_pkthdr.csum_flags |= 3672 (CSUM_DATA_VALID | CSUM_PSEUDO_HDR); 3673 mp->m_pkthdr.csum_data = htons(0xffff); 3674 } 3675 } 3676 } 3677 3678 3679 static void 3680 em_enable_vlans(struct adapter *adapter) 3681 { 3682 uint32_t ctrl; 3683 3684 E1000_WRITE_REG(&adapter->hw, VET, ETHERTYPE_VLAN); 3685 3686 ctrl = E1000_READ_REG(&adapter->hw, CTRL); 3687 ctrl |= E1000_CTRL_VME; 3688 E1000_WRITE_REG(&adapter->hw, CTRL, ctrl); 3689 } 3690 3691 static void 3692 em_disable_vlans(struct adapter *adapter) 3693 { 3694 uint32_t ctrl; 3695 3696 ctrl = E1000_READ_REG(&adapter->hw, CTRL); 3697 ctrl &= ~E1000_CTRL_VME; 3698 E1000_WRITE_REG(&adapter->hw, CTRL, ctrl); 3699 } 3700 3701 static void 3702 em_enable_intr(struct adapter *adapter) 3703 { 3704 E1000_WRITE_REG(&adapter->hw, IMS, (IMS_ENABLE_MASK)); 3705 } 3706 3707 static void 3708 em_disable_intr(struct adapter *adapter) 3709 { 3710 /* 3711 * The first version of 82542 had an errata where when link was forced 3712 * it would stay up even up even if the cable was disconnected. 3713 * Sequence errors were used to detect the disconnect and then the 3714 * driver would unforce the link. This code in the in the ISR. For this 3715 * to work correctly the Sequence error interrupt had to be enabled 3716 * all the time. 3717 */ 3718 3719 if (adapter->hw.mac_type == em_82542_rev2_0) 3720 E1000_WRITE_REG(&adapter->hw, IMC, 3721 (0xffffffff & ~E1000_IMC_RXSEQ)); 3722 else 3723 E1000_WRITE_REG(&adapter->hw, IMC, 0xffffffff); 3724 } 3725 3726 static int 3727 em_is_valid_ether_addr(uint8_t *addr) 3728 { 3729 char zero_addr[6] = { 0, 0, 0, 0, 0, 0 }; 3730 3731 if ((addr[0] & 1) || (!bcmp(addr, zero_addr, ETHER_ADDR_LEN))) { 3732 return (FALSE); 3733 } 3734 3735 return (TRUE); 3736 } 3737 3738 void 3739 em_write_pci_cfg(struct em_hw *hw, uint32_t reg, uint16_t *value) 3740 { 3741 pci_write_config(((struct em_osdep *)hw->back)->dev, reg, *value, 2); 3742 } 3743 3744 void 3745 em_read_pci_cfg(struct em_hw *hw, uint32_t reg, uint16_t *value) 3746 { 3747 *value = pci_read_config(((struct em_osdep *)hw->back)->dev, reg, 2); 3748 } 3749 3750 void 3751 em_pci_set_mwi(struct em_hw *hw) 3752 { 3753 pci_write_config(((struct em_osdep *)hw->back)->dev, PCIR_COMMAND, 3754 (hw->pci_cmd_word | CMD_MEM_WRT_INVALIDATE), 2); 3755 } 3756 3757 void 3758 em_pci_clear_mwi(struct em_hw *hw) 3759 { 3760 pci_write_config(((struct em_osdep *)hw->back)->dev, PCIR_COMMAND, 3761 (hw->pci_cmd_word & ~CMD_MEM_WRT_INVALIDATE), 2); 3762 } 3763 3764 uint32_t 3765 em_io_read(struct em_hw *hw, unsigned long port) 3766 { 3767 struct em_osdep *io = hw->back; 3768 uint32_t ret; 3769 3770 ret = bus_space_read_4(io->io_bus_space_tag, 3771 io->io_bus_space_handle, port); 3772 return (ret); 3773 } 3774 3775 void 3776 em_io_write(struct em_hw *hw, unsigned long port, uint32_t value) 3777 { 3778 struct em_osdep *io = hw->back; 3779 3780 bus_space_write_4(io->io_bus_space_tag, 3781 io->io_bus_space_handle, port, value); 3782 return; 3783 } 3784 3785 /* 3786 * We may eventually really do this, but its unnecessary 3787 * for now so we just return unsupported. 3788 */ 3789 int32_t 3790 em_read_pcie_cap_reg(struct em_hw *hw, uint32_t reg, uint16_t *value) 3791 { 3792 return (0); 3793 } 3794 3795 /********************************************************************* 3796 * 82544 Coexistence issue workaround. 3797 * There are 2 issues. 3798 * 1. Transmit Hang issue. 3799 * To detect this issue, following equation can be used... 3800 * SIZE[3:0] + ADDR[2:0] = SUM[3:0]. 3801 * If SUM[3:0] is in between 1 to 4, we will have this issue. 3802 * 3803 * 2. DAC issue. 3804 * To detect this issue, following equation can be used... 3805 * SIZE[3:0] + ADDR[2:0] = SUM[3:0]. 3806 * If SUM[3:0] is in between 9 to c, we will have this issue. 3807 * 3808 * 3809 * WORKAROUND: 3810 * Make sure we do not have ending address 3811 * as 1,2,3,4(Hang) or 9,a,b,c (DAC) 3812 * 3813 *************************************************************************/ 3814 static uint32_t 3815 em_fill_descriptors (bus_addr_t address, uint32_t length, 3816 PDESC_ARRAY desc_array) 3817 { 3818 /* Since issue is sensitive to length and address.*/ 3819 /* Let us first check the address...*/ 3820 uint32_t safe_terminator; 3821 if (length <= 4) { 3822 desc_array->descriptor[0].address = address; 3823 desc_array->descriptor[0].length = length; 3824 desc_array->elements = 1; 3825 return (desc_array->elements); 3826 } 3827 safe_terminator = (uint32_t)((((uint32_t)address & 0x7) + 3828 (length & 0xF)) & 0xF); 3829 /* if it does not fall between 0x1 to 0x4 and 0x9 to 0xC then return */ 3830 if (safe_terminator == 0 || 3831 (safe_terminator > 4 && 3832 safe_terminator < 9) || 3833 (safe_terminator > 0xC && 3834 safe_terminator <= 0xF)) { 3835 desc_array->descriptor[0].address = address; 3836 desc_array->descriptor[0].length = length; 3837 desc_array->elements = 1; 3838 return (desc_array->elements); 3839 } 3840 3841 desc_array->descriptor[0].address = address; 3842 desc_array->descriptor[0].length = length - 4; 3843 desc_array->descriptor[1].address = address + (length - 4); 3844 desc_array->descriptor[1].length = 4; 3845 desc_array->elements = 2; 3846 return (desc_array->elements); 3847 } 3848 3849 /********************************************************************** 3850 * 3851 * Update the board statistics counters. 3852 * 3853 **********************************************************************/ 3854 static void 3855 em_update_stats_counters(struct adapter *adapter) 3856 { 3857 struct ifnet *ifp; 3858 3859 if(adapter->hw.media_type == em_media_type_copper || 3860 (E1000_READ_REG(&adapter->hw, STATUS) & E1000_STATUS_LU)) { 3861 adapter->stats.symerrs += E1000_READ_REG(&adapter->hw, SYMERRS); 3862 adapter->stats.sec += E1000_READ_REG(&adapter->hw, SEC); 3863 } 3864 adapter->stats.crcerrs += E1000_READ_REG(&adapter->hw, CRCERRS); 3865 adapter->stats.mpc += E1000_READ_REG(&adapter->hw, MPC); 3866 adapter->stats.scc += E1000_READ_REG(&adapter->hw, SCC); 3867 adapter->stats.ecol += E1000_READ_REG(&adapter->hw, ECOL); 3868 3869 adapter->stats.mcc += E1000_READ_REG(&adapter->hw, MCC); 3870 adapter->stats.latecol += E1000_READ_REG(&adapter->hw, LATECOL); 3871 adapter->stats.colc += E1000_READ_REG(&adapter->hw, COLC); 3872 adapter->stats.dc += E1000_READ_REG(&adapter->hw, DC); 3873 adapter->stats.rlec += E1000_READ_REG(&adapter->hw, RLEC); 3874 adapter->stats.xonrxc += E1000_READ_REG(&adapter->hw, XONRXC); 3875 adapter->stats.xontxc += E1000_READ_REG(&adapter->hw, XONTXC); 3876 adapter->stats.xoffrxc += E1000_READ_REG(&adapter->hw, XOFFRXC); 3877 adapter->stats.xofftxc += E1000_READ_REG(&adapter->hw, XOFFTXC); 3878 adapter->stats.fcruc += E1000_READ_REG(&adapter->hw, FCRUC); 3879 adapter->stats.prc64 += E1000_READ_REG(&adapter->hw, PRC64); 3880 adapter->stats.prc127 += E1000_READ_REG(&adapter->hw, PRC127); 3881 adapter->stats.prc255 += E1000_READ_REG(&adapter->hw, PRC255); 3882 adapter->stats.prc511 += E1000_READ_REG(&adapter->hw, PRC511); 3883 adapter->stats.prc1023 += E1000_READ_REG(&adapter->hw, PRC1023); 3884 adapter->stats.prc1522 += E1000_READ_REG(&adapter->hw, PRC1522); 3885 adapter->stats.gprc += E1000_READ_REG(&adapter->hw, GPRC); 3886 adapter->stats.bprc += E1000_READ_REG(&adapter->hw, BPRC); 3887 adapter->stats.mprc += E1000_READ_REG(&adapter->hw, MPRC); 3888 adapter->stats.gptc += E1000_READ_REG(&adapter->hw, GPTC); 3889 3890 /* For the 64-bit byte counters the low dword must be read first. */ 3891 /* Both registers clear on the read of the high dword */ 3892 3893 adapter->stats.gorcl += E1000_READ_REG(&adapter->hw, GORCL); 3894 adapter->stats.gorch += E1000_READ_REG(&adapter->hw, GORCH); 3895 adapter->stats.gotcl += E1000_READ_REG(&adapter->hw, GOTCL); 3896 adapter->stats.gotch += E1000_READ_REG(&adapter->hw, GOTCH); 3897 3898 adapter->stats.rnbc += E1000_READ_REG(&adapter->hw, RNBC); 3899 adapter->stats.ruc += E1000_READ_REG(&adapter->hw, RUC); 3900 adapter->stats.rfc += E1000_READ_REG(&adapter->hw, RFC); 3901 adapter->stats.roc += E1000_READ_REG(&adapter->hw, ROC); 3902 adapter->stats.rjc += E1000_READ_REG(&adapter->hw, RJC); 3903 3904 adapter->stats.torl += E1000_READ_REG(&adapter->hw, TORL); 3905 adapter->stats.torh += E1000_READ_REG(&adapter->hw, TORH); 3906 adapter->stats.totl += E1000_READ_REG(&adapter->hw, TOTL); 3907 adapter->stats.toth += E1000_READ_REG(&adapter->hw, TOTH); 3908 3909 adapter->stats.tpr += E1000_READ_REG(&adapter->hw, TPR); 3910 adapter->stats.tpt += E1000_READ_REG(&adapter->hw, TPT); 3911 adapter->stats.ptc64 += E1000_READ_REG(&adapter->hw, PTC64); 3912 adapter->stats.ptc127 += E1000_READ_REG(&adapter->hw, PTC127); 3913 adapter->stats.ptc255 += E1000_READ_REG(&adapter->hw, PTC255); 3914 adapter->stats.ptc511 += E1000_READ_REG(&adapter->hw, PTC511); 3915 adapter->stats.ptc1023 += E1000_READ_REG(&adapter->hw, PTC1023); 3916 adapter->stats.ptc1522 += E1000_READ_REG(&adapter->hw, PTC1522); 3917 adapter->stats.mptc += E1000_READ_REG(&adapter->hw, MPTC); 3918 adapter->stats.bptc += E1000_READ_REG(&adapter->hw, BPTC); 3919 3920 if (adapter->hw.mac_type >= em_82543) { 3921 adapter->stats.algnerrc += 3922 E1000_READ_REG(&adapter->hw, ALGNERRC); 3923 adapter->stats.rxerrc += 3924 E1000_READ_REG(&adapter->hw, RXERRC); 3925 adapter->stats.tncrs += 3926 E1000_READ_REG(&adapter->hw, TNCRS); 3927 adapter->stats.cexterr += 3928 E1000_READ_REG(&adapter->hw, CEXTERR); 3929 adapter->stats.tsctc += 3930 E1000_READ_REG(&adapter->hw, TSCTC); 3931 adapter->stats.tsctfc += 3932 E1000_READ_REG(&adapter->hw, TSCTFC); 3933 } 3934 ifp = adapter->ifp; 3935 3936 ifp->if_collisions = adapter->stats.colc; 3937 3938 /* Rx Errors */ 3939 ifp->if_ierrors = adapter->dropped_pkts + adapter->stats.rxerrc + 3940 adapter->stats.crcerrs + adapter->stats.algnerrc + 3941 adapter->stats.ruc + adapter->stats.roc + 3942 adapter->stats.mpc + adapter->stats.cexterr; 3943 3944 /* Tx Errors */ 3945 ifp->if_oerrors = adapter->stats.ecol + 3946 adapter->stats.latecol + adapter->watchdog_events; 3947 } 3948 3949 3950 /********************************************************************** 3951 * 3952 * This routine is called only when em_display_debug_stats is enabled. 3953 * This routine provides a way to take a look at important statistics 3954 * maintained by the driver and hardware. 3955 * 3956 **********************************************************************/ 3957 static void 3958 em_print_debug_info(struct adapter *adapter) 3959 { 3960 device_t dev = adapter->dev; 3961 uint8_t *hw_addr = adapter->hw.hw_addr; 3962 3963 device_printf(dev, "Adapter hardware address = %p \n", hw_addr); 3964 device_printf(dev, "CTRL = 0x%x RCTL = 0x%x \n", 3965 E1000_READ_REG(&adapter->hw, CTRL), 3966 E1000_READ_REG(&adapter->hw, RCTL)); 3967 device_printf(dev, "Packet buffer = Tx=%dk Rx=%dk \n", 3968 ((E1000_READ_REG(&adapter->hw, PBA) & 0xffff0000) >> 16),\ 3969 (E1000_READ_REG(&adapter->hw, PBA) & 0xffff) ); 3970 device_printf(dev, "Flow control watermarks high = %d low = %d\n", 3971 adapter->hw.fc_high_water, 3972 adapter->hw.fc_low_water); 3973 device_printf(dev, "tx_int_delay = %d, tx_abs_int_delay = %d\n", 3974 E1000_READ_REG(&adapter->hw, TIDV), 3975 E1000_READ_REG(&adapter->hw, TADV)); 3976 device_printf(dev, "rx_int_delay = %d, rx_abs_int_delay = %d\n", 3977 E1000_READ_REG(&adapter->hw, RDTR), 3978 E1000_READ_REG(&adapter->hw, RADV)); 3979 device_printf(dev, "fifo workaround = %lld, fifo_reset_count = %lld\n", 3980 (long long)adapter->tx_fifo_wrk_cnt, 3981 (long long)adapter->tx_fifo_reset_cnt); 3982 device_printf(dev, "hw tdh = %d, hw tdt = %d\n", 3983 E1000_READ_REG(&adapter->hw, TDH), 3984 E1000_READ_REG(&adapter->hw, TDT)); 3985 device_printf(dev, "Num Tx descriptors avail = %d\n", 3986 adapter->num_tx_desc_avail); 3987 device_printf(dev, "Tx Descriptors not avail1 = %ld\n", 3988 adapter->no_tx_desc_avail1); 3989 device_printf(dev, "Tx Descriptors not avail2 = %ld\n", 3990 adapter->no_tx_desc_avail2); 3991 device_printf(dev, "Std mbuf failed = %ld\n", 3992 adapter->mbuf_alloc_failed); 3993 device_printf(dev, "Std mbuf cluster failed = %ld\n", 3994 adapter->mbuf_cluster_failed); 3995 device_printf(dev, "Driver dropped packets = %ld\n", 3996 adapter->dropped_pkts); 3997 device_printf(dev, "Driver tx dma failure in encap = %ld\n", 3998 adapter->no_tx_dma_setup); 3999 } 4000 4001 static void 4002 em_print_hw_stats(struct adapter *adapter) 4003 { 4004 device_t dev = adapter->dev; 4005 4006 device_printf(dev, "Excessive collisions = %lld\n", 4007 (long long)adapter->stats.ecol); 4008 #if (DEBUG_HW > 0) /* Dont output these errors normally */ 4009 device_printf(dev, "Symbol errors = %lld\n", 4010 (long long)adapter->stats.symerrs); 4011 #endif 4012 device_printf(dev, "Sequence errors = %lld\n", 4013 (long long)adapter->stats.sec); 4014 device_printf(dev, "Defer count = %lld\n", 4015 (long long)adapter->stats.dc); 4016 device_printf(dev, "Missed Packets = %lld\n", 4017 (long long)adapter->stats.mpc); 4018 device_printf(dev, "Receive No Buffers = %lld\n", 4019 (long long)adapter->stats.rnbc); 4020 /* RLEC is inaccurate on some hardware, calculate our own. */ 4021 device_printf(dev, "Receive Length Errors = %lld\n", 4022 ((long long)adapter->stats.roc + (long long)adapter->stats.ruc)); 4023 device_printf(dev, "Receive errors = %lld\n", 4024 (long long)adapter->stats.rxerrc); 4025 device_printf(dev, "Crc errors = %lld\n", 4026 (long long)adapter->stats.crcerrs); 4027 device_printf(dev, "Alignment errors = %lld\n", 4028 (long long)adapter->stats.algnerrc); 4029 device_printf(dev, "Carrier extension errors = %lld\n", 4030 (long long)adapter->stats.cexterr); 4031 device_printf(dev, "RX overruns = %ld\n", adapter->rx_overruns); 4032 device_printf(dev, "watchdog timeouts = %ld\n", 4033 adapter->watchdog_events); 4034 device_printf(dev, "XON Rcvd = %lld\n", 4035 (long long)adapter->stats.xonrxc); 4036 device_printf(dev, "XON Xmtd = %lld\n", 4037 (long long)adapter->stats.xontxc); 4038 device_printf(dev, "XOFF Rcvd = %lld\n", 4039 (long long)adapter->stats.xoffrxc); 4040 device_printf(dev, "XOFF Xmtd = %lld\n", 4041 (long long)adapter->stats.xofftxc); 4042 device_printf(dev, "Good Packets Rcvd = %lld\n", 4043 (long long)adapter->stats.gprc); 4044 device_printf(dev, "Good Packets Xmtd = %lld\n", 4045 (long long)adapter->stats.gptc); 4046 #ifdef EM_TSO 4047 device_printf(dev, "TSO Contexts Xmtd = %lld\n", 4048 (long long)adapter->stats.tsctc); 4049 device_printf(dev, "TSO Contexts Failed = %lld\n", 4050 (long long)adapter->stats.tsctfc); 4051 #endif 4052 } 4053 4054 static int 4055 em_sysctl_debug_info(SYSCTL_HANDLER_ARGS) 4056 { 4057 struct adapter *adapter; 4058 int error; 4059 int result; 4060 4061 result = -1; 4062 error = sysctl_handle_int(oidp, &result, 0, req); 4063 4064 if (error || !req->newptr) 4065 return (error); 4066 4067 if (result == 1) { 4068 adapter = (struct adapter *)arg1; 4069 em_print_debug_info(adapter); 4070 } 4071 4072 return (error); 4073 } 4074 4075 4076 static int 4077 em_sysctl_stats(SYSCTL_HANDLER_ARGS) 4078 { 4079 struct adapter *adapter; 4080 int error; 4081 int result; 4082 4083 result = -1; 4084 error = sysctl_handle_int(oidp, &result, 0, req); 4085 4086 if (error || !req->newptr) 4087 return (error); 4088 4089 if (result == 1) { 4090 adapter = (struct adapter *)arg1; 4091 em_print_hw_stats(adapter); 4092 } 4093 4094 return (error); 4095 } 4096 4097 static int 4098 em_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 4099 { 4100 struct em_int_delay_info *info; 4101 struct adapter *adapter; 4102 uint32_t regval; 4103 int error; 4104 int usecs; 4105 int ticks; 4106 4107 info = (struct em_int_delay_info *)arg1; 4108 usecs = info->value; 4109 error = sysctl_handle_int(oidp, &usecs, 0, req); 4110 if (error != 0 || req->newptr == NULL) 4111 return (error); 4112 if (usecs < 0 || usecs > E1000_TICKS_TO_USECS(65535)) 4113 return (EINVAL); 4114 info->value = usecs; 4115 ticks = E1000_USECS_TO_TICKS(usecs); 4116 4117 adapter = info->adapter; 4118 4119 EM_LOCK(adapter); 4120 regval = E1000_READ_OFFSET(&adapter->hw, info->offset); 4121 regval = (regval & ~0xffff) | (ticks & 0xffff); 4122 /* Handle a few special cases. */ 4123 switch (info->offset) { 4124 case E1000_RDTR: 4125 case E1000_82542_RDTR: 4126 regval |= E1000_RDT_FPDB; 4127 break; 4128 case E1000_TIDV: 4129 case E1000_82542_TIDV: 4130 if (ticks == 0) { 4131 adapter->txd_cmd &= ~E1000_TXD_CMD_IDE; 4132 /* Don't write 0 into the TIDV register. */ 4133 regval++; 4134 } else 4135 adapter->txd_cmd |= E1000_TXD_CMD_IDE; 4136 break; 4137 } 4138 E1000_WRITE_OFFSET(&adapter->hw, info->offset, regval); 4139 EM_UNLOCK(adapter); 4140 return (0); 4141 } 4142 4143 static void 4144 em_add_int_delay_sysctl(struct adapter *adapter, const char *name, 4145 const char *description, struct em_int_delay_info *info, 4146 int offset, int value) 4147 { 4148 info->adapter = adapter; 4149 info->offset = offset; 4150 info->value = value; 4151 SYSCTL_ADD_PROC(device_get_sysctl_ctx(adapter->dev), 4152 SYSCTL_CHILDREN(device_get_sysctl_tree(adapter->dev)), 4153 OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW, 4154 info, 0, em_sysctl_int_delay, "I", description); 4155 } 4156 4157 static void 4158 em_add_rx_process_limit(struct adapter *adapter, const char *name, 4159 const char *description, int *limit, int value) 4160 { 4161 *limit = value; 4162 SYSCTL_ADD_INT(device_get_sysctl_ctx(adapter->dev), 4163 SYSCTL_CHILDREN(device_get_sysctl_tree(adapter->dev)), 4164 OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW, limit, value, description); 4165 }
Cache object: 8a29e2b09b1da0a33fefeea0cadd4280
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