Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/dev/em/if_em.c
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1 /************************************************************************** 2 3 Copyright (c) 2001-2007, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ***************************************************************************/ 33 /* $FreeBSD$ */ 34 35 36 #ifdef HAVE_KERNEL_OPTION_HEADERS 37 #include "opt_device_polling.h" 38 #endif 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/bus.h> 43 #include <sys/endian.h> 44 #include <sys/kernel.h> 45 #include <sys/kthread.h> 46 #include <sys/malloc.h> 47 #include <sys/mbuf.h> 48 #include <sys/module.h> 49 #include <sys/rman.h> 50 #include <sys/socket.h> 51 #include <sys/sockio.h> 52 #include <sys/sysctl.h> 53 #include <sys/taskqueue.h> 54 55 #include <machine/bus.h> 56 #include <machine/resource.h> 57 58 #include <net/bpf.h> 59 #include <net/ethernet.h> 60 #include <net/if.h> 61 #include <net/if_arp.h> 62 #include <net/if_dl.h> 63 #include <net/if_media.h> 64 65 #include <net/if_types.h> 66 #include <net/if_vlan_var.h> 67 68 #include <netinet/in_systm.h> 69 #include <netinet/in.h> 70 #include <netinet/if_ether.h> 71 #include <netinet/ip.h> 72 #include <netinet/ip6.h> 73 #include <netinet/tcp.h> 74 #include <netinet/udp.h> 75 76 #include <machine/in_cksum.h> 77 #include <dev/pci/pcivar.h> 78 #include <dev/pci/pcireg.h> 79 80 #include "e1000_api.h" 81 #include "e1000_82575.h" 82 #include "if_em.h" 83 84 /********************************************************************* 85 * Set this to one to display debug statistics 86 *********************************************************************/ 87 int em_display_debug_stats = 0; 88 89 /********************************************************************* 90 * Driver version: 91 *********************************************************************/ 92 char em_driver_version[] = "Version - 6.7.3"; 93 94 95 /********************************************************************* 96 * PCI Device ID Table 97 * 98 * Used by probe to select devices to load on 99 * Last field stores an index into e1000_strings 100 * Last entry must be all 0s 101 * 102 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, String Index } 103 *********************************************************************/ 104 105 static em_vendor_info_t em_vendor_info_array[] = 106 { 107 /* Intel(R) PRO/1000 Network Connection */ 108 { 0x8086, E1000_DEV_ID_82540EM, PCI_ANY_ID, PCI_ANY_ID, 0}, 109 { 0x8086, E1000_DEV_ID_82540EM_LOM, PCI_ANY_ID, PCI_ANY_ID, 0}, 110 { 0x8086, E1000_DEV_ID_82540EP, PCI_ANY_ID, PCI_ANY_ID, 0}, 111 { 0x8086, E1000_DEV_ID_82540EP_LOM, PCI_ANY_ID, PCI_ANY_ID, 0}, 112 { 0x8086, E1000_DEV_ID_82540EP_LP, PCI_ANY_ID, PCI_ANY_ID, 0}, 113 114 { 0x8086, E1000_DEV_ID_82541EI, PCI_ANY_ID, PCI_ANY_ID, 0}, 115 { 0x8086, E1000_DEV_ID_82541ER, PCI_ANY_ID, PCI_ANY_ID, 0}, 116 { 0x8086, E1000_DEV_ID_82541ER_LOM, PCI_ANY_ID, PCI_ANY_ID, 0}, 117 { 0x8086, E1000_DEV_ID_82541EI_MOBILE, PCI_ANY_ID, PCI_ANY_ID, 0}, 118 { 0x8086, E1000_DEV_ID_82541GI, PCI_ANY_ID, PCI_ANY_ID, 0}, 119 { 0x8086, E1000_DEV_ID_82541GI_LF, PCI_ANY_ID, PCI_ANY_ID, 0}, 120 { 0x8086, E1000_DEV_ID_82541GI_MOBILE, PCI_ANY_ID, PCI_ANY_ID, 0}, 121 122 { 0x8086, E1000_DEV_ID_82542, PCI_ANY_ID, PCI_ANY_ID, 0}, 123 124 { 0x8086, E1000_DEV_ID_82543GC_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 125 { 0x8086, E1000_DEV_ID_82543GC_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 126 127 { 0x8086, E1000_DEV_ID_82544EI_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 128 { 0x8086, E1000_DEV_ID_82544EI_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 129 { 0x8086, E1000_DEV_ID_82544GC_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 130 { 0x8086, E1000_DEV_ID_82544GC_LOM, PCI_ANY_ID, PCI_ANY_ID, 0}, 131 132 { 0x8086, E1000_DEV_ID_82545EM_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 133 { 0x8086, E1000_DEV_ID_82545EM_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 134 { 0x8086, E1000_DEV_ID_82545GM_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 135 { 0x8086, E1000_DEV_ID_82545GM_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 136 { 0x8086, E1000_DEV_ID_82545GM_SERDES, PCI_ANY_ID, PCI_ANY_ID, 0}, 137 138 { 0x8086, E1000_DEV_ID_82546EB_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 139 { 0x8086, E1000_DEV_ID_82546EB_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 140 { 0x8086, E1000_DEV_ID_82546EB_QUAD_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 141 { 0x8086, E1000_DEV_ID_82546GB_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 142 { 0x8086, E1000_DEV_ID_82546GB_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 143 { 0x8086, E1000_DEV_ID_82546GB_SERDES, PCI_ANY_ID, PCI_ANY_ID, 0}, 144 { 0x8086, E1000_DEV_ID_82546GB_PCIE, PCI_ANY_ID, PCI_ANY_ID, 0}, 145 { 0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 146 { 0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3, 147 PCI_ANY_ID, PCI_ANY_ID, 0}, 148 149 { 0x8086, E1000_DEV_ID_82547EI, PCI_ANY_ID, PCI_ANY_ID, 0}, 150 { 0x8086, E1000_DEV_ID_82547EI_MOBILE, PCI_ANY_ID, PCI_ANY_ID, 0}, 151 { 0x8086, E1000_DEV_ID_82547GI, PCI_ANY_ID, PCI_ANY_ID, 0}, 152 153 { 0x8086, E1000_DEV_ID_82571EB_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 154 { 0x8086, E1000_DEV_ID_82571EB_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 155 { 0x8086, E1000_DEV_ID_82571EB_SERDES, PCI_ANY_ID, PCI_ANY_ID, 0}, 156 { 0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER, 157 PCI_ANY_ID, PCI_ANY_ID, 0}, 158 { 0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER_LP, 159 PCI_ANY_ID, PCI_ANY_ID, 0}, 160 { 0x8086, E1000_DEV_ID_82571EB_QUAD_FIBER, 161 PCI_ANY_ID, PCI_ANY_ID, 0}, 162 { 0x8086, E1000_DEV_ID_82571PT_QUAD_COPPER, 163 PCI_ANY_ID, PCI_ANY_ID, 0}, 164 { 0x8086, E1000_DEV_ID_82572EI_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 165 { 0x8086, E1000_DEV_ID_82572EI_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0}, 166 { 0x8086, E1000_DEV_ID_82572EI_SERDES, PCI_ANY_ID, PCI_ANY_ID, 0}, 167 { 0x8086, E1000_DEV_ID_82572EI, PCI_ANY_ID, PCI_ANY_ID, 0}, 168 169 { 0x8086, E1000_DEV_ID_82573E, PCI_ANY_ID, PCI_ANY_ID, 0}, 170 { 0x8086, E1000_DEV_ID_82573E_IAMT, PCI_ANY_ID, PCI_ANY_ID, 0}, 171 { 0x8086, E1000_DEV_ID_82573L, PCI_ANY_ID, PCI_ANY_ID, 0}, 172 { 0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_SPT, 173 PCI_ANY_ID, PCI_ANY_ID, 0}, 174 { 0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_SPT, 175 PCI_ANY_ID, PCI_ANY_ID, 0}, 176 { 0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_DPT, 177 PCI_ANY_ID, PCI_ANY_ID, 0}, 178 { 0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_DPT, 179 PCI_ANY_ID, PCI_ANY_ID, 0}, 180 { 0x8086, E1000_DEV_ID_ICH8_IGP_M_AMT, PCI_ANY_ID, PCI_ANY_ID, 0}, 181 { 0x8086, E1000_DEV_ID_ICH8_IGP_AMT, PCI_ANY_ID, PCI_ANY_ID, 0}, 182 { 0x8086, E1000_DEV_ID_ICH8_IGP_C, PCI_ANY_ID, PCI_ANY_ID, 0}, 183 { 0x8086, E1000_DEV_ID_ICH8_IFE, PCI_ANY_ID, PCI_ANY_ID, 0}, 184 { 0x8086, E1000_DEV_ID_ICH8_IFE_GT, PCI_ANY_ID, PCI_ANY_ID, 0}, 185 { 0x8086, E1000_DEV_ID_ICH8_IFE_G, PCI_ANY_ID, PCI_ANY_ID, 0}, 186 { 0x8086, E1000_DEV_ID_ICH8_IGP_M, PCI_ANY_ID, PCI_ANY_ID, 0}, 187 188 { 0x8086, E1000_DEV_ID_ICH9_IGP_AMT, PCI_ANY_ID, PCI_ANY_ID, 0}, 189 { 0x8086, E1000_DEV_ID_ICH9_IGP_C, PCI_ANY_ID, PCI_ANY_ID, 0}, 190 { 0x8086, E1000_DEV_ID_ICH9_IFE, PCI_ANY_ID, PCI_ANY_ID, 0}, 191 { 0x8086, E1000_DEV_ID_ICH9_IFE_GT, PCI_ANY_ID, PCI_ANY_ID, 0}, 192 { 0x8086, E1000_DEV_ID_ICH9_IFE_G, PCI_ANY_ID, PCI_ANY_ID, 0}, 193 194 { 0x8086, E1000_DEV_ID_82575EB_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0}, 195 { 0x8086, E1000_DEV_ID_82575EB_FIBER_SERDES, 196 PCI_ANY_ID, PCI_ANY_ID, 0}, 197 { 0x8086, E1000_DEV_ID_82575GB_QUAD_COPPER, 198 PCI_ANY_ID, PCI_ANY_ID, 0}, 199 /* required last entry */ 200 { 0, 0, 0, 0, 0} 201 }; 202 203 /********************************************************************* 204 * Table of branding strings for all supported NICs. 205 *********************************************************************/ 206 207 static char *em_strings[] = { 208 "Intel(R) PRO/1000 Network Connection" 209 }; 210 211 /********************************************************************* 212 * Function prototypes 213 *********************************************************************/ 214 static int em_probe(device_t); 215 static int em_attach(device_t); 216 static int em_detach(device_t); 217 static int em_shutdown(device_t); 218 static int em_suspend(device_t); 219 static int em_resume(device_t); 220 static void em_start(struct ifnet *); 221 static void em_start_locked(struct ifnet *ifp); 222 static int em_ioctl(struct ifnet *, u_long, caddr_t); 223 static void em_watchdog(struct adapter *); 224 static void em_init(void *); 225 static void em_init_locked(struct adapter *); 226 static void em_stop(void *); 227 static void em_media_status(struct ifnet *, struct ifmediareq *); 228 static int em_media_change(struct ifnet *); 229 static void em_identify_hardware(struct adapter *); 230 static int em_allocate_pci_resources(struct adapter *); 231 static int em_allocate_intr(struct adapter *); 232 static bool em_setup_msix(struct adapter *); 233 static void em_free_intr(struct adapter *); 234 static void em_free_pci_resources(struct adapter *); 235 static void em_local_timer(void *); 236 static int em_hardware_init(struct adapter *); 237 static void em_setup_interface(device_t, struct adapter *); 238 static void em_setup_transmit_structures(struct adapter *); 239 static void em_initialize_transmit_unit(struct adapter *); 240 static int em_setup_receive_structures(struct adapter *); 241 static void em_initialize_receive_unit(struct adapter *); 242 static void em_enable_intr(struct adapter *); 243 static void em_disable_intr(struct adapter *); 244 static void em_free_transmit_structures(struct adapter *); 245 static void em_free_receive_structures(struct adapter *); 246 static void em_update_stats_counters(struct adapter *); 247 static void em_txeof(struct adapter *); 248 static void em_tx_purge(struct adapter *); 249 static int em_allocate_receive_structures(struct adapter *); 250 static int em_allocate_transmit_structures(struct adapter *); 251 static int em_rxeof(struct adapter *, int); 252 #ifndef __NO_STRICT_ALIGNMENT 253 static int em_fixup_rx(struct adapter *); 254 #endif 255 static void em_receive_checksum(struct adapter *, struct e1000_rx_desc *, 256 struct mbuf *); 257 static void em_transmit_checksum_setup(struct adapter *, struct mbuf *, 258 uint32_t *, uint32_t *); 259 static boolean_t em_tx_adv_ctx_setup(struct adapter *, struct mbuf *); 260 #if __FreeBSD_version >= 700000 261 static boolean_t em_tso_setup(struct adapter *, struct mbuf *, uint32_t *, 262 uint32_t *); 263 static boolean_t em_tso_adv_setup(struct adapter *, struct mbuf *, uint32_t *); 264 #endif /* FreeBSD_version >= 700000 */ 265 static void em_set_promisc(struct adapter *); 266 static void em_disable_promisc(struct adapter *); 267 static void em_set_multi(struct adapter *); 268 static void em_print_hw_stats(struct adapter *); 269 static void em_update_link_status(struct adapter *); 270 static int em_get_buf(struct adapter *, int); 271 static void em_enable_hw_vlans(struct adapter *); 272 static int em_encap(struct adapter *, struct mbuf **); 273 static int em_adv_encap(struct adapter *, struct mbuf **); 274 static void em_smartspeed(struct adapter *); 275 static int em_82547_fifo_workaround(struct adapter *, int); 276 static void em_82547_update_fifo_head(struct adapter *, int); 277 static int em_82547_tx_fifo_reset(struct adapter *); 278 static void em_82547_move_tail(void *); 279 static int em_dma_malloc(struct adapter *, bus_size_t, 280 struct em_dma_alloc *, int); 281 static void em_dma_free(struct adapter *, struct em_dma_alloc *); 282 static void em_print_debug_info(struct adapter *); 283 static void em_print_nvm_info(struct adapter *); 284 static int em_is_valid_ether_addr(uint8_t *); 285 static int em_sysctl_stats(SYSCTL_HANDLER_ARGS); 286 static int em_sysctl_debug_info(SYSCTL_HANDLER_ARGS); 287 static uint32_t em_fill_descriptors (bus_addr_t address, uint32_t length, 288 PDESC_ARRAY desc_array); 289 static int em_sysctl_int_delay(SYSCTL_HANDLER_ARGS); 290 static void em_add_int_delay_sysctl(struct adapter *, const char *, 291 const char *, struct em_int_delay_info *, int, int); 292 /* Management and WOL Support */ 293 static void em_init_manageability(struct adapter *); 294 static void em_release_manageability(struct adapter *); 295 static void em_get_hw_control(struct adapter *); 296 static void em_release_hw_control(struct adapter *); 297 static void em_enable_wakeup(device_t); 298 299 #ifndef EM_FAST_IRQ 300 static void em_intr(void *); 301 #else /* FAST IRQ */ 302 #if __FreeBSD_version < 700000 303 static void em_intr_fast(void *); 304 #else 305 static int em_intr_fast(void *); 306 #endif 307 static void em_add_rx_process_limit(struct adapter *, const char *, 308 const char *, int *, int); 309 static void em_handle_rxtx(void *context, int pending); 310 static void em_handle_link(void *context, int pending); 311 #endif /* EM_FAST_IRQ */ 312 313 #ifdef DEVICE_POLLING 314 static poll_handler_t em_poll; 315 #endif /* POLLING */ 316 317 /********************************************************************* 318 * FreeBSD Device Interface Entry Points 319 *********************************************************************/ 320 321 static device_method_t em_methods[] = { 322 /* Device interface */ 323 DEVMETHOD(device_probe, em_probe), 324 DEVMETHOD(device_attach, em_attach), 325 DEVMETHOD(device_detach, em_detach), 326 DEVMETHOD(device_shutdown, em_shutdown), 327 DEVMETHOD(device_suspend, em_suspend), 328 DEVMETHOD(device_resume, em_resume), 329 {0, 0} 330 }; 331 332 static driver_t em_driver = { 333 "em", em_methods, sizeof(struct adapter), 334 }; 335 336 static devclass_t em_devclass; 337 DRIVER_MODULE(em, pci, em_driver, em_devclass, 0, 0); 338 MODULE_DEPEND(em, pci, 1, 1, 1); 339 MODULE_DEPEND(em, ether, 1, 1, 1); 340 341 /********************************************************************* 342 * Tunable default values. 343 *********************************************************************/ 344 345 #define EM_TICKS_TO_USECS(ticks) ((1024 * (ticks) + 500) / 1000) 346 #define EM_USECS_TO_TICKS(usecs) ((1000 * (usecs) + 512) / 1024) 347 #define M_TSO_LEN 66 348 349 /* Allow common code without TSO */ 350 #ifndef CSUM_TSO 351 #define CSUM_TSO 0 352 #endif 353 354 static int em_tx_int_delay_dflt = EM_TICKS_TO_USECS(EM_TIDV); 355 static int em_rx_int_delay_dflt = EM_TICKS_TO_USECS(EM_RDTR); 356 static int em_tx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_TADV); 357 static int em_rx_abs_int_delay_dflt = EM_TICKS_TO_USECS(EM_RADV); 358 static int em_rxd = EM_DEFAULT_RXD; 359 static int em_txd = EM_DEFAULT_TXD; 360 static int em_smart_pwr_down = FALSE; 361 362 TUNABLE_INT("hw.em.tx_int_delay", &em_tx_int_delay_dflt); 363 TUNABLE_INT("hw.em.rx_int_delay", &em_rx_int_delay_dflt); 364 TUNABLE_INT("hw.em.tx_abs_int_delay", &em_tx_abs_int_delay_dflt); 365 TUNABLE_INT("hw.em.rx_abs_int_delay", &em_rx_abs_int_delay_dflt); 366 TUNABLE_INT("hw.em.rxd", &em_rxd); 367 TUNABLE_INT("hw.em.txd", &em_txd); 368 TUNABLE_INT("hw.em.smart_pwr_down", &em_smart_pwr_down); 369 #ifdef EM_FAST_IRQ 370 /* How many packets rxeof tries to clean at a time */ 371 static int em_rx_process_limit = 100; 372 TUNABLE_INT("hw.em.rx_process_limit", &em_rx_process_limit); 373 #endif 374 /* Global used in WOL setup with multiport cards */ 375 static int global_quad_port_a = 0; 376 377 /********************************************************************* 378 * Device identification routine 379 * 380 * em_probe determines if the driver should be loaded on 381 * adapter based on PCI vendor/device id of the adapter. 382 * 383 * return BUS_PROBE_DEFAULT on success, positive on failure 384 *********************************************************************/ 385 386 static int 387 em_probe(device_t dev) 388 { 389 char adapter_name[60]; 390 uint16_t pci_vendor_id = 0; 391 uint16_t pci_device_id = 0; 392 uint16_t pci_subvendor_id = 0; 393 uint16_t pci_subdevice_id = 0; 394 em_vendor_info_t *ent; 395 396 INIT_DEBUGOUT("em_probe: begin"); 397 398 pci_vendor_id = pci_get_vendor(dev); 399 if (pci_vendor_id != EM_VENDOR_ID) 400 return (ENXIO); 401 402 pci_device_id = pci_get_device(dev); 403 pci_subvendor_id = pci_get_subvendor(dev); 404 pci_subdevice_id = pci_get_subdevice(dev); 405 406 ent = em_vendor_info_array; 407 while (ent->vendor_id != 0) { 408 if ((pci_vendor_id == ent->vendor_id) && 409 (pci_device_id == ent->device_id) && 410 411 ((pci_subvendor_id == ent->subvendor_id) || 412 (ent->subvendor_id == PCI_ANY_ID)) && 413 414 ((pci_subdevice_id == ent->subdevice_id) || 415 (ent->subdevice_id == PCI_ANY_ID))) { 416 sprintf(adapter_name, "%s %s", 417 em_strings[ent->index], 418 em_driver_version); 419 device_set_desc_copy(dev, adapter_name); 420 return (BUS_PROBE_DEFAULT); 421 } 422 ent++; 423 } 424 425 return (ENXIO); 426 } 427 428 /********************************************************************* 429 * Device initialization routine 430 * 431 * The attach entry point is called when the driver is being loaded. 432 * This routine identifies the type of hardware, allocates all resources 433 * and initializes the hardware. 434 * 435 * return 0 on success, positive on failure 436 *********************************************************************/ 437 438 static int 439 em_attach(device_t dev) 440 { 441 struct adapter *adapter; 442 int tsize, rsize; 443 int error = 0; 444 u16 eeprom_data, device_id; 445 446 INIT_DEBUGOUT("em_attach: begin"); 447 448 adapter = device_get_softc(dev); 449 adapter->dev = adapter->osdep.dev = dev; 450 EM_CORE_LOCK_INIT(adapter, device_get_nameunit(dev)); 451 EM_TX_LOCK_INIT(adapter, device_get_nameunit(dev)); 452 453 /* SYSCTL stuff */ 454 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 455 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 456 OID_AUTO, "debug", CTLTYPE_INT|CTLFLAG_RW, adapter, 0, 457 em_sysctl_debug_info, "I", "Debug Information"); 458 459 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 460 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 461 OID_AUTO, "stats", CTLTYPE_INT|CTLFLAG_RW, adapter, 0, 462 em_sysctl_stats, "I", "Statistics"); 463 464 callout_init_mtx(&adapter->timer, &adapter->core_mtx, 0); 465 callout_init_mtx(&adapter->tx_fifo_timer, &adapter->tx_mtx, 0); 466 467 /* Determine hardware and mac info */ 468 em_identify_hardware(adapter); 469 470 /* Setup PCI resources */ 471 if (em_allocate_pci_resources(adapter)) { 472 device_printf(dev, "Allocation of PCI resources failed\n"); 473 error = ENXIO; 474 goto err_pci; 475 } 476 477 /* 478 ** For ICH8 and family we need to 479 ** map the flash memory, and this 480 ** must happen after the MAC is 481 ** identified 482 */ 483 if ((adapter->hw.mac.type == e1000_ich8lan) || 484 (adapter->hw.mac.type == e1000_ich9lan)) { 485 int rid = EM_BAR_TYPE_FLASH; 486 adapter->flash_mem = bus_alloc_resource_any(dev, 487 SYS_RES_MEMORY, &rid, RF_ACTIVE); 488 /* This is used in the shared code */ 489 adapter->hw.flash_address = (u8 *)adapter->flash_mem; 490 adapter->osdep.flash_bus_space_tag = 491 rman_get_bustag(adapter->flash_mem); 492 adapter->osdep.flash_bus_space_handle = 493 rman_get_bushandle(adapter->flash_mem); 494 } 495 496 /* Do Shared Code initialization */ 497 if (e1000_setup_init_funcs(&adapter->hw, TRUE)) { 498 device_printf(dev, "Setup of Shared code failed\n"); 499 error = ENXIO; 500 goto err_pci; 501 } 502 503 e1000_get_bus_info(&adapter->hw); 504 505 /* Set up some sysctls for the tunable interrupt delays */ 506 em_add_int_delay_sysctl(adapter, "rx_int_delay", 507 "receive interrupt delay in usecs", &adapter->rx_int_delay, 508 E1000_REGISTER(&adapter->hw, E1000_RDTR), em_rx_int_delay_dflt); 509 em_add_int_delay_sysctl(adapter, "tx_int_delay", 510 "transmit interrupt delay in usecs", &adapter->tx_int_delay, 511 E1000_REGISTER(&adapter->hw, E1000_TIDV), em_tx_int_delay_dflt); 512 if (adapter->hw.mac.type >= e1000_82540) { 513 em_add_int_delay_sysctl(adapter, "rx_abs_int_delay", 514 "receive interrupt delay limit in usecs", 515 &adapter->rx_abs_int_delay, 516 E1000_REGISTER(&adapter->hw, E1000_RADV), 517 em_rx_abs_int_delay_dflt); 518 em_add_int_delay_sysctl(adapter, "tx_abs_int_delay", 519 "transmit interrupt delay limit in usecs", 520 &adapter->tx_abs_int_delay, 521 E1000_REGISTER(&adapter->hw, E1000_TADV), 522 em_tx_abs_int_delay_dflt); 523 } 524 525 #ifdef EM_FAST_IRQ 526 /* Sysctls for limiting the amount of work done in the taskqueue */ 527 em_add_rx_process_limit(adapter, "rx_processing_limit", 528 "max number of rx packets to process", &adapter->rx_process_limit, 529 em_rx_process_limit); 530 #endif 531 532 /* 533 * Validate number of transmit and receive descriptors. It 534 * must not exceed hardware maximum, and must be multiple 535 * of E1000_DBA_ALIGN. 536 */ 537 if (((em_txd * sizeof(struct e1000_tx_desc)) % EM_DBA_ALIGN) != 0 || 538 (adapter->hw.mac.type >= e1000_82544 && em_txd > EM_MAX_TXD) || 539 (adapter->hw.mac.type < e1000_82544 && em_txd > EM_MAX_TXD_82543) || 540 (em_txd < EM_MIN_TXD)) { 541 device_printf(dev, "Using %d TX descriptors instead of %d!\n", 542 EM_DEFAULT_TXD, em_txd); 543 adapter->num_tx_desc = EM_DEFAULT_TXD; 544 } else 545 adapter->num_tx_desc = em_txd; 546 if (((em_rxd * sizeof(struct e1000_rx_desc)) % EM_DBA_ALIGN) != 0 || 547 (adapter->hw.mac.type >= e1000_82544 && em_rxd > EM_MAX_RXD) || 548 (adapter->hw.mac.type < e1000_82544 && em_rxd > EM_MAX_RXD_82543) || 549 (em_rxd < EM_MIN_RXD)) { 550 device_printf(dev, "Using %d RX descriptors instead of %d!\n", 551 EM_DEFAULT_RXD, em_rxd); 552 adapter->num_rx_desc = EM_DEFAULT_RXD; 553 } else 554 adapter->num_rx_desc = em_rxd; 555 556 adapter->hw.mac.autoneg = DO_AUTO_NEG; 557 adapter->hw.phy.autoneg_wait_to_complete = FALSE; 558 adapter->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 559 adapter->rx_buffer_len = 2048; 560 561 e1000_init_script_state_82541(&adapter->hw, TRUE); 562 e1000_set_tbi_compatibility_82543(&adapter->hw, TRUE); 563 564 /* Copper options */ 565 if (adapter->hw.phy.media_type == e1000_media_type_copper) { 566 adapter->hw.phy.mdix = AUTO_ALL_MODES; 567 adapter->hw.phy.disable_polarity_correction = FALSE; 568 adapter->hw.phy.ms_type = EM_MASTER_SLAVE; 569 } 570 571 /* 572 * Set the frame limits assuming 573 * standard ethernet sized frames. 574 */ 575 adapter->max_frame_size = ETHERMTU + ETHER_HDR_LEN + ETHERNET_FCS_SIZE; 576 adapter->min_frame_size = ETH_ZLEN + ETHERNET_FCS_SIZE; 577 578 /* 579 * This controls when hardware reports transmit completion 580 * status. 581 */ 582 adapter->hw.mac.report_tx_early = 1; 583 584 tsize = roundup2(adapter->num_tx_desc * sizeof(struct e1000_tx_desc), 585 EM_DBA_ALIGN); 586 587 /* Allocate Transmit Descriptor ring */ 588 if (em_dma_malloc(adapter, tsize, &adapter->txdma, BUS_DMA_NOWAIT)) { 589 device_printf(dev, "Unable to allocate tx_desc memory\n"); 590 error = ENOMEM; 591 goto err_tx_desc; 592 } 593 adapter->tx_desc_base = 594 (struct e1000_tx_desc *)adapter->txdma.dma_vaddr; 595 596 rsize = roundup2(adapter->num_rx_desc * sizeof(struct e1000_rx_desc), 597 EM_DBA_ALIGN); 598 599 /* Allocate Receive Descriptor ring */ 600 if (em_dma_malloc(adapter, rsize, &adapter->rxdma, BUS_DMA_NOWAIT)) { 601 device_printf(dev, "Unable to allocate rx_desc memory\n"); 602 error = ENOMEM; 603 goto err_rx_desc; 604 } 605 adapter->rx_desc_base = 606 (struct e1000_rx_desc *)adapter->rxdma.dma_vaddr; 607 608 /* Make sure we have a good EEPROM before we read from it */ 609 if (e1000_validate_nvm_checksum(&adapter->hw) < 0) { 610 /* 611 ** Some PCI-E parts fail the first check due to 612 ** the link being in sleep state, call it again, 613 ** if it fails a second time its a real issue. 614 */ 615 if (e1000_validate_nvm_checksum(&adapter->hw) < 0) { 616 device_printf(dev, 617 "The EEPROM Checksum Is Not Valid\n"); 618 error = EIO; 619 goto err_hw_init; 620 } 621 } 622 623 /* Initialize the hardware */ 624 if (em_hardware_init(adapter)) { 625 device_printf(dev, "Unable to initialize the hardware\n"); 626 error = EIO; 627 goto err_hw_init; 628 } 629 630 /* Copy the permanent MAC address out of the EEPROM */ 631 if (e1000_read_mac_addr(&adapter->hw) < 0) { 632 device_printf(dev, "EEPROM read error while reading MAC" 633 " address\n"); 634 error = EIO; 635 goto err_hw_init; 636 } 637 638 if (!em_is_valid_ether_addr(adapter->hw.mac.addr)) { 639 device_printf(dev, "Invalid MAC address\n"); 640 error = EIO; 641 goto err_hw_init; 642 } 643 644 /* Allocate transmit descriptors and buffers */ 645 if (em_allocate_transmit_structures(adapter)) { 646 device_printf(dev, "Could not setup transmit structures\n"); 647 error = ENOMEM; 648 goto err_tx_struct; 649 } 650 651 /* Allocate receive descriptors and buffers */ 652 if (em_allocate_receive_structures(adapter)) { 653 device_printf(dev, "Could not setup receive structures\n"); 654 error = ENOMEM; 655 goto err_rx_struct; 656 } 657 658 /* Setup OS specific network interface */ 659 em_setup_interface(dev, adapter); 660 661 em_allocate_intr(adapter); 662 663 /* Initialize statistics */ 664 em_update_stats_counters(adapter); 665 666 adapter->hw.mac.get_link_status = 1; 667 em_update_link_status(adapter); 668 669 /* Indicate SOL/IDER usage */ 670 if (e1000_check_reset_block(&adapter->hw)) 671 device_printf(dev, 672 "PHY reset is blocked due to SOL/IDER session.\n"); 673 674 /* Determine if we have to control management hardware */ 675 adapter->has_manage = e1000_enable_mng_pass_thru(&adapter->hw); 676 677 /* 678 * Setup Wake-on-Lan 679 */ 680 switch (adapter->hw.mac.type) { 681 682 case e1000_82542: 683 case e1000_82543: 684 break; 685 case e1000_82546: 686 case e1000_82546_rev_3: 687 case e1000_82571: 688 case e1000_80003es2lan: 689 if (adapter->hw.bus.func == 1) 690 e1000_read_nvm(&adapter->hw, 691 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 692 else 693 e1000_read_nvm(&adapter->hw, 694 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 695 eeprom_data &= EM_EEPROM_APME; 696 break; 697 default: 698 /* APME bit in EEPROM is mapped to WUC.APME */ 699 eeprom_data = E1000_READ_REG(&adapter->hw, E1000_WUC) & 700 E1000_WUC_APME; 701 break; 702 } 703 if (eeprom_data) 704 adapter->wol = E1000_WUFC_MAG; 705 /* 706 * We have the eeprom settings, now apply the special cases 707 * where the eeprom may be wrong or the board won't support 708 * wake on lan on a particular port 709 */ 710 device_id = pci_get_device(dev); 711 switch (device_id) { 712 case E1000_DEV_ID_82546GB_PCIE: 713 adapter->wol = 0; 714 break; 715 case E1000_DEV_ID_82546EB_FIBER: 716 case E1000_DEV_ID_82546GB_FIBER: 717 case E1000_DEV_ID_82571EB_FIBER: 718 /* Wake events only supported on port A for dual fiber 719 * regardless of eeprom setting */ 720 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) & 721 E1000_STATUS_FUNC_1) 722 adapter->wol = 0; 723 break; 724 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: 725 case E1000_DEV_ID_82571EB_QUAD_COPPER: 726 case E1000_DEV_ID_82571EB_QUAD_FIBER: 727 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP: 728 /* if quad port adapter, disable WoL on all but port A */ 729 if (global_quad_port_a != 0) 730 adapter->wol = 0; 731 /* Reset for multiple quad port adapters */ 732 if (++global_quad_port_a == 4) 733 global_quad_port_a = 0; 734 break; 735 } 736 737 /* Do we need workaround for 82544 PCI-X adapter? */ 738 if (adapter->hw.bus.type == e1000_bus_type_pcix && 739 adapter->hw.mac.type == e1000_82544) 740 adapter->pcix_82544 = TRUE; 741 else 742 adapter->pcix_82544 = FALSE; 743 744 /* Tell the stack that the interface is not active */ 745 adapter->ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 746 747 INIT_DEBUGOUT("em_attach: end"); 748 749 return (0); 750 751 err_rx_struct: 752 em_free_transmit_structures(adapter); 753 err_tx_struct: 754 err_hw_init: 755 em_release_hw_control(adapter); 756 e1000_remove_device(&adapter->hw); 757 em_dma_free(adapter, &adapter->rxdma); 758 err_rx_desc: 759 em_dma_free(adapter, &adapter->txdma); 760 err_tx_desc: 761 err_pci: 762 em_free_intr(adapter); 763 em_free_pci_resources(adapter); 764 EM_TX_LOCK_DESTROY(adapter); 765 EM_CORE_LOCK_DESTROY(adapter); 766 767 return (error); 768 } 769 770 /********************************************************************* 771 * Device removal routine 772 * 773 * The detach entry point is called when the driver is being removed. 774 * This routine stops the adapter and deallocates all the resources 775 * that were allocated for driver operation. 776 * 777 * return 0 on success, positive on failure 778 *********************************************************************/ 779 780 static int 781 em_detach(device_t dev) 782 { 783 struct adapter *adapter = device_get_softc(dev); 784 struct ifnet *ifp = adapter->ifp; 785 786 INIT_DEBUGOUT("em_detach: begin"); 787 788 /* Make sure VLANS are not using driver */ 789 #if __FreeBSD_version >= 700000 790 if (adapter->ifp->if_vlantrunk != NULL) { 791 #else 792 if (adapter->ifp->if_nvlans != 0) { 793 #endif 794 device_printf(dev,"Vlan in use, detach first\n"); 795 return (EBUSY); 796 } 797 798 #ifdef DEVICE_POLLING 799 if (ifp->if_capenable & IFCAP_POLLING) 800 ether_poll_deregister(ifp); 801 #endif 802 803 em_disable_intr(adapter); 804 em_free_intr(adapter); 805 EM_CORE_LOCK(adapter); 806 EM_TX_LOCK(adapter); 807 adapter->in_detach = 1; 808 em_stop(adapter); 809 e1000_phy_hw_reset(&adapter->hw); 810 811 em_release_manageability(adapter); 812 813 if (((adapter->hw.mac.type == e1000_82573) || 814 (adapter->hw.mac.type == e1000_ich8lan) || 815 (adapter->hw.mac.type == e1000_ich9lan)) && 816 e1000_check_mng_mode(&adapter->hw)) 817 em_release_hw_control(adapter); 818 819 if (adapter->wol) { 820 E1000_WRITE_REG(&adapter->hw, E1000_WUC, E1000_WUC_PME_EN); 821 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, adapter->wol); 822 em_enable_wakeup(dev); 823 } 824 825 ether_ifdetach(adapter->ifp); 826 827 callout_drain(&adapter->timer); 828 callout_drain(&adapter->tx_fifo_timer); 829 830 em_free_pci_resources(adapter); 831 bus_generic_detach(dev); 832 if_free(ifp); 833 834 e1000_remove_device(&adapter->hw); 835 em_free_transmit_structures(adapter); 836 em_free_receive_structures(adapter); 837 EM_TX_UNLOCK(adapter); 838 EM_CORE_UNLOCK(adapter); 839 840 /* Free Transmit Descriptor ring */ 841 if (adapter->tx_desc_base) { 842 em_dma_free(adapter, &adapter->txdma); 843 adapter->tx_desc_base = NULL; 844 } 845 846 /* Free Receive Descriptor ring */ 847 if (adapter->rx_desc_base) { 848 em_dma_free(adapter, &adapter->rxdma); 849 adapter->rx_desc_base = NULL; 850 } 851 852 EM_TX_LOCK_DESTROY(adapter); 853 EM_CORE_LOCK_DESTROY(adapter); 854 855 return (0); 856 } 857 858 /********************************************************************* 859 * 860 * Shutdown entry point 861 * 862 **********************************************************************/ 863 864 static int 865 em_shutdown(device_t dev) 866 { 867 return em_suspend(dev); 868 } 869 870 /* 871 * Suspend/resume device methods. 872 */ 873 static int 874 em_suspend(device_t dev) 875 { 876 struct adapter *adapter = device_get_softc(dev); 877 878 EM_CORE_LOCK(adapter); 879 880 EM_TX_LOCK(adapter); 881 em_stop(adapter); 882 EM_TX_UNLOCK(adapter); 883 884 em_release_manageability(adapter); 885 886 if (((adapter->hw.mac.type == e1000_82573) || 887 (adapter->hw.mac.type == e1000_ich8lan) || 888 (adapter->hw.mac.type == e1000_ich9lan)) && 889 e1000_check_mng_mode(&adapter->hw)) 890 em_release_hw_control(adapter); 891 892 if (adapter->wol) { 893 E1000_WRITE_REG(&adapter->hw, E1000_WUC, E1000_WUC_PME_EN); 894 E1000_WRITE_REG(&adapter->hw, E1000_WUFC, adapter->wol); 895 em_enable_wakeup(dev); 896 } 897 898 EM_CORE_UNLOCK(adapter); 899 900 return bus_generic_suspend(dev); 901 } 902 903 static int 904 em_resume(device_t dev) 905 { 906 struct adapter *adapter = device_get_softc(dev); 907 struct ifnet *ifp = adapter->ifp; 908 909 EM_CORE_LOCK(adapter); 910 em_init_locked(adapter); 911 em_init_manageability(adapter); 912 913 if ((ifp->if_flags & IFF_UP) && 914 (ifp->if_drv_flags & IFF_DRV_RUNNING)) 915 em_start_locked(ifp); 916 917 EM_CORE_UNLOCK(adapter); 918 919 return bus_generic_resume(dev); 920 } 921 922 923 /********************************************************************* 924 * Transmit entry point 925 * 926 * em_start is called by the stack to initiate a transmit. 927 * The driver will remain in this routine as long as there are 928 * packets to transmit and transmit resources are available. 929 * In case resources are not available stack is notified and 930 * the packet is requeued. 931 **********************************************************************/ 932 933 static void 934 em_start_locked(struct ifnet *ifp) 935 { 936 struct adapter *adapter = ifp->if_softc; 937 struct mbuf *m_head; 938 939 EM_TX_LOCK_ASSERT(adapter); 940 941 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING|IFF_DRV_OACTIVE)) != 942 IFF_DRV_RUNNING) 943 return; 944 if (!adapter->link_active) 945 return; 946 947 while (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 948 949 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 950 if (m_head == NULL) 951 break; 952 /* 953 * Encapsulation can modify our pointer, and or make it 954 * NULL on failure. In that event, we can't requeue. 955 * 956 * We now use a pointer to accomodate legacy and 957 * advanced transmit functions. 958 */ 959 if (adapter->em_xmit(adapter, &m_head)) { 960 if (m_head == NULL) 961 break; 962 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 963 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 964 break; 965 } 966 967 /* Send a copy of the frame to the BPF listener */ 968 ETHER_BPF_MTAP(ifp, m_head); 969 970 /* Set timeout in case hardware has problems transmitting. */ 971 adapter->watchdog_timer = EM_TX_TIMEOUT; 972 } 973 } 974 975 static void 976 em_start(struct ifnet *ifp) 977 { 978 struct adapter *adapter = ifp->if_softc; 979 980 EM_TX_LOCK(adapter); 981 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 982 em_start_locked(ifp); 983 EM_TX_UNLOCK(adapter); 984 } 985 986 /********************************************************************* 987 * Ioctl entry point 988 * 989 * em_ioctl is called when the user wants to configure the 990 * interface. 991 * 992 * return 0 on success, positive on failure 993 **********************************************************************/ 994 995 static int 996 em_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 997 { 998 struct adapter *adapter = ifp->if_softc; 999 struct ifreq *ifr = (struct ifreq *)data; 1000 struct ifaddr *ifa = (struct ifaddr *)data; 1001 int error = 0; 1002 1003 if (adapter->in_detach) 1004 return (error); 1005 1006 switch (command) { 1007 case SIOCSIFADDR: 1008 if (ifa->ifa_addr->sa_family == AF_INET) { 1009 /* 1010 * XXX 1011 * Since resetting hardware takes a very long time 1012 * and results in link renegotiation we only 1013 * initialize the hardware only when it is absolutely 1014 * required. 1015 */ 1016 ifp->if_flags |= IFF_UP; 1017 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 1018 EM_CORE_LOCK(adapter); 1019 em_init_locked(adapter); 1020 EM_CORE_UNLOCK(adapter); 1021 } 1022 arp_ifinit(ifp, ifa); 1023 } else 1024 error = ether_ioctl(ifp, command, data); 1025 break; 1026 case SIOCSIFMTU: 1027 { 1028 int max_frame_size; 1029 uint16_t eeprom_data = 0; 1030 1031 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFMTU (Set Interface MTU)"); 1032 1033 EM_CORE_LOCK(adapter); 1034 switch (adapter->hw.mac.type) { 1035 case e1000_82573: 1036 /* 1037 * 82573 only supports jumbo frames 1038 * if ASPM is disabled. 1039 */ 1040 e1000_read_nvm(&adapter->hw, 1041 NVM_INIT_3GIO_3, 1, &eeprom_data); 1042 if (eeprom_data & NVM_WORD1A_ASPM_MASK) { 1043 max_frame_size = ETHER_MAX_LEN; 1044 break; 1045 } 1046 /* Allow Jumbo frames - fall thru */ 1047 case e1000_82571: 1048 case e1000_82572: 1049 case e1000_ich9lan: 1050 case e1000_82575: 1051 case e1000_80003es2lan: /* Limit Jumbo Frame size */ 1052 max_frame_size = 9234; 1053 break; 1054 /* Adapters that do not support jumbo frames */ 1055 case e1000_82542: 1056 case e1000_ich8lan: 1057 max_frame_size = ETHER_MAX_LEN; 1058 break; 1059 default: 1060 max_frame_size = MAX_JUMBO_FRAME_SIZE; 1061 } 1062 if (ifr->ifr_mtu > max_frame_size - ETHER_HDR_LEN - 1063 ETHER_CRC_LEN) { 1064 EM_CORE_UNLOCK(adapter); 1065 error = EINVAL; 1066 break; 1067 } 1068 1069 ifp->if_mtu = ifr->ifr_mtu; 1070 adapter->max_frame_size = 1071 ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; 1072 em_init_locked(adapter); 1073 EM_CORE_UNLOCK(adapter); 1074 break; 1075 } 1076 case SIOCSIFFLAGS: 1077 IOCTL_DEBUGOUT("ioctl rcv'd:\ 1078 SIOCSIFFLAGS (Set Interface Flags)"); 1079 EM_CORE_LOCK(adapter); 1080 if (ifp->if_flags & IFF_UP) { 1081 if ((ifp->if_drv_flags & IFF_DRV_RUNNING)) { 1082 if ((ifp->if_flags ^ adapter->if_flags) & 1083 IFF_PROMISC) { 1084 em_disable_promisc(adapter); 1085 em_set_promisc(adapter); 1086 } 1087 } else 1088 em_init_locked(adapter); 1089 } else 1090 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1091 EM_TX_LOCK(adapter); 1092 em_stop(adapter); 1093 EM_TX_UNLOCK(adapter); 1094 } 1095 adapter->if_flags = ifp->if_flags; 1096 EM_CORE_UNLOCK(adapter); 1097 break; 1098 case SIOCADDMULTI: 1099 case SIOCDELMULTI: 1100 IOCTL_DEBUGOUT("ioctl rcv'd: SIOC(ADD|DEL)MULTI"); 1101 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1102 EM_CORE_LOCK(adapter); 1103 em_disable_intr(adapter); 1104 em_set_multi(adapter); 1105 if (adapter->hw.mac.type == e1000_82542 && 1106 adapter->hw.revision_id == E1000_REVISION_2) { 1107 em_initialize_receive_unit(adapter); 1108 } 1109 #ifdef DEVICE_POLLING 1110 if (!(ifp->if_capenable & IFCAP_POLLING)) 1111 #endif 1112 em_enable_intr(adapter); 1113 EM_CORE_UNLOCK(adapter); 1114 } 1115 break; 1116 case SIOCSIFMEDIA: 1117 /* Check SOL/IDER usage */ 1118 EM_CORE_LOCK(adapter); 1119 if (e1000_check_reset_block(&adapter->hw)) { 1120 EM_CORE_UNLOCK(adapter); 1121 device_printf(adapter->dev, "Media change is" 1122 " blocked due to SOL/IDER session.\n"); 1123 break; 1124 } 1125 EM_CORE_UNLOCK(adapter); 1126 case SIOCGIFMEDIA: 1127 IOCTL_DEBUGOUT("ioctl rcv'd: \ 1128 SIOCxIFMEDIA (Get/Set Interface Media)"); 1129 error = ifmedia_ioctl(ifp, ifr, &adapter->media, command); 1130 break; 1131 case SIOCSIFCAP: 1132 { 1133 int mask, reinit; 1134 1135 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFCAP (Set Capabilities)"); 1136 reinit = 0; 1137 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1138 #ifdef DEVICE_POLLING 1139 if (mask & IFCAP_POLLING) { 1140 if (ifr->ifr_reqcap & IFCAP_POLLING) { 1141 error = ether_poll_register(em_poll, ifp); 1142 if (error) 1143 return (error); 1144 EM_CORE_LOCK(adapter); 1145 em_disable_intr(adapter); 1146 ifp->if_capenable |= IFCAP_POLLING; 1147 EM_CORE_UNLOCK(adapter); 1148 } else { 1149 error = ether_poll_deregister(ifp); 1150 /* Enable interrupt even in error case */ 1151 EM_CORE_LOCK(adapter); 1152 em_enable_intr(adapter); 1153 ifp->if_capenable &= ~IFCAP_POLLING; 1154 EM_CORE_UNLOCK(adapter); 1155 } 1156 } 1157 #endif 1158 if (mask & IFCAP_HWCSUM) { 1159 ifp->if_capenable ^= IFCAP_HWCSUM; 1160 reinit = 1; 1161 } 1162 #if __FreeBSD_version >= 700000 1163 if (mask & IFCAP_TSO4) { 1164 ifp->if_capenable ^= IFCAP_TSO4; 1165 reinit = 1; 1166 } 1167 #endif 1168 if (mask & IFCAP_VLAN_HWTAGGING) { 1169 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 1170 reinit = 1; 1171 } 1172 if (reinit && (ifp->if_drv_flags & IFF_DRV_RUNNING)) 1173 em_init(adapter); 1174 #if __FreeBSD_version >= 700000 1175 VLAN_CAPABILITIES(ifp); 1176 #endif 1177 break; 1178 } 1179 default: 1180 error = ether_ioctl(ifp, command, data); 1181 break; 1182 } 1183 1184 return (error); 1185 } 1186 1187 /********************************************************************* 1188 * Watchdog timer: 1189 * 1190 * This routine is called from the local timer every second. 1191 * As long as transmit descriptors are being cleaned the value 1192 * is non-zero and we do nothing. Reaching 0 indicates a tx hang 1193 * and we then reset the device. 1194 * 1195 **********************************************************************/ 1196 1197 static void 1198 em_watchdog(struct adapter *adapter) 1199 { 1200 1201 EM_CORE_LOCK_ASSERT(adapter); 1202 1203 /* 1204 ** The timer is set to 5 every time start queues a packet. 1205 ** Then txeof keeps resetting it as long as it cleans at 1206 ** least one descriptor. 1207 ** Finally, anytime all descriptors are clean the timer is 1208 ** set to 0. 1209 */ 1210 if ((adapter->watchdog_timer == 0) || (--adapter->watchdog_timer)) 1211 return; 1212 1213 /* If we are in this routine because of pause frames, then 1214 * don't reset the hardware. 1215 */ 1216 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) & 1217 E1000_STATUS_TXOFF) { 1218 adapter->watchdog_timer = EM_TX_TIMEOUT; 1219 return; 1220 } 1221 1222 if (e1000_check_for_link(&adapter->hw) == 0) 1223 device_printf(adapter->dev, "watchdog timeout -- resetting\n"); 1224 adapter->ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1225 adapter->watchdog_events++; 1226 1227 em_init_locked(adapter); 1228 } 1229 1230 /********************************************************************* 1231 * Init entry point 1232 * 1233 * This routine is used in two ways. It is used by the stack as 1234 * init entry point in network interface structure. It is also used 1235 * by the driver as a hw/sw initialization routine to get to a 1236 * consistent state. 1237 * 1238 * return 0 on success, positive on failure 1239 **********************************************************************/ 1240 1241 static void 1242 em_init_locked(struct adapter *adapter) 1243 { 1244 struct ifnet *ifp = adapter->ifp; 1245 device_t dev = adapter->dev; 1246 uint32_t pba; 1247 1248 INIT_DEBUGOUT("em_init: begin"); 1249 1250 EM_CORE_LOCK_ASSERT(adapter); 1251 1252 EM_TX_LOCK(adapter); 1253 em_stop(adapter); 1254 EM_TX_UNLOCK(adapter); 1255 1256 /* 1257 * Packet Buffer Allocation (PBA) 1258 * Writing PBA sets the receive portion of the buffer 1259 * the remainder is used for the transmit buffer. 1260 * 1261 * Devices before the 82547 had a Packet Buffer of 64K. 1262 * Default allocation: PBA=48K for Rx, leaving 16K for Tx. 1263 * After the 82547 the buffer was reduced to 40K. 1264 * Default allocation: PBA=30K for Rx, leaving 10K for Tx. 1265 * Note: default does not leave enough room for Jumbo Frame >10k. 1266 */ 1267 switch (adapter->hw.mac.type) { 1268 case e1000_82547: 1269 case e1000_82547_rev_2: /* 82547: Total Packet Buffer is 40K */ 1270 if (adapter->max_frame_size > 8192) 1271 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */ 1272 else 1273 pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */ 1274 adapter->tx_fifo_head = 0; 1275 adapter->tx_head_addr = pba << EM_TX_HEAD_ADDR_SHIFT; 1276 adapter->tx_fifo_size = 1277 (E1000_PBA_40K - pba) << EM_PBA_BYTES_SHIFT; 1278 break; 1279 /* Total Packet Buffer on these is 48K */ 1280 case e1000_82571: 1281 case e1000_82572: 1282 case e1000_82575: 1283 case e1000_80003es2lan: 1284 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */ 1285 break; 1286 case e1000_82573: /* 82573: Total Packet Buffer is 32K */ 1287 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */ 1288 break; 1289 case e1000_ich9lan: 1290 #define E1000_PBA_10K 0x000A 1291 pba = E1000_PBA_10K; 1292 break; 1293 case e1000_ich8lan: 1294 pba = E1000_PBA_8K; 1295 break; 1296 default: 1297 /* Devices before 82547 had a Packet Buffer of 64K. */ 1298 if (adapter->max_frame_size > 8192) 1299 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 1300 else 1301 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 1302 } 1303 1304 INIT_DEBUGOUT1("em_init: pba=%dK",pba); 1305 E1000_WRITE_REG(&adapter->hw, E1000_PBA, pba); 1306 1307 /* Get the latest mac address, User can use a LAA */ 1308 bcopy(IF_LLADDR(adapter->ifp), adapter->hw.mac.addr, 1309 ETHER_ADDR_LEN); 1310 1311 /* Put the address into the Receive Address Array */ 1312 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 0); 1313 1314 /* 1315 * With the 82571 adapter, RAR[0] may be overwritten 1316 * when the other port is reset, we make a duplicate 1317 * in RAR[14] for that eventuality, this assures 1318 * the interface continues to function. 1319 */ 1320 if (adapter->hw.mac.type == e1000_82571) { 1321 e1000_set_laa_state_82571(&adapter->hw, TRUE); 1322 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 1323 E1000_RAR_ENTRIES - 1); 1324 } 1325 1326 /* Initialize the hardware */ 1327 if (em_hardware_init(adapter)) { 1328 device_printf(dev, "Unable to initialize the hardware\n"); 1329 return; 1330 } 1331 em_update_link_status(adapter); 1332 1333 /* Setup VLAN support, basic and offload if available */ 1334 E1000_WRITE_REG(&adapter->hw, E1000_VET, ETHERTYPE_VLAN); 1335 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) 1336 em_enable_hw_vlans(adapter); 1337 1338 /* Set hardware offload abilities */ 1339 ifp->if_hwassist = 0; 1340 if (adapter->hw.mac.type >= e1000_82543) { 1341 if (ifp->if_capenable & IFCAP_TXCSUM) 1342 ifp->if_hwassist |= (CSUM_TCP | CSUM_UDP); 1343 #if __FreeBSD_version >= 700000 1344 if (ifp->if_capenable & IFCAP_TSO4) 1345 ifp->if_hwassist |= CSUM_TSO; 1346 #endif 1347 } 1348 1349 /* Configure for OS presence */ 1350 em_init_manageability(adapter); 1351 1352 /* Prepare transmit descriptors and buffers */ 1353 em_setup_transmit_structures(adapter); 1354 em_initialize_transmit_unit(adapter); 1355 1356 /* Setup Multicast table */ 1357 em_set_multi(adapter); 1358 1359 /* Prepare receive descriptors and buffers */ 1360 if (em_setup_receive_structures(adapter)) { 1361 device_printf(dev, "Could not setup receive structures\n"); 1362 EM_TX_LOCK(adapter); 1363 em_stop(adapter); 1364 EM_TX_UNLOCK(adapter); 1365 return; 1366 } 1367 em_initialize_receive_unit(adapter); 1368 1369 /* Don't lose promiscuous settings */ 1370 em_set_promisc(adapter); 1371 1372 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1373 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1374 1375 callout_reset(&adapter->timer, hz, em_local_timer, adapter); 1376 e1000_clear_hw_cntrs_base_generic(&adapter->hw); 1377 1378 #ifdef DEVICE_POLLING 1379 /* 1380 * Only enable interrupts if we are not polling, make sure 1381 * they are off otherwise. 1382 */ 1383 if (ifp->if_capenable & IFCAP_POLLING) 1384 em_disable_intr(adapter); 1385 else 1386 #endif /* DEVICE_POLLING */ 1387 em_enable_intr(adapter); 1388 1389 /* Don't reset the phy next time init gets called */ 1390 adapter->hw.phy.reset_disable = TRUE; 1391 } 1392 1393 static void 1394 em_init(void *arg) 1395 { 1396 struct adapter *adapter = arg; 1397 1398 EM_CORE_LOCK(adapter); 1399 em_init_locked(adapter); 1400 EM_CORE_UNLOCK(adapter); 1401 } 1402 1403 1404 #ifdef DEVICE_POLLING 1405 /********************************************************************* 1406 * 1407 * Legacy polling routine 1408 * 1409 *********************************************************************/ 1410 static void 1411 em_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1412 { 1413 struct adapter *adapter = ifp->if_softc; 1414 uint32_t reg_icr; 1415 1416 EM_CORE_LOCK(adapter); 1417 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 1418 EM_CORE_UNLOCK(adapter); 1419 return; 1420 } 1421 1422 if (cmd == POLL_AND_CHECK_STATUS) { 1423 reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR); 1424 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 1425 callout_stop(&adapter->timer); 1426 adapter->hw.mac.get_link_status = 1; 1427 e1000_check_for_link(&adapter->hw); 1428 em_update_link_status(adapter); 1429 callout_reset(&adapter->timer, hz, 1430 em_local_timer, adapter); 1431 } 1432 } 1433 em_rxeof(adapter, count); 1434 EM_CORE_UNLOCK(adapter); 1435 1436 EM_TX_LOCK(adapter); 1437 em_txeof(adapter); 1438 1439 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1440 em_start_locked(ifp); 1441 EM_TX_UNLOCK(adapter); 1442 } 1443 #endif /* DEVICE_POLLING */ 1444 1445 #ifndef EM_FAST_IRQ 1446 /********************************************************************* 1447 * 1448 * Legacy Interrupt Service routine 1449 * 1450 *********************************************************************/ 1451 1452 static void 1453 em_intr(void *arg) 1454 { 1455 struct adapter *adapter = arg; 1456 struct ifnet *ifp; 1457 uint32_t reg_icr; 1458 1459 EM_CORE_LOCK(adapter); 1460 ifp = adapter->ifp; 1461 1462 if (ifp->if_capenable & IFCAP_POLLING) { 1463 EM_CORE_UNLOCK(adapter); 1464 return; 1465 } 1466 1467 for (;;) { 1468 reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR); 1469 1470 if (adapter->hw.mac.type >= e1000_82571 && 1471 (reg_icr & E1000_ICR_INT_ASSERTED) == 0) 1472 break; 1473 else if (reg_icr == 0) 1474 break; 1475 1476 /* 1477 * XXX: some laptops trigger several spurious interrupts 1478 * on em(4) when in the resume cycle. The ICR register 1479 * reports all-ones value in this case. Processing such 1480 * interrupts would lead to a freeze. I don't know why. 1481 */ 1482 if (reg_icr == 0xffffffff) 1483 break; 1484 1485 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1486 em_rxeof(adapter, -1); 1487 EM_TX_LOCK(adapter); 1488 em_txeof(adapter); 1489 EM_TX_UNLOCK(adapter); 1490 } 1491 1492 /* Link status change */ 1493 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 1494 callout_stop(&adapter->timer); 1495 adapter->hw.mac.get_link_status = 1; 1496 e1000_check_for_link(&adapter->hw); 1497 em_update_link_status(adapter); 1498 /* Deal with TX cruft when link lost */ 1499 em_tx_purge(adapter); 1500 callout_reset(&adapter->timer, hz, 1501 em_local_timer, adapter); 1502 } 1503 1504 if (reg_icr & E1000_ICR_RXO) 1505 adapter->rx_overruns++; 1506 } 1507 EM_CORE_UNLOCK(adapter); 1508 1509 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 1510 !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1511 em_start(ifp); 1512 } 1513 1514 #else /* EM_FAST_IRQ, then fast interrupt routines only */ 1515 1516 static void 1517 em_handle_link(void *context, int pending) 1518 { 1519 struct adapter *adapter = context; 1520 struct ifnet *ifp; 1521 1522 ifp = adapter->ifp; 1523 1524 EM_CORE_LOCK(adapter); 1525 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 1526 EM_CORE_UNLOCK(adapter); 1527 return; 1528 } 1529 1530 callout_stop(&adapter->timer); 1531 adapter->hw.mac.get_link_status = 1; 1532 e1000_check_for_link(&adapter->hw); 1533 em_update_link_status(adapter); 1534 /* Deal with TX cruft when link lost */ 1535 em_tx_purge(adapter); 1536 callout_reset(&adapter->timer, hz, em_local_timer, adapter); 1537 EM_CORE_UNLOCK(adapter); 1538 } 1539 1540 #if __FreeBSD_version >= 700000 1541 #if !defined(NET_LOCK_GIANT) 1542 #define NET_LOCK_GIANT() 1543 #define NET_UNLOCK_GIANT() 1544 #endif 1545 #endif 1546 1547 static void 1548 em_handle_rxtx(void *context, int pending) 1549 { 1550 struct adapter *adapter = context; 1551 struct ifnet *ifp; 1552 1553 NET_LOCK_GIANT(); 1554 ifp = adapter->ifp; 1555 1556 /* 1557 * TODO: 1558 * It should be possible to run the tx clean loop without the lock. 1559 */ 1560 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1561 if (em_rxeof(adapter, adapter->rx_process_limit) != 0) 1562 taskqueue_enqueue(adapter->tq, &adapter->rxtx_task); 1563 EM_TX_LOCK(adapter); 1564 em_txeof(adapter); 1565 1566 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1567 em_start_locked(ifp); 1568 EM_TX_UNLOCK(adapter); 1569 } 1570 1571 em_enable_intr(adapter); 1572 NET_UNLOCK_GIANT(); 1573 } 1574 1575 /********************************************************************* 1576 * 1577 * Fast Interrupt Service routine 1578 * 1579 *********************************************************************/ 1580 #if __FreeBSD_version < 700000 1581 #define FILTER_STRAY 1582 #define FILTER_HANDLED 1583 static void 1584 #else 1585 static int 1586 #endif 1587 em_intr_fast(void *arg) 1588 { 1589 struct adapter *adapter = arg; 1590 struct ifnet *ifp; 1591 uint32_t reg_icr; 1592 1593 ifp = adapter->ifp; 1594 1595 reg_icr = E1000_READ_REG(&adapter->hw, E1000_ICR); 1596 1597 /* Hot eject? */ 1598 if (reg_icr == 0xffffffff) 1599 return FILTER_STRAY; 1600 1601 /* Definitely not our interrupt. */ 1602 if (reg_icr == 0x0) 1603 return FILTER_STRAY; 1604 1605 /* 1606 * Starting with the 82571 chip, bit 31 should be used to 1607 * determine whether the interrupt belongs to us. 1608 */ 1609 if (adapter->hw.mac.type >= e1000_82571 && 1610 (reg_icr & E1000_ICR_INT_ASSERTED) == 0) 1611 return FILTER_STRAY; 1612 1613 /* 1614 * Mask interrupts until the taskqueue is finished running. This is 1615 * cheap, just assume that it is needed. This also works around the 1616 * MSI message reordering errata on certain systems. 1617 */ 1618 em_disable_intr(adapter); 1619 taskqueue_enqueue(adapter->tq, &adapter->rxtx_task); 1620 1621 /* Link status change */ 1622 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) 1623 taskqueue_enqueue(taskqueue_fast, &adapter->link_task); 1624 1625 if (reg_icr & E1000_ICR_RXO) 1626 adapter->rx_overruns++; 1627 return FILTER_HANDLED; 1628 } 1629 #endif /* EM_FAST_IRQ */ 1630 1631 /********************************************************************* 1632 * 1633 * Media Ioctl callback 1634 * 1635 * This routine is called whenever the user queries the status of 1636 * the interface using ifconfig. 1637 * 1638 **********************************************************************/ 1639 static void 1640 em_media_status(struct ifnet *ifp, struct ifmediareq *ifmr) 1641 { 1642 struct adapter *adapter = ifp->if_softc; 1643 u_char fiber_type = IFM_1000_SX; 1644 1645 INIT_DEBUGOUT("em_media_status: begin"); 1646 1647 EM_CORE_LOCK(adapter); 1648 e1000_check_for_link(&adapter->hw); 1649 em_update_link_status(adapter); 1650 1651 ifmr->ifm_status = IFM_AVALID; 1652 ifmr->ifm_active = IFM_ETHER; 1653 1654 if (!adapter->link_active) { 1655 EM_CORE_UNLOCK(adapter); 1656 return; 1657 } 1658 1659 ifmr->ifm_status |= IFM_ACTIVE; 1660 1661 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) || 1662 (adapter->hw.phy.media_type == e1000_media_type_internal_serdes)) { 1663 if (adapter->hw.mac.type == e1000_82545) 1664 fiber_type = IFM_1000_LX; 1665 ifmr->ifm_active |= fiber_type | IFM_FDX; 1666 } else { 1667 switch (adapter->link_speed) { 1668 case 10: 1669 ifmr->ifm_active |= IFM_10_T; 1670 break; 1671 case 100: 1672 ifmr->ifm_active |= IFM_100_TX; 1673 break; 1674 case 1000: 1675 ifmr->ifm_active |= IFM_1000_T; 1676 break; 1677 } 1678 if (adapter->link_duplex == FULL_DUPLEX) 1679 ifmr->ifm_active |= IFM_FDX; 1680 else 1681 ifmr->ifm_active |= IFM_HDX; 1682 } 1683 EM_CORE_UNLOCK(adapter); 1684 } 1685 1686 /********************************************************************* 1687 * 1688 * Media Ioctl callback 1689 * 1690 * This routine is called when the user changes speed/duplex using 1691 * media/mediopt option with ifconfig. 1692 * 1693 **********************************************************************/ 1694 static int 1695 em_media_change(struct ifnet *ifp) 1696 { 1697 struct adapter *adapter = ifp->if_softc; 1698 struct ifmedia *ifm = &adapter->media; 1699 1700 INIT_DEBUGOUT("em_media_change: begin"); 1701 1702 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1703 return (EINVAL); 1704 1705 EM_CORE_LOCK(adapter); 1706 switch (IFM_SUBTYPE(ifm->ifm_media)) { 1707 case IFM_AUTO: 1708 adapter->hw.mac.autoneg = DO_AUTO_NEG; 1709 adapter->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT; 1710 break; 1711 case IFM_1000_LX: 1712 case IFM_1000_SX: 1713 case IFM_1000_T: 1714 adapter->hw.mac.autoneg = DO_AUTO_NEG; 1715 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 1716 break; 1717 case IFM_100_TX: 1718 adapter->hw.mac.autoneg = FALSE; 1719 adapter->hw.phy.autoneg_advertised = 0; 1720 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1721 adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL; 1722 else 1723 adapter->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF; 1724 break; 1725 case IFM_10_T: 1726 adapter->hw.mac.autoneg = FALSE; 1727 adapter->hw.phy.autoneg_advertised = 0; 1728 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1729 adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL; 1730 else 1731 adapter->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF; 1732 break; 1733 default: 1734 device_printf(adapter->dev, "Unsupported media type\n"); 1735 } 1736 1737 /* As the speed/duplex settings my have changed we need to 1738 * reset the PHY. 1739 */ 1740 adapter->hw.phy.reset_disable = FALSE; 1741 1742 em_init_locked(adapter); 1743 EM_CORE_UNLOCK(adapter); 1744 1745 return (0); 1746 } 1747 1748 /********************************************************************* 1749 * 1750 * This routine maps the mbufs to tx descriptors. 1751 * 1752 * return 0 on success, positive on failure 1753 **********************************************************************/ 1754 1755 static int 1756 em_encap(struct adapter *adapter, struct mbuf **m_headp) 1757 { 1758 bus_dma_segment_t segs[EM_MAX_SCATTER]; 1759 bus_dmamap_t map; 1760 struct em_buffer *tx_buffer, *tx_buffer_mapped; 1761 struct e1000_tx_desc *ctxd = NULL; 1762 struct mbuf *m_head; 1763 uint32_t txd_upper, txd_lower, txd_used, txd_saved; 1764 int nsegs, i, j, first, last = 0; 1765 int error, do_tso, tso_desc = 0; 1766 #if __FreeBSD_version < 700000 1767 struct m_tag *mtag; 1768 #endif 1769 m_head = *m_headp; 1770 txd_upper = txd_lower = txd_used = txd_saved = 0; 1771 1772 #if __FreeBSD_version >= 700000 1773 do_tso = ((m_head->m_pkthdr.csum_flags & CSUM_TSO) != 0); 1774 #else 1775 do_tso = 0; 1776 #endif 1777 1778 /* 1779 * Force a cleanup if number of TX descriptors 1780 * available hits the threshold 1781 */ 1782 if (adapter->num_tx_desc_avail <= EM_TX_CLEANUP_THRESHOLD) { 1783 em_txeof(adapter); 1784 /* Now do we at least have a minimal? */ 1785 if (adapter->num_tx_desc_avail <= EM_TX_OP_THRESHOLD) { 1786 adapter->no_tx_desc_avail1++; 1787 return (ENOBUFS); 1788 } 1789 } 1790 1791 1792 /* 1793 * TSO workaround: 1794 * If an mbuf is only header we need 1795 * to pull 4 bytes of data into it. 1796 */ 1797 if (do_tso && (m_head->m_len <= M_TSO_LEN)) { 1798 m_head = m_pullup(m_head, M_TSO_LEN + 4); 1799 *m_headp = m_head; 1800 if (m_head == NULL) 1801 return (ENOBUFS); 1802 } 1803 1804 /* 1805 * Map the packet for DMA 1806 * 1807 * Capture the first descriptor index, 1808 * this descriptor will have the index 1809 * of the EOP which is the only one that 1810 * now gets a DONE bit writeback. 1811 */ 1812 first = adapter->next_avail_tx_desc; 1813 tx_buffer = &adapter->tx_buffer_area[first]; 1814 tx_buffer_mapped = tx_buffer; 1815 map = tx_buffer->map; 1816 1817 error = bus_dmamap_load_mbuf_sg(adapter->txtag, map, 1818 *m_headp, segs, &nsegs, BUS_DMA_NOWAIT); 1819 1820 /* 1821 * There are two types of errors we can (try) to handle: 1822 * - EFBIG means the mbuf chain was too long and bus_dma ran 1823 * out of segments. Defragment the mbuf chain and try again. 1824 * - ENOMEM means bus_dma could not obtain enough bounce buffers 1825 * at this point in time. Defer sending and try again later. 1826 * All other errors, in particular EINVAL, are fatal and prevent the 1827 * mbuf chain from ever going through. Drop it and report error. 1828 */ 1829 if (error == EFBIG) { 1830 struct mbuf *m; 1831 1832 m = m_defrag(*m_headp, M_DONTWAIT); 1833 if (m == NULL) { 1834 adapter->mbuf_alloc_failed++; 1835 m_freem(*m_headp); 1836 *m_headp = NULL; 1837 return (ENOBUFS); 1838 } 1839 *m_headp = m; 1840 1841 /* Try it again */ 1842 error = bus_dmamap_load_mbuf_sg(adapter->txtag, map, 1843 *m_headp, segs, &nsegs, BUS_DMA_NOWAIT); 1844 1845 if (error == ENOMEM) { 1846 adapter->no_tx_dma_setup++; 1847 return (error); 1848 } else if (error != 0) { 1849 adapter->no_tx_dma_setup++; 1850 m_freem(*m_headp); 1851 *m_headp = NULL; 1852 return (error); 1853 } 1854 } else if (error == ENOMEM) { 1855 adapter->no_tx_dma_setup++; 1856 return (error); 1857 } else if (error != 0) { 1858 adapter->no_tx_dma_setup++; 1859 m_freem(*m_headp); 1860 *m_headp = NULL; 1861 return (error); 1862 } 1863 1864 /* 1865 * TSO Hardware workaround, if this packet is not 1866 * TSO, and is only a single descriptor long, and 1867 * it follows a TSO burst, then we need to add a 1868 * sentinel descriptor to prevent premature writeback. 1869 */ 1870 if ((do_tso == 0) && (adapter->tx_tso == TRUE)) { 1871 if (nsegs == 1) 1872 tso_desc = TRUE; 1873 adapter->tx_tso = FALSE; 1874 } 1875 1876 if (nsegs > (adapter->num_tx_desc_avail - 2)) { 1877 adapter->no_tx_desc_avail2++; 1878 bus_dmamap_unload(adapter->txtag, map); 1879 return (ENOBUFS); 1880 } 1881 m_head = *m_headp; 1882 1883 /* Do hardware assists */ 1884 #if __FreeBSD_version >= 700000 1885 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) { 1886 error = em_tso_setup(adapter, m_head, &txd_upper, &txd_lower); 1887 if (error != TRUE) 1888 return (ENXIO); /* something foobar */ 1889 /* we need to make a final sentinel transmit desc */ 1890 tso_desc = TRUE; 1891 } else 1892 #endif 1893 if (m_head->m_pkthdr.csum_flags & CSUM_OFFLOAD) 1894 em_transmit_checksum_setup(adapter, m_head, 1895 &txd_upper, &txd_lower); 1896 1897 i = adapter->next_avail_tx_desc; 1898 if (adapter->pcix_82544) 1899 txd_saved = i; 1900 1901 /* Set up our transmit descriptors */ 1902 for (j = 0; j < nsegs; j++) { 1903 bus_size_t seg_len; 1904 bus_addr_t seg_addr; 1905 /* If adapter is 82544 and on PCIX bus */ 1906 if(adapter->pcix_82544) { 1907 DESC_ARRAY desc_array; 1908 uint32_t array_elements, counter; 1909 /* 1910 * Check the Address and Length combination and 1911 * split the data accordingly 1912 */ 1913 array_elements = em_fill_descriptors(segs[j].ds_addr, 1914 segs[j].ds_len, &desc_array); 1915 for (counter = 0; counter < array_elements; counter++) { 1916 if (txd_used == adapter->num_tx_desc_avail) { 1917 adapter->next_avail_tx_desc = txd_saved; 1918 adapter->no_tx_desc_avail2++; 1919 bus_dmamap_unload(adapter->txtag, map); 1920 return (ENOBUFS); 1921 } 1922 tx_buffer = &adapter->tx_buffer_area[i]; 1923 ctxd = &adapter->tx_desc_base[i]; 1924 ctxd->buffer_addr = htole64( 1925 desc_array.descriptor[counter].address); 1926 ctxd->lower.data = htole32( 1927 (adapter->txd_cmd | txd_lower | (uint16_t) 1928 desc_array.descriptor[counter].length)); 1929 ctxd->upper.data = 1930 htole32((txd_upper)); 1931 last = i; 1932 if (++i == adapter->num_tx_desc) 1933 i = 0; 1934 tx_buffer->m_head = NULL; 1935 tx_buffer->next_eop = -1; 1936 txd_used++; 1937 } 1938 } else { 1939 tx_buffer = &adapter->tx_buffer_area[i]; 1940 ctxd = &adapter->tx_desc_base[i]; 1941 seg_addr = segs[j].ds_addr; 1942 seg_len = segs[j].ds_len; 1943 /* 1944 ** TSO Workaround: 1945 ** If this is the last descriptor, we want to 1946 ** split it so we have a small final sentinel 1947 */ 1948 if (tso_desc && (j == (nsegs -1)) && (seg_len > 8)) { 1949 seg_len -= 4; 1950 ctxd->buffer_addr = htole64(seg_addr); 1951 ctxd->lower.data = htole32( 1952 adapter->txd_cmd | txd_lower | seg_len); 1953 ctxd->upper.data = 1954 htole32(txd_upper); 1955 if (++i == adapter->num_tx_desc) 1956 i = 0; 1957 /* Now make the sentinel */ 1958 ++txd_used; /* using an extra txd */ 1959 ctxd = &adapter->tx_desc_base[i]; 1960 tx_buffer = &adapter->tx_buffer_area[i]; 1961 ctxd->buffer_addr = 1962 htole64(seg_addr + seg_len); 1963 ctxd->lower.data = htole32( 1964 adapter->txd_cmd | txd_lower | 4); 1965 ctxd->upper.data = 1966 htole32(txd_upper); 1967 last = i; 1968 if (++i == adapter->num_tx_desc) 1969 i = 0; 1970 } else { 1971 ctxd->buffer_addr = htole64(seg_addr); 1972 ctxd->lower.data = htole32( 1973 adapter->txd_cmd | txd_lower | seg_len); 1974 ctxd->upper.data = 1975 htole32(txd_upper); 1976 last = i; 1977 if (++i == adapter->num_tx_desc) 1978 i = 0; 1979 } 1980 tx_buffer->m_head = NULL; 1981 tx_buffer->next_eop = -1; 1982 } 1983 } 1984 1985 adapter->next_avail_tx_desc = i; 1986 if (adapter->pcix_82544) 1987 adapter->num_tx_desc_avail -= txd_used; 1988 else { 1989 adapter->num_tx_desc_avail -= nsegs; 1990 if (tso_desc) /* TSO used an extra for sentinel */ 1991 adapter->num_tx_desc_avail -= txd_used; 1992 } 1993 1994 /* 1995 ** Handle VLAN tag, this is the 1996 ** biggest difference between 1997 ** 6.x and 7 1998 */ 1999 #if __FreeBSD_version < 700000 2000 /* Find out if we are in vlan mode. */ 2001 mtag = VLAN_OUTPUT_TAG(ifp, m_head); 2002 if (mtag != NULL) { 2003 ctxd->upper.fields.special = 2004 htole16(VLAN_TAG_VALUE(mtag)); 2005 #else /* FreeBSD 7 */ 2006 if (m_head->m_flags & M_VLANTAG) { 2007 /* Set the vlan id. */ 2008 ctxd->upper.fields.special = 2009 htole16(m_head->m_pkthdr.ether_vtag); 2010 #endif 2011 /* Tell hardware to add tag */ 2012 ctxd->lower.data |= htole32(E1000_TXD_CMD_VLE); 2013 } 2014 2015 tx_buffer->m_head = m_head; 2016 tx_buffer_mapped->map = tx_buffer->map; 2017 tx_buffer->map = map; 2018 bus_dmamap_sync(adapter->txtag, map, BUS_DMASYNC_PREWRITE); 2019 2020 /* 2021 * Last Descriptor of Packet 2022 * needs End Of Packet (EOP) 2023 * and Report Status (RS) 2024 */ 2025 ctxd->lower.data |= 2026 htole32(E1000_TXD_CMD_EOP | E1000_TXD_CMD_RS); 2027 /* 2028 * Keep track in the first buffer which 2029 * descriptor will be written back 2030 */ 2031 tx_buffer = &adapter->tx_buffer_area[first]; 2032 tx_buffer->next_eop = last; 2033 2034 /* 2035 * Advance the Transmit Descriptor Tail (TDT), this tells the E1000 2036 * that this frame is available to transmit. 2037 */ 2038 bus_dmamap_sync(adapter->txdma.dma_tag, adapter->txdma.dma_map, 2039 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2040 if (adapter->hw.mac.type == e1000_82547 && 2041 adapter->link_duplex == HALF_DUPLEX) 2042 em_82547_move_tail(adapter); 2043 else { 2044 E1000_WRITE_REG(&adapter->hw, E1000_TDT(0), i); 2045 if (adapter->hw.mac.type == e1000_82547) 2046 em_82547_update_fifo_head(adapter, 2047 m_head->m_pkthdr.len); 2048 } 2049 2050 return (0); 2051 } 2052 2053 /********************************************************************* 2054 * 2055 * This routine maps the mbufs to Advanced TX descriptors. 2056 * used by the 82575 adapter. It also needs no workarounds. 2057 * 2058 **********************************************************************/ 2059 2060 static int 2061 em_adv_encap(struct adapter *adapter, struct mbuf **m_headp) 2062 { 2063 bus_dma_segment_t segs[EM_MAX_SCATTER]; 2064 bus_dmamap_t map; 2065 struct em_buffer *tx_buffer, *tx_buffer_mapped; 2066 union e1000_adv_tx_desc *txd = NULL; 2067 struct mbuf *m_head; 2068 u32 olinfo_status = 0, cmd_type_len = 0; 2069 int nsegs, i, j, error, first, last = 0; 2070 #if __FreeBSD_version < 700000 2071 struct m_tag *mtag; 2072 #else 2073 u32 hdrlen = 0; 2074 #endif 2075 2076 m_head = *m_headp; 2077 2078 2079 /* Set basic descriptor constants */ 2080 cmd_type_len |= E1000_ADVTXD_DTYP_DATA; 2081 cmd_type_len |= E1000_ADVTXD_DCMD_IFCS | E1000_ADVTXD_DCMD_DEXT; 2082 #if __FreeBSD_version < 700000 2083 mtag = VLAN_OUTPUT_TAG(ifp, m_head); 2084 if (mtag != NULL) 2085 #else 2086 if (m_head->m_flags & M_VLANTAG) 2087 #endif 2088 cmd_type_len |= E1000_ADVTXD_DCMD_VLE; 2089 2090 /* 2091 * Force a cleanup if number of TX descriptors 2092 * available hits the threshold 2093 */ 2094 if (adapter->num_tx_desc_avail <= EM_TX_CLEANUP_THRESHOLD) { 2095 em_txeof(adapter); 2096 /* Now do we at least have a minimal? */ 2097 if (adapter->num_tx_desc_avail <= EM_TX_OP_THRESHOLD) { 2098 adapter->no_tx_desc_avail1++; 2099 return (ENOBUFS); 2100 } 2101 } 2102 2103 /* 2104 * Map the packet for DMA. 2105 * 2106 * Capture the first descriptor index, 2107 * this descriptor will have the index 2108 * of the EOP which is the only one that 2109 * now gets a DONE bit writeback. 2110 */ 2111 first = adapter->next_avail_tx_desc; 2112 tx_buffer = &adapter->tx_buffer_area[first]; 2113 tx_buffer_mapped = tx_buffer; 2114 map = tx_buffer->map; 2115 2116 error = bus_dmamap_load_mbuf_sg(adapter->txtag, map, 2117 *m_headp, segs, &nsegs, BUS_DMA_NOWAIT); 2118 2119 if (error == EFBIG) { 2120 struct mbuf *m; 2121 2122 m = m_defrag(*m_headp, M_DONTWAIT); 2123 if (m == NULL) { 2124 adapter->mbuf_alloc_failed++; 2125 m_freem(*m_headp); 2126 *m_headp = NULL; 2127 return (ENOBUFS); 2128 } 2129 *m_headp = m; 2130 2131 /* Try it again */ 2132 error = bus_dmamap_load_mbuf_sg(adapter->txtag, map, 2133 *m_headp, segs, &nsegs, BUS_DMA_NOWAIT); 2134 2135 if (error == ENOMEM) { 2136 adapter->no_tx_dma_setup++; 2137 return (error); 2138 } else if (error != 0) { 2139 adapter->no_tx_dma_setup++; 2140 m_freem(*m_headp); 2141 *m_headp = NULL; 2142 return (error); 2143 } 2144 } else if (error == ENOMEM) { 2145 adapter->no_tx_dma_setup++; 2146 return (error); 2147 } else if (error != 0) { 2148 adapter->no_tx_dma_setup++; 2149 m_freem(*m_headp); 2150 *m_headp = NULL; 2151 return (error); 2152 } 2153 2154 /* Check again to be sure we have enough descriptors */ 2155 if (nsegs > (adapter->num_tx_desc_avail - 2)) { 2156 adapter->no_tx_desc_avail2++; 2157 bus_dmamap_unload(adapter->txtag, map); 2158 return (ENOBUFS); 2159 } 2160 m_head = *m_headp; 2161 2162 /* 2163 * Set up the context descriptor: 2164 * used when any hardware offload is done. 2165 * This includes CSUM, VLAN, and TSO. It 2166 * will use the first descriptor. 2167 */ 2168 #if __FreeBSD_version >= 700000 2169 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) { 2170 if (em_tso_adv_setup(adapter, m_head, &hdrlen)) { 2171 cmd_type_len |= E1000_ADVTXD_DCMD_TSE; 2172 olinfo_status |= E1000_TXD_POPTS_IXSM << 8; 2173 olinfo_status |= E1000_TXD_POPTS_TXSM << 8; 2174 } else 2175 return (ENXIO); 2176 } 2177 #endif 2178 /* Do all other context descriptor setup */ 2179 if (em_tx_adv_ctx_setup(adapter, m_head)) 2180 olinfo_status |= E1000_TXD_POPTS_TXSM << 8; 2181 2182 /* Calculate payload length */ 2183 olinfo_status |= ((m_head->m_pkthdr.len - hdrlen) 2184 << E1000_ADVTXD_PAYLEN_SHIFT); 2185 2186 /* Set up our transmit descriptors */ 2187 i = adapter->next_avail_tx_desc; 2188 for (j = 0; j < nsegs; j++) { 2189 bus_size_t seg_len; 2190 bus_addr_t seg_addr; 2191 2192 tx_buffer = &adapter->tx_buffer_area[i]; 2193 txd = (union e1000_adv_tx_desc *)&adapter->tx_desc_base[i]; 2194 seg_addr = segs[j].ds_addr; 2195 seg_len = segs[j].ds_len; 2196 2197 txd->read.buffer_addr = htole64(seg_addr); 2198 txd->read.cmd_type_len = htole32( 2199 adapter->txd_cmd | cmd_type_len | seg_len); 2200 txd->read.olinfo_status = htole32(olinfo_status); 2201 last = i; 2202 if (++i == adapter->num_tx_desc) 2203 i = 0; 2204 tx_buffer->m_head = NULL; 2205 tx_buffer->next_eop = -1; 2206 } 2207 2208 adapter->next_avail_tx_desc = i; 2209 adapter->num_tx_desc_avail -= nsegs; 2210 2211 tx_buffer->m_head = m_head; 2212 tx_buffer_mapped->map = tx_buffer->map; 2213 tx_buffer->map = map; 2214 bus_dmamap_sync(adapter->txtag, map, BUS_DMASYNC_PREWRITE); 2215 2216 /* 2217 * Last Descriptor of Packet 2218 * needs End Of Packet (EOP) 2219 * and Report Status (RS) 2220 */ 2221 txd->read.cmd_type_len |= 2222 htole32(E1000_TXD_CMD_EOP | E1000_TXD_CMD_RS); 2223 /* 2224 * Keep track in the first buffer which 2225 * descriptor will be written back 2226 */ 2227 tx_buffer = &adapter->tx_buffer_area[first]; 2228 tx_buffer->next_eop = last; 2229 2230 /* 2231 * Advance the Transmit Descriptor Tail (TDT), this tells the E1000 2232 * that this frame is available to transmit. 2233 */ 2234 bus_dmamap_sync(adapter->txdma.dma_tag, adapter->txdma.dma_map, 2235 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2236 E1000_WRITE_REG(&adapter->hw, E1000_TDT(0), i); 2237 2238 return (0); 2239 2240 } 2241 2242 /********************************************************************* 2243 * 2244 * 82547 workaround to avoid controller hang in half-duplex environment. 2245 * The workaround is to avoid queuing a large packet that would span 2246 * the internal Tx FIFO ring boundary. We need to reset the FIFO pointers 2247 * in this case. We do that only when FIFO is quiescent. 2248 * 2249 **********************************************************************/ 2250 static void 2251 em_82547_move_tail(void *arg) 2252 { 2253 struct adapter *adapter = arg; 2254 uint16_t hw_tdt; 2255 uint16_t sw_tdt; 2256 struct e1000_tx_desc *tx_desc; 2257 uint16_t length = 0; 2258 boolean_t eop = 0; 2259 2260 EM_TX_LOCK_ASSERT(adapter); 2261 2262 hw_tdt = E1000_READ_REG(&adapter->hw, E1000_TDT(0)); 2263 sw_tdt = adapter->next_avail_tx_desc; 2264 2265 while (hw_tdt != sw_tdt) { 2266 tx_desc = &adapter->tx_desc_base[hw_tdt]; 2267 length += tx_desc->lower.flags.length; 2268 eop = tx_desc->lower.data & E1000_TXD_CMD_EOP; 2269 if (++hw_tdt == adapter->num_tx_desc) 2270 hw_tdt = 0; 2271 2272 if (eop) { 2273 if (em_82547_fifo_workaround(adapter, length)) { 2274 adapter->tx_fifo_wrk_cnt++; 2275 callout_reset(&adapter->tx_fifo_timer, 1, 2276 em_82547_move_tail, adapter); 2277 break; 2278 } 2279 E1000_WRITE_REG(&adapter->hw, E1000_TDT(0), hw_tdt); 2280 em_82547_update_fifo_head(adapter, length); 2281 length = 0; 2282 } 2283 } 2284 } 2285 2286 static int 2287 em_82547_fifo_workaround(struct adapter *adapter, int len) 2288 { 2289 int fifo_space, fifo_pkt_len; 2290 2291 fifo_pkt_len = roundup2(len + EM_FIFO_HDR, EM_FIFO_HDR); 2292 2293 if (adapter->link_duplex == HALF_DUPLEX) { 2294 fifo_space = adapter->tx_fifo_size - adapter->tx_fifo_head; 2295 2296 if (fifo_pkt_len >= (EM_82547_PKT_THRESH + fifo_space)) { 2297 if (em_82547_tx_fifo_reset(adapter)) 2298 return (0); 2299 else 2300 return (1); 2301 } 2302 } 2303 2304 return (0); 2305 } 2306 2307 static void 2308 em_82547_update_fifo_head(struct adapter *adapter, int len) 2309 { 2310 int fifo_pkt_len = roundup2(len + EM_FIFO_HDR, EM_FIFO_HDR); 2311 2312 /* tx_fifo_head is always 16 byte aligned */ 2313 adapter->tx_fifo_head += fifo_pkt_len; 2314 if (adapter->tx_fifo_head >= adapter->tx_fifo_size) { 2315 adapter->tx_fifo_head -= adapter->tx_fifo_size; 2316 } 2317 } 2318 2319 2320 static int 2321 em_82547_tx_fifo_reset(struct adapter *adapter) 2322 { 2323 uint32_t tctl; 2324 2325 if ((E1000_READ_REG(&adapter->hw, E1000_TDT(0)) == 2326 E1000_READ_REG(&adapter->hw, E1000_TDH(0))) && 2327 (E1000_READ_REG(&adapter->hw, E1000_TDFT) == 2328 E1000_READ_REG(&adapter->hw, E1000_TDFH)) && 2329 (E1000_READ_REG(&adapter->hw, E1000_TDFTS) == 2330 E1000_READ_REG(&adapter->hw, E1000_TDFHS)) && 2331 (E1000_READ_REG(&adapter->hw, E1000_TDFPC) == 0)) { 2332 /* Disable TX unit */ 2333 tctl = E1000_READ_REG(&adapter->hw, E1000_TCTL); 2334 E1000_WRITE_REG(&adapter->hw, E1000_TCTL, 2335 tctl & ~E1000_TCTL_EN); 2336 2337 /* Reset FIFO pointers */ 2338 E1000_WRITE_REG(&adapter->hw, E1000_TDFT, 2339 adapter->tx_head_addr); 2340 E1000_WRITE_REG(&adapter->hw, E1000_TDFH, 2341 adapter->tx_head_addr); 2342 E1000_WRITE_REG(&adapter->hw, E1000_TDFTS, 2343 adapter->tx_head_addr); 2344 E1000_WRITE_REG(&adapter->hw, E1000_TDFHS, 2345 adapter->tx_head_addr); 2346 2347 /* Re-enable TX unit */ 2348 E1000_WRITE_REG(&adapter->hw, E1000_TCTL, tctl); 2349 E1000_WRITE_FLUSH(&adapter->hw); 2350 2351 adapter->tx_fifo_head = 0; 2352 adapter->tx_fifo_reset_cnt++; 2353 2354 return (TRUE); 2355 } 2356 else { 2357 return (FALSE); 2358 } 2359 } 2360 2361 static void 2362 em_set_promisc(struct adapter *adapter) 2363 { 2364 struct ifnet *ifp = adapter->ifp; 2365 uint32_t reg_rctl; 2366 2367 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 2368 2369 if (ifp->if_flags & IFF_PROMISC) { 2370 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 2371 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 2372 } else if (ifp->if_flags & IFF_ALLMULTI) { 2373 reg_rctl |= E1000_RCTL_MPE; 2374 reg_rctl &= ~E1000_RCTL_UPE; 2375 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 2376 } 2377 } 2378 2379 static void 2380 em_disable_promisc(struct adapter *adapter) 2381 { 2382 uint32_t reg_rctl; 2383 2384 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 2385 2386 reg_rctl &= (~E1000_RCTL_UPE); 2387 reg_rctl &= (~E1000_RCTL_MPE); 2388 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 2389 } 2390 2391 2392 /********************************************************************* 2393 * Multicast Update 2394 * 2395 * This routine is called whenever multicast address list is updated. 2396 * 2397 **********************************************************************/ 2398 2399 static void 2400 em_set_multi(struct adapter *adapter) 2401 { 2402 struct ifnet *ifp = adapter->ifp; 2403 struct ifmultiaddr *ifma; 2404 uint32_t reg_rctl = 0; 2405 uint8_t mta[512]; /* Largest MTS is 4096 bits */ 2406 int mcnt = 0; 2407 2408 IOCTL_DEBUGOUT("em_set_multi: begin"); 2409 2410 if (adapter->hw.mac.type == e1000_82542 && 2411 adapter->hw.revision_id == E1000_REVISION_2) { 2412 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 2413 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 2414 e1000_pci_clear_mwi(&adapter->hw); 2415 reg_rctl |= E1000_RCTL_RST; 2416 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 2417 msec_delay(5); 2418 } 2419 2420 IF_ADDR_LOCK(ifp); 2421 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2422 if (ifma->ifma_addr->sa_family != AF_LINK) 2423 continue; 2424 2425 if (mcnt == MAX_NUM_MULTICAST_ADDRESSES) 2426 break; 2427 2428 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 2429 &mta[mcnt * ETH_ADDR_LEN], ETH_ADDR_LEN); 2430 mcnt++; 2431 } 2432 IF_ADDR_UNLOCK(ifp); 2433 2434 if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES) { 2435 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 2436 reg_rctl |= E1000_RCTL_MPE; 2437 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 2438 } else 2439 e1000_update_mc_addr_list(&adapter->hw, mta, 2440 mcnt, 1, adapter->hw.mac.rar_entry_count); 2441 2442 if (adapter->hw.mac.type == e1000_82542 && 2443 adapter->hw.revision_id == E1000_REVISION_2) { 2444 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 2445 reg_rctl &= ~E1000_RCTL_RST; 2446 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 2447 msec_delay(5); 2448 if (adapter->hw.bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 2449 e1000_pci_set_mwi(&adapter->hw); 2450 } 2451 } 2452 2453 2454 /********************************************************************* 2455 * Timer routine 2456 * 2457 * This routine checks for link status and updates statistics. 2458 * 2459 **********************************************************************/ 2460 2461 static void 2462 em_local_timer(void *arg) 2463 { 2464 struct adapter *adapter = arg; 2465 struct ifnet *ifp = adapter->ifp; 2466 2467 EM_CORE_LOCK_ASSERT(adapter); 2468 2469 e1000_check_for_link(&adapter->hw); 2470 em_update_link_status(adapter); 2471 em_update_stats_counters(adapter); 2472 2473 /* Reset LAA into RAR[0] on 82571 */ 2474 if (e1000_get_laa_state_82571(&adapter->hw) == TRUE) 2475 e1000_rar_set(&adapter->hw, adapter->hw.mac.addr, 0); 2476 2477 if (em_display_debug_stats && ifp->if_drv_flags & IFF_DRV_RUNNING) 2478 em_print_hw_stats(adapter); 2479 2480 em_smartspeed(adapter); 2481 2482 /* 2483 * Each second we check the watchdog to 2484 * protect against hardware hangs. 2485 */ 2486 em_watchdog(adapter); 2487 2488 callout_reset(&adapter->timer, hz, em_local_timer, adapter); 2489 2490 } 2491 2492 static void 2493 em_update_link_status(struct adapter *adapter) 2494 { 2495 struct ifnet *ifp = adapter->ifp; 2496 device_t dev = adapter->dev; 2497 2498 if (E1000_READ_REG(&adapter->hw, E1000_STATUS) & 2499 E1000_STATUS_LU) { 2500 if (adapter->link_active == 0) { 2501 e1000_get_speed_and_duplex(&adapter->hw, 2502 &adapter->link_speed, &adapter->link_duplex); 2503 /* Check if we must disable SPEED_MODE bit on PCI-E */ 2504 if ((adapter->link_speed != SPEED_1000) && 2505 ((adapter->hw.mac.type == e1000_82571) || 2506 (adapter->hw.mac.type == e1000_82572))) { 2507 int tarc0; 2508 2509 tarc0 = E1000_READ_REG(&adapter->hw, 2510 E1000_TARC(0)); 2511 tarc0 &= ~SPEED_MODE_BIT; 2512 E1000_WRITE_REG(&adapter->hw, 2513 E1000_TARC(0), tarc0); 2514 } 2515 if (bootverbose) 2516 device_printf(dev, "Link is up %d Mbps %s\n", 2517 adapter->link_speed, 2518 ((adapter->link_duplex == FULL_DUPLEX) ? 2519 "Full Duplex" : "Half Duplex")); 2520 adapter->link_active = 1; 2521 adapter->smartspeed = 0; 2522 ifp->if_baudrate = adapter->link_speed * 1000000; 2523 if_link_state_change(ifp, LINK_STATE_UP); 2524 } 2525 } else { 2526 if (adapter->link_active == 1) { 2527 ifp->if_baudrate = adapter->link_speed = 0; 2528 adapter->link_duplex = 0; 2529 if (bootverbose) 2530 device_printf(dev, "Link is Down\n"); 2531 adapter->link_active = 0; 2532 if_link_state_change(ifp, LINK_STATE_DOWN); 2533 } 2534 } 2535 } 2536 2537 /********************************************************************* 2538 * 2539 * This routine disables all traffic on the adapter by issuing a 2540 * global reset on the MAC and deallocates TX/RX buffers. 2541 * 2542 * This routine should always be called with BOTH the CORE 2543 * and TX locks. 2544 **********************************************************************/ 2545 2546 static void 2547 em_stop(void *arg) 2548 { 2549 struct adapter *adapter = arg; 2550 struct ifnet *ifp = adapter->ifp; 2551 2552 EM_CORE_LOCK_ASSERT(adapter); 2553 EM_TX_LOCK_ASSERT(adapter); 2554 2555 INIT_DEBUGOUT("em_stop: begin"); 2556 2557 em_disable_intr(adapter); 2558 callout_stop(&adapter->timer); 2559 callout_stop(&adapter->tx_fifo_timer); 2560 2561 /* Tell the stack that the interface is no longer active */ 2562 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2563 2564 e1000_reset_hw(&adapter->hw); 2565 if (adapter->hw.mac.type >= e1000_82544) 2566 E1000_WRITE_REG(&adapter->hw, E1000_WUC, 0); 2567 } 2568 2569 2570 /********************************************************************* 2571 * 2572 * Determine hardware revision. 2573 * 2574 **********************************************************************/ 2575 static void 2576 em_identify_hardware(struct adapter *adapter) 2577 { 2578 device_t dev = adapter->dev; 2579 2580 /* Make sure our PCI config space has the necessary stuff set */ 2581 adapter->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2); 2582 if (!((adapter->hw.bus.pci_cmd_word & PCIM_CMD_BUSMASTEREN) && 2583 (adapter->hw.bus.pci_cmd_word & PCIM_CMD_MEMEN))) { 2584 device_printf(dev, "Memory Access and/or Bus Master bits " 2585 "were not set!\n"); 2586 adapter->hw.bus.pci_cmd_word |= 2587 (PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN); 2588 pci_write_config(dev, PCIR_COMMAND, 2589 adapter->hw.bus.pci_cmd_word, 2); 2590 } 2591 2592 /* Save off the information about this board */ 2593 adapter->hw.vendor_id = pci_get_vendor(dev); 2594 adapter->hw.device_id = pci_get_device(dev); 2595 adapter->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1); 2596 adapter->hw.subsystem_vendor_id = 2597 pci_read_config(dev, PCIR_SUBVEND_0, 2); 2598 adapter->hw.subsystem_device_id = 2599 pci_read_config(dev, PCIR_SUBDEV_0, 2); 2600 2601 /* Do Shared Code Init and Setup */ 2602 if (e1000_set_mac_type(&adapter->hw)) { 2603 device_printf(dev, "Setup init failure\n"); 2604 return; 2605 } 2606 } 2607 2608 static int 2609 em_allocate_pci_resources(struct adapter *adapter) 2610 { 2611 device_t dev = adapter->dev; 2612 int val, rid; 2613 2614 rid = PCIR_BAR(0); 2615 adapter->res_memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 2616 &rid, RF_ACTIVE); 2617 if (adapter->res_memory == NULL) { 2618 device_printf(dev, "Unable to allocate bus resource: memory\n"); 2619 return (ENXIO); 2620 } 2621 adapter->osdep.mem_bus_space_tag = 2622 rman_get_bustag(adapter->res_memory); 2623 adapter->osdep.mem_bus_space_handle = 2624 rman_get_bushandle(adapter->res_memory); 2625 adapter->hw.hw_addr = (uint8_t *)&adapter->osdep.mem_bus_space_handle; 2626 2627 /* Only older adapters use IO mapping */ 2628 if ((adapter->hw.mac.type > e1000_82543) && 2629 (adapter->hw.mac.type < e1000_82571)) { 2630 /* Figure our where our IO BAR is ? */ 2631 for (rid = PCIR_BAR(0); rid < PCIR_CIS;) { 2632 val = pci_read_config(dev, rid, 4); 2633 if (EM_BAR_TYPE(val) == EM_BAR_TYPE_IO) { 2634 adapter->io_rid = rid; 2635 break; 2636 } 2637 rid += 4; 2638 /* check for 64bit BAR */ 2639 if (EM_BAR_MEM_TYPE(val) == EM_BAR_MEM_TYPE_64BIT) 2640 rid += 4; 2641 } 2642 if (rid >= PCIR_CIS) { 2643 device_printf(dev, "Unable to locate IO BAR\n"); 2644 return (ENXIO); 2645 } 2646 adapter->res_ioport = bus_alloc_resource_any(dev, 2647 SYS_RES_IOPORT, &adapter->io_rid, RF_ACTIVE); 2648 if (adapter->res_ioport == NULL) { 2649 device_printf(dev, "Unable to allocate bus resource: " 2650 "ioport\n"); 2651 return (ENXIO); 2652 } 2653 adapter->hw.io_base = 0; 2654 adapter->osdep.io_bus_space_tag = 2655 rman_get_bustag(adapter->res_ioport); 2656 adapter->osdep.io_bus_space_handle = 2657 rman_get_bushandle(adapter->res_ioport); 2658 } 2659 2660 /* 2661 * Setup MSI/X or MSI if PCI Express 2662 * only the latest can use MSI/X and 2663 * real support for it is forthcoming 2664 */ 2665 adapter->msi = 0; /* Set defaults */ 2666 rid = 0x0; 2667 2668 #if __FreeBSD_version > 602111 /* MSI support is present */ 2669 /* This will setup either MSI/X or MSI */ 2670 if (em_setup_msix(adapter)) 2671 rid = 1; 2672 #endif /* FreeBSD_version */ 2673 2674 adapter->res_interrupt = bus_alloc_resource_any(dev, 2675 SYS_RES_IRQ, &rid, RF_SHAREABLE | RF_ACTIVE); 2676 if (adapter->res_interrupt == NULL) { 2677 device_printf(dev, "Unable to allocate bus resource: " 2678 "interrupt\n"); 2679 return (ENXIO); 2680 } 2681 2682 adapter->hw.back = &adapter->osdep; 2683 2684 return (0); 2685 } 2686 2687 /********************************************************************* 2688 * 2689 * Setup the appropriate Interrupt handlers. 2690 * 2691 **********************************************************************/ 2692 int 2693 em_allocate_intr(struct adapter *adapter) 2694 { 2695 device_t dev = adapter->dev; 2696 int error; 2697 2698 /* Manually turn off all interrupts */ 2699 E1000_WRITE_REG(&adapter->hw, E1000_IMC, 0xffffffff); 2700 2701 #ifndef EM_FAST_IRQ 2702 /* We do Legacy setup */ 2703 if (adapter->int_handler_tag == NULL && 2704 (error = bus_setup_intr(dev, adapter->res_interrupt, 2705 #if __FreeBSD_version > 700000 2706 INTR_TYPE_NET | INTR_MPSAFE, NULL, em_intr, adapter, 2707 #else /* 6.X */ 2708 INTR_TYPE_NET | INTR_MPSAFE, em_intr, adapter, 2709 #endif 2710 &adapter->int_handler_tag)) != 0) { 2711 device_printf(dev, "Failed to register interrupt handler"); 2712 return (error); 2713 } 2714 2715 #else /* FAST_IRQ */ 2716 /* 2717 * Try allocating a fast interrupt and the associated deferred 2718 * processing contexts. 2719 */ 2720 TASK_INIT(&adapter->rxtx_task, 0, em_handle_rxtx, adapter); 2721 TASK_INIT(&adapter->link_task, 0, em_handle_link, adapter); 2722 adapter->tq = taskqueue_create_fast("em_taskq", M_NOWAIT, 2723 taskqueue_thread_enqueue, &adapter->tq); 2724 taskqueue_start_threads(&adapter->tq, 1, PI_NET, "%s taskq", 2725 device_get_nameunit(adapter->dev)); 2726 #if __FreeBSD_version < 700000 2727 if ((error = bus_setup_intr(dev, adapter->res_interrupt, 2728 INTR_TYPE_NET | INTR_FAST, em_intr_fast, adapter, 2729 #else 2730 if ((error = bus_setup_intr(dev, adapter->res_interrupt, 2731 INTR_TYPE_NET, em_intr_fast, NULL, adapter, 2732 #endif 2733 &adapter->int_handler_tag)) != 0) { 2734 device_printf(dev, "Failed to register fast interrupt " 2735 "handler: %d\n", error); 2736 taskqueue_free(adapter->tq); 2737 adapter->tq = NULL; 2738 return (error); 2739 } 2740 #endif /* EM_FAST_IRQ */ 2741 2742 em_enable_intr(adapter); 2743 return (0); 2744 } 2745 2746 static void 2747 em_free_intr(struct adapter *adapter) 2748 { 2749 device_t dev = adapter->dev; 2750 2751 if (adapter->res_interrupt != NULL) { 2752 bus_teardown_intr(dev, adapter->res_interrupt, 2753 adapter->int_handler_tag); 2754 adapter->int_handler_tag = NULL; 2755 } 2756 if (adapter->tq != NULL) { 2757 taskqueue_drain(adapter->tq, &adapter->rxtx_task); 2758 taskqueue_drain(taskqueue_fast, &adapter->link_task); 2759 taskqueue_free(adapter->tq); 2760 adapter->tq = NULL; 2761 } 2762 } 2763 2764 static void 2765 em_free_pci_resources(struct adapter *adapter) 2766 { 2767 device_t dev = adapter->dev; 2768 2769 if (adapter->res_interrupt != NULL) 2770 bus_release_resource(dev, SYS_RES_IRQ, 2771 adapter->msi ? 1 : 0, adapter->res_interrupt); 2772 2773 #if __FreeBSD_version > 602111 /* MSI support is present */ 2774 if (adapter->msix_mem != NULL) 2775 bus_release_resource(dev, SYS_RES_MEMORY, 2776 PCIR_BAR(EM_MSIX_BAR), adapter->msix_mem); 2777 2778 if (adapter->msi) 2779 pci_release_msi(dev); 2780 #endif /* FreeBSD_version */ 2781 2782 if (adapter->res_memory != NULL) 2783 bus_release_resource(dev, SYS_RES_MEMORY, 2784 PCIR_BAR(0), adapter->res_memory); 2785 2786 if (adapter->flash_mem != NULL) 2787 bus_release_resource(dev, SYS_RES_MEMORY, 2788 EM_FLASH, adapter->flash_mem); 2789 2790 if (adapter->res_ioport != NULL) 2791 bus_release_resource(dev, SYS_RES_IOPORT, 2792 adapter->io_rid, adapter->res_ioport); 2793 } 2794 2795 #if __FreeBSD_version > 602111 /* MSI support is present */ 2796 /* 2797 * Setup MSI/X 2798 */ 2799 static bool 2800 em_setup_msix(struct adapter *adapter) 2801 { 2802 device_t dev = adapter->dev; 2803 int rid, val; 2804 2805 if (adapter->hw.mac.type < e1000_82571) 2806 return (FALSE); 2807 2808 /* First try MSI/X if possible */ 2809 if (adapter->hw.mac.type >= e1000_82575) { 2810 rid = PCIR_BAR(EM_MSIX_BAR); 2811 adapter->msix_mem = bus_alloc_resource_any(dev, 2812 SYS_RES_MEMORY, &rid, RF_ACTIVE); 2813 if (!adapter->msix_mem) { 2814 /* May not be enabled */ 2815 device_printf(adapter->dev, 2816 "Unable to map MSIX table \n"); 2817 goto msi; 2818 } 2819 val = pci_msix_count(dev); 2820 if ((val) && pci_alloc_msix(dev, &val) == 0) { 2821 adapter->msi = 1; 2822 device_printf(adapter->dev,"Using MSIX interrupts\n"); 2823 return (TRUE); 2824 } 2825 } 2826 msi: 2827 val = pci_msi_count(dev); 2828 if (val == 1 && pci_alloc_msi(dev, &val) == 0) { 2829 adapter->msi = 1; 2830 device_printf(adapter->dev,"Using MSI interrupt\n"); 2831 return (TRUE); 2832 } 2833 return (FALSE); 2834 } 2835 #endif /* FreeBSD_version */ 2836 2837 /********************************************************************* 2838 * 2839 * Initialize the hardware to a configuration 2840 * as specified by the adapter structure. 2841 * 2842 **********************************************************************/ 2843 static int 2844 em_hardware_init(struct adapter *adapter) 2845 { 2846 device_t dev = adapter->dev; 2847 uint16_t rx_buffer_size; 2848 2849 INIT_DEBUGOUT("em_hardware_init: begin"); 2850 2851 /* Issue a global reset */ 2852 e1000_reset_hw(&adapter->hw); 2853 2854 /* Get control from any management/hw control */ 2855 if (((adapter->hw.mac.type == e1000_82573) || 2856 (adapter->hw.mac.type == e1000_ich8lan) || 2857 (adapter->hw.mac.type == e1000_ich9lan)) && 2858 e1000_check_mng_mode(&adapter->hw)) 2859 em_get_hw_control(adapter); 2860 2861 /* When hardware is reset, fifo_head is also reset */ 2862 adapter->tx_fifo_head = 0; 2863 2864 /* Set up smart power down as default off on newer adapters. */ 2865 if (!em_smart_pwr_down && (adapter->hw.mac.type == e1000_82571 || 2866 adapter->hw.mac.type == e1000_82572)) { 2867 uint16_t phy_tmp = 0; 2868 2869 /* Speed up time to link by disabling smart power down. */ 2870 e1000_read_phy_reg(&adapter->hw, 2871 IGP02E1000_PHY_POWER_MGMT, &phy_tmp); 2872 phy_tmp &= ~IGP02E1000_PM_SPD; 2873 e1000_write_phy_reg(&adapter->hw, 2874 IGP02E1000_PHY_POWER_MGMT, phy_tmp); 2875 } 2876 2877 /* 2878 * These parameters control the automatic generation (Tx) and 2879 * response (Rx) to Ethernet PAUSE frames. 2880 * - High water mark should allow for at least two frames to be 2881 * received after sending an XOFF. 2882 * - Low water mark works best when it is very near the high water mark. 2883 * This allows the receiver to restart by sending XON when it has 2884 * drained a bit. Here we use an arbitary value of 1500 which will 2885 * restart after one full frame is pulled from the buffer. There 2886 * could be several smaller frames in the buffer and if so they will 2887 * not trigger the XON until their total number reduces the buffer 2888 * by 1500. 2889 * - The pause time is fairly large at 1000 x 512ns = 512 usec. 2890 */ 2891 rx_buffer_size = ((E1000_READ_REG(&adapter->hw, E1000_PBA) & 2892 0xffff) << 10 ); 2893 2894 adapter->hw.fc.high_water = rx_buffer_size - 2895 roundup2(adapter->max_frame_size, 1024); 2896 adapter->hw.fc.low_water = adapter->hw.fc.high_water - 1500; 2897 2898 if (adapter->hw.mac.type == e1000_80003es2lan) 2899 adapter->hw.fc.pause_time = 0xFFFF; 2900 else 2901 adapter->hw.fc.pause_time = EM_FC_PAUSE_TIME; 2902 adapter->hw.fc.send_xon = TRUE; 2903 adapter->hw.fc.type = e1000_fc_full; 2904 2905 if (e1000_init_hw(&adapter->hw) < 0) { 2906 device_printf(dev, "Hardware Initialization Failed\n"); 2907 return (EIO); 2908 } 2909 2910 e1000_check_for_link(&adapter->hw); 2911 2912 return (0); 2913 } 2914 2915 /********************************************************************* 2916 * 2917 * Setup networking device structure and register an interface. 2918 * 2919 **********************************************************************/ 2920 static void 2921 em_setup_interface(device_t dev, struct adapter *adapter) 2922 { 2923 struct ifnet *ifp; 2924 2925 INIT_DEBUGOUT("em_setup_interface: begin"); 2926 2927 ifp = adapter->ifp = if_alloc(IFT_ETHER); 2928 if (ifp == NULL) 2929 panic("%s: can not if_alloc()", device_get_nameunit(dev)); 2930 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 2931 ifp->if_mtu = ETHERMTU; 2932 ifp->if_init = em_init; 2933 ifp->if_softc = adapter; 2934 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2935 ifp->if_ioctl = em_ioctl; 2936 ifp->if_start = em_start; 2937 IFQ_SET_MAXLEN(&ifp->if_snd, adapter->num_tx_desc - 1); 2938 ifp->if_snd.ifq_drv_maxlen = adapter->num_tx_desc - 1; 2939 IFQ_SET_READY(&ifp->if_snd); 2940 2941 ether_ifattach(ifp, adapter->hw.mac.addr); 2942 2943 ifp->if_capabilities = ifp->if_capenable = 0; 2944 2945 if (adapter->hw.mac.type >= e1000_82543) { 2946 int version_cap; 2947 #if __FreeBSD_version < 700000 2948 version_cap = IFCAP_HWCSUM; 2949 #else 2950 version_cap = IFCAP_HWCSUM | IFCAP_VLAN_HWCSUM; 2951 #endif 2952 ifp->if_capabilities |= version_cap; 2953 ifp->if_capenable |= version_cap; 2954 } 2955 2956 #if __FreeBSD_version >= 700000 2957 /* Identify TSO capable adapters */ 2958 if ((adapter->hw.mac.type > e1000_82544) && 2959 (adapter->hw.mac.type != e1000_82547)) 2960 ifp->if_capabilities |= IFCAP_TSO4; 2961 /* 2962 * By default only enable on PCI-E, this 2963 * can be overriden by ifconfig. 2964 */ 2965 if (adapter->hw.mac.type >= e1000_82571) 2966 ifp->if_capenable |= IFCAP_TSO4; 2967 #endif 2968 2969 /* 2970 * Tell the upper layer(s) we support long frames. 2971 */ 2972 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 2973 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU; 2974 ifp->if_capenable |= IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU; 2975 2976 #ifdef DEVICE_POLLING 2977 ifp->if_capabilities |= IFCAP_POLLING; 2978 #endif 2979 2980 /* 2981 * Specify the media types supported by this adapter and register 2982 * callbacks to update media and link information 2983 */ 2984 ifmedia_init(&adapter->media, IFM_IMASK, 2985 em_media_change, em_media_status); 2986 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) || 2987 (adapter->hw.phy.media_type == e1000_media_type_internal_serdes)) { 2988 u_char fiber_type = IFM_1000_SX; /* default type */ 2989 2990 if (adapter->hw.mac.type == e1000_82545) 2991 fiber_type = IFM_1000_LX; 2992 ifmedia_add(&adapter->media, IFM_ETHER | fiber_type | IFM_FDX, 2993 0, NULL); 2994 ifmedia_add(&adapter->media, IFM_ETHER | fiber_type, 0, NULL); 2995 } else { 2996 ifmedia_add(&adapter->media, IFM_ETHER | IFM_10_T, 0, NULL); 2997 ifmedia_add(&adapter->media, IFM_ETHER | IFM_10_T | IFM_FDX, 2998 0, NULL); 2999 ifmedia_add(&adapter->media, IFM_ETHER | IFM_100_TX, 3000 0, NULL); 3001 ifmedia_add(&adapter->media, IFM_ETHER | IFM_100_TX | IFM_FDX, 3002 0, NULL); 3003 if (adapter->hw.phy.type != e1000_phy_ife) { 3004 ifmedia_add(&adapter->media, 3005 IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 3006 ifmedia_add(&adapter->media, 3007 IFM_ETHER | IFM_1000_T, 0, NULL); 3008 } 3009 } 3010 ifmedia_add(&adapter->media, IFM_ETHER | IFM_AUTO, 0, NULL); 3011 ifmedia_set(&adapter->media, IFM_ETHER | IFM_AUTO); 3012 } 3013 3014 3015 /********************************************************************* 3016 * 3017 * Workaround for SmartSpeed on 82541 and 82547 controllers 3018 * 3019 **********************************************************************/ 3020 static void 3021 em_smartspeed(struct adapter *adapter) 3022 { 3023 uint16_t phy_tmp; 3024 3025 if (adapter->link_active || (adapter->hw.phy.type != e1000_phy_igp) || 3026 adapter->hw.mac.autoneg == 0 || 3027 (adapter->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0) 3028 return; 3029 3030 if (adapter->smartspeed == 0) { 3031 /* If Master/Slave config fault is asserted twice, 3032 * we assume back-to-back */ 3033 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp); 3034 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT)) 3035 return; 3036 e1000_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp); 3037 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) { 3038 e1000_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_tmp); 3039 if(phy_tmp & CR_1000T_MS_ENABLE) { 3040 phy_tmp &= ~CR_1000T_MS_ENABLE; 3041 e1000_write_phy_reg(&adapter->hw, PHY_1000T_CTRL, 3042 phy_tmp); 3043 adapter->smartspeed++; 3044 if(adapter->hw.mac.autoneg && 3045 !e1000_phy_setup_autoneg(&adapter->hw) && 3046 !e1000_read_phy_reg(&adapter->hw, PHY_CONTROL, 3047 &phy_tmp)) { 3048 phy_tmp |= (MII_CR_AUTO_NEG_EN | 3049 MII_CR_RESTART_AUTO_NEG); 3050 e1000_write_phy_reg(&adapter->hw, PHY_CONTROL, 3051 phy_tmp); 3052 } 3053 } 3054 } 3055 return; 3056 } else if(adapter->smartspeed == EM_SMARTSPEED_DOWNSHIFT) { 3057 /* If still no link, perhaps using 2/3 pair cable */ 3058 e1000_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_tmp); 3059 phy_tmp |= CR_1000T_MS_ENABLE; 3060 e1000_write_phy_reg(&adapter->hw, PHY_1000T_CTRL, phy_tmp); 3061 if(adapter->hw.mac.autoneg && 3062 !e1000_phy_setup_autoneg(&adapter->hw) && 3063 !e1000_read_phy_reg(&adapter->hw, PHY_CONTROL, &phy_tmp)) { 3064 phy_tmp |= (MII_CR_AUTO_NEG_EN | 3065 MII_CR_RESTART_AUTO_NEG); 3066 e1000_write_phy_reg(&adapter->hw, PHY_CONTROL, phy_tmp); 3067 } 3068 } 3069 /* Restart process after EM_SMARTSPEED_MAX iterations */ 3070 if(adapter->smartspeed++ == EM_SMARTSPEED_MAX) 3071 adapter->smartspeed = 0; 3072 } 3073 3074 3075 /* 3076 * Manage DMA'able memory. 3077 */ 3078 static void 3079 em_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 3080 { 3081 if (error) 3082 return; 3083 *(bus_addr_t *) arg = segs[0].ds_addr; 3084 } 3085 3086 static int 3087 em_dma_malloc(struct adapter *adapter, bus_size_t size, 3088 struct em_dma_alloc *dma, int mapflags) 3089 { 3090 int error; 3091 3092 #if __FreeBSD_version >= 700000 3093 error = bus_dma_tag_create(bus_get_dma_tag(adapter->dev), /* parent */ 3094 #else 3095 error = bus_dma_tag_create(NULL, /* parent */ 3096 #endif 3097 EM_DBA_ALIGN, 0, /* alignment, bounds */ 3098 BUS_SPACE_MAXADDR, /* lowaddr */ 3099 BUS_SPACE_MAXADDR, /* highaddr */ 3100 NULL, NULL, /* filter, filterarg */ 3101 size, /* maxsize */ 3102 1, /* nsegments */ 3103 size, /* maxsegsize */ 3104 0, /* flags */ 3105 NULL, /* lockfunc */ 3106 NULL, /* lockarg */ 3107 &dma->dma_tag); 3108 if (error) { 3109 device_printf(adapter->dev, 3110 "%s: bus_dma_tag_create failed: %d\n", 3111 __func__, error); 3112 goto fail_0; 3113 } 3114 3115 error = bus_dmamem_alloc(dma->dma_tag, (void**) &dma->dma_vaddr, 3116 BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &dma->dma_map); 3117 if (error) { 3118 device_printf(adapter->dev, 3119 "%s: bus_dmamem_alloc(%ju) failed: %d\n", 3120 __func__, (uintmax_t)size, error); 3121 goto fail_2; 3122 } 3123 3124 dma->dma_paddr = 0; 3125 error = bus_dmamap_load(dma->dma_tag, dma->dma_map, dma->dma_vaddr, 3126 size, em_dmamap_cb, &dma->dma_paddr, mapflags | BUS_DMA_NOWAIT); 3127 if (error || dma->dma_paddr == 0) { 3128 device_printf(adapter->dev, 3129 "%s: bus_dmamap_load failed: %d\n", 3130 __func__, error); 3131 goto fail_3; 3132 } 3133 3134 return (0); 3135 3136 fail_3: 3137 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 3138 fail_2: 3139 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 3140 bus_dma_tag_destroy(dma->dma_tag); 3141 fail_0: 3142 dma->dma_map = NULL; 3143 dma->dma_tag = NULL; 3144 3145 return (error); 3146 } 3147 3148 static void 3149 em_dma_free(struct adapter *adapter, struct em_dma_alloc *dma) 3150 { 3151 if (dma->dma_tag == NULL) 3152 return; 3153 if (dma->dma_map != NULL) { 3154 bus_dmamap_sync(dma->dma_tag, dma->dma_map, 3155 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3156 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 3157 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 3158 dma->dma_map = NULL; 3159 } 3160 bus_dma_tag_destroy(dma->dma_tag); 3161 dma->dma_tag = NULL; 3162 } 3163 3164 3165 /********************************************************************* 3166 * 3167 * Allocate memory for tx_buffer structures. The tx_buffer stores all 3168 * the information needed to transmit a packet on the wire. 3169 * 3170 **********************************************************************/ 3171 static int 3172 em_allocate_transmit_structures(struct adapter *adapter) 3173 { 3174 device_t dev = adapter->dev; 3175 struct em_buffer *tx_buffer; 3176 int error; 3177 3178 /* 3179 * Create DMA tags for tx descriptors 3180 */ 3181 #if __FreeBSD_version >= 700000 3182 if ((error = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 3183 #else 3184 if ((error = bus_dma_tag_create(NULL, /* parent */ 3185 #endif 3186 1, 0, /* alignment, bounds */ 3187 BUS_SPACE_MAXADDR, /* lowaddr */ 3188 BUS_SPACE_MAXADDR, /* highaddr */ 3189 NULL, NULL, /* filter, filterarg */ 3190 EM_TSO_SIZE, /* maxsize */ 3191 EM_MAX_SCATTER, /* nsegments */ 3192 EM_TSO_SEG_SIZE, /* maxsegsize */ 3193 0, /* flags */ 3194 NULL, /* lockfunc */ 3195 NULL, /* lockarg */ 3196 &adapter->txtag)) != 0) { 3197 device_printf(dev, "Unable to allocate TX DMA tag\n"); 3198 goto fail; 3199 } 3200 3201 adapter->tx_buffer_area = malloc(sizeof(struct em_buffer) * 3202 adapter->num_tx_desc, M_DEVBUF, M_NOWAIT | M_ZERO); 3203 if (adapter->tx_buffer_area == NULL) { 3204 device_printf(dev, "Unable to allocate tx_buffer memory\n"); 3205 error = ENOMEM; 3206 goto fail; 3207 } 3208 3209 /* Create the descriptor buffer dma maps */ 3210 for (int i = 0; i < adapter->num_tx_desc; i++) { 3211 tx_buffer = &adapter->tx_buffer_area[i]; 3212 error = bus_dmamap_create(adapter->txtag, 0, &tx_buffer->map); 3213 if (error != 0) { 3214 device_printf(dev, "Unable to create TX DMA map\n"); 3215 goto fail; 3216 } 3217 tx_buffer->next_eop = -1; 3218 } 3219 3220 return (0); 3221 fail: 3222 em_free_transmit_structures(adapter); 3223 return (error); 3224 } 3225 3226 /********************************************************************* 3227 * 3228 * (Re)Initialize transmit structures. 3229 * 3230 **********************************************************************/ 3231 static void 3232 em_setup_transmit_structures(struct adapter *adapter) 3233 { 3234 struct em_buffer *tx_buffer; 3235 3236 /* Clear the old ring contents */ 3237 bzero(adapter->tx_desc_base, 3238 (sizeof(struct e1000_tx_desc)) * adapter->num_tx_desc); 3239 3240 /* Free any existing TX buffers */ 3241 for (int i = 0; i < adapter->num_tx_desc; i++, tx_buffer++) { 3242 tx_buffer = &adapter->tx_buffer_area[i]; 3243 bus_dmamap_sync(adapter->txtag, tx_buffer->map, 3244 BUS_DMASYNC_POSTWRITE); 3245 bus_dmamap_unload(adapter->txtag, tx_buffer->map); 3246 m_freem(tx_buffer->m_head); 3247 tx_buffer->m_head = NULL; 3248 tx_buffer->next_eop = -1; 3249 } 3250 3251 /* Reset state */ 3252 adapter->next_avail_tx_desc = 0; 3253 adapter->next_tx_to_clean = 0; 3254 adapter->num_tx_desc_avail = adapter->num_tx_desc; 3255 3256 bus_dmamap_sync(adapter->txdma.dma_tag, adapter->txdma.dma_map, 3257 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3258 3259 return; 3260 } 3261 3262 /********************************************************************* 3263 * 3264 * Enable transmit unit. 3265 * 3266 **********************************************************************/ 3267 static void 3268 em_initialize_transmit_unit(struct adapter *adapter) 3269 { 3270 uint32_t tctl, tarc, tipg = 0; 3271 uint64_t bus_addr; 3272 3273 INIT_DEBUGOUT("em_initialize_transmit_unit: begin"); 3274 /* Setup the Base and Length of the Tx Descriptor Ring */ 3275 bus_addr = adapter->txdma.dma_paddr; 3276 E1000_WRITE_REG(&adapter->hw, E1000_TDLEN(0), 3277 adapter->num_tx_desc * sizeof(struct e1000_tx_desc)); 3278 E1000_WRITE_REG(&adapter->hw, E1000_TDBAH(0), 3279 (uint32_t)(bus_addr >> 32)); 3280 E1000_WRITE_REG(&adapter->hw, E1000_TDBAL(0), 3281 (uint32_t)bus_addr); 3282 /* Setup the HW Tx Head and Tail descriptor pointers */ 3283 E1000_WRITE_REG(&adapter->hw, E1000_TDT(0), 0); 3284 E1000_WRITE_REG(&adapter->hw, E1000_TDH(0), 0); 3285 3286 HW_DEBUGOUT2("Base = %x, Length = %x\n", 3287 E1000_READ_REG(&adapter->hw, E1000_TDBAL(0)), 3288 E1000_READ_REG(&adapter->hw, E1000_TDLEN(0))); 3289 3290 /* Set the default values for the Tx Inter Packet Gap timer */ 3291 switch (adapter->hw.mac.type) { 3292 case e1000_82542: 3293 tipg = DEFAULT_82542_TIPG_IPGT; 3294 tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 3295 tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 3296 break; 3297 case e1000_80003es2lan: 3298 tipg = DEFAULT_82543_TIPG_IPGR1; 3299 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 << 3300 E1000_TIPG_IPGR2_SHIFT; 3301 break; 3302 default: 3303 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) || 3304 (adapter->hw.phy.media_type == 3305 e1000_media_type_internal_serdes)) 3306 tipg = DEFAULT_82543_TIPG_IPGT_FIBER; 3307 else 3308 tipg = DEFAULT_82543_TIPG_IPGT_COPPER; 3309 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 3310 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 3311 } 3312 3313 E1000_WRITE_REG(&adapter->hw, E1000_TIPG, tipg); 3314 E1000_WRITE_REG(&adapter->hw, E1000_TIDV, adapter->tx_int_delay.value); 3315 if(adapter->hw.mac.type >= e1000_82540) 3316 E1000_WRITE_REG(&adapter->hw, E1000_TADV, 3317 adapter->tx_abs_int_delay.value); 3318 3319 if ((adapter->hw.mac.type == e1000_82571) || 3320 (adapter->hw.mac.type == e1000_82572)) { 3321 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0)); 3322 tarc |= SPEED_MODE_BIT; 3323 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc); 3324 } else if (adapter->hw.mac.type == e1000_80003es2lan) { 3325 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(0)); 3326 tarc |= 1; 3327 E1000_WRITE_REG(&adapter->hw, E1000_TARC(0), tarc); 3328 tarc = E1000_READ_REG(&adapter->hw, E1000_TARC(1)); 3329 tarc |= 1; 3330 E1000_WRITE_REG(&adapter->hw, E1000_TARC(1), tarc); 3331 } 3332 3333 /* Program the Transmit Control Register */ 3334 tctl = E1000_READ_REG(&adapter->hw, E1000_TCTL); 3335 tctl &= ~E1000_TCTL_CT; 3336 tctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN | 3337 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT)); 3338 3339 if (adapter->hw.mac.type >= e1000_82571) 3340 tctl |= E1000_TCTL_MULR; 3341 3342 /* This write will effectively turn on the transmit unit. */ 3343 E1000_WRITE_REG(&adapter->hw, E1000_TCTL, tctl); 3344 3345 /* Setup Transmit Descriptor Base Settings */ 3346 adapter->txd_cmd = E1000_TXD_CMD_IFCS; 3347 3348 if ((adapter->tx_int_delay.value > 0) && 3349 (adapter->hw.mac.type != e1000_82575)) 3350 adapter->txd_cmd |= E1000_TXD_CMD_IDE; 3351 3352 /* Set the function pointer for the transmit routine */ 3353 if (adapter->hw.mac.type >= e1000_82575) 3354 adapter->em_xmit = em_adv_encap; 3355 else 3356 adapter->em_xmit = em_encap; 3357 } 3358 3359 /********************************************************************* 3360 * 3361 * Free all transmit related data structures. 3362 * 3363 **********************************************************************/ 3364 static void 3365 em_free_transmit_structures(struct adapter *adapter) 3366 { 3367 struct em_buffer *tx_buffer; 3368 3369 INIT_DEBUGOUT("free_transmit_structures: begin"); 3370 3371 if (adapter->tx_buffer_area != NULL) { 3372 for (int i = 0; i < adapter->num_tx_desc; i++) { 3373 tx_buffer = &adapter->tx_buffer_area[i]; 3374 if (tx_buffer->m_head != NULL) { 3375 bus_dmamap_sync(adapter->txtag, tx_buffer->map, 3376 BUS_DMASYNC_POSTWRITE); 3377 bus_dmamap_unload(adapter->txtag, 3378 tx_buffer->map); 3379 m_freem(tx_buffer->m_head); 3380 tx_buffer->m_head = NULL; 3381 } else if (tx_buffer->map != NULL) 3382 bus_dmamap_unload(adapter->txtag, 3383 tx_buffer->map); 3384 if (tx_buffer->map != NULL) { 3385 bus_dmamap_destroy(adapter->txtag, 3386 tx_buffer->map); 3387 tx_buffer->map = NULL; 3388 } 3389 } 3390 } 3391 if (adapter->tx_buffer_area != NULL) { 3392 free(adapter->tx_buffer_area, M_DEVBUF); 3393 adapter->tx_buffer_area = NULL; 3394 } 3395 if (adapter->txtag != NULL) { 3396 bus_dma_tag_destroy(adapter->txtag); 3397 adapter->txtag = NULL; 3398 } 3399 } 3400 3401 /********************************************************************* 3402 * 3403 * The offload context needs to be set when we transfer the first 3404 * packet of a particular protocol (TCP/UDP). This routine has been 3405 * enhanced to deal with inserted VLAN headers, and IPV6 (not complete) 3406 * 3407 **********************************************************************/ 3408 static void 3409 em_transmit_checksum_setup(struct adapter *adapter, struct mbuf *mp, 3410 uint32_t *txd_upper, uint32_t *txd_lower) 3411 { 3412 struct e1000_context_desc *TXD; 3413 struct em_buffer *tx_buffer; 3414 struct ether_vlan_header *eh; 3415 struct ip *ip; 3416 struct ip6_hdr *ip6; 3417 struct tcp_hdr *th; 3418 int curr_txd, ehdrlen, hdr_len, ip_hlen; 3419 uint32_t cmd = 0; 3420 uint16_t etype; 3421 uint8_t ipproto; 3422 3423 /* Setup checksum offload context. */ 3424 curr_txd = adapter->next_avail_tx_desc; 3425 tx_buffer = &adapter->tx_buffer_area[curr_txd]; 3426 TXD = (struct e1000_context_desc *) &adapter->tx_desc_base[curr_txd]; 3427 3428 *txd_lower = E1000_TXD_CMD_DEXT | /* Extended descr type */ 3429 E1000_TXD_DTYP_D; /* Data descr */ 3430 3431 /* 3432 * Determine where frame payload starts. 3433 * Jump over vlan headers if already present, 3434 * helpful for QinQ too. 3435 */ 3436 eh = mtod(mp, struct ether_vlan_header *); 3437 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 3438 etype = ntohs(eh->evl_proto); 3439 ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 3440 } else { 3441 etype = ntohs(eh->evl_encap_proto); 3442 ehdrlen = ETHER_HDR_LEN; 3443 } 3444 3445 /* 3446 * We only support TCP/UDP for IPv4 and IPv6 for the moment. 3447 * TODO: Support SCTP too when it hits the tree. 3448 */ 3449 switch (etype) { 3450 case ETHERTYPE_IP: 3451 ip = (struct ip *)(mp->m_data + ehdrlen); 3452 ip_hlen = ip->ip_hl << 2; 3453 3454 /* Setup of IP header checksum. */ 3455 if (mp->m_pkthdr.csum_flags & CSUM_IP) { 3456 /* 3457 * Start offset for header checksum calculation. 3458 * End offset for header checksum calculation. 3459 * Offset of place to put the checksum. 3460 */ 3461 TXD->lower_setup.ip_fields.ipcss = ehdrlen; 3462 TXD->lower_setup.ip_fields.ipcse = 3463 htole16(ehdrlen + ip_hlen); 3464 TXD->lower_setup.ip_fields.ipcso = 3465 ehdrlen + offsetof(struct ip, ip_sum); 3466 cmd |= E1000_TXD_CMD_IP; 3467 *txd_upper |= E1000_TXD_POPTS_IXSM << 8; 3468 } 3469 3470 if (mp->m_len < ehdrlen + ip_hlen) 3471 return; /* failure */ 3472 3473 hdr_len = ehdrlen + ip_hlen; 3474 ipproto = ip->ip_p; 3475 3476 break; 3477 case ETHERTYPE_IPV6: 3478 ip6 = (struct ip6_hdr *)(mp->m_data + ehdrlen); 3479 ip_hlen = sizeof(struct ip6_hdr); /* XXX: No header stacking. */ 3480 3481 if (mp->m_len < ehdrlen + ip_hlen) 3482 return; /* failure */ 3483 3484 /* IPv6 doesn't have a header checksum. */ 3485 3486 hdr_len = ehdrlen + ip_hlen; 3487 ipproto = ip6->ip6_nxt; 3488 3489 break; 3490 default: 3491 *txd_upper = 0; 3492 *txd_lower = 0; 3493 return; 3494 } 3495 3496 switch (ipproto) { 3497 case IPPROTO_TCP: 3498 if (mp->m_pkthdr.csum_flags & CSUM_TCP) { 3499 /* 3500 * Start offset for payload checksum calculation. 3501 * End offset for payload checksum calculation. 3502 * Offset of place to put the checksum. 3503 */ 3504 th = (struct tcp_hdr *)(mp->m_data + hdr_len); 3505 TXD->upper_setup.tcp_fields.tucss = hdr_len; 3506 TXD->upper_setup.tcp_fields.tucse = htole16(0); 3507 TXD->upper_setup.tcp_fields.tucso = 3508 hdr_len + offsetof(struct tcphdr, th_sum); 3509 cmd |= E1000_TXD_CMD_TCP; 3510 *txd_upper |= E1000_TXD_POPTS_TXSM << 8; 3511 } 3512 break; 3513 case IPPROTO_UDP: 3514 if (mp->m_pkthdr.csum_flags & CSUM_UDP) { 3515 /* 3516 * Start offset for header checksum calculation. 3517 * End offset for header checksum calculation. 3518 * Offset of place to put the checksum. 3519 */ 3520 TXD->upper_setup.tcp_fields.tucss = hdr_len; 3521 TXD->upper_setup.tcp_fields.tucse = htole16(0); 3522 TXD->upper_setup.tcp_fields.tucso = 3523 hdr_len + offsetof(struct udphdr, uh_sum); 3524 *txd_upper |= E1000_TXD_POPTS_TXSM << 8; 3525 } 3526 break; 3527 default: 3528 break; 3529 } 3530 3531 TXD->tcp_seg_setup.data = htole32(0); 3532 TXD->cmd_and_length = 3533 htole32(adapter->txd_cmd | E1000_TXD_CMD_DEXT | cmd); 3534 tx_buffer->m_head = NULL; 3535 tx_buffer->next_eop = -1; 3536 3537 if (++curr_txd == adapter->num_tx_desc) 3538 curr_txd = 0; 3539 3540 adapter->num_tx_desc_avail--; 3541 adapter->next_avail_tx_desc = curr_txd; 3542 } 3543 3544 3545 #if __FreeBSD_version >= 700000 3546 /********************************************************************** 3547 * 3548 * Setup work for hardware segmentation offload (TSO) 3549 * 3550 **********************************************************************/ 3551 static bool 3552 em_tso_setup(struct adapter *adapter, struct mbuf *mp, uint32_t *txd_upper, 3553 uint32_t *txd_lower) 3554 { 3555 struct e1000_context_desc *TXD; 3556 struct em_buffer *tx_buffer; 3557 struct ether_vlan_header *eh; 3558 struct ip *ip; 3559 struct ip6_hdr *ip6; 3560 struct tcphdr *th; 3561 int curr_txd, ehdrlen, hdr_len, ip_hlen, isip6; 3562 uint16_t etype; 3563 3564 /* 3565 * This function could/should be extended to support IP/IPv6 3566 * fragmentation as well. But as they say, one step at a time. 3567 */ 3568 3569 /* 3570 * Determine where frame payload starts. 3571 * Jump over vlan headers if already present, 3572 * helpful for QinQ too. 3573 */ 3574 eh = mtod(mp, struct ether_vlan_header *); 3575 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 3576 etype = ntohs(eh->evl_proto); 3577 ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 3578 } else { 3579 etype = ntohs(eh->evl_encap_proto); 3580 ehdrlen = ETHER_HDR_LEN; 3581 } 3582 3583 /* Ensure we have at least the IP+TCP header in the first mbuf. */ 3584 if (mp->m_len < ehdrlen + sizeof(struct ip) + sizeof(struct tcphdr)) 3585 return FALSE; /* -1 */ 3586 3587 /* 3588 * We only support TCP for IPv4 and IPv6 (notyet) for the moment. 3589 * TODO: Support SCTP too when it hits the tree. 3590 */ 3591 switch (etype) { 3592 case ETHERTYPE_IP: 3593 isip6 = 0; 3594 ip = (struct ip *)(mp->m_data + ehdrlen); 3595 if (ip->ip_p != IPPROTO_TCP) 3596 return FALSE; /* 0 */ 3597 ip->ip_len = 0; 3598 ip->ip_sum = 0; 3599 ip_hlen = ip->ip_hl << 2; 3600 if (mp->m_len < ehdrlen + ip_hlen + sizeof(struct tcphdr)) 3601 return FALSE; /* -1 */ 3602 th = (struct tcphdr *)((caddr_t)ip + ip_hlen); 3603 #if 1 3604 th->th_sum = in_pseudo(ip->ip_src.s_addr, 3605 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 3606 #else 3607 th->th_sum = mp->m_pkthdr.csum_data; 3608 #endif 3609 break; 3610 case ETHERTYPE_IPV6: 3611 isip6 = 1; 3612 return FALSE; /* Not supported yet. */ 3613 ip6 = (struct ip6_hdr *)(mp->m_data + ehdrlen); 3614 if (ip6->ip6_nxt != IPPROTO_TCP) 3615 return FALSE; /* 0 */ 3616 ip6->ip6_plen = 0; 3617 ip_hlen = sizeof(struct ip6_hdr); /* XXX: no header stacking. */ 3618 if (mp->m_len < ehdrlen + ip_hlen + sizeof(struct tcphdr)) 3619 return FALSE; /* -1 */ 3620 th = (struct tcphdr *)((caddr_t)ip6 + ip_hlen); 3621 #if 0 3622 th->th_sum = in6_pseudo(ip6->ip6_src, ip->ip6_dst, 3623 htons(IPPROTO_TCP)); /* XXX: function notyet. */ 3624 #else 3625 th->th_sum = mp->m_pkthdr.csum_data; 3626 #endif 3627 break; 3628 default: 3629 return FALSE; 3630 } 3631 hdr_len = ehdrlen + ip_hlen + (th->th_off << 2); 3632 3633 *txd_lower = (E1000_TXD_CMD_DEXT | /* Extended descr type */ 3634 E1000_TXD_DTYP_D | /* Data descr type */ 3635 E1000_TXD_CMD_TSE); /* Do TSE on this packet */ 3636 3637 /* IP and/or TCP header checksum calculation and insertion. */ 3638 *txd_upper = ((isip6 ? 0 : E1000_TXD_POPTS_IXSM) | 3639 E1000_TXD_POPTS_TXSM) << 8; 3640 3641 curr_txd = adapter->next_avail_tx_desc; 3642 tx_buffer = &adapter->tx_buffer_area[curr_txd]; 3643 TXD = (struct e1000_context_desc *) &adapter->tx_desc_base[curr_txd]; 3644 3645 /* IPv6 doesn't have a header checksum. */ 3646 if (!isip6) { 3647 /* 3648 * Start offset for header checksum calculation. 3649 * End offset for header checksum calculation. 3650 * Offset of place put the checksum. 3651 */ 3652 TXD->lower_setup.ip_fields.ipcss = ehdrlen; 3653 TXD->lower_setup.ip_fields.ipcse = 3654 htole16(ehdrlen + ip_hlen - 1); 3655 TXD->lower_setup.ip_fields.ipcso = 3656 ehdrlen + offsetof(struct ip, ip_sum); 3657 } 3658 /* 3659 * Start offset for payload checksum calculation. 3660 * End offset for payload checksum calculation. 3661 * Offset of place to put the checksum. 3662 */ 3663 TXD->upper_setup.tcp_fields.tucss = 3664 ehdrlen + ip_hlen; 3665 TXD->upper_setup.tcp_fields.tucse = 0; 3666 TXD->upper_setup.tcp_fields.tucso = 3667 ehdrlen + ip_hlen + offsetof(struct tcphdr, th_sum); 3668 /* 3669 * Payload size per packet w/o any headers. 3670 * Length of all headers up to payload. 3671 */ 3672 TXD->tcp_seg_setup.fields.mss = htole16(mp->m_pkthdr.tso_segsz); 3673 TXD->tcp_seg_setup.fields.hdr_len = hdr_len; 3674 3675 TXD->cmd_and_length = htole32(adapter->txd_cmd | 3676 E1000_TXD_CMD_DEXT | /* Extended descr */ 3677 E1000_TXD_CMD_TSE | /* TSE context */ 3678 (isip6 ? 0 : E1000_TXD_CMD_IP) | /* Do IP csum */ 3679 E1000_TXD_CMD_TCP | /* Do TCP checksum */ 3680 (mp->m_pkthdr.len - (hdr_len))); /* Total len */ 3681 3682 tx_buffer->m_head = NULL; 3683 tx_buffer->next_eop = -1; 3684 3685 if (++curr_txd == adapter->num_tx_desc) 3686 curr_txd = 0; 3687 3688 adapter->num_tx_desc_avail--; 3689 adapter->next_avail_tx_desc = curr_txd; 3690 adapter->tx_tso = TRUE; 3691 3692 return TRUE; 3693 } 3694 3695 3696 /********************************************************************** 3697 * 3698 * Setup work for hardware segmentation offload (TSO) on 3699 * adapters using advanced tx descriptors (82575) 3700 * 3701 **********************************************************************/ 3702 static boolean_t 3703 em_tso_adv_setup(struct adapter *adapter, struct mbuf *mp, u32 *hdrlen) 3704 { 3705 struct e1000_adv_tx_context_desc *TXD; 3706 struct em_buffer *tx_buffer; 3707 u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0; 3708 u32 mss_l4len_idx = 0; 3709 u16 vtag = 0; 3710 int ctxd, ehdrlen, ip_hlen, tcp_hlen; 3711 struct ether_vlan_header *eh; 3712 struct ip *ip; 3713 struct tcphdr *th; 3714 3715 /* 3716 * Determine where frame payload starts. 3717 * Jump over vlan headers if already present 3718 */ 3719 eh = mtod(mp, struct ether_vlan_header *); 3720 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) 3721 ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 3722 else 3723 ehdrlen = ETHER_HDR_LEN; 3724 3725 /* Ensure we have at least the IP+TCP header in the first mbuf. */ 3726 if (mp->m_len < ehdrlen + sizeof(struct ip) + sizeof(struct tcphdr)) 3727 return FALSE; 3728 3729 /* Only supports IPV4 for now */ 3730 ctxd = adapter->next_avail_tx_desc; 3731 tx_buffer = &adapter->tx_buffer_area[ctxd]; 3732 TXD = (struct e1000_adv_tx_context_desc *) &adapter->tx_desc_base[ctxd]; 3733 3734 ip = (struct ip *)(mp->m_data + ehdrlen); 3735 if (ip->ip_p != IPPROTO_TCP) 3736 return FALSE; /* 0 */ 3737 ip->ip_len = 0; 3738 ip->ip_sum = 0; 3739 ip_hlen = ip->ip_hl << 2; 3740 th = (struct tcphdr *)((caddr_t)ip + ip_hlen); 3741 th->th_sum = in_pseudo(ip->ip_src.s_addr, 3742 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 3743 tcp_hlen = th->th_off << 2; 3744 /* 3745 * Calculate header length, this is used 3746 * in the transmit desc in igb_encap 3747 */ 3748 *hdrlen = ehdrlen + ip_hlen + tcp_hlen; 3749 3750 /* VLAN MACLEN IPLEN */ 3751 if (mp->m_flags & M_VLANTAG) { 3752 vtag = htole16(mp->m_pkthdr.ether_vtag); 3753 vlan_macip_lens |= (vtag << E1000_ADVTXD_VLAN_SHIFT); 3754 } 3755 3756 vlan_macip_lens |= (ehdrlen << E1000_ADVTXD_MACLEN_SHIFT); 3757 vlan_macip_lens |= ip_hlen; 3758 TXD->vlan_macip_lens |= htole32(vlan_macip_lens); 3759 3760 /* ADV DTYPE TUCMD */ 3761 type_tucmd_mlhl |= E1000_ADVTXD_DCMD_DEXT | E1000_ADVTXD_DTYP_CTXT; 3762 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_TCP; 3763 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_IPV4; 3764 TXD->type_tucmd_mlhl |= htole32(type_tucmd_mlhl); 3765 3766 /* MSS L4LEN IDX */ 3767 mss_l4len_idx |= (mp->m_pkthdr.tso_segsz << E1000_ADVTXD_MSS_SHIFT); 3768 mss_l4len_idx |= (tcp_hlen << E1000_ADVTXD_L4LEN_SHIFT); 3769 TXD->mss_l4len_idx = htole32(mss_l4len_idx); 3770 3771 TXD->seqnum_seed = htole32(0); 3772 tx_buffer->m_head = NULL; 3773 tx_buffer->next_eop = -1; 3774 3775 if (++ctxd == adapter->num_tx_desc) 3776 ctxd = 0; 3777 3778 adapter->num_tx_desc_avail--; 3779 adapter->next_avail_tx_desc = ctxd; 3780 return TRUE; 3781 } 3782 3783 #endif /* FreeBSD_version >= 700000 */ 3784 3785 /********************************************************************* 3786 * 3787 * Advanced Context Descriptor setup for VLAN or CSUM 3788 * 3789 **********************************************************************/ 3790 3791 static boolean_t 3792 em_tx_adv_ctx_setup(struct adapter *adapter, struct mbuf *mp) 3793 { 3794 struct e1000_adv_tx_context_desc *TXD; 3795 struct em_buffer *tx_buffer; 3796 uint32_t vlan_macip_lens = 0, type_tucmd_mlhl = 0; 3797 struct ether_vlan_header *eh; 3798 struct ip *ip; 3799 struct ip6_hdr *ip6; 3800 int ehdrlen, ip_hlen = 0; 3801 u16 etype; 3802 u8 ipproto = 0; 3803 bool offload = TRUE; 3804 #if __FreeBSD_version < 700000 3805 struct m_tag *mtag; 3806 #else 3807 u16 vtag = 0; 3808 #endif 3809 3810 int ctxd = adapter->next_avail_tx_desc; 3811 tx_buffer = &adapter->tx_buffer_area[ctxd]; 3812 TXD = (struct e1000_adv_tx_context_desc *) &adapter->tx_desc_base[ctxd]; 3813 3814 if ((mp->m_pkthdr.csum_flags & CSUM_OFFLOAD) == 0) 3815 offload = FALSE; /* Only here to handle VLANs */ 3816 /* 3817 ** In advanced descriptors the vlan tag must 3818 ** be placed into the descriptor itself. 3819 */ 3820 #if __FreeBSD_version < 700000 3821 mtag = VLAN_OUTPUT_TAG(ifp, mp); 3822 if (mtag != NULL) { 3823 vlan_macip_lens |= 3824 htole16(VLAN_TAG_VALUE(mtag)) << E1000_ADVTXD_VLAN_SHIFT; 3825 } else if (offload == FALSE) 3826 return FALSE; /* No CTX needed */ 3827 #else 3828 if (mp->m_flags & M_VLANTAG) { 3829 vtag = htole16(mp->m_pkthdr.ether_vtag); 3830 vlan_macip_lens |= (vtag << E1000_ADVTXD_VLAN_SHIFT); 3831 } else if (offload == FALSE) 3832 return FALSE; 3833 #endif 3834 /* 3835 * Determine where frame payload starts. 3836 * Jump over vlan headers if already present, 3837 * helpful for QinQ too. 3838 */ 3839 eh = mtod(mp, struct ether_vlan_header *); 3840 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 3841 etype = ntohs(eh->evl_proto); 3842 ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 3843 } else { 3844 etype = ntohs(eh->evl_encap_proto); 3845 ehdrlen = ETHER_HDR_LEN; 3846 } 3847 3848 /* Set the ether header length */ 3849 vlan_macip_lens |= ehdrlen << E1000_ADVTXD_MACLEN_SHIFT; 3850 3851 switch (etype) { 3852 case ETHERTYPE_IP: 3853 ip = (struct ip *)(mp->m_data + ehdrlen); 3854 ip_hlen = ip->ip_hl << 2; 3855 if (mp->m_len < ehdrlen + ip_hlen) { 3856 offload = FALSE; 3857 break; 3858 } 3859 ipproto = ip->ip_p; 3860 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_IPV4; 3861 break; 3862 case ETHERTYPE_IPV6: 3863 ip6 = (struct ip6_hdr *)(mp->m_data + ehdrlen); 3864 ip_hlen = sizeof(struct ip6_hdr); 3865 if (mp->m_len < ehdrlen + ip_hlen) 3866 return FALSE; /* failure */ 3867 ipproto = ip6->ip6_nxt; 3868 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_IPV6; 3869 break; 3870 default: 3871 offload = FALSE; 3872 break; 3873 } 3874 3875 vlan_macip_lens |= ip_hlen; 3876 type_tucmd_mlhl |= E1000_ADVTXD_DCMD_DEXT | E1000_ADVTXD_DTYP_CTXT; 3877 3878 switch (ipproto) { 3879 case IPPROTO_TCP: 3880 if (mp->m_pkthdr.csum_flags & CSUM_TCP) 3881 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_TCP; 3882 break; 3883 case IPPROTO_UDP: 3884 if (mp->m_pkthdr.csum_flags & CSUM_UDP) 3885 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_UDP; 3886 break; 3887 default: 3888 offload = FALSE; 3889 break; 3890 } 3891 3892 /* Now copy bits into descriptor */ 3893 TXD->vlan_macip_lens |= htole32(vlan_macip_lens); 3894 TXD->type_tucmd_mlhl |= htole32(type_tucmd_mlhl); 3895 TXD->seqnum_seed = htole32(0); 3896 TXD->mss_l4len_idx = htole32(0); 3897 3898 tx_buffer->m_head = NULL; 3899 tx_buffer->next_eop = -1; 3900 3901 /* We've consumed the first desc, adjust counters */ 3902 if (++ctxd == adapter->num_tx_desc) 3903 ctxd = 0; 3904 adapter->next_avail_tx_desc = ctxd; 3905 --adapter->num_tx_desc_avail; 3906 3907 return (offload); 3908 } 3909 3910 3911 /********************************************************************** 3912 * 3913 * Examine each tx_buffer in the used queue. If the hardware is done 3914 * processing the packet then free associated resources. The 3915 * tx_buffer is put back on the free queue. 3916 * 3917 **********************************************************************/ 3918 static void 3919 em_txeof(struct adapter *adapter) 3920 { 3921 int first, last, done, num_avail; 3922 struct em_buffer *tx_buffer; 3923 struct e1000_tx_desc *tx_desc, *eop_desc; 3924 struct ifnet *ifp = adapter->ifp; 3925 3926 EM_TX_LOCK_ASSERT(adapter); 3927 3928 if (adapter->num_tx_desc_avail == adapter->num_tx_desc) 3929 return; 3930 3931 num_avail = adapter->num_tx_desc_avail; 3932 first = adapter->next_tx_to_clean; 3933 tx_desc = &adapter->tx_desc_base[first]; 3934 tx_buffer = &adapter->tx_buffer_area[first]; 3935 last = tx_buffer->next_eop; 3936 eop_desc = &adapter->tx_desc_base[last]; 3937 3938 /* 3939 * What this does is get the index of the 3940 * first descriptor AFTER the EOP of the 3941 * first packet, that way we can do the 3942 * simple comparison on the inner while loop. 3943 */ 3944 if (++last == adapter->num_tx_desc) 3945 last = 0; 3946 done = last; 3947 3948 bus_dmamap_sync(adapter->txdma.dma_tag, adapter->txdma.dma_map, 3949 BUS_DMASYNC_POSTREAD); 3950 3951 while (eop_desc->upper.fields.status & E1000_TXD_STAT_DD) { 3952 /* We clean the range of the packet */ 3953 while (first != done) { 3954 tx_desc->upper.data = 0; 3955 tx_desc->lower.data = 0; 3956 tx_desc->buffer_addr = 0; 3957 num_avail++; 3958 3959 if (tx_buffer->m_head) { 3960 ifp->if_opackets++; 3961 bus_dmamap_sync(adapter->txtag, 3962 tx_buffer->map, 3963 BUS_DMASYNC_POSTWRITE); 3964 bus_dmamap_unload(adapter->txtag, 3965 tx_buffer->map); 3966 3967 m_freem(tx_buffer->m_head); 3968 tx_buffer->m_head = NULL; 3969 } 3970 tx_buffer->next_eop = -1; 3971 3972 if (++first == adapter->num_tx_desc) 3973 first = 0; 3974 3975 tx_buffer = &adapter->tx_buffer_area[first]; 3976 tx_desc = &adapter->tx_desc_base[first]; 3977 } 3978 /* See if we can continue to the next packet */ 3979 last = tx_buffer->next_eop; 3980 if (last != -1) { 3981 eop_desc = &adapter->tx_desc_base[last]; 3982 /* Get new done point */ 3983 if (++last == adapter->num_tx_desc) last = 0; 3984 done = last; 3985 } else 3986 break; 3987 } 3988 bus_dmamap_sync(adapter->txdma.dma_tag, adapter->txdma.dma_map, 3989 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3990 3991 adapter->next_tx_to_clean = first; 3992 3993 /* 3994 * If we have enough room, clear IFF_DRV_OACTIVE to tell the stack 3995 * that it is OK to send packets. 3996 * If there are no pending descriptors, clear the timeout. Otherwise, 3997 * if some descriptors have been freed, restart the timeout. 3998 */ 3999 if (num_avail > EM_TX_CLEANUP_THRESHOLD) { 4000 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 4001 /* All clean, turn off the timer */ 4002 if (num_avail == adapter->num_tx_desc) 4003 adapter->watchdog_timer = 0; 4004 /* Some cleaned, reset the timer */ 4005 else if (num_avail != adapter->num_tx_desc_avail) 4006 adapter->watchdog_timer = EM_TX_TIMEOUT; 4007 } 4008 adapter->num_tx_desc_avail = num_avail; 4009 return; 4010 } 4011 4012 /********************************************************************* 4013 * 4014 * When Link is lost sometimes there is work still in the TX ring 4015 * which will result in a watchdog, rather than allow that do an 4016 * attempted cleanup and then reinit here. Note that this has been 4017 * seens mostly with fiber adapters. 4018 * 4019 **********************************************************************/ 4020 static void 4021 em_tx_purge(struct adapter *adapter) 4022 { 4023 if ((!adapter->link_active) && (adapter->watchdog_timer)) { 4024 EM_TX_LOCK(adapter); 4025 em_txeof(adapter); 4026 EM_TX_UNLOCK(adapter); 4027 if (adapter->watchdog_timer) { /* Still not clean? */ 4028 adapter->watchdog_timer = 0; 4029 em_init_locked(adapter); 4030 } 4031 } 4032 } 4033 4034 /********************************************************************* 4035 * 4036 * Get a buffer from system mbuf buffer pool. 4037 * 4038 **********************************************************************/ 4039 static int 4040 em_get_buf(struct adapter *adapter, int i) 4041 { 4042 struct mbuf *m; 4043 bus_dma_segment_t segs[1]; 4044 bus_dmamap_t map; 4045 struct em_buffer *rx_buffer; 4046 int error, nsegs; 4047 4048 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 4049 if (m == NULL) { 4050 adapter->mbuf_cluster_failed++; 4051 return (ENOBUFS); 4052 } 4053 m->m_len = m->m_pkthdr.len = MCLBYTES; 4054 4055 if (adapter->max_frame_size <= (MCLBYTES - ETHER_ALIGN)) 4056 m_adj(m, ETHER_ALIGN); 4057 4058 /* 4059 * Using memory from the mbuf cluster pool, invoke the 4060 * bus_dma machinery to arrange the memory mapping. 4061 */ 4062 error = bus_dmamap_load_mbuf_sg(adapter->rxtag, 4063 adapter->rx_sparemap, m, segs, &nsegs, BUS_DMA_NOWAIT); 4064 if (error != 0) { 4065 m_free(m); 4066 return (error); 4067 } 4068 4069 /* If nsegs is wrong then the stack is corrupt. */ 4070 KASSERT(nsegs == 1, ("Too many segments returned!")); 4071 4072 rx_buffer = &adapter->rx_buffer_area[i]; 4073 if (rx_buffer->m_head != NULL) 4074 bus_dmamap_unload(adapter->rxtag, rx_buffer->map); 4075 4076 map = rx_buffer->map; 4077 rx_buffer->map = adapter->rx_sparemap; 4078 adapter->rx_sparemap = map; 4079 bus_dmamap_sync(adapter->rxtag, rx_buffer->map, BUS_DMASYNC_PREREAD); 4080 rx_buffer->m_head = m; 4081 4082 adapter->rx_desc_base[i].buffer_addr = htole64(segs[0].ds_addr); 4083 return (0); 4084 } 4085 4086 /********************************************************************* 4087 * 4088 * Allocate memory for rx_buffer structures. Since we use one 4089 * rx_buffer per received packet, the maximum number of rx_buffer's 4090 * that we'll need is equal to the number of receive descriptors 4091 * that we've allocated. 4092 * 4093 **********************************************************************/ 4094 static int 4095 em_allocate_receive_structures(struct adapter *adapter) 4096 { 4097 device_t dev = adapter->dev; 4098 struct em_buffer *rx_buffer; 4099 int i, error; 4100 4101 adapter->rx_buffer_area = malloc(sizeof(struct em_buffer) * 4102 adapter->num_rx_desc, M_DEVBUF, M_NOWAIT | M_ZERO); 4103 if (adapter->rx_buffer_area == NULL) { 4104 device_printf(dev, "Unable to allocate rx_buffer memory\n"); 4105 return (ENOMEM); 4106 } 4107 4108 #if __FreeBSD_version >= 700000 4109 error = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 4110 #else 4111 error = bus_dma_tag_create(NULL, /* parent */ 4112 #endif 4113 1, 0, /* alignment, bounds */ 4114 BUS_SPACE_MAXADDR, /* lowaddr */ 4115 BUS_SPACE_MAXADDR, /* highaddr */ 4116 NULL, NULL, /* filter, filterarg */ 4117 MCLBYTES, /* maxsize */ 4118 1, /* nsegments */ 4119 MCLBYTES, /* maxsegsize */ 4120 0, /* flags */ 4121 NULL, /* lockfunc */ 4122 NULL, /* lockarg */ 4123 &adapter->rxtag); 4124 if (error) { 4125 device_printf(dev, "%s: bus_dma_tag_create failed %d\n", 4126 __func__, error); 4127 goto fail; 4128 } 4129 4130 /* Create the spare map (used by getbuf) */ 4131 error = bus_dmamap_create(adapter->rxtag, BUS_DMA_NOWAIT, 4132 &adapter->rx_sparemap); 4133 if (error) { 4134 device_printf(dev, "%s: bus_dmamap_create failed: %d\n", 4135 __func__, error); 4136 goto fail; 4137 } 4138 4139 rx_buffer = adapter->rx_buffer_area; 4140 for (i = 0; i < adapter->num_rx_desc; i++, rx_buffer++) { 4141 error = bus_dmamap_create(adapter->rxtag, BUS_DMA_NOWAIT, 4142 &rx_buffer->map); 4143 if (error) { 4144 device_printf(dev, "%s: bus_dmamap_create failed: %d\n", 4145 __func__, error); 4146 goto fail; 4147 } 4148 } 4149 4150 return (0); 4151 4152 fail: 4153 em_free_receive_structures(adapter); 4154 return (error); 4155 } 4156 4157 /********************************************************************* 4158 * 4159 * (Re)initialize receive structures. 4160 * 4161 **********************************************************************/ 4162 static int 4163 em_setup_receive_structures(struct adapter *adapter) 4164 { 4165 struct em_buffer *rx_buffer; 4166 int i, error; 4167 4168 /* Reset descriptor ring */ 4169 bzero(adapter->rx_desc_base, 4170 (sizeof(struct e1000_rx_desc)) * adapter->num_rx_desc); 4171 4172 /* Free current RX buffers. */ 4173 rx_buffer = adapter->rx_buffer_area; 4174 for (i = 0; i < adapter->num_rx_desc; i++, rx_buffer++) { 4175 if (rx_buffer->m_head != NULL) { 4176 bus_dmamap_sync(adapter->rxtag, rx_buffer->map, 4177 BUS_DMASYNC_POSTREAD); 4178 bus_dmamap_unload(adapter->rxtag, rx_buffer->map); 4179 m_freem(rx_buffer->m_head); 4180 rx_buffer->m_head = NULL; 4181 } 4182 } 4183 4184 /* Allocate new ones. */ 4185 for (i = 0; i < adapter->num_rx_desc; i++) { 4186 error = em_get_buf(adapter, i); 4187 if (error) 4188 return (error); 4189 } 4190 4191 /* Setup our descriptor pointers */ 4192 adapter->next_rx_desc_to_check = 0; 4193 bus_dmamap_sync(adapter->rxdma.dma_tag, adapter->rxdma.dma_map, 4194 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4195 4196 return (0); 4197 } 4198 4199 /********************************************************************* 4200 * 4201 * Enable receive unit. 4202 * 4203 **********************************************************************/ 4204 static void 4205 em_initialize_receive_unit(struct adapter *adapter) 4206 { 4207 struct ifnet *ifp = adapter->ifp; 4208 uint64_t bus_addr; 4209 uint32_t reg_rctl; 4210 uint32_t reg_rxcsum; 4211 4212 INIT_DEBUGOUT("em_initialize_receive_unit: begin"); 4213 4214 /* 4215 * Make sure receives are disabled while setting 4216 * up the descriptor ring 4217 */ 4218 reg_rctl = E1000_READ_REG(&adapter->hw, E1000_RCTL); 4219 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl & ~E1000_RCTL_EN); 4220 4221 if(adapter->hw.mac.type >= e1000_82540) { 4222 E1000_WRITE_REG(&adapter->hw, E1000_RADV, 4223 adapter->rx_abs_int_delay.value); 4224 /* 4225 * Set the interrupt throttling rate. Value is calculated 4226 * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) 4227 */ 4228 #define MAX_INTS_PER_SEC 8000 4229 #define DEFAULT_ITR 1000000000/(MAX_INTS_PER_SEC * 256) 4230 E1000_WRITE_REG(&adapter->hw, E1000_ITR, DEFAULT_ITR); 4231 } 4232 4233 /* Setup the Base and Length of the Rx Descriptor Ring */ 4234 bus_addr = adapter->rxdma.dma_paddr; 4235 E1000_WRITE_REG(&adapter->hw, E1000_RDLEN(0), 4236 adapter->num_rx_desc * sizeof(struct e1000_rx_desc)); 4237 E1000_WRITE_REG(&adapter->hw, E1000_RDBAH(0), 4238 (uint32_t)(bus_addr >> 32)); 4239 E1000_WRITE_REG(&adapter->hw, E1000_RDBAL(0), 4240 (uint32_t)bus_addr); 4241 4242 /* Setup the Receive Control Register */ 4243 reg_rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 4244 reg_rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO | 4245 E1000_RCTL_RDMTS_HALF | 4246 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 4247 4248 /* Make sure VLAN Filters are off */ 4249 reg_rctl &= ~E1000_RCTL_VFE; 4250 4251 if (e1000_tbi_sbp_enabled_82543(&adapter->hw)) 4252 reg_rctl |= E1000_RCTL_SBP; 4253 else 4254 reg_rctl &= ~E1000_RCTL_SBP; 4255 4256 switch (adapter->rx_buffer_len) { 4257 default: 4258 case 2048: 4259 reg_rctl |= E1000_RCTL_SZ_2048; 4260 break; 4261 case 4096: 4262 reg_rctl |= E1000_RCTL_SZ_4096 | 4263 E1000_RCTL_BSEX | E1000_RCTL_LPE; 4264 break; 4265 case 8192: 4266 reg_rctl |= E1000_RCTL_SZ_8192 | 4267 E1000_RCTL_BSEX | E1000_RCTL_LPE; 4268 break; 4269 case 16384: 4270 reg_rctl |= E1000_RCTL_SZ_16384 | 4271 E1000_RCTL_BSEX | E1000_RCTL_LPE; 4272 break; 4273 } 4274 4275 if (ifp->if_mtu > ETHERMTU) 4276 reg_rctl |= E1000_RCTL_LPE; 4277 else 4278 reg_rctl &= ~E1000_RCTL_LPE; 4279 4280 /* Enable 82543 Receive Checksum Offload for TCP and UDP */ 4281 if ((adapter->hw.mac.type >= e1000_82543) && 4282 (ifp->if_capenable & IFCAP_RXCSUM)) { 4283 reg_rxcsum = E1000_READ_REG(&adapter->hw, E1000_RXCSUM); 4284 reg_rxcsum |= (E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL); 4285 E1000_WRITE_REG(&adapter->hw, E1000_RXCSUM, reg_rxcsum); 4286 } 4287 4288 /* 4289 ** XXX TEMPORARY WORKAROUND: on some systems with 82573 4290 ** long latencies are observed, like Lenovo X60. This 4291 ** change eliminates the problem, but since having positive 4292 ** values in RDTR is a known source of problems on other 4293 ** platforms another solution is being sought. 4294 */ 4295 if (adapter->hw.mac.type == e1000_82573) 4296 E1000_WRITE_REG(&adapter->hw, E1000_RDTR, 0x20); 4297 4298 /* Enable Receives */ 4299 E1000_WRITE_REG(&adapter->hw, E1000_RCTL, reg_rctl); 4300 4301 /* 4302 * Setup the HW Rx Head and 4303 * Tail Descriptor Pointers 4304 */ 4305 E1000_WRITE_REG(&adapter->hw, E1000_RDH(0), 0); 4306 E1000_WRITE_REG(&adapter->hw, E1000_RDT(0), adapter->num_rx_desc - 1); 4307 4308 return; 4309 } 4310 4311 /********************************************************************* 4312 * 4313 * Free receive related data structures. 4314 * 4315 **********************************************************************/ 4316 static void 4317 em_free_receive_structures(struct adapter *adapter) 4318 { 4319 struct em_buffer *rx_buffer; 4320 int i; 4321 4322 INIT_DEBUGOUT("free_receive_structures: begin"); 4323 4324 if (adapter->rx_sparemap) { 4325 bus_dmamap_destroy(adapter->rxtag, adapter->rx_sparemap); 4326 adapter->rx_sparemap = NULL; 4327 } 4328 4329 /* Cleanup any existing buffers */ 4330 if (adapter->rx_buffer_area != NULL) { 4331 rx_buffer = adapter->rx_buffer_area; 4332 for (i = 0; i < adapter->num_rx_desc; i++, rx_buffer++) { 4333 if (rx_buffer->m_head != NULL) { 4334 bus_dmamap_sync(adapter->rxtag, rx_buffer->map, 4335 BUS_DMASYNC_POSTREAD); 4336 bus_dmamap_unload(adapter->rxtag, 4337 rx_buffer->map); 4338 m_freem(rx_buffer->m_head); 4339 rx_buffer->m_head = NULL; 4340 } else if (rx_buffer->map != NULL) 4341 bus_dmamap_unload(adapter->rxtag, 4342 rx_buffer->map); 4343 if (rx_buffer->map != NULL) { 4344 bus_dmamap_destroy(adapter->rxtag, 4345 rx_buffer->map); 4346 rx_buffer->map = NULL; 4347 } 4348 } 4349 } 4350 4351 if (adapter->rx_buffer_area != NULL) { 4352 free(adapter->rx_buffer_area, M_DEVBUF); 4353 adapter->rx_buffer_area = NULL; 4354 } 4355 4356 if (adapter->rxtag != NULL) { 4357 bus_dma_tag_destroy(adapter->rxtag); 4358 adapter->rxtag = NULL; 4359 } 4360 } 4361 4362 /********************************************************************* 4363 * 4364 * This routine executes in interrupt context. It replenishes 4365 * the mbufs in the descriptor and sends data which has been 4366 * dma'ed into host memory to upper layer. 4367 * 4368 * We loop at most count times if count is > 0, or until done if 4369 * count < 0. 4370 * 4371 *********************************************************************/ 4372 static int 4373 em_rxeof(struct adapter *adapter, int count) 4374 { 4375 struct ifnet *ifp; 4376 struct mbuf *mp; 4377 uint8_t accept_frame = 0; 4378 uint8_t eop = 0; 4379 uint16_t len, desc_len, prev_len_adj; 4380 int i; 4381 4382 /* Pointer to the receive descriptor being examined. */ 4383 struct e1000_rx_desc *current_desc; 4384 uint8_t status; 4385 4386 ifp = adapter->ifp; 4387 i = adapter->next_rx_desc_to_check; 4388 current_desc = &adapter->rx_desc_base[i]; 4389 bus_dmamap_sync(adapter->rxdma.dma_tag, adapter->rxdma.dma_map, 4390 BUS_DMASYNC_POSTREAD); 4391 4392 if (!((current_desc->status) & E1000_RXD_STAT_DD)) 4393 return (0); 4394 4395 while ((current_desc->status & E1000_RXD_STAT_DD) && 4396 (count != 0) && 4397 (ifp->if_drv_flags & IFF_DRV_RUNNING)) { 4398 struct mbuf *m = NULL; 4399 4400 mp = adapter->rx_buffer_area[i].m_head; 4401 /* 4402 * Can't defer bus_dmamap_sync(9) because TBI_ACCEPT 4403 * needs to access the last received byte in the mbuf. 4404 */ 4405 bus_dmamap_sync(adapter->rxtag, adapter->rx_buffer_area[i].map, 4406 BUS_DMASYNC_POSTREAD); 4407 4408 accept_frame = 1; 4409 prev_len_adj = 0; 4410 desc_len = le16toh(current_desc->length); 4411 status = current_desc->status; 4412 if (status & E1000_RXD_STAT_EOP) { 4413 count--; 4414 eop = 1; 4415 if (desc_len < ETHER_CRC_LEN) { 4416 len = 0; 4417 prev_len_adj = ETHER_CRC_LEN - desc_len; 4418 } else 4419 len = desc_len - ETHER_CRC_LEN; 4420 } else { 4421 eop = 0; 4422 len = desc_len; 4423 } 4424 4425 if (current_desc->errors & E1000_RXD_ERR_FRAME_ERR_MASK) { 4426 uint8_t last_byte; 4427 uint32_t pkt_len = desc_len; 4428 4429 if (adapter->fmp != NULL) 4430 pkt_len += adapter->fmp->m_pkthdr.len; 4431 4432 last_byte = *(mtod(mp, caddr_t) + desc_len - 1); 4433 if (TBI_ACCEPT(&adapter->hw, status, 4434 current_desc->errors, pkt_len, last_byte, 4435 adapter->min_frame_size, adapter->max_frame_size)) { 4436 e1000_tbi_adjust_stats_82543(&adapter->hw, 4437 &adapter->stats, pkt_len, 4438 adapter->hw.mac.addr, 4439 adapter->max_frame_size); 4440 if (len > 0) 4441 len--; 4442 } else 4443 accept_frame = 0; 4444 } 4445 4446 if (accept_frame) { 4447 if (em_get_buf(adapter, i) != 0) { 4448 ifp->if_iqdrops++; 4449 goto discard; 4450 } 4451 4452 /* Assign correct length to the current fragment */ 4453 mp->m_len = len; 4454 4455 if (adapter->fmp == NULL) { 4456 mp->m_pkthdr.len = len; 4457 adapter->fmp = mp; /* Store the first mbuf */ 4458 adapter->lmp = mp; 4459 } else { 4460 /* Chain mbuf's together */ 4461 mp->m_flags &= ~M_PKTHDR; 4462 /* 4463 * Adjust length of previous mbuf in chain if 4464 * we received less than 4 bytes in the last 4465 * descriptor. 4466 */ 4467 if (prev_len_adj > 0) { 4468 adapter->lmp->m_len -= prev_len_adj; 4469 adapter->fmp->m_pkthdr.len -= 4470 prev_len_adj; 4471 } 4472 adapter->lmp->m_next = mp; 4473 adapter->lmp = adapter->lmp->m_next; 4474 adapter->fmp->m_pkthdr.len += len; 4475 } 4476 4477 if (eop) { 4478 adapter->fmp->m_pkthdr.rcvif = ifp; 4479 ifp->if_ipackets++; 4480 em_receive_checksum(adapter, current_desc, 4481 adapter->fmp); 4482 #ifndef __NO_STRICT_ALIGNMENT 4483 if (adapter->max_frame_size > 4484 (MCLBYTES - ETHER_ALIGN) && 4485 em_fixup_rx(adapter) != 0) 4486 goto skip; 4487 #endif 4488 if (status & E1000_RXD_STAT_VP) { 4489 #if __FreeBSD_version < 700000 4490 VLAN_INPUT_TAG_NEW(ifp, adapter->fmp, 4491 (le16toh(current_desc->special) & 4492 E1000_RXD_SPC_VLAN_MASK)); 4493 #else 4494 adapter->fmp->m_pkthdr.ether_vtag = 4495 (le16toh(current_desc->special) & 4496 E1000_RXD_SPC_VLAN_MASK); 4497 adapter->fmp->m_flags |= M_VLANTAG; 4498 #endif 4499 } 4500 #ifndef __NO_STRICT_ALIGNMENT 4501 skip: 4502 #endif 4503 m = adapter->fmp; 4504 adapter->fmp = NULL; 4505 adapter->lmp = NULL; 4506 } 4507 } else { 4508 ifp->if_ierrors++; 4509 discard: 4510 /* Reuse loaded DMA map and just update mbuf chain */ 4511 mp = adapter->rx_buffer_area[i].m_head; 4512 mp->m_len = mp->m_pkthdr.len = MCLBYTES; 4513 mp->m_data = mp->m_ext.ext_buf; 4514 mp->m_next = NULL; 4515 if (adapter->max_frame_size <= 4516 (MCLBYTES - ETHER_ALIGN)) 4517 m_adj(mp, ETHER_ALIGN); 4518 if (adapter->fmp != NULL) { 4519 m_freem(adapter->fmp); 4520 adapter->fmp = NULL; 4521 adapter->lmp = NULL; 4522 } 4523 m = NULL; 4524 } 4525 4526 /* Zero out the receive descriptors status. */ 4527 current_desc->status = 0; 4528 bus_dmamap_sync(adapter->rxdma.dma_tag, adapter->rxdma.dma_map, 4529 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4530 4531 /* Advance our pointers to the next descriptor. */ 4532 if (++i == adapter->num_rx_desc) 4533 i = 0; 4534 if (m != NULL) { 4535 adapter->next_rx_desc_to_check = i; 4536 #ifndef EM_FAST_IRQ 4537 EM_CORE_UNLOCK(adapter); 4538 (*ifp->if_input)(ifp, m); 4539 EM_CORE_LOCK(adapter); 4540 #else 4541 /* Already running unlocked */ 4542 (*ifp->if_input)(ifp, m); 4543 #endif 4544 i = adapter->next_rx_desc_to_check; 4545 } 4546 current_desc = &adapter->rx_desc_base[i]; 4547 } 4548 adapter->next_rx_desc_to_check = i; 4549 4550 /* Advance the E1000's Receive Queue #0 "Tail Pointer". */ 4551 if (--i < 0) 4552 i = adapter->num_rx_desc - 1; 4553 E1000_WRITE_REG(&adapter->hw, E1000_RDT(0), i); 4554 if (!((current_desc->status) & E1000_RXD_STAT_DD)) 4555 return (0); 4556 4557 return (1); 4558 } 4559 4560 #ifndef __NO_STRICT_ALIGNMENT 4561 /* 4562 * When jumbo frames are enabled we should realign entire payload on 4563 * architecures with strict alignment. This is serious design mistake of 8254x 4564 * as it nullifies DMA operations. 8254x just allows RX buffer size to be 4565 * 2048/4096/8192/16384. What we really want is 2048 - ETHER_ALIGN to align its 4566 * payload. On architecures without strict alignment restrictions 8254x still 4567 * performs unaligned memory access which would reduce the performance too. 4568 * To avoid copying over an entire frame to align, we allocate a new mbuf and 4569 * copy ethernet header to the new mbuf. The new mbuf is prepended into the 4570 * existing mbuf chain. 4571 * 4572 * Be aware, best performance of the 8254x is achived only when jumbo frame is 4573 * not used at all on architectures with strict alignment. 4574 */ 4575 static int 4576 em_fixup_rx(struct adapter *adapter) 4577 { 4578 struct mbuf *m, *n; 4579 int error; 4580 4581 error = 0; 4582 m = adapter->fmp; 4583 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) { 4584 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len); 4585 m->m_data += ETHER_HDR_LEN; 4586 } else { 4587 MGETHDR(n, M_DONTWAIT, MT_DATA); 4588 if (n != NULL) { 4589 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 4590 m->m_data += ETHER_HDR_LEN; 4591 m->m_len -= ETHER_HDR_LEN; 4592 n->m_len = ETHER_HDR_LEN; 4593 M_MOVE_PKTHDR(n, m); 4594 n->m_next = m; 4595 adapter->fmp = n; 4596 } else { 4597 adapter->dropped_pkts++; 4598 m_freem(adapter->fmp); 4599 adapter->fmp = NULL; 4600 error = ENOMEM; 4601 } 4602 } 4603 4604 return (error); 4605 } 4606 #endif 4607 4608 /********************************************************************* 4609 * 4610 * Verify that the hardware indicated that the checksum is valid. 4611 * Inform the stack about the status of checksum so that stack 4612 * doesn't spend time verifying the checksum. 4613 * 4614 *********************************************************************/ 4615 static void 4616 em_receive_checksum(struct adapter *adapter, 4617 struct e1000_rx_desc *rx_desc, struct mbuf *mp) 4618 { 4619 /* 82543 or newer only */ 4620 if ((adapter->hw.mac.type < e1000_82543) || 4621 /* Ignore Checksum bit is set */ 4622 (rx_desc->status & E1000_RXD_STAT_IXSM)) { 4623 mp->m_pkthdr.csum_flags = 0; 4624 return; 4625 } 4626 4627 if (rx_desc->status & E1000_RXD_STAT_IPCS) { 4628 /* Did it pass? */ 4629 if (!(rx_desc->errors & E1000_RXD_ERR_IPE)) { 4630 /* IP Checksum Good */ 4631 mp->m_pkthdr.csum_flags = CSUM_IP_CHECKED; 4632 mp->m_pkthdr.csum_flags |= CSUM_IP_VALID; 4633 4634 } else { 4635 mp->m_pkthdr.csum_flags = 0; 4636 } 4637 } 4638 4639 if (rx_desc->status & E1000_RXD_STAT_TCPCS) { 4640 /* Did it pass? */ 4641 if (!(rx_desc->errors & E1000_RXD_ERR_TCPE)) { 4642 mp->m_pkthdr.csum_flags |= 4643 (CSUM_DATA_VALID | CSUM_PSEUDO_HDR); 4644 mp->m_pkthdr.csum_data = htons(0xffff); 4645 } 4646 } 4647 } 4648 4649 /* 4650 * This turns on the hardware offload of the VLAN 4651 * tag insertion and strip 4652 */ 4653 static void 4654 em_enable_hw_vlans(struct adapter *adapter) 4655 { 4656 uint32_t ctrl; 4657 4658 ctrl = E1000_READ_REG(&adapter->hw, E1000_CTRL); 4659 ctrl |= E1000_CTRL_VME; 4660 E1000_WRITE_REG(&adapter->hw, E1000_CTRL, ctrl); 4661 } 4662 4663 static void 4664 em_enable_intr(struct adapter *adapter) 4665 { 4666 E1000_WRITE_REG(&adapter->hw, E1000_IMS, 4667 (IMS_ENABLE_MASK)); 4668 } 4669 4670 static void 4671 em_disable_intr(struct adapter *adapter) 4672 { 4673 E1000_WRITE_REG(&adapter->hw, E1000_IMC, 0xffffffff); 4674 } 4675 4676 /* 4677 * Bit of a misnomer, what this really means is 4678 * to enable OS management of the system... aka 4679 * to disable special hardware management features 4680 */ 4681 static void 4682 em_init_manageability(struct adapter *adapter) 4683 { 4684 /* A shared code workaround */ 4685 #define E1000_82542_MANC2H E1000_MANC2H 4686 if (adapter->has_manage) { 4687 int manc2h = E1000_READ_REG(&adapter->hw, E1000_MANC2H); 4688 int manc = E1000_READ_REG(&adapter->hw, E1000_MANC); 4689 4690 /* disable hardware interception of ARP */ 4691 manc &= ~(E1000_MANC_ARP_EN); 4692 4693 /* enable receiving management packets to the host */ 4694 if (adapter->hw.mac.type >= e1000_82571) { 4695 manc |= E1000_MANC_EN_MNG2HOST; 4696 #define E1000_MNG2HOST_PORT_623 (1 << 5) 4697 #define E1000_MNG2HOST_PORT_664 (1 << 6) 4698 manc2h |= E1000_MNG2HOST_PORT_623; 4699 manc2h |= E1000_MNG2HOST_PORT_664; 4700 E1000_WRITE_REG(&adapter->hw, E1000_MANC2H, manc2h); 4701 } 4702 4703 E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc); 4704 } 4705 } 4706 4707 /* 4708 * Give control back to hardware management 4709 * controller if there is one. 4710 */ 4711 static void 4712 em_release_manageability(struct adapter *adapter) 4713 { 4714 if (adapter->has_manage) { 4715 int manc = E1000_READ_REG(&adapter->hw, E1000_MANC); 4716 4717 /* re-enable hardware interception of ARP */ 4718 manc |= E1000_MANC_ARP_EN; 4719 4720 if (adapter->hw.mac.type >= e1000_82571) 4721 manc &= ~E1000_MANC_EN_MNG2HOST; 4722 4723 E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc); 4724 } 4725 } 4726 4727 /* 4728 * em_get_hw_control sets {CTRL_EXT|FWSM}:DRV_LOAD bit. 4729 * For ASF and Pass Through versions of f/w this means that 4730 * the driver is loaded. For AMT version (only with 82573) 4731 * of the f/w this means that the network i/f is open. 4732 * 4733 */ 4734 static void 4735 em_get_hw_control(struct adapter *adapter) 4736 { 4737 u32 ctrl_ext, swsm; 4738 4739 /* Let firmware know the driver has taken over */ 4740 switch (adapter->hw.mac.type) { 4741 case e1000_82573: 4742 swsm = E1000_READ_REG(&adapter->hw, E1000_SWSM); 4743 E1000_WRITE_REG(&adapter->hw, E1000_SWSM, 4744 swsm | E1000_SWSM_DRV_LOAD); 4745 break; 4746 case e1000_82571: 4747 case e1000_82572: 4748 case e1000_80003es2lan: 4749 case e1000_ich8lan: 4750 case e1000_ich9lan: 4751 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 4752 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, 4753 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 4754 break; 4755 default: 4756 break; 4757 } 4758 } 4759 4760 /* 4761 * em_release_hw_control resets {CTRL_EXT|FWSM}:DRV_LOAD bit. 4762 * For ASF and Pass Through versions of f/w this means that the 4763 * driver is no longer loaded. For AMT version (only with 82573) i 4764 * of the f/w this means that the network i/f is closed. 4765 * 4766 */ 4767 static void 4768 em_release_hw_control(struct adapter *adapter) 4769 { 4770 u32 ctrl_ext, swsm; 4771 4772 /* Let firmware taken over control of h/w */ 4773 switch (adapter->hw.mac.type) { 4774 case e1000_82573: 4775 swsm = E1000_READ_REG(&adapter->hw, E1000_SWSM); 4776 E1000_WRITE_REG(&adapter->hw, E1000_SWSM, 4777 swsm & ~E1000_SWSM_DRV_LOAD); 4778 break; 4779 case e1000_82571: 4780 case e1000_82572: 4781 case e1000_80003es2lan: 4782 case e1000_ich8lan: 4783 case e1000_ich9lan: 4784 ctrl_ext = E1000_READ_REG(&adapter->hw, E1000_CTRL_EXT); 4785 E1000_WRITE_REG(&adapter->hw, E1000_CTRL_EXT, 4786 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 4787 break; 4788 default: 4789 break; 4790 4791 } 4792 } 4793 4794 static int 4795 em_is_valid_ether_addr(uint8_t *addr) 4796 { 4797 char zero_addr[6] = { 0, 0, 0, 0, 0, 0 }; 4798 4799 if ((addr[0] & 1) || (!bcmp(addr, zero_addr, ETHER_ADDR_LEN))) { 4800 return (FALSE); 4801 } 4802 4803 return (TRUE); 4804 } 4805 4806 /* 4807 * NOTE: the following routines using the e1000 4808 * naming style are provided to the shared 4809 * code which expects that rather than 'em' 4810 */ 4811 4812 void 4813 e1000_write_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t *value) 4814 { 4815 pci_write_config(((struct e1000_osdep *)hw->back)->dev, reg, *value, 2); 4816 } 4817 4818 void 4819 e1000_read_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t *value) 4820 { 4821 *value = pci_read_config(((struct e1000_osdep *)hw->back)->dev, reg, 2); 4822 } 4823 4824 void 4825 e1000_pci_set_mwi(struct e1000_hw *hw) 4826 { 4827 pci_write_config(((struct e1000_osdep *)hw->back)->dev, PCIR_COMMAND, 4828 (hw->bus.pci_cmd_word | CMD_MEM_WRT_INVALIDATE), 2); 4829 } 4830 4831 void 4832 e1000_pci_clear_mwi(struct e1000_hw *hw) 4833 { 4834 pci_write_config(((struct e1000_osdep *)hw->back)->dev, PCIR_COMMAND, 4835 (hw->bus.pci_cmd_word & ~CMD_MEM_WRT_INVALIDATE), 2); 4836 } 4837 4838 /* 4839 * Read the PCI Express capabilities 4840 */ 4841 int32_t 4842 e1000_read_pcie_cap_reg(struct e1000_hw *hw, uint32_t reg, uint16_t *value) 4843 { 4844 int32_t error = E1000_SUCCESS; 4845 uint16_t cap_off; 4846 4847 switch (hw->mac.type) { 4848 4849 case e1000_82571: 4850 case e1000_82572: 4851 case e1000_82573: 4852 case e1000_80003es2lan: 4853 cap_off = 0xE0; 4854 e1000_read_pci_cfg(hw, cap_off + reg, value); 4855 break; 4856 default: 4857 error = ~E1000_NOT_IMPLEMENTED; 4858 break; 4859 } 4860 4861 return (error); 4862 } 4863 4864 int32_t 4865 e1000_alloc_zeroed_dev_spec_struct(struct e1000_hw *hw, uint32_t size) 4866 { 4867 int32_t error = 0; 4868 4869 hw->dev_spec = malloc(size, M_DEVBUF, M_NOWAIT | M_ZERO); 4870 if (hw->dev_spec == NULL) 4871 error = ENOMEM; 4872 4873 return (error); 4874 } 4875 4876 void 4877 e1000_free_dev_spec_struct(struct e1000_hw *hw) 4878 { 4879 if (hw->dev_spec != NULL) 4880 free(hw->dev_spec, M_DEVBUF); 4881 return; 4882 } 4883 4884 /* 4885 * Enable PCI Wake On Lan capability 4886 */ 4887 void 4888 em_enable_wakeup(device_t dev) 4889 { 4890 u16 cap, status; 4891 u8 id; 4892 4893 /* First find the capabilities pointer*/ 4894 cap = pci_read_config(dev, PCIR_CAP_PTR, 2); 4895 /* Read the PM Capabilities */ 4896 id = pci_read_config(dev, cap, 1); 4897 if (id != PCIY_PMG) /* Something wrong */ 4898 return; 4899 /* OK, we have the power capabilities, so 4900 now get the status register */ 4901 cap += PCIR_POWER_STATUS; 4902 status = pci_read_config(dev, cap, 2); 4903 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 4904 pci_write_config(dev, cap, status, 2); 4905 return; 4906 } 4907 4908 4909 /********************************************************************* 4910 * 82544 Coexistence issue workaround. 4911 * There are 2 issues. 4912 * 1. Transmit Hang issue. 4913 * To detect this issue, following equation can be used... 4914 * SIZE[3:0] + ADDR[2:0] = SUM[3:0]. 4915 * If SUM[3:0] is in between 1 to 4, we will have this issue. 4916 * 4917 * 2. DAC issue. 4918 * To detect this issue, following equation can be used... 4919 * SIZE[3:0] + ADDR[2:0] = SUM[3:0]. 4920 * If SUM[3:0] is in between 9 to c, we will have this issue. 4921 * 4922 * 4923 * WORKAROUND: 4924 * Make sure we do not have ending address 4925 * as 1,2,3,4(Hang) or 9,a,b,c (DAC) 4926 * 4927 *************************************************************************/ 4928 static uint32_t 4929 em_fill_descriptors (bus_addr_t address, uint32_t length, 4930 PDESC_ARRAY desc_array) 4931 { 4932 /* Since issue is sensitive to length and address.*/ 4933 /* Let us first check the address...*/ 4934 uint32_t safe_terminator; 4935 if (length <= 4) { 4936 desc_array->descriptor[0].address = address; 4937 desc_array->descriptor[0].length = length; 4938 desc_array->elements = 1; 4939 return (desc_array->elements); 4940 } 4941 safe_terminator = (uint32_t)((((uint32_t)address & 0x7) + 4942 (length & 0xF)) & 0xF); 4943 /* if it does not fall between 0x1 to 0x4 and 0x9 to 0xC then return */ 4944 if (safe_terminator == 0 || 4945 (safe_terminator > 4 && 4946 safe_terminator < 9) || 4947 (safe_terminator > 0xC && 4948 safe_terminator <= 0xF)) { 4949 desc_array->descriptor[0].address = address; 4950 desc_array->descriptor[0].length = length; 4951 desc_array->elements = 1; 4952 return (desc_array->elements); 4953 } 4954 4955 desc_array->descriptor[0].address = address; 4956 desc_array->descriptor[0].length = length - 4; 4957 desc_array->descriptor[1].address = address + (length - 4); 4958 desc_array->descriptor[1].length = 4; 4959 desc_array->elements = 2; 4960 return (desc_array->elements); 4961 } 4962 4963 /********************************************************************** 4964 * 4965 * Update the board statistics counters. 4966 * 4967 **********************************************************************/ 4968 static void 4969 em_update_stats_counters(struct adapter *adapter) 4970 { 4971 struct ifnet *ifp; 4972 4973 if(adapter->hw.phy.media_type == e1000_media_type_copper || 4974 (E1000_READ_REG(&adapter->hw, E1000_STATUS) & E1000_STATUS_LU)) { 4975 adapter->stats.symerrs += E1000_READ_REG(&adapter->hw, E1000_SYMERRS); 4976 adapter->stats.sec += E1000_READ_REG(&adapter->hw, E1000_SEC); 4977 } 4978 adapter->stats.crcerrs += E1000_READ_REG(&adapter->hw, E1000_CRCERRS); 4979 adapter->stats.mpc += E1000_READ_REG(&adapter->hw, E1000_MPC); 4980 adapter->stats.scc += E1000_READ_REG(&adapter->hw, E1000_SCC); 4981 adapter->stats.ecol += E1000_READ_REG(&adapter->hw, E1000_ECOL); 4982 4983 adapter->stats.mcc += E1000_READ_REG(&adapter->hw, E1000_MCC); 4984 adapter->stats.latecol += E1000_READ_REG(&adapter->hw, E1000_LATECOL); 4985 adapter->stats.colc += E1000_READ_REG(&adapter->hw, E1000_COLC); 4986 adapter->stats.dc += E1000_READ_REG(&adapter->hw, E1000_DC); 4987 adapter->stats.rlec += E1000_READ_REG(&adapter->hw, E1000_RLEC); 4988 adapter->stats.xonrxc += E1000_READ_REG(&adapter->hw, E1000_XONRXC); 4989 adapter->stats.xontxc += E1000_READ_REG(&adapter->hw, E1000_XONTXC); 4990 adapter->stats.xoffrxc += E1000_READ_REG(&adapter->hw, E1000_XOFFRXC); 4991 adapter->stats.xofftxc += E1000_READ_REG(&adapter->hw, E1000_XOFFTXC); 4992 adapter->stats.fcruc += E1000_READ_REG(&adapter->hw, E1000_FCRUC); 4993 adapter->stats.prc64 += E1000_READ_REG(&adapter->hw, E1000_PRC64); 4994 adapter->stats.prc127 += E1000_READ_REG(&adapter->hw, E1000_PRC127); 4995 adapter->stats.prc255 += E1000_READ_REG(&adapter->hw, E1000_PRC255); 4996 adapter->stats.prc511 += E1000_READ_REG(&adapter->hw, E1000_PRC511); 4997 adapter->stats.prc1023 += E1000_READ_REG(&adapter->hw, E1000_PRC1023); 4998 adapter->stats.prc1522 += E1000_READ_REG(&adapter->hw, E1000_PRC1522); 4999 adapter->stats.gprc += E1000_READ_REG(&adapter->hw, E1000_GPRC); 5000 adapter->stats.bprc += E1000_READ_REG(&adapter->hw, E1000_BPRC); 5001 adapter->stats.mprc += E1000_READ_REG(&adapter->hw, E1000_MPRC); 5002 adapter->stats.gptc += E1000_READ_REG(&adapter->hw, E1000_GPTC); 5003 5004 /* For the 64-bit byte counters the low dword must be read first. */ 5005 /* Both registers clear on the read of the high dword */ 5006 5007 adapter->stats.gorc += E1000_READ_REG(&adapter->hw, E1000_GORCH); 5008 adapter->stats.gotc += E1000_READ_REG(&adapter->hw, E1000_GOTCH); 5009 5010 adapter->stats.rnbc += E1000_READ_REG(&adapter->hw, E1000_RNBC); 5011 adapter->stats.ruc += E1000_READ_REG(&adapter->hw, E1000_RUC); 5012 adapter->stats.rfc += E1000_READ_REG(&adapter->hw, E1000_RFC); 5013 adapter->stats.roc += E1000_READ_REG(&adapter->hw, E1000_ROC); 5014 adapter->stats.rjc += E1000_READ_REG(&adapter->hw, E1000_RJC); 5015 5016 adapter->stats.tor += E1000_READ_REG(&adapter->hw, E1000_TORH); 5017 adapter->stats.tot += E1000_READ_REG(&adapter->hw, E1000_TOTH); 5018 5019 adapter->stats.tpr += E1000_READ_REG(&adapter->hw, E1000_TPR); 5020 adapter->stats.tpt += E1000_READ_REG(&adapter->hw, E1000_TPT); 5021 adapter->stats.ptc64 += E1000_READ_REG(&adapter->hw, E1000_PTC64); 5022 adapter->stats.ptc127 += E1000_READ_REG(&adapter->hw, E1000_PTC127); 5023 adapter->stats.ptc255 += E1000_READ_REG(&adapter->hw, E1000_PTC255); 5024 adapter->stats.ptc511 += E1000_READ_REG(&adapter->hw, E1000_PTC511); 5025 adapter->stats.ptc1023 += E1000_READ_REG(&adapter->hw, E1000_PTC1023); 5026 adapter->stats.ptc1522 += E1000_READ_REG(&adapter->hw, E1000_PTC1522); 5027 adapter->stats.mptc += E1000_READ_REG(&adapter->hw, E1000_MPTC); 5028 adapter->stats.bptc += E1000_READ_REG(&adapter->hw, E1000_BPTC); 5029 5030 if (adapter->hw.mac.type >= e1000_82543) { 5031 adapter->stats.algnerrc += 5032 E1000_READ_REG(&adapter->hw, E1000_ALGNERRC); 5033 adapter->stats.rxerrc += 5034 E1000_READ_REG(&adapter->hw, E1000_RXERRC); 5035 adapter->stats.tncrs += 5036 E1000_READ_REG(&adapter->hw, E1000_TNCRS); 5037 adapter->stats.cexterr += 5038 E1000_READ_REG(&adapter->hw, E1000_CEXTERR); 5039 adapter->stats.tsctc += 5040 E1000_READ_REG(&adapter->hw, E1000_TSCTC); 5041 adapter->stats.tsctfc += 5042 E1000_READ_REG(&adapter->hw, E1000_TSCTFC); 5043 } 5044 ifp = adapter->ifp; 5045 5046 ifp->if_collisions = adapter->stats.colc; 5047 5048 /* Rx Errors */ 5049 ifp->if_ierrors = adapter->dropped_pkts + adapter->stats.rxerrc + 5050 adapter->stats.crcerrs + adapter->stats.algnerrc + 5051 adapter->stats.ruc + adapter->stats.roc + 5052 adapter->stats.mpc + adapter->stats.cexterr; 5053 5054 /* Tx Errors */ 5055 ifp->if_oerrors = adapter->stats.ecol + 5056 adapter->stats.latecol + adapter->watchdog_events; 5057 } 5058 5059 5060 /********************************************************************** 5061 * 5062 * This routine is called only when em_display_debug_stats is enabled. 5063 * This routine provides a way to take a look at important statistics 5064 * maintained by the driver and hardware. 5065 * 5066 **********************************************************************/ 5067 static void 5068 em_print_debug_info(struct adapter *adapter) 5069 { 5070 device_t dev = adapter->dev; 5071 uint8_t *hw_addr = adapter->hw.hw_addr; 5072 5073 device_printf(dev, "Adapter hardware address = %p \n", hw_addr); 5074 device_printf(dev, "CTRL = 0x%x RCTL = 0x%x \n", 5075 E1000_READ_REG(&adapter->hw, E1000_CTRL), 5076 E1000_READ_REG(&adapter->hw, E1000_RCTL)); 5077 device_printf(dev, "Packet buffer = Tx=%dk Rx=%dk \n", 5078 ((E1000_READ_REG(&adapter->hw, E1000_PBA) & 0xffff0000) >> 16),\ 5079 (E1000_READ_REG(&adapter->hw, E1000_PBA) & 0xffff) ); 5080 device_printf(dev, "Flow control watermarks high = %d low = %d\n", 5081 adapter->hw.fc.high_water, 5082 adapter->hw.fc.low_water); 5083 device_printf(dev, "tx_int_delay = %d, tx_abs_int_delay = %d\n", 5084 E1000_READ_REG(&adapter->hw, E1000_TIDV), 5085 E1000_READ_REG(&adapter->hw, E1000_TADV)); 5086 device_printf(dev, "rx_int_delay = %d, rx_abs_int_delay = %d\n", 5087 E1000_READ_REG(&adapter->hw, E1000_RDTR), 5088 E1000_READ_REG(&adapter->hw, E1000_RADV)); 5089 device_printf(dev, "fifo workaround = %lld, fifo_reset_count = %lld\n", 5090 (long long)adapter->tx_fifo_wrk_cnt, 5091 (long long)adapter->tx_fifo_reset_cnt); 5092 device_printf(dev, "hw tdh = %d, hw tdt = %d\n", 5093 E1000_READ_REG(&adapter->hw, E1000_TDH(0)), 5094 E1000_READ_REG(&adapter->hw, E1000_TDT(0))); 5095 device_printf(dev, "hw rdh = %d, hw rdt = %d\n", 5096 E1000_READ_REG(&adapter->hw, E1000_RDH(0)), 5097 E1000_READ_REG(&adapter->hw, E1000_RDT(0))); 5098 device_printf(dev, "Num Tx descriptors avail = %d\n", 5099 adapter->num_tx_desc_avail); 5100 device_printf(dev, "Tx Descriptors not avail1 = %ld\n", 5101 adapter->no_tx_desc_avail1); 5102 device_printf(dev, "Tx Descriptors not avail2 = %ld\n", 5103 adapter->no_tx_desc_avail2); 5104 device_printf(dev, "Std mbuf failed = %ld\n", 5105 adapter->mbuf_alloc_failed); 5106 device_printf(dev, "Std mbuf cluster failed = %ld\n", 5107 adapter->mbuf_cluster_failed); 5108 device_printf(dev, "Driver dropped packets = %ld\n", 5109 adapter->dropped_pkts); 5110 device_printf(dev, "Driver tx dma failure in encap = %ld\n", 5111 adapter->no_tx_dma_setup); 5112 } 5113 5114 static void 5115 em_print_hw_stats(struct adapter *adapter) 5116 { 5117 device_t dev = adapter->dev; 5118 5119 device_printf(dev, "Excessive collisions = %lld\n", 5120 (long long)adapter->stats.ecol); 5121 #if (DEBUG_HW > 0) /* Dont output these errors normally */ 5122 device_printf(dev, "Symbol errors = %lld\n", 5123 (long long)adapter->stats.symerrs); 5124 #endif 5125 device_printf(dev, "Sequence errors = %lld\n", 5126 (long long)adapter->stats.sec); 5127 device_printf(dev, "Defer count = %lld\n", 5128 (long long)adapter->stats.dc); 5129 device_printf(dev, "Missed Packets = %lld\n", 5130 (long long)adapter->stats.mpc); 5131 device_printf(dev, "Receive No Buffers = %lld\n", 5132 (long long)adapter->stats.rnbc); 5133 /* RLEC is inaccurate on some hardware, calculate our own. */ 5134 device_printf(dev, "Receive Length Errors = %lld\n", 5135 ((long long)adapter->stats.roc + (long long)adapter->stats.ruc)); 5136 device_printf(dev, "Receive errors = %lld\n", 5137 (long long)adapter->stats.rxerrc); 5138 device_printf(dev, "Crc errors = %lld\n", 5139 (long long)adapter->stats.crcerrs); 5140 device_printf(dev, "Alignment errors = %lld\n", 5141 (long long)adapter->stats.algnerrc); 5142 /* On 82575 these are collision counts */ 5143 device_printf(dev, "Collision/Carrier extension errors = %lld\n", 5144 (long long)adapter->stats.cexterr); 5145 device_printf(dev, "RX overruns = %ld\n", adapter->rx_overruns); 5146 device_printf(dev, "watchdog timeouts = %ld\n", 5147 adapter->watchdog_events); 5148 device_printf(dev, "XON Rcvd = %lld\n", 5149 (long long)adapter->stats.xonrxc); 5150 device_printf(dev, "XON Xmtd = %lld\n", 5151 (long long)adapter->stats.xontxc); 5152 device_printf(dev, "XOFF Rcvd = %lld\n", 5153 (long long)adapter->stats.xoffrxc); 5154 device_printf(dev, "XOFF Xmtd = %lld\n", 5155 (long long)adapter->stats.xofftxc); 5156 device_printf(dev, "Good Packets Rcvd = %lld\n", 5157 (long long)adapter->stats.gprc); 5158 device_printf(dev, "Good Packets Xmtd = %lld\n", 5159 (long long)adapter->stats.gptc); 5160 device_printf(dev, "TSO Contexts Xmtd = %lld\n", 5161 (long long)adapter->stats.tsctc); 5162 device_printf(dev, "TSO Contexts Failed = %lld\n", 5163 (long long)adapter->stats.tsctfc); 5164 } 5165 5166 /********************************************************************** 5167 * 5168 * This routine provides a way to dump out the adapter eeprom, 5169 * often a useful debug/service tool. This only dumps the first 5170 * 32 words, stuff that matters is in that extent. 5171 * 5172 **********************************************************************/ 5173 static void 5174 em_print_nvm_info(struct adapter *adapter) 5175 { 5176 u16 eeprom_data; 5177 int i, j, row = 0; 5178 5179 /* Its a bit crude, but it gets the job done */ 5180 printf("\nInterface EEPROM Dump:\n"); 5181 printf("Offset\n0x0000 "); 5182 for (i = 0, j = 0; i < 32; i++, j++) { 5183 if (j == 8) { /* Make the offset block */ 5184 j = 0; ++row; 5185 printf("\n0x00%x0 ",row); 5186 } 5187 e1000_read_nvm(&adapter->hw, i, 1, &eeprom_data); 5188 printf("%04x ", eeprom_data); 5189 } 5190 printf("\n"); 5191 } 5192 5193 static int 5194 em_sysctl_debug_info(SYSCTL_HANDLER_ARGS) 5195 { 5196 struct adapter *adapter; 5197 int error; 5198 int result; 5199 5200 result = -1; 5201 error = sysctl_handle_int(oidp, &result, 0, req); 5202 5203 if (error || !req->newptr) 5204 return (error); 5205 5206 if (result == 1) { 5207 adapter = (struct adapter *)arg1; 5208 em_print_debug_info(adapter); 5209 } 5210 /* 5211 * This value will cause a hex dump of the 5212 * first 32 16-bit words of the EEPROM to 5213 * the screen. 5214 */ 5215 if (result == 2) { 5216 adapter = (struct adapter *)arg1; 5217 em_print_nvm_info(adapter); 5218 } 5219 5220 return (error); 5221 } 5222 5223 5224 static int 5225 em_sysctl_stats(SYSCTL_HANDLER_ARGS) 5226 { 5227 struct adapter *adapter; 5228 int error; 5229 int result; 5230 5231 result = -1; 5232 error = sysctl_handle_int(oidp, &result, 0, req); 5233 5234 if (error || !req->newptr) 5235 return (error); 5236 5237 if (result == 1) { 5238 adapter = (struct adapter *)arg1; 5239 em_print_hw_stats(adapter); 5240 } 5241 5242 return (error); 5243 } 5244 5245 static int 5246 em_sysctl_int_delay(SYSCTL_HANDLER_ARGS) 5247 { 5248 struct em_int_delay_info *info; 5249 struct adapter *adapter; 5250 uint32_t regval; 5251 int error; 5252 int usecs; 5253 int ticks; 5254 5255 info = (struct em_int_delay_info *)arg1; 5256 usecs = info->value; 5257 error = sysctl_handle_int(oidp, &usecs, 0, req); 5258 if (error != 0 || req->newptr == NULL) 5259 return (error); 5260 if (usecs < 0 || usecs > EM_TICKS_TO_USECS(65535)) 5261 return (EINVAL); 5262 info->value = usecs; 5263 ticks = EM_USECS_TO_TICKS(usecs); 5264 5265 adapter = info->adapter; 5266 5267 EM_CORE_LOCK(adapter); 5268 regval = E1000_READ_OFFSET(&adapter->hw, info->offset); 5269 regval = (regval & ~0xffff) | (ticks & 0xffff); 5270 /* Handle a few special cases. */ 5271 switch (info->offset) { 5272 case E1000_RDTR: 5273 break; 5274 case E1000_TIDV: 5275 if (ticks == 0) { 5276 adapter->txd_cmd &= ~E1000_TXD_CMD_IDE; 5277 /* Don't write 0 into the TIDV register. */ 5278 regval++; 5279 } else 5280 if (adapter->hw.mac.type != e1000_82575) 5281 adapter->txd_cmd |= E1000_TXD_CMD_IDE; 5282 break; 5283 } 5284 E1000_WRITE_OFFSET(&adapter->hw, info->offset, regval); 5285 EM_CORE_UNLOCK(adapter); 5286 return (0); 5287 } 5288 5289 static void 5290 em_add_int_delay_sysctl(struct adapter *adapter, const char *name, 5291 const char *description, struct em_int_delay_info *info, 5292 int offset, int value) 5293 { 5294 info->adapter = adapter; 5295 info->offset = offset; 5296 info->value = value; 5297 SYSCTL_ADD_PROC(device_get_sysctl_ctx(adapter->dev), 5298 SYSCTL_CHILDREN(device_get_sysctl_tree(adapter->dev)), 5299 OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW, 5300 info, 0, em_sysctl_int_delay, "I", description); 5301 } 5302 5303 #ifdef EM_FAST_IRQ 5304 static void 5305 em_add_rx_process_limit(struct adapter *adapter, const char *name, 5306 const char *description, int *limit, int value) 5307 { 5308 *limit = value; 5309 SYSCTL_ADD_INT(device_get_sysctl_ctx(adapter->dev), 5310 SYSCTL_CHILDREN(device_get_sysctl_tree(adapter->dev)), 5311 OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW, limit, value, description); 5312 } 5313 #endif
Cache object: d5d41ee11843e626709dbbe37af9e0fa
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