Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/dev/eqos/if_eqos_reg.h
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1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2022 Jared McNeill <jmcneill@invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $Id: eqos_reg.h 921 2022-08-09 18:38:11Z sos $ 29 */ 30 31 /* 32 * DesignWare Ethernet Quality-of-Service controller 33 */ 34 35 #ifndef _EQOS_REG_H 36 #define _EQOS_REG_H 37 38 #define GMAC_MAC_CONFIGURATION 0x0000 39 #define GMAC_MAC_CONFIGURATION_CST (1U << 21) 40 #define GMAC_MAC_CONFIGURATION_ACS (1U << 20) 41 #define GMAC_MAC_CONFIGURATION_BE (1U << 18) 42 #define GMAC_MAC_CONFIGURATION_JD (1U << 17) 43 #define GMAC_MAC_CONFIGURATION_JE (1U << 16) 44 #define GMAC_MAC_CONFIGURATION_PS (1U << 15) 45 #define GMAC_MAC_CONFIGURATION_FES (1U << 14) 46 #define GMAC_MAC_CONFIGURATION_DM (1U << 13) 47 #define GMAC_MAC_CONFIGURATION_DCRS (1U << 9) 48 #define GMAC_MAC_CONFIGURATION_TE (1U << 1) 49 #define GMAC_MAC_CONFIGURATION_RE (1U << 0) 50 #define GMAC_MAC_EXT_CONFIGURATION 0x0004 51 #define GMAC_MAC_PACKET_FILTER 0x0008 52 #define GMAC_MAC_PACKET_FILTER_HPF (1U << 10) 53 #define GMAC_MAC_PACKET_FILTER_PCF_MASK (3U << 6) 54 #define GMAC_MAC_PACKET_FILTER_PCF_ALL (2U << 6) 55 #define GMAC_MAC_PACKET_FILTER_DBF (1U << 5) 56 #define GMAC_MAC_PACKET_FILTER_PM (1U << 4) 57 #define GMAC_MAC_PACKET_FILTER_HMC (1U << 2) 58 #define GMAC_MAC_PACKET_FILTER_HUC (1U << 1) 59 #define GMAC_MAC_PACKET_FILTER_PR (1U << 0) 60 #define GMAC_MAC_WATCHDOG_TIMEOUT 0x000C 61 #define GMAC_MAC_HASH_TABLE_REG0 0x0010 62 #define GMAC_MAC_HASH_TABLE_REG1 0x0014 63 #define GMAC_MAC_VLAN_TAG 0x0050 64 #define GMAC_MAC_Q0_TX_FLOW_CTRL 0x0070 65 #define GMAC_MAC_Q0_TX_FLOW_CTRL_PT_SHIFT 16 66 #define GMAC_MAC_Q0_TX_FLOW_CTRL_TFE (1U << 1) 67 #define GMAC_MAC_RX_FLOW_CTRL 0x0090 68 #define GMAC_MAC_RX_FLOW_CTRL_RFE (1U << 0) 69 #define GMAC_RXQ_CTRL0 0x00A0 70 #define GMAC_RXQ_CTRL0_EN_MASK 0x3 71 #define GMAC_RXQ_CTRL0_EN_DCB 0x2 72 #define GMAC_RXQ_CTRL1 0x00A4 73 #define GMAC_MAC_INTERRUPT_STATUS 0x00B0 74 #define GMAC_MAC_INTERRUPT_ENABLE 0x00B4 75 #define GMAC_MAC_RX_TX_STATUS 0x00B8 76 #define GMAC_MAC_RX_TX_STATUS_RWT (1U << 8) 77 #define GMAC_MAC_RX_TX_STATUS_EXCOL (1U << 5) 78 #define GMAC_MAC_RX_TX_STATUS_LCOL (1U << 4) 79 #define GMAC_MAC_RX_TX_STATUS_EXDEF (1U << 3) 80 #define GMAC_MAC_RX_TX_STATUS_LCARR (1U << 2) 81 #define GMAC_MAC_RX_TX_STATUS_NCARR (1U << 1) 82 #define GMAC_MAC_RX_TX_STATUS_TJT (1U << 0) 83 #define GMAC_MAC_PMT_CONTROL_STATUS 0x00C0 84 #define GMAC_MAC_RWK_PACKET_FILTER 0x00C4 85 #define GMAC_MAC_LPI_CONTROL_STATUS 0x00D0 86 #define GMAC_MAC_LPI_TIMERS_CONTROL 0x00D4 87 #define GMAC_MAC_LPI_ENTRY_TIMER 0x00D8 88 #define GMAC_MAC_1US_TIC_COUNTER 0x00DC 89 #define GMAC_MAC_PHYIF_CONTROL_STATUS 0x00F8 90 #define GMAC_MAC_VERSION 0x0110 91 #define GMAC_MAC_VERSION_USERVER_SHIFT 8 92 #define GMAC_MAC_VERSION_USERVER_MASK (0xFFU << GMAC_MAC_VERSION_USERVER_SHIFT) 93 #define GMAC_MAC_VERSION_SNPSVER_MASK 0xFFU 94 #define GMAC_MAC_DEBUG 0x0114 95 #define GMAC_MAC_HW_FEATURE(n) (0x011C + 0x4 * (n)) 96 #define GMAC_MAC_HW_FEATURE1_ADDR64_SHIFT 14 97 #define GMAC_MAC_HW_FEATURE1_ADDR64_MASK (0x3U << GMAC_MAC_HW_FEATURE1_ADDR64_SHIFT) 98 #define GMAC_MAC_HW_FEATURE1_ADDR64_32BIT (0x0U << GMAC_MAC_HW_FEATURE1_ADDR64_SHIFT) 99 #define GMAC_MAC_MDIO_ADDRESS 0x0200 100 #define GMAC_MAC_MDIO_ADDRESS_PA_SHIFT 21 101 #define GMAC_MAC_MDIO_ADDRESS_RDA_SHIFT 16 102 #define GMAC_MAC_MDIO_ADDRESS_CR_SHIFT 8 103 #define GMAC_MAC_MDIO_ADDRESS_CR_MASK (0x7U << GMAC_MAC_MDIO_ADDRESS_CR_SHIFT) 104 #define GMAC_MAC_MDIO_ADDRESS_CR_60_100 (0U << GMAC_MAC_MDIO_ADDRESS_CR_SHIFT) 105 #define GMAC_MAC_MDIO_ADDRESS_CR_100_150 (1U << GMAC_MAC_MDIO_ADDRESS_CR_SHIFT) 106 #define GMAC_MAC_MDIO_ADDRESS_CR_20_35 (2U << GMAC_MAC_MDIO_ADDRESS_CR_SHIFT) 107 #define GMAC_MAC_MDIO_ADDRESS_CR_35_60 (3U << GMAC_MAC_MDIO_ADDRESS_CR_SHIFT) 108 #define GMAC_MAC_MDIO_ADDRESS_CR_150_250 (4U << GMAC_MAC_MDIO_ADDRESS_CR_SHIFT) 109 #define GMAC_MAC_MDIO_ADDRESS_CR_250_300 (5U << GMAC_MAC_MDIO_ADDRESS_CR_SHIFT) 110 #define GMAC_MAC_MDIO_ADDRESS_CR_300_500 (6U << GMAC_MAC_MDIO_ADDRESS_CR_SHIFT) 111 #define GMAC_MAC_MDIO_ADDRESS_CR_500_800 (7U << GMAC_MAC_MDIO_ADDRESS_CR_SHIFT) 112 #define GMAC_MAC_MDIO_ADDRESS_SKAP (1U << 4) 113 #define GMAC_MAC_MDIO_ADDRESS_GOC_SHIFT 2 114 #define GMAC_MAC_MDIO_ADDRESS_GOC_READ (3U << GMAC_MAC_MDIO_ADDRESS_GOC_SHIFT) 115 #define GMAC_MAC_MDIO_ADDRESS_GOC_WRITE (1U << GMAC_MAC_MDIO_ADDRESS_GOC_SHIFT) 116 #define GMAC_MAC_MDIO_ADDRESS_C45E (1U << 1) 117 #define GMAC_MAC_MDIO_ADDRESS_GB (1U << 0) 118 #define GMAC_MAC_MDIO_DATA 0x0204 119 #define GMAC_MAC_CSR_SW_CTRL 0x0230 120 #define GMAC_MAC_ADDRESS0_HIGH 0x0300 121 #define GMAC_MAC_ADDRESS0_LOW 0x0304 122 #define GMAC_MMC_CONTROL 0x0700 123 #define GMAC_MMC_CONTROL_UCDBC (1U << 8) 124 #define GMAC_MMC_CONTROL_CNTPRSTLVL (1U << 5) 125 #define GMAC_MMC_CONTROL_CNTPRST (1U << 4) 126 #define GMAC_MMC_CONTROL_CNTFREEZ (1U << 3) 127 #define GMAC_MMC_CONTROL_RSTONRD (1U << 2) 128 #define GMAC_MMC_CONTROL_CNTSTOPRO (1U << 1) 129 #define GMAC_MMC_CONTROL_CNTRST (1U << 0) 130 #define GMAC_MMC_RX_INTERRUPT 0x0704 131 #define GMAC_MMC_TX_INTERRUPT 0x0708 132 #define GMAC_MMC_RX_INTERRUPT_MASK 0x070C 133 #define GMAC_MMC_TX_INTERRUPT_MASK 0x0710 134 #define GMAC_TX_OCTET_COUNT_GOOD_BAD 0x0714 135 #define GMAC_TX_PACKET_COUNT_GOOD_BAD 0x0718 136 #define GMAC_TX_UNDERFLOW_ERROR_PACKETS 0x0748 137 #define GMAC_TX_CARRIER_ERROR_PACKETS 0x0760 138 #define GMAC_TX_OCTET_COUNT_GOOD 0x0764 139 #define GMAC_TX_PACKET_COUNT_GOOD 0x0768 140 #define GMAC_RX_PACKETS_COUNT_GOOD_BAD 0x0780 141 #define GMAC_RX_OCTET_COUNT_GOOD_BAD 0x0784 142 #define GMAC_RX_OCTET_COUNT_GOOD 0x0788 143 #define GMAC_RX_MULTICAST_PACKETS_GOOD 0x0790 144 #define GMAC_RX_CRC_ERROR_PACKETS 0x0794 145 #define GMAC_RX_LENGTH_ERROR_PACKETS 0x07C8 146 #define GMAC_RX_FIFO_OVERFLOW_PACKETS 0x07D4 147 #define GMAC_MMC_IPC_RX_INTERRUPT_MASK 0x0800 148 #define GMAC_MMC_IPC_RX_INTERRUPT 0x0808 149 #define GMAC_RXIPV4_GOOD_PACKETS 0x0810 150 #define GMAC_RXIPV4_HEADER_ERROR_PACKETS 0x0814 151 #define GMAC_RXIPV6_GOOD_PACKETS 0x0824 152 #define GMAC_RXIPV6_HEADER_ERROR_PACKETS 0x0828 153 #define GMAC_RXUDP_ERROR_PACKETS 0x0834 154 #define GMAC_RXTCP_ERROR_PACKETS 0x083C 155 #define GMAC_RXICMP_ERROR_PACKETS 0x0844 156 #define GMAC_RXIPV4_HEADER_ERROR_OCTETS 0x0854 157 #define GMAC_RXIPV6_HEADER_ERROR_OCTETS 0x0868 158 #define GMAC_RXUDP_ERROR_OCTETS 0x0874 159 #define GMAC_RXTCP_ERROR_OCTETS 0x087C 160 #define GMAC_RXICMP_ERROR_OCTETS 0x0884 161 #define GMAC_MAC_TIMESTAMP_CONTROL 0x0B00 162 #define GMAC_MAC_SUB_SECOND_INCREMENT 0x0B04 163 #define GMAC_MAC_SYSTEM_TIME_SECS 0x0B08 164 #define GMAC_MAC_SYSTEM_TIME_NS 0x0B0C 165 #define GMAC_MAC_SYS_TIME_SECS_UPDATE 0x0B10 166 #define GMAC_MAC_SYS_TIME_NS_UPDATE 0x0B14 167 #define GMAC_MAC_TIMESTAMP_ADDEND 0x0B18 168 #define GMAC_MAC_TIMESTAMP_STATUS 0x0B20 169 #define GMAC_MAC_TX_TS_STATUS_NS 0x0B30 170 #define GMAC_MAC_TX_TS_STATUS_SECS 0x0B34 171 #define GMAC_MAC_AUXILIARY_CONTROL 0x0B40 172 #define GMAC_MAC_AUXILIARY_TS_NS 0x0B48 173 #define GMAC_MAC_AUXILIARY_TS_SECS 0x0B4C 174 #define GMAC_MAC_TS_INGRESS_CORR_NS 0x0B58 175 #define GMAC_MAC_TS_EGRESS_CORR_NS 0x0B5C 176 #define GMAC_MAC_TS_INGRESS_LATENCY 0x0B68 177 #define GMAC_MAC_TS_EGRESS_LATENCY 0x0B6C 178 #define GMAC_MAC_PPS_CONTROL 0x0B70 179 #define GMAC_MTL_DBG_CTL 0x0C08 180 #define GMAC_MTL_DBG_STS 0x0C0C 181 #define GMAC_MTL_FIFO_DEBUG_DATA 0x0C10 182 #define GMAC_MTL_INTERRUPT_STATUS 0x0C20 183 #define GMAC_MTL_INTERRUPT_STATUS_DBGIS (1U << 17) 184 #define GMAC_MTL_INTERRUPT_STATUS_Q0IS (1U << 0) 185 #define GMAC_MTL_TXQ0_OPERATION_MODE 0x0D00 186 #define GMAC_MTL_TXQ0_OPERATION_MODE_TXQEN_SHIFT 2 187 #define GMAC_MTL_TXQ0_OPERATION_MODE_TXQEN_MASK (0x3U << GMAC_MTL_TXQ0_OPERATION_MODE_TXQEN_SHIFT) 188 #define GMAC_MTL_TXQ0_OPERATION_MODE_TXQEN_EN (2U << GMAC_MTL_TXQ0_OPERATION_MODE_TXQEN_SHIFT) 189 #define GMAC_MTL_TXQ0_OPERATION_MODE_TSF (1U << 1) 190 #define GMAC_MTL_TXQ0_OPERATION_MODE_FTQ (1U << 0) 191 #define GMAC_MTL_TXQ0_UNDERFLOW 0x0D04 192 #define GMAC_MTL_TXQ0_DEBUG 0x0D08 193 #define GMAC_MTL_Q0_INTERRUPT_CTRL_STATUS 0x0D2C 194 #define GMAC_MTL_Q0_INTERRUPT_CTRL_STATUS_RXOIE (1U << 24) 195 #define GMAC_MTL_Q0_INTERRUPT_CTRL_STATUS_RXOVFIS (1U << 16) 196 #define GMAC_MTL_Q0_INTERRUPT_CTRL_STATUS_TXUIE (1U << 8) 197 #define GMAC_MTL_Q0_INTERRUPT_CTRL_STATUS_TXUNFIS (1U << 0) 198 #define GMAC_MTL_RXQ0_OPERATION_MODE 0x0D30 199 #define GMAC_MTL_RXQ0_OPERATION_MODE_RSF (1U << 5) 200 #define GMAC_MTL_RXQ0_OPERATION_MODE_FEP (1U << 4) 201 #define GMAC_MTL_RXQ0_OPERATION_MODE_FUP (1U << 3) 202 #define GMAC_MTL_RXQ0_MISS_PKT_OVF_CNT 0x0D34 203 #define GMAC_MTL_RXQ0_DEBUG 0x0D38 204 #define GMAC_DMA_MODE 0x1000 205 #define GMAC_DMA_MODE_SWR (1U << 0) 206 #define GMAC_DMA_SYSBUS_MODE 0x1004 207 #define GMAC_DMA_SYSBUS_MODE_WR_OSR_LMT_SHIFT 24 208 #define GMAC_DMA_SYSBUS_MODE_WR_OSR_LMT_MASK (0x3U << GMAC_DMA_SYSBUS_MODE_WR_OSR_LMT_SHIFT) 209 #define GMAC_DMA_SYSBUS_MODE_RD_OSR_LMT_SHIFT 16 210 #define GMAC_DMA_SYSBUS_MODE_RD_OSR_LMT_MASK (0x7U << GMAC_DMA_SYSBUS_MODE_RD_OSR_LMT_SHIFT) 211 #define GMAC_DMA_SYSBUS_MODE_MB (1U << 14) 212 #define GMAC_DMA_SYSBUS_MODE_EAME (1U << 11) 213 #define GMAC_DMA_SYSBUS_MODE_BLEN16 (1U << 3) 214 #define GMAC_DMA_SYSBUS_MODE_BLEN8 (1U << 2) 215 #define GMAC_DMA_SYSBUS_MODE_BLEN4 (1U << 1) 216 #define GMAC_DMA_SYSBUS_MODE_FB (1U << 0) 217 #define GMAC_DMA_INTERRUPT_STATUS 0x1008 218 #define GMAC_DMA_DEBUG_STATUS0 0x100C 219 #define GMAC_AXI_LPI_ENTRY_INTERVAL 0x1040 220 #define GMAC_RWK_FILTERn_BYTE_MASK(n) (0x10C0 + 0x4 * (n)) 221 #define GMAC_RWK_FILTER01_CRC 0x10D0 222 #define GMAC_RWK_FILTER23_CRC 0x10D4 223 #define GMAC_RWK_FILTER_OFFSET 0x10D8 224 #define GMAC_RWK_FILTER_COMMAND 0x10DC 225 #define GMAC_DMA_CHAN0_CONTROL 0x1100 226 #define GMAC_DMA_CHAN0_CONTROL_DSL_SHIFT 18 227 #define GMAC_DMA_CHAN0_CONTROL_DSL_MASK (0x7U << GMAC_DMA_CHAN0_CONTROL_DSL_SHIFT) 228 #define GMAC_DMA_CHAN0_CONTROL_PBLX8 (1U << 16) 229 #define GMAC_DMA_CHAN0_TX_CONTROL 0x1104 230 #define GMAC_DMA_CHAN0_TX_CONTROL_OSP (1U << 4) 231 #define GMAC_DMA_CHAN0_TX_CONTROL_START (1U << 0) 232 #define GMAC_DMA_CHAN0_RX_CONTROL 0x1108 233 #define GMAC_DMA_CHAN0_RX_CONTROL_RBSZ_SHIFT 1 234 #define GMAC_DMA_CHAN0_RX_CONTROL_RBSZ_MASK (0x3FFFU << GMAC_DMA_CHAN0_RX_CONTROL_RBSZ_SHIFT) 235 #define GMAC_DMA_CHAN0_RX_CONTROL_START (1U << 0) 236 #define GMAC_DMA_CHAN0_TX_BASE_ADDR_HI 0x1110 237 #define GMAC_DMA_CHAN0_TX_BASE_ADDR 0x1114 238 #define GMAC_DMA_CHAN0_RX_BASE_ADDR_HI 0x1118 239 #define GMAC_DMA_CHAN0_RX_BASE_ADDR 0x111C 240 #define GMAC_DMA_CHAN0_TX_END_ADDR 0x1120 241 #define GMAC_DMA_CHAN0_RX_END_ADDR 0x1128 242 #define GMAC_DMA_CHAN0_TX_RING_LEN 0x112C 243 #define GMAC_DMA_CHAN0_RX_RING_LEN 0x1130 244 #define GMAC_DMA_CHAN0_INTR_ENABLE 0x1134 245 #define GMAC_DMA_CHAN0_INTR_ENABLE_NIE (1U << 15) 246 #define GMAC_DMA_CHAN0_INTR_ENABLE_AIE (1U << 14) 247 #define GMAC_DMA_CHAN0_INTR_ENABLE_CDE (1U << 13) 248 #define GMAC_DMA_CHAN0_INTR_ENABLE_FBE (1U << 12) 249 #define GMAC_DMA_CHAN0_INTR_ENABLE_ERI (1U << 11) 250 #define GMAC_DMA_CHAN0_INTR_ENABLE_ETI (1U << 10) 251 #define GMAC_DMA_CHAN0_INTR_ENABLE_RWT (1U << 9) 252 #define GMAC_DMA_CHAN0_INTR_ENABLE_RPS (1U << 8) 253 #define GMAC_DMA_CHAN0_INTR_ENABLE_RBU (1U << 7) 254 #define GMAC_DMA_CHAN0_INTR_ENABLE_RIE (1U << 6) 255 #define GMAC_DMA_CHAN0_INTR_ENABLE_TPU (1U << 2) 256 #define GMAC_DMA_CHAN0_INTR_ENABLE_TPS (1U << 1) 257 #define GMAC_DMA_CHAN0_INTR_ENABLE_TIE (1U << 0) 258 #define GMAC_DMA_CHAN0_RX_WATCHDOG 0x1138 259 #define GMAC_DMA_CHAN0_SLOT_CTRL_STATUS 0x113C 260 #define GMAC_DMA_CHAN0_CUR_TX_DESC 0x1144 261 #define GMAC_DMA_CHAN0_CUR_RX_DESC 0x114C 262 #define GMAC_DMA_CHAN0_CUR_TX_BUF_ADDR 0x1154 263 #define GMAC_DMA_CHAN0_CUR_RX_BUF_ADDR 0x115C 264 #define GMAC_DMA_CHAN0_STATUS 0x1160 265 #define GMAC_DMA_CHAN0_STATUS_NIS (1U << 15) 266 #define GMAC_DMA_CHAN0_STATUS_AIS (1U << 14) 267 #define GMAC_DMA_CHAN0_STATUS_CDE (1U << 13) 268 #define GMAC_DMA_CHAN0_STATUS_FB (1U << 12) 269 #define GMAC_DMA_CHAN0_STATUS_ERI (1U << 11) 270 #define GMAC_DMA_CHAN0_STATUS_ETI (1U << 10) 271 #define GMAC_DMA_CHAN0_STATUS_RWT (1U << 9) 272 #define GMAC_DMA_CHAN0_STATUS_RPS (1U << 8) 273 #define GMAC_DMA_CHAN0_STATUS_RBU (1U << 7) 274 #define GMAC_DMA_CHAN0_STATUS_RI (1U << 6) 275 #define GMAC_DMA_CHAN0_STATUS_TPU (1U << 2) 276 #define GMAC_DMA_CHAN0_STATUS_TPS (1U << 1) 277 #define GMAC_DMA_CHAN0_STATUS_TI (1U << 0) 278 279 #define EQOS_TDES2_IOC (1U << 31) 280 #define EQOS_TDES3_OWN (1U << 31) 281 #define EQOS_TDES3_FD (1U << 29) 282 #define EQOS_TDES3_LD (1U << 28) 283 #define EQOS_TDES3_DE (1U << 23) 284 #define EQOS_TDES3_OE (1U << 21) 285 #define EQOS_TDES3_ES (1U << 15) 286 287 #define EQOS_RDES3_OWN (1U << 31) 288 #define EQOS_RDES3_IOC (1U << 30) 289 #define EQOS_RDES3_BUF1V (1U << 24) 290 #define EQOS_RDES3_GP (1U << 23) 291 #define EQOS_RDES3_OE (1U << 21) 292 #define EQOS_RDES3_RE (1U << 20) 293 #define EQOS_RDES3_LENGTH_MASK 0x7FFFU 294 295 #endif
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