Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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sys/dev/esp/ncr53c9xvar.h
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1 /* $NetBSD: ncr53c9xvar.h,v 1.55 2011/07/31 18:39:00 jakllsch Exp $ */ 2 3 /*- 4 * SPDX-License-Identifier: BSD-2-Clause-NetBSD AND BSD-4-Clause 5 * 6 * Copyright (c) 1997 The NetBSD Foundation, Inc. 7 * All rights reserved. 8 * 9 * This code is derived from software contributed to The NetBSD Foundation 10 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 11 * NASA Ames Research Center. 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 23 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 24 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 25 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32 * POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 /*- 36 * Copyright (c) 1994 Peter Galbavy. All rights reserved. 37 * 38 * Redistribution and use in source and binary forms, with or without 39 * modification, are permitted provided that the following conditions 40 * are met: 41 * 1. Redistributions of source code must retain the above copyright 42 * notice, this list of conditions and the following disclaimer. 43 * 2. Redistributions in binary form must reproduce the above copyright 44 * notice, this list of conditions and the following disclaimer in the 45 * documentation and/or other materials provided with the distribution. 46 * 3. All advertising materials mentioning features or use of this software 47 * must display the following acknowledgement: 48 * This product includes software developed by Peter Galbavy. 49 * 4. The name of the author may not be used to endorse or promote products 50 * derived from this software without specific prior written permission. 51 * 52 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 53 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 54 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 55 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 56 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 57 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 58 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 59 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 60 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 61 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 62 */ 63 64 /* $FreeBSD$ */ 65 66 #ifndef _NCR53C9XVAR_H_ 67 #define _NCR53C9XVAR_H_ 68 69 #include <sys/lock.h> 70 71 /* Set this to 1 for normal debug, or 2 for per-target tracing. */ 72 /* #define NCR53C9X_DEBUG 2 */ 73 74 /* Wide or differential can have 16 targets */ 75 #define NCR_NLUN 8 76 77 #define NCR_ABORT_TIMEOUT 2000 /* time to wait for abort */ 78 #define NCR_SENSE_TIMEOUT 1000 /* time to wait for sense */ 79 80 #define FREQTOCCF(freq) (((freq + 4) / 5)) 81 82 /* 83 * NCR 53c9x variants. Note these values are used as indexes into 84 * a table; do not modify them unless you know what you are doing. 85 */ 86 #define NCR_VARIANT_ESP100 0 87 #define NCR_VARIANT_ESP100A 1 88 #define NCR_VARIANT_ESP200 2 89 #define NCR_VARIANT_NCR53C94 3 90 #define NCR_VARIANT_NCR53C96 4 91 #define NCR_VARIANT_ESP406 5 92 #define NCR_VARIANT_FAS408 6 93 #define NCR_VARIANT_FAS216 7 94 #define NCR_VARIANT_AM53C974 8 95 #define NCR_VARIANT_FAS366 9 96 #define NCR_VARIANT_NCR53C90_86C01 10 97 #define NCR_VARIANT_FAS100A 11 98 #define NCR_VARIANT_FAS236 12 99 #define NCR_VARIANT_MAX 13 100 101 /* XXX Max tag depth. Should this be defined in the register header? */ 102 #define NCR_TAG_DEPTH 256 103 104 /* 105 * ECB. Holds additional information for each SCSI command Comments: We 106 * need a separate scsi command block because we may need to overwrite it 107 * with a request sense command. Basically, we refrain from fiddling with 108 * the ccb union (except do the expected updating of return values). 109 * We'll generally update: ccb->ccb_h.status and ccb->csio.{resid, 110 * scsi_status,sense_data}. 111 */ 112 struct ncr53c9x_ecb { 113 /* These fields are preserved between alloc and free. */ 114 struct callout ch; 115 struct ncr53c9x_softc *sc; 116 int tag_id; 117 int flags; 118 119 union ccb *ccb; /* SCSI xfer ctrl block from above */ 120 TAILQ_ENTRY(ncr53c9x_ecb) free_links; 121 TAILQ_ENTRY(ncr53c9x_ecb) chain; 122 #define ECB_ALLOC 0x01 123 #define ECB_READY 0x02 124 #define ECB_SENSE 0x04 125 #define ECB_ABORT 0x40 126 #define ECB_RESET 0x80 127 #define ECB_TENTATIVE_DONE 0x100 128 int timeout; 129 130 struct { 131 uint8_t msg[3]; /* Selection Id msg and tags */ 132 struct scsi_generic cmd; /* SCSI command block */ 133 } cmd; 134 uint8_t *daddr; /* Saved data pointer */ 135 int clen; /* Size of command in cmd.cmd */ 136 int dleft; /* Residue */ 137 uint8_t stat; /* SCSI status byte */ 138 uint8_t tag[2]; /* TAG bytes */ 139 uint8_t pad[1]; 140 141 #if defined(NCR53C9X_DEBUG) && NCR53C9X_DEBUG > 1 142 char trace[1000]; 143 #endif 144 }; 145 #if defined(NCR53C9X_DEBUG) && NCR53C9X_DEBUG > 1 146 #define ECB_TRACE(ecb, msg, a, b) do { \ 147 const char *f = "[" msg "]"; \ 148 int n = strlen((ecb)->trace); \ 149 if (n < (sizeof((ecb)->trace)-100)) \ 150 sprintf((ecb)->trace + n, f, a, b); \ 151 } while (/* CONSTCOND */0) 152 #else 153 #define ECB_TRACE(ecb, msg, a, b) 154 #endif 155 156 /* 157 * Some info about each (possible) target and LUN on the SCSI bus. 158 * 159 * SCSI I and II devices can have up to 8 LUNs, each with up to 256 160 * outstanding tags. SCSI III devices have 64-bit LUN identifiers 161 * that can be sparsely allocated. 162 * 163 * Since SCSI II devices can have up to 8 LUNs, we use an array 164 * of 8 pointers to ncr53c9x_linfo structures for fast lookup. 165 * Longer LUNs need to traverse the linked list. 166 */ 167 168 struct ncr53c9x_linfo { 169 int64_t lun; 170 LIST_ENTRY(ncr53c9x_linfo) link; 171 time_t last_used; 172 uint8_t used; /* # slots in use */ 173 uint8_t avail; /* where to start scanning */ 174 uint8_t busy; 175 struct ncr53c9x_ecb *untagged; 176 struct ncr53c9x_ecb *queued[NCR_TAG_DEPTH]; 177 }; 178 179 struct ncr53c9x_xinfo { 180 uint8_t period; 181 uint8_t offset; 182 uint8_t width; 183 }; 184 185 struct ncr53c9x_tinfo { 186 int cmds; /* # of commands processed */ 187 int dconns; /* # of disconnects */ 188 int touts; /* # of timeouts */ 189 int perrs; /* # of parity errors */ 190 int senses; /* # of request sense commands sent */ 191 uint8_t flags; 192 #define T_SYNCHOFF 0x01 /* SYNC mode is permanently off */ 193 #define T_RSELECTOFF 0x02 /* RE-SELECT mode is off */ 194 #define T_TAG 0x04 /* Turn on TAG QUEUEs */ 195 #define T_SDTRSENT 0x08 /* SDTR message has been sent to */ 196 #define T_WDTRSENT 0x10 /* WDTR message has been sent to */ 197 struct ncr53c9x_xinfo curr; 198 struct ncr53c9x_xinfo goal; 199 LIST_HEAD(lun_list, ncr53c9x_linfo) luns; 200 struct ncr53c9x_linfo *lun[NCR_NLUN]; /* For speedy lookups */ 201 }; 202 203 /* Look up a lun in a tinfo */ 204 #define TINFO_LUN(t, l) ( \ 205 (((l) < NCR_NLUN) && (((t)->lun[(l)]) != NULL)) \ 206 ? ((t)->lun[(l)]) \ 207 : ncr53c9x_lunsearch((t), (int64_t)(l)) \ 208 ) 209 210 /* Register a linenumber (for debugging). */ 211 #define LOGLINE(p) 212 213 #define NCR_SHOWECBS 0x01 214 #define NCR_SHOWINTS 0x02 215 #define NCR_SHOWCMDS 0x04 216 #define NCR_SHOWMISC 0x08 217 #define NCR_SHOWTRAC 0x10 218 #define NCR_SHOWSTART 0x20 219 #define NCR_SHOWPHASE 0x40 220 #define NCR_SHOWDMA 0x80 221 #define NCR_SHOWCCMDS 0x100 222 #define NCR_SHOWMSGS 0x200 223 224 #ifdef NCR53C9X_DEBUG 225 extern int ncr53c9x_debug; 226 #define NCR_ECBS(str) \ 227 do { \ 228 if ((ncr53c9x_debug & NCR_SHOWECBS) != 0) \ 229 printf str; \ 230 } while (/* CONSTCOND */0) 231 #define NCR_MISC(str) \ 232 do { \ 233 if ((ncr53c9x_debug & NCR_SHOWMISC) != 0) \ 234 printf str; \ 235 } while (/* CONSTCOND */0) 236 #define NCR_INTS(str) \ 237 do { \ 238 if ((ncr53c9x_debug & NCR_SHOWINTS) != 0) \ 239 printf str; \ 240 } while (/* CONSTCOND */0) 241 #define NCR_TRACE(str) \ 242 do { \ 243 if ((ncr53c9x_debug & NCR_SHOWTRAC) != 0) \ 244 printf str; \ 245 } while (/* CONSTCOND */0) 246 #define NCR_CMDS(str) \ 247 do { \ 248 if ((ncr53c9x_debug & NCR_SHOWCMDS) != 0) \ 249 printf str; \ 250 } while (/* CONSTCOND */0) 251 #define NCR_START(str) \ 252 do { \ 253 if ((ncr53c9x_debug & NCR_SHOWSTART) != 0) \ 254 printf str; \ 255 } while (/* CONSTCOND */0) 256 #define NCR_PHASE(str) \ 257 do { \ 258 if ((ncr53c9x_debug & NCR_SHOWPHASE) != 0) \ 259 printf str; \ 260 } while (/* CONSTCOND */0) 261 #define NCR_DMA(str) \ 262 do { \ 263 if ((ncr53c9x_debug & NCR_SHOWDMA) != 0) \ 264 printf str; \ 265 } while (/* CONSTCOND */0) 266 #define NCR_MSGS(str) \ 267 do { \ 268 if ((ncr53c9x_debug & NCR_SHOWMSGS) != 0) \ 269 printf str; \ 270 } while (/* CONSTCOND */0) 271 #else 272 #define NCR_ECBS(str) 273 #define NCR_MISC(str) 274 #define NCR_INTS(str) 275 #define NCR_TRACE(str) 276 #define NCR_CMDS(str) 277 #define NCR_START(str) 278 #define NCR_PHASE(str) 279 #define NCR_DMA(str) 280 #define NCR_MSGS(str) 281 #endif 282 283 #define NCR_MAX_MSG_LEN 8 284 285 struct ncr53c9x_softc; 286 287 /* 288 * Function switch used as glue to MD code 289 */ 290 struct ncr53c9x_glue { 291 /* Mandatory entry points. */ 292 uint8_t (*gl_read_reg)(struct ncr53c9x_softc *, int); 293 void (*gl_write_reg)(struct ncr53c9x_softc *, int, uint8_t); 294 int (*gl_dma_isintr)(struct ncr53c9x_softc *); 295 void (*gl_dma_reset)(struct ncr53c9x_softc *); 296 int (*gl_dma_intr)(struct ncr53c9x_softc *); 297 int (*gl_dma_setup)(struct ncr53c9x_softc *, void **, size_t *, 298 int, size_t *); 299 void (*gl_dma_go)(struct ncr53c9x_softc *); 300 void (*gl_dma_stop)(struct ncr53c9x_softc *); 301 int (*gl_dma_isactive)(struct ncr53c9x_softc *); 302 }; 303 304 struct ncr53c9x_softc { 305 device_t sc_dev; /* us as a device */ 306 307 struct cam_sim *sc_sim; /* our scsi adapter */ 308 struct cam_path *sc_path; /* our scsi channel */ 309 struct callout sc_watchdog; /* periodic timer */ 310 311 const struct ncr53c9x_glue *sc_glue; /* glue to MD code */ 312 313 int sc_cfflags; /* Copy of config flags */ 314 315 /* register defaults */ 316 uint8_t sc_cfg1; /* Config 1 */ 317 uint8_t sc_cfg2; /* Config 2, not ESP100 */ 318 uint8_t sc_cfg3; /* Config 3, ESP200,FAS */ 319 uint8_t sc_cfg3_fscsi; /* Chip-specific FSCSI bit */ 320 uint8_t sc_cfg4; /* Config 4, only ESP200 */ 321 uint8_t sc_cfg5; /* Config 5, only ESP200 */ 322 uint8_t sc_ccf; /* Clock Conversion */ 323 uint8_t sc_timeout; 324 325 /* register copies, see ncr53c9x_readregs() */ 326 uint8_t sc_espintr; 327 uint8_t sc_espstat; 328 uint8_t sc_espstep; 329 uint8_t sc_espstat2; 330 uint8_t sc_espfflags; 331 332 /* Lists of command blocks */ 333 TAILQ_HEAD(ecb_list, ncr53c9x_ecb) ready_list; 334 335 struct ncr53c9x_ecb *sc_nexus; /* Current command */ 336 int sc_ntarg; 337 struct ncr53c9x_tinfo *sc_tinfo; 338 339 /* Data about the current nexus (updated for every cmd switch) */ 340 void *sc_dp; /* Current data pointer */ 341 ssize_t sc_dleft; /* Data left to transfer */ 342 343 /* Adapter state */ 344 int sc_phase; /* Copy of what bus phase we are in */ 345 int sc_prevphase; /* Copy of what bus phase we were in */ 346 uint8_t sc_state; /* State applicable to the adapter */ 347 uint8_t sc_flags; /* See below */ 348 uint8_t sc_selid; 349 uint8_t sc_lastcmd; 350 351 /* Message stuff */ 352 uint16_t sc_msgify; /* IDENTIFY message associated with nexus */ 353 uint16_t sc_msgout; /* What message is on its way out? */ 354 uint16_t sc_msgpriq; /* One or more messages to send (encoded) */ 355 uint16_t sc_msgoutq; /* What messages have been sent so far? */ 356 357 uint8_t *sc_omess; /* MSGOUT buffer */ 358 int sc_omess_self; /* MSGOUT buffer is self-allocated */ 359 void *sc_omp; /* Message pointer (for multibyte messages) */ 360 size_t sc_omlen; 361 uint8_t *sc_imess; /* MSGIN buffer */ 362 int sc_imess_self; /* MSGIN buffer is self-allocated */ 363 void *sc_imp; /* Message pointer (for multibyte messages) */ 364 size_t sc_imlen; 365 366 void *sc_cmdp; /* Command pointer (for DMAed commands) */ 367 size_t sc_cmdlen; /* Size of command in transit */ 368 369 /* Hardware attributes */ 370 int sc_freq; /* SCSI bus frequency in MHz */ 371 int sc_id; /* Our SCSI id */ 372 int sc_rev; /* Chip revision */ 373 int sc_features; /* Chip features */ 374 int sc_minsync; /* Minimum sync period / 4 */ 375 int sc_maxxfer; /* Maximum transfer size */ 376 int sc_maxoffset; /* Maximum offset */ 377 int sc_maxwidth; /* Maximum width */ 378 int sc_extended_geom; /* Should we return extended geometry */ 379 380 struct mtx sc_lock; /* driver mutex */ 381 382 struct ncr53c9x_ecb *ecb_array; 383 TAILQ_HEAD(,ncr53c9x_ecb) free_list; 384 }; 385 386 /* values for sc_state */ 387 #define NCR_IDLE 1 /* Waiting for something to do */ 388 #define NCR_SELECTING 2 /* SCSI command is arbiting */ 389 #define NCR_RESELECTED 3 /* Has been reselected */ 390 #define NCR_IDENTIFIED 4 /* Has gotten IFY but not TAG */ 391 #define NCR_CONNECTED 5 /* Actively using the SCSI bus */ 392 #define NCR_DISCONNECT 6 /* MSG_DISCONNECT received */ 393 #define NCR_CMDCOMPLETE 7 /* MSG_CMDCOMPLETE received */ 394 #define NCR_CLEANING 8 395 #define NCR_SBR 9 /* Expect a SCSI RST because we commanded it */ 396 397 /* values for sc_flags */ 398 #define NCR_DROP_MSGI 0x01 /* Discard all msgs (parity err detected) */ 399 #define NCR_ABORTING 0x02 /* Bailing out */ 400 #define NCR_ICCS 0x04 /* Expect status phase results */ 401 #define NCR_WAITI 0x08 /* Waiting for non-DMA data to arrive */ 402 #define NCR_ATN 0x10 /* ATN asserted */ 403 #define NCR_EXPECT_ILLCMD 0x20 /* Expect Illegal Command Interrupt */ 404 405 /* values for sc_features */ 406 #define NCR_F_HASCFG3 0x01 /* chip has CFG3 register */ 407 #define NCR_F_FASTSCSI 0x02 /* chip supports Fast mode */ 408 #define NCR_F_DMASELECT 0x04 /* can do dmaselect */ 409 #define NCR_F_SELATN3 0x08 /* chip supports SELATN3 command */ 410 #define NCR_F_LARGEXFER 0x10 /* chip supports transfers > 64k */ 411 412 /* values for sc_msgout */ 413 #define SEND_DEV_RESET 0x0001 414 #define SEND_PARITY_ERROR 0x0002 415 #define SEND_INIT_DET_ERR 0x0004 416 #define SEND_REJECT 0x0008 417 #define SEND_IDENTIFY 0x0010 418 #define SEND_ABORT 0x0020 419 #define SEND_TAG 0x0040 420 #define SEND_WDTR 0x0080 421 #define SEND_SDTR 0x0100 422 423 /* SCSI Status codes */ 424 #define ST_MASK 0x3e /* bit 0,6,7 is reserved */ 425 426 /* phase bits */ 427 #define IOI 0x01 428 #define CDI 0x02 429 #define MSGI 0x04 430 431 /* Information transfer phases */ 432 #define DATA_OUT_PHASE (0) 433 #define DATA_IN_PHASE (IOI) 434 #define COMMAND_PHASE (CDI) 435 #define STATUS_PHASE (CDI | IOI) 436 #define MESSAGE_OUT_PHASE (MSGI | CDI) 437 #define MESSAGE_IN_PHASE (MSGI | CDI | IOI) 438 439 #define PHASE_MASK (MSGI | CDI | IOI) 440 441 /* Some pseudo phases for getphase()*/ 442 #define BUSFREE_PHASE 0x100 /* Re/Selection no longer valid */ 443 #define INVALID_PHASE 0x101 /* Re/Selection valid, but no REQ yet */ 444 #define PSEUDO_PHASE 0x100 /* "pseudo" bit */ 445 446 /* 447 * Macros to read and write the chip's registers. 448 */ 449 #define NCR_READ_REG(sc, reg) \ 450 (*(sc)->sc_glue->gl_read_reg)((sc), (reg)) 451 #define NCR_WRITE_REG(sc, reg, val) \ 452 (*(sc)->sc_glue->gl_write_reg)((sc), (reg), (val)) 453 454 #ifdef NCR53C9X_DEBUG 455 #define NCRCMD(sc, cmd) do { \ 456 if ((ncr53c9x_debug & NCR_SHOWCCMDS) != 0) \ 457 printf("<CMD:0x%x %d>", (unsigned int)cmd, __LINE__); \ 458 sc->sc_lastcmd = cmd; \ 459 NCR_WRITE_REG(sc, NCR_CMD, cmd); \ 460 } while (/* CONSTCOND */ 0) 461 #else 462 #define NCRCMD(sc, cmd) NCR_WRITE_REG(sc, NCR_CMD, cmd) 463 #endif 464 465 /* 466 * Macros for locking 467 */ 468 #define NCR_LOCK_INIT(_sc) \ 469 mtx_init(&(_sc)->sc_lock, "ncr", "ncr53c9x lock", MTX_DEF); 470 #define NCR_LOCK_INITIALIZED(_sc) mtx_initialized(&(_sc)->sc_lock) 471 #define NCR_LOCK(_sc) mtx_lock(&(_sc)->sc_lock) 472 #define NCR_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_lock) 473 #define NCR_LOCK_ASSERT(_sc, _what) mtx_assert(&(_sc)->sc_lock, (_what)) 474 #define NCR_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_lock) 475 476 /* 477 * DMA macros for NCR53c9x 478 */ 479 #define NCRDMA_ISINTR(sc) (*(sc)->sc_glue->gl_dma_isintr)((sc)) 480 #define NCRDMA_RESET(sc) (*(sc)->sc_glue->gl_dma_reset)((sc)) 481 #define NCRDMA_INTR(sc) (*(sc)->sc_glue->gl_dma_intr)((sc)) 482 #define NCRDMA_SETUP(sc, addr, len, datain, dmasize) \ 483 (*(sc)->sc_glue->gl_dma_setup)((sc), (addr), (len), (datain), (dmasize)) 484 #define NCRDMA_GO(sc) (*(sc)->sc_glue->gl_dma_go)((sc)) 485 #define NCRDMA_STOP(sc) (*(sc)->sc_glue->gl_dma_stop)((sc)) 486 #define NCRDMA_ISACTIVE(sc) (*(sc)->sc_glue->gl_dma_isactive)((sc)) 487 488 /* 489 * Macro to convert the chip register Clock Per Byte value to 490 * Synchronous Transfer Period. 491 */ 492 #define ncr53c9x_cpb2stp(sc, cpb) \ 493 ((250 * (cpb)) / (sc)->sc_freq) 494 495 extern devclass_t esp_devclass; 496 497 int ncr53c9x_attach(struct ncr53c9x_softc *sc); 498 int ncr53c9x_detach(struct ncr53c9x_softc *sc); 499 void ncr53c9x_intr(void *arg); 500 501 #endif /* _NCR53C9XVAR_H_ */
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