Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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sys/dev/et/if_et.c
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1 /*- 2 * SPDX-License-Identifier: BSD-3-Clause 3 * 4 * Copyright (c) 2007 Sepherosa Ziehau. All rights reserved. 5 * 6 * This code is derived from software contributed to The DragonFly Project 7 * by Sepherosa Ziehau <sepherosa@gmail.com> 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in 17 * the documentation and/or other materials provided with the 18 * distribution. 19 * 3. Neither the name of The DragonFly Project nor the names of its 20 * contributors may be used to endorse or promote products derived 21 * from this software without specific, prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 24 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 25 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 26 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 27 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 28 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 29 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 30 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 31 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 33 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * $DragonFly: src/sys/dev/netif/et/if_et.c,v 1.10 2008/05/18 07:47:14 sephe Exp $ 37 */ 38 39 #include <sys/cdefs.h> 40 __FBSDID("$FreeBSD$"); 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/endian.h> 45 #include <sys/kernel.h> 46 #include <sys/bus.h> 47 #include <sys/malloc.h> 48 #include <sys/mbuf.h> 49 #include <sys/proc.h> 50 #include <sys/rman.h> 51 #include <sys/module.h> 52 #include <sys/socket.h> 53 #include <sys/sockio.h> 54 #include <sys/sysctl.h> 55 56 #include <net/ethernet.h> 57 #include <net/if.h> 58 #include <net/if_var.h> 59 #include <net/if_dl.h> 60 #include <net/if_types.h> 61 #include <net/bpf.h> 62 #include <net/if_arp.h> 63 #include <net/if_media.h> 64 #include <net/if_vlan_var.h> 65 66 #include <machine/bus.h> 67 68 #include <dev/mii/mii.h> 69 #include <dev/mii/miivar.h> 70 71 #include <dev/pci/pcireg.h> 72 #include <dev/pci/pcivar.h> 73 74 #include <dev/et/if_etreg.h> 75 #include <dev/et/if_etvar.h> 76 77 #include "miibus_if.h" 78 79 MODULE_DEPEND(et, pci, 1, 1, 1); 80 MODULE_DEPEND(et, ether, 1, 1, 1); 81 MODULE_DEPEND(et, miibus, 1, 1, 1); 82 83 /* Tunables. */ 84 static int msi_disable = 0; 85 TUNABLE_INT("hw.et.msi_disable", &msi_disable); 86 87 #define ET_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 88 89 static int et_probe(device_t); 90 static int et_attach(device_t); 91 static int et_detach(device_t); 92 static int et_shutdown(device_t); 93 static int et_suspend(device_t); 94 static int et_resume(device_t); 95 96 static int et_miibus_readreg(device_t, int, int); 97 static int et_miibus_writereg(device_t, int, int, int); 98 static void et_miibus_statchg(device_t); 99 100 static void et_init_locked(struct et_softc *); 101 static void et_init(void *); 102 static int et_ioctl(struct ifnet *, u_long, caddr_t); 103 static void et_start_locked(struct ifnet *); 104 static void et_start(struct ifnet *); 105 static int et_watchdog(struct et_softc *); 106 static int et_ifmedia_upd_locked(struct ifnet *); 107 static int et_ifmedia_upd(struct ifnet *); 108 static void et_ifmedia_sts(struct ifnet *, struct ifmediareq *); 109 static uint64_t et_get_counter(struct ifnet *, ift_counter); 110 111 static void et_add_sysctls(struct et_softc *); 112 static int et_sysctl_rx_intr_npkts(SYSCTL_HANDLER_ARGS); 113 static int et_sysctl_rx_intr_delay(SYSCTL_HANDLER_ARGS); 114 115 static void et_intr(void *); 116 static void et_rxeof(struct et_softc *); 117 static void et_txeof(struct et_softc *); 118 119 static int et_dma_alloc(struct et_softc *); 120 static void et_dma_free(struct et_softc *); 121 static void et_dma_map_addr(void *, bus_dma_segment_t *, int, int); 122 static int et_dma_ring_alloc(struct et_softc *, bus_size_t, bus_size_t, 123 bus_dma_tag_t *, uint8_t **, bus_dmamap_t *, bus_addr_t *, 124 const char *); 125 static void et_dma_ring_free(struct et_softc *, bus_dma_tag_t *, uint8_t **, 126 bus_dmamap_t, bus_addr_t *); 127 static void et_init_tx_ring(struct et_softc *); 128 static int et_init_rx_ring(struct et_softc *); 129 static void et_free_tx_ring(struct et_softc *); 130 static void et_free_rx_ring(struct et_softc *); 131 static int et_encap(struct et_softc *, struct mbuf **); 132 static int et_newbuf_cluster(struct et_rxbuf_data *, int); 133 static int et_newbuf_hdr(struct et_rxbuf_data *, int); 134 static void et_rxbuf_discard(struct et_rxbuf_data *, int); 135 136 static void et_stop(struct et_softc *); 137 static int et_chip_init(struct et_softc *); 138 static void et_chip_attach(struct et_softc *); 139 static void et_init_mac(struct et_softc *); 140 static void et_init_rxmac(struct et_softc *); 141 static void et_init_txmac(struct et_softc *); 142 static int et_init_rxdma(struct et_softc *); 143 static int et_init_txdma(struct et_softc *); 144 static int et_start_rxdma(struct et_softc *); 145 static int et_start_txdma(struct et_softc *); 146 static int et_stop_rxdma(struct et_softc *); 147 static int et_stop_txdma(struct et_softc *); 148 static void et_reset(struct et_softc *); 149 static int et_bus_config(struct et_softc *); 150 static void et_get_eaddr(device_t, uint8_t[]); 151 static void et_setmulti(struct et_softc *); 152 static void et_tick(void *); 153 static void et_stats_update(struct et_softc *); 154 155 static const struct et_dev { 156 uint16_t vid; 157 uint16_t did; 158 const char *desc; 159 } et_devices[] = { 160 { PCI_VENDOR_LUCENT, PCI_PRODUCT_LUCENT_ET1310, 161 "Agere ET1310 Gigabit Ethernet" }, 162 { PCI_VENDOR_LUCENT, PCI_PRODUCT_LUCENT_ET1310_FAST, 163 "Agere ET1310 Fast Ethernet" }, 164 { 0, 0, NULL } 165 }; 166 167 static device_method_t et_methods[] = { 168 DEVMETHOD(device_probe, et_probe), 169 DEVMETHOD(device_attach, et_attach), 170 DEVMETHOD(device_detach, et_detach), 171 DEVMETHOD(device_shutdown, et_shutdown), 172 DEVMETHOD(device_suspend, et_suspend), 173 DEVMETHOD(device_resume, et_resume), 174 175 DEVMETHOD(miibus_readreg, et_miibus_readreg), 176 DEVMETHOD(miibus_writereg, et_miibus_writereg), 177 DEVMETHOD(miibus_statchg, et_miibus_statchg), 178 179 DEVMETHOD_END 180 }; 181 182 static driver_t et_driver = { 183 "et", 184 et_methods, 185 sizeof(struct et_softc) 186 }; 187 188 static devclass_t et_devclass; 189 190 DRIVER_MODULE(et, pci, et_driver, et_devclass, 0, 0); 191 MODULE_PNP_INFO("U16:vendor;U16:device;D:#", pci, et, et_devices, 192 nitems(et_devices) - 1); 193 DRIVER_MODULE(miibus, et, miibus_driver, miibus_devclass, 0, 0); 194 195 static int et_rx_intr_npkts = 32; 196 static int et_rx_intr_delay = 20; /* x10 usec */ 197 static int et_tx_intr_nsegs = 126; 198 static uint32_t et_timer = 1000 * 1000 * 1000; /* nanosec */ 199 200 TUNABLE_INT("hw.et.timer", &et_timer); 201 TUNABLE_INT("hw.et.rx_intr_npkts", &et_rx_intr_npkts); 202 TUNABLE_INT("hw.et.rx_intr_delay", &et_rx_intr_delay); 203 TUNABLE_INT("hw.et.tx_intr_nsegs", &et_tx_intr_nsegs); 204 205 static int 206 et_probe(device_t dev) 207 { 208 const struct et_dev *d; 209 uint16_t did, vid; 210 211 vid = pci_get_vendor(dev); 212 did = pci_get_device(dev); 213 214 for (d = et_devices; d->desc != NULL; ++d) { 215 if (vid == d->vid && did == d->did) { 216 device_set_desc(dev, d->desc); 217 return (BUS_PROBE_DEFAULT); 218 } 219 } 220 return (ENXIO); 221 } 222 223 static int 224 et_attach(device_t dev) 225 { 226 struct et_softc *sc; 227 struct ifnet *ifp; 228 uint8_t eaddr[ETHER_ADDR_LEN]; 229 uint32_t pmcfg; 230 int cap, error, msic; 231 232 sc = device_get_softc(dev); 233 sc->dev = dev; 234 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 235 MTX_DEF); 236 callout_init_mtx(&sc->sc_tick, &sc->sc_mtx, 0); 237 238 ifp = sc->ifp = if_alloc(IFT_ETHER); 239 if (ifp == NULL) { 240 device_printf(dev, "can not if_alloc()\n"); 241 error = ENOSPC; 242 goto fail; 243 } 244 245 /* 246 * Initialize tunables 247 */ 248 sc->sc_rx_intr_npkts = et_rx_intr_npkts; 249 sc->sc_rx_intr_delay = et_rx_intr_delay; 250 sc->sc_tx_intr_nsegs = et_tx_intr_nsegs; 251 sc->sc_timer = et_timer; 252 253 /* Enable bus mastering */ 254 pci_enable_busmaster(dev); 255 256 /* 257 * Allocate IO memory 258 */ 259 sc->sc_mem_rid = PCIR_BAR(0); 260 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 261 &sc->sc_mem_rid, RF_ACTIVE); 262 if (sc->sc_mem_res == NULL) { 263 device_printf(dev, "can't allocate IO memory\n"); 264 return (ENXIO); 265 } 266 267 msic = 0; 268 if (pci_find_cap(dev, PCIY_EXPRESS, &cap) == 0) { 269 sc->sc_expcap = cap; 270 sc->sc_flags |= ET_FLAG_PCIE; 271 msic = pci_msi_count(dev); 272 if (bootverbose) 273 device_printf(dev, "MSI count: %d\n", msic); 274 } 275 if (msic > 0 && msi_disable == 0) { 276 msic = 1; 277 if (pci_alloc_msi(dev, &msic) == 0) { 278 if (msic == 1) { 279 device_printf(dev, "Using %d MSI message\n", 280 msic); 281 sc->sc_flags |= ET_FLAG_MSI; 282 } else 283 pci_release_msi(dev); 284 } 285 } 286 287 /* 288 * Allocate IRQ 289 */ 290 if ((sc->sc_flags & ET_FLAG_MSI) == 0) { 291 sc->sc_irq_rid = 0; 292 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, 293 &sc->sc_irq_rid, RF_SHAREABLE | RF_ACTIVE); 294 } else { 295 sc->sc_irq_rid = 1; 296 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, 297 &sc->sc_irq_rid, RF_ACTIVE); 298 } 299 if (sc->sc_irq_res == NULL) { 300 device_printf(dev, "can't allocate irq\n"); 301 error = ENXIO; 302 goto fail; 303 } 304 305 if (pci_get_device(dev) == PCI_PRODUCT_LUCENT_ET1310_FAST) 306 sc->sc_flags |= ET_FLAG_FASTETHER; 307 308 error = et_bus_config(sc); 309 if (error) 310 goto fail; 311 312 et_get_eaddr(dev, eaddr); 313 314 /* Take PHY out of COMA and enable clocks. */ 315 pmcfg = ET_PM_SYSCLK_GATE | ET_PM_TXCLK_GATE | ET_PM_RXCLK_GATE; 316 if ((sc->sc_flags & ET_FLAG_FASTETHER) == 0) 317 pmcfg |= EM_PM_GIGEPHY_ENB; 318 CSR_WRITE_4(sc, ET_PM, pmcfg); 319 320 et_reset(sc); 321 322 error = et_dma_alloc(sc); 323 if (error) 324 goto fail; 325 326 ifp->if_softc = sc; 327 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 328 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 329 ifp->if_init = et_init; 330 ifp->if_ioctl = et_ioctl; 331 ifp->if_start = et_start; 332 ifp->if_get_counter = et_get_counter; 333 ifp->if_capabilities = IFCAP_TXCSUM | IFCAP_VLAN_MTU; 334 ifp->if_capenable = ifp->if_capabilities; 335 ifp->if_snd.ifq_drv_maxlen = ET_TX_NDESC - 1; 336 IFQ_SET_MAXLEN(&ifp->if_snd, ET_TX_NDESC - 1); 337 IFQ_SET_READY(&ifp->if_snd); 338 339 et_chip_attach(sc); 340 341 error = mii_attach(dev, &sc->sc_miibus, ifp, et_ifmedia_upd, 342 et_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 343 MIIF_DOPAUSE); 344 if (error) { 345 device_printf(dev, "attaching PHYs failed\n"); 346 goto fail; 347 } 348 349 ether_ifattach(ifp, eaddr); 350 351 /* Tell the upper layer(s) we support long frames. */ 352 ifp->if_hdrlen = sizeof(struct ether_vlan_header); 353 354 error = bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_NET | INTR_MPSAFE, 355 NULL, et_intr, sc, &sc->sc_irq_handle); 356 if (error) { 357 ether_ifdetach(ifp); 358 device_printf(dev, "can't setup intr\n"); 359 goto fail; 360 } 361 362 et_add_sysctls(sc); 363 364 return (0); 365 fail: 366 et_detach(dev); 367 return (error); 368 } 369 370 static int 371 et_detach(device_t dev) 372 { 373 struct et_softc *sc; 374 375 sc = device_get_softc(dev); 376 if (device_is_attached(dev)) { 377 ether_ifdetach(sc->ifp); 378 ET_LOCK(sc); 379 et_stop(sc); 380 ET_UNLOCK(sc); 381 callout_drain(&sc->sc_tick); 382 } 383 384 if (sc->sc_miibus != NULL) 385 device_delete_child(dev, sc->sc_miibus); 386 bus_generic_detach(dev); 387 388 if (sc->sc_irq_handle != NULL) 389 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_irq_handle); 390 if (sc->sc_irq_res != NULL) 391 bus_release_resource(dev, SYS_RES_IRQ, 392 rman_get_rid(sc->sc_irq_res), sc->sc_irq_res); 393 if ((sc->sc_flags & ET_FLAG_MSI) != 0) 394 pci_release_msi(dev); 395 if (sc->sc_mem_res != NULL) 396 bus_release_resource(dev, SYS_RES_MEMORY, 397 rman_get_rid(sc->sc_mem_res), sc->sc_mem_res); 398 399 if (sc->ifp != NULL) 400 if_free(sc->ifp); 401 402 et_dma_free(sc); 403 404 mtx_destroy(&sc->sc_mtx); 405 406 return (0); 407 } 408 409 static int 410 et_shutdown(device_t dev) 411 { 412 struct et_softc *sc; 413 414 sc = device_get_softc(dev); 415 ET_LOCK(sc); 416 et_stop(sc); 417 ET_UNLOCK(sc); 418 return (0); 419 } 420 421 static int 422 et_miibus_readreg(device_t dev, int phy, int reg) 423 { 424 struct et_softc *sc; 425 uint32_t val; 426 int i, ret; 427 428 sc = device_get_softc(dev); 429 /* Stop any pending operations */ 430 CSR_WRITE_4(sc, ET_MII_CMD, 0); 431 432 val = (phy << ET_MII_ADDR_PHY_SHIFT) & ET_MII_ADDR_PHY_MASK; 433 val |= (reg << ET_MII_ADDR_REG_SHIFT) & ET_MII_ADDR_REG_MASK; 434 CSR_WRITE_4(sc, ET_MII_ADDR, val); 435 436 /* Start reading */ 437 CSR_WRITE_4(sc, ET_MII_CMD, ET_MII_CMD_READ); 438 439 #define NRETRY 50 440 441 for (i = 0; i < NRETRY; ++i) { 442 val = CSR_READ_4(sc, ET_MII_IND); 443 if ((val & (ET_MII_IND_BUSY | ET_MII_IND_INVALID)) == 0) 444 break; 445 DELAY(50); 446 } 447 if (i == NRETRY) { 448 if_printf(sc->ifp, 449 "read phy %d, reg %d timed out\n", phy, reg); 450 ret = 0; 451 goto back; 452 } 453 454 #undef NRETRY 455 456 val = CSR_READ_4(sc, ET_MII_STAT); 457 ret = val & ET_MII_STAT_VALUE_MASK; 458 459 back: 460 /* Make sure that the current operation is stopped */ 461 CSR_WRITE_4(sc, ET_MII_CMD, 0); 462 return (ret); 463 } 464 465 static int 466 et_miibus_writereg(device_t dev, int phy, int reg, int val0) 467 { 468 struct et_softc *sc; 469 uint32_t val; 470 int i; 471 472 sc = device_get_softc(dev); 473 /* Stop any pending operations */ 474 CSR_WRITE_4(sc, ET_MII_CMD, 0); 475 476 val = (phy << ET_MII_ADDR_PHY_SHIFT) & ET_MII_ADDR_PHY_MASK; 477 val |= (reg << ET_MII_ADDR_REG_SHIFT) & ET_MII_ADDR_REG_MASK; 478 CSR_WRITE_4(sc, ET_MII_ADDR, val); 479 480 /* Start writing */ 481 CSR_WRITE_4(sc, ET_MII_CTRL, 482 (val0 << ET_MII_CTRL_VALUE_SHIFT) & ET_MII_CTRL_VALUE_MASK); 483 484 #define NRETRY 100 485 486 for (i = 0; i < NRETRY; ++i) { 487 val = CSR_READ_4(sc, ET_MII_IND); 488 if ((val & ET_MII_IND_BUSY) == 0) 489 break; 490 DELAY(50); 491 } 492 if (i == NRETRY) { 493 if_printf(sc->ifp, 494 "write phy %d, reg %d timed out\n", phy, reg); 495 et_miibus_readreg(dev, phy, reg); 496 } 497 498 #undef NRETRY 499 500 /* Make sure that the current operation is stopped */ 501 CSR_WRITE_4(sc, ET_MII_CMD, 0); 502 return (0); 503 } 504 505 static void 506 et_miibus_statchg(device_t dev) 507 { 508 struct et_softc *sc; 509 struct mii_data *mii; 510 struct ifnet *ifp; 511 uint32_t cfg1, cfg2, ctrl; 512 int i; 513 514 sc = device_get_softc(dev); 515 516 mii = device_get_softc(sc->sc_miibus); 517 ifp = sc->ifp; 518 if (mii == NULL || ifp == NULL || 519 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 520 return; 521 522 sc->sc_flags &= ~ET_FLAG_LINK; 523 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 524 (IFM_ACTIVE | IFM_AVALID)) { 525 switch (IFM_SUBTYPE(mii->mii_media_active)) { 526 case IFM_10_T: 527 case IFM_100_TX: 528 sc->sc_flags |= ET_FLAG_LINK; 529 break; 530 case IFM_1000_T: 531 if ((sc->sc_flags & ET_FLAG_FASTETHER) == 0) 532 sc->sc_flags |= ET_FLAG_LINK; 533 break; 534 } 535 } 536 537 /* XXX Stop TX/RX MAC? */ 538 if ((sc->sc_flags & ET_FLAG_LINK) == 0) 539 return; 540 541 /* Program MACs with resolved speed/duplex/flow-control. */ 542 ctrl = CSR_READ_4(sc, ET_MAC_CTRL); 543 ctrl &= ~(ET_MAC_CTRL_GHDX | ET_MAC_CTRL_MODE_MII); 544 cfg1 = CSR_READ_4(sc, ET_MAC_CFG1); 545 cfg1 &= ~(ET_MAC_CFG1_TXFLOW | ET_MAC_CFG1_RXFLOW | 546 ET_MAC_CFG1_LOOPBACK); 547 cfg2 = CSR_READ_4(sc, ET_MAC_CFG2); 548 cfg2 &= ~(ET_MAC_CFG2_MODE_MII | ET_MAC_CFG2_MODE_GMII | 549 ET_MAC_CFG2_FDX | ET_MAC_CFG2_BIGFRM); 550 cfg2 |= ET_MAC_CFG2_LENCHK | ET_MAC_CFG2_CRC | ET_MAC_CFG2_PADCRC | 551 ((7 << ET_MAC_CFG2_PREAMBLE_LEN_SHIFT) & 552 ET_MAC_CFG2_PREAMBLE_LEN_MASK); 553 554 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) 555 cfg2 |= ET_MAC_CFG2_MODE_GMII; 556 else { 557 cfg2 |= ET_MAC_CFG2_MODE_MII; 558 ctrl |= ET_MAC_CTRL_MODE_MII; 559 } 560 561 if (IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) { 562 cfg2 |= ET_MAC_CFG2_FDX; 563 /* 564 * Controller lacks automatic TX pause frame 565 * generation so it should be handled by driver. 566 * Even though driver can send pause frame with 567 * arbitrary pause time, controller does not 568 * provide a way that tells how many free RX 569 * buffers are available in controller. This 570 * limitation makes it hard to generate XON frame 571 * in time on driver side so don't enable TX flow 572 * control. 573 */ 574 #ifdef notyet 575 if (IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) 576 cfg1 |= ET_MAC_CFG1_TXFLOW; 577 #endif 578 if (IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) 579 cfg1 |= ET_MAC_CFG1_RXFLOW; 580 } else 581 ctrl |= ET_MAC_CTRL_GHDX; 582 583 CSR_WRITE_4(sc, ET_MAC_CTRL, ctrl); 584 CSR_WRITE_4(sc, ET_MAC_CFG2, cfg2); 585 cfg1 |= ET_MAC_CFG1_TXEN | ET_MAC_CFG1_RXEN; 586 CSR_WRITE_4(sc, ET_MAC_CFG1, cfg1); 587 588 #define NRETRY 50 589 590 for (i = 0; i < NRETRY; ++i) { 591 cfg1 = CSR_READ_4(sc, ET_MAC_CFG1); 592 if ((cfg1 & (ET_MAC_CFG1_SYNC_TXEN | ET_MAC_CFG1_SYNC_RXEN)) == 593 (ET_MAC_CFG1_SYNC_TXEN | ET_MAC_CFG1_SYNC_RXEN)) 594 break; 595 DELAY(100); 596 } 597 if (i == NRETRY) 598 if_printf(ifp, "can't enable RX/TX\n"); 599 sc->sc_flags |= ET_FLAG_TXRX_ENABLED; 600 601 #undef NRETRY 602 } 603 604 static int 605 et_ifmedia_upd_locked(struct ifnet *ifp) 606 { 607 struct et_softc *sc; 608 struct mii_data *mii; 609 struct mii_softc *miisc; 610 611 sc = ifp->if_softc; 612 mii = device_get_softc(sc->sc_miibus); 613 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 614 PHY_RESET(miisc); 615 return (mii_mediachg(mii)); 616 } 617 618 static int 619 et_ifmedia_upd(struct ifnet *ifp) 620 { 621 struct et_softc *sc; 622 int res; 623 624 sc = ifp->if_softc; 625 ET_LOCK(sc); 626 res = et_ifmedia_upd_locked(ifp); 627 ET_UNLOCK(sc); 628 629 return (res); 630 } 631 632 static void 633 et_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 634 { 635 struct et_softc *sc; 636 struct mii_data *mii; 637 638 sc = ifp->if_softc; 639 ET_LOCK(sc); 640 if ((ifp->if_flags & IFF_UP) == 0) { 641 ET_UNLOCK(sc); 642 return; 643 } 644 645 mii = device_get_softc(sc->sc_miibus); 646 mii_pollstat(mii); 647 ifmr->ifm_active = mii->mii_media_active; 648 ifmr->ifm_status = mii->mii_media_status; 649 ET_UNLOCK(sc); 650 } 651 652 static void 653 et_stop(struct et_softc *sc) 654 { 655 struct ifnet *ifp; 656 657 ET_LOCK_ASSERT(sc); 658 659 ifp = sc->ifp; 660 callout_stop(&sc->sc_tick); 661 /* Disable interrupts. */ 662 CSR_WRITE_4(sc, ET_INTR_MASK, 0xffffffff); 663 664 CSR_WRITE_4(sc, ET_MAC_CFG1, CSR_READ_4(sc, ET_MAC_CFG1) & ~( 665 ET_MAC_CFG1_TXEN | ET_MAC_CFG1_RXEN)); 666 DELAY(100); 667 668 et_stop_rxdma(sc); 669 et_stop_txdma(sc); 670 et_stats_update(sc); 671 672 et_free_tx_ring(sc); 673 et_free_rx_ring(sc); 674 675 sc->sc_tx = 0; 676 sc->sc_tx_intr = 0; 677 sc->sc_flags &= ~ET_FLAG_TXRX_ENABLED; 678 679 sc->watchdog_timer = 0; 680 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 681 } 682 683 static int 684 et_bus_config(struct et_softc *sc) 685 { 686 uint32_t val, max_plsz; 687 uint16_t ack_latency, replay_timer; 688 689 /* 690 * Test whether EEPROM is valid 691 * NOTE: Read twice to get the correct value 692 */ 693 pci_read_config(sc->dev, ET_PCIR_EEPROM_STATUS, 1); 694 val = pci_read_config(sc->dev, ET_PCIR_EEPROM_STATUS, 1); 695 if (val & ET_PCIM_EEPROM_STATUS_ERROR) { 696 device_printf(sc->dev, "EEPROM status error 0x%02x\n", val); 697 return (ENXIO); 698 } 699 700 /* TODO: LED */ 701 702 if ((sc->sc_flags & ET_FLAG_PCIE) == 0) 703 return (0); 704 705 /* 706 * Configure ACK latency and replay timer according to 707 * max playload size 708 */ 709 val = pci_read_config(sc->dev, 710 sc->sc_expcap + PCIER_DEVICE_CAP, 4); 711 max_plsz = val & PCIEM_CAP_MAX_PAYLOAD; 712 713 switch (max_plsz) { 714 case ET_PCIV_DEVICE_CAPS_PLSZ_128: 715 ack_latency = ET_PCIV_ACK_LATENCY_128; 716 replay_timer = ET_PCIV_REPLAY_TIMER_128; 717 break; 718 719 case ET_PCIV_DEVICE_CAPS_PLSZ_256: 720 ack_latency = ET_PCIV_ACK_LATENCY_256; 721 replay_timer = ET_PCIV_REPLAY_TIMER_256; 722 break; 723 724 default: 725 ack_latency = pci_read_config(sc->dev, ET_PCIR_ACK_LATENCY, 2); 726 replay_timer = pci_read_config(sc->dev, 727 ET_PCIR_REPLAY_TIMER, 2); 728 device_printf(sc->dev, "ack latency %u, replay timer %u\n", 729 ack_latency, replay_timer); 730 break; 731 } 732 if (ack_latency != 0) { 733 pci_write_config(sc->dev, ET_PCIR_ACK_LATENCY, ack_latency, 2); 734 pci_write_config(sc->dev, ET_PCIR_REPLAY_TIMER, replay_timer, 735 2); 736 } 737 738 /* 739 * Set L0s and L1 latency timer to 2us 740 */ 741 val = pci_read_config(sc->dev, ET_PCIR_L0S_L1_LATENCY, 4); 742 val &= ~(PCIEM_LINK_CAP_L0S_EXIT | PCIEM_LINK_CAP_L1_EXIT); 743 /* L0s exit latency : 2us */ 744 val |= 0x00005000; 745 /* L1 exit latency : 2us */ 746 val |= 0x00028000; 747 pci_write_config(sc->dev, ET_PCIR_L0S_L1_LATENCY, val, 4); 748 749 /* 750 * Set max read request size to 2048 bytes 751 */ 752 pci_set_max_read_req(sc->dev, 2048); 753 754 return (0); 755 } 756 757 static void 758 et_get_eaddr(device_t dev, uint8_t eaddr[]) 759 { 760 uint32_t val; 761 int i; 762 763 val = pci_read_config(dev, ET_PCIR_MAC_ADDR0, 4); 764 for (i = 0; i < 4; ++i) 765 eaddr[i] = (val >> (8 * i)) & 0xff; 766 767 val = pci_read_config(dev, ET_PCIR_MAC_ADDR1, 2); 768 for (; i < ETHER_ADDR_LEN; ++i) 769 eaddr[i] = (val >> (8 * (i - 4))) & 0xff; 770 } 771 772 static void 773 et_reset(struct et_softc *sc) 774 { 775 776 CSR_WRITE_4(sc, ET_MAC_CFG1, 777 ET_MAC_CFG1_RST_TXFUNC | ET_MAC_CFG1_RST_RXFUNC | 778 ET_MAC_CFG1_RST_TXMC | ET_MAC_CFG1_RST_RXMC | 779 ET_MAC_CFG1_SIM_RST | ET_MAC_CFG1_SOFT_RST); 780 781 CSR_WRITE_4(sc, ET_SWRST, 782 ET_SWRST_TXDMA | ET_SWRST_RXDMA | 783 ET_SWRST_TXMAC | ET_SWRST_RXMAC | 784 ET_SWRST_MAC | ET_SWRST_MAC_STAT | ET_SWRST_MMC); 785 786 CSR_WRITE_4(sc, ET_MAC_CFG1, 787 ET_MAC_CFG1_RST_TXFUNC | ET_MAC_CFG1_RST_RXFUNC | 788 ET_MAC_CFG1_RST_TXMC | ET_MAC_CFG1_RST_RXMC); 789 CSR_WRITE_4(sc, ET_MAC_CFG1, 0); 790 /* Disable interrupts. */ 791 CSR_WRITE_4(sc, ET_INTR_MASK, 0xffffffff); 792 } 793 794 struct et_dmamap_arg { 795 bus_addr_t et_busaddr; 796 }; 797 798 static void 799 et_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 800 { 801 struct et_dmamap_arg *ctx; 802 803 if (error) 804 return; 805 806 KASSERT(nseg == 1, ("%s: %d segments returned!", __func__, nseg)); 807 808 ctx = arg; 809 ctx->et_busaddr = segs->ds_addr; 810 } 811 812 static int 813 et_dma_ring_alloc(struct et_softc *sc, bus_size_t alignment, bus_size_t maxsize, 814 bus_dma_tag_t *tag, uint8_t **ring, bus_dmamap_t *map, bus_addr_t *paddr, 815 const char *msg) 816 { 817 struct et_dmamap_arg ctx; 818 int error; 819 820 error = bus_dma_tag_create(sc->sc_dtag, alignment, 0, BUS_SPACE_MAXADDR, 821 BUS_SPACE_MAXADDR, NULL, NULL, maxsize, 1, maxsize, 0, NULL, NULL, 822 tag); 823 if (error != 0) { 824 device_printf(sc->dev, "could not create %s dma tag\n", msg); 825 return (error); 826 } 827 /* Allocate DMA'able memory for ring. */ 828 error = bus_dmamem_alloc(*tag, (void **)ring, 829 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, map); 830 if (error != 0) { 831 device_printf(sc->dev, 832 "could not allocate DMA'able memory for %s\n", msg); 833 return (error); 834 } 835 /* Load the address of the ring. */ 836 ctx.et_busaddr = 0; 837 error = bus_dmamap_load(*tag, *map, *ring, maxsize, et_dma_map_addr, 838 &ctx, BUS_DMA_NOWAIT); 839 if (error != 0) { 840 device_printf(sc->dev, 841 "could not load DMA'able memory for %s\n", msg); 842 return (error); 843 } 844 *paddr = ctx.et_busaddr; 845 return (0); 846 } 847 848 static void 849 et_dma_ring_free(struct et_softc *sc, bus_dma_tag_t *tag, uint8_t **ring, 850 bus_dmamap_t map, bus_addr_t *paddr) 851 { 852 853 if (*paddr != 0) { 854 bus_dmamap_unload(*tag, map); 855 *paddr = 0; 856 } 857 if (*ring != NULL) { 858 bus_dmamem_free(*tag, *ring, map); 859 *ring = NULL; 860 } 861 if (*tag) { 862 bus_dma_tag_destroy(*tag); 863 *tag = NULL; 864 } 865 } 866 867 static int 868 et_dma_alloc(struct et_softc *sc) 869 { 870 struct et_txdesc_ring *tx_ring; 871 struct et_rxdesc_ring *rx_ring; 872 struct et_rxstat_ring *rxst_ring; 873 struct et_rxstatus_data *rxsd; 874 struct et_rxbuf_data *rbd; 875 struct et_txbuf_data *tbd; 876 struct et_txstatus_data *txsd; 877 int i, error; 878 879 error = bus_dma_tag_create(bus_get_dma_tag(sc->dev), 1, 0, 880 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 881 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL, 882 &sc->sc_dtag); 883 if (error != 0) { 884 device_printf(sc->dev, "could not allocate parent dma tag\n"); 885 return (error); 886 } 887 888 /* TX ring. */ 889 tx_ring = &sc->sc_tx_ring; 890 error = et_dma_ring_alloc(sc, ET_RING_ALIGN, ET_TX_RING_SIZE, 891 &tx_ring->tr_dtag, (uint8_t **)&tx_ring->tr_desc, &tx_ring->tr_dmap, 892 &tx_ring->tr_paddr, "TX ring"); 893 if (error) 894 return (error); 895 896 /* TX status block. */ 897 txsd = &sc->sc_tx_status; 898 error = et_dma_ring_alloc(sc, ET_STATUS_ALIGN, sizeof(uint32_t), 899 &txsd->txsd_dtag, (uint8_t **)&txsd->txsd_status, &txsd->txsd_dmap, 900 &txsd->txsd_paddr, "TX status block"); 901 if (error) 902 return (error); 903 904 /* RX ring 0, used as to recive small sized frames. */ 905 rx_ring = &sc->sc_rx_ring[0]; 906 error = et_dma_ring_alloc(sc, ET_RING_ALIGN, ET_RX_RING_SIZE, 907 &rx_ring->rr_dtag, (uint8_t **)&rx_ring->rr_desc, &rx_ring->rr_dmap, 908 &rx_ring->rr_paddr, "RX ring 0"); 909 rx_ring->rr_posreg = ET_RX_RING0_POS; 910 if (error) 911 return (error); 912 913 /* RX ring 1, used as to store normal sized frames. */ 914 rx_ring = &sc->sc_rx_ring[1]; 915 error = et_dma_ring_alloc(sc, ET_RING_ALIGN, ET_RX_RING_SIZE, 916 &rx_ring->rr_dtag, (uint8_t **)&rx_ring->rr_desc, &rx_ring->rr_dmap, 917 &rx_ring->rr_paddr, "RX ring 1"); 918 rx_ring->rr_posreg = ET_RX_RING1_POS; 919 if (error) 920 return (error); 921 922 /* RX stat ring. */ 923 rxst_ring = &sc->sc_rxstat_ring; 924 error = et_dma_ring_alloc(sc, ET_RING_ALIGN, ET_RXSTAT_RING_SIZE, 925 &rxst_ring->rsr_dtag, (uint8_t **)&rxst_ring->rsr_stat, 926 &rxst_ring->rsr_dmap, &rxst_ring->rsr_paddr, "RX stat ring"); 927 if (error) 928 return (error); 929 930 /* RX status block. */ 931 rxsd = &sc->sc_rx_status; 932 error = et_dma_ring_alloc(sc, ET_STATUS_ALIGN, 933 sizeof(struct et_rxstatus), &rxsd->rxsd_dtag, 934 (uint8_t **)&rxsd->rxsd_status, &rxsd->rxsd_dmap, 935 &rxsd->rxsd_paddr, "RX status block"); 936 if (error) 937 return (error); 938 939 /* Create parent DMA tag for mbufs. */ 940 error = bus_dma_tag_create(bus_get_dma_tag(sc->dev), 1, 0, 941 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 942 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL, 943 &sc->sc_mbuf_dtag); 944 if (error != 0) { 945 device_printf(sc->dev, 946 "could not allocate parent dma tag for mbuf\n"); 947 return (error); 948 } 949 950 /* Create DMA tag for mini RX mbufs to use RX ring 0. */ 951 error = bus_dma_tag_create(sc->sc_mbuf_dtag, 1, 0, 952 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MHLEN, 1, 953 MHLEN, 0, NULL, NULL, &sc->sc_rx_mini_tag); 954 if (error) { 955 device_printf(sc->dev, "could not create mini RX dma tag\n"); 956 return (error); 957 } 958 959 /* Create DMA tag for standard RX mbufs to use RX ring 1. */ 960 error = bus_dma_tag_create(sc->sc_mbuf_dtag, 1, 0, 961 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1, 962 MCLBYTES, 0, NULL, NULL, &sc->sc_rx_tag); 963 if (error) { 964 device_printf(sc->dev, "could not create RX dma tag\n"); 965 return (error); 966 } 967 968 /* Create DMA tag for TX mbufs. */ 969 error = bus_dma_tag_create(sc->sc_mbuf_dtag, 1, 0, 970 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 971 MCLBYTES * ET_NSEG_MAX, ET_NSEG_MAX, MCLBYTES, 0, NULL, NULL, 972 &sc->sc_tx_tag); 973 if (error) { 974 device_printf(sc->dev, "could not create TX dma tag\n"); 975 return (error); 976 } 977 978 /* Initialize RX ring 0. */ 979 rbd = &sc->sc_rx_data[0]; 980 rbd->rbd_bufsize = ET_RXDMA_CTRL_RING0_128; 981 rbd->rbd_newbuf = et_newbuf_hdr; 982 rbd->rbd_discard = et_rxbuf_discard; 983 rbd->rbd_softc = sc; 984 rbd->rbd_ring = &sc->sc_rx_ring[0]; 985 /* Create DMA maps for mini RX buffers, ring 0. */ 986 for (i = 0; i < ET_RX_NDESC; i++) { 987 error = bus_dmamap_create(sc->sc_rx_mini_tag, 0, 988 &rbd->rbd_buf[i].rb_dmap); 989 if (error) { 990 device_printf(sc->dev, 991 "could not create DMA map for mini RX mbufs\n"); 992 return (error); 993 } 994 } 995 996 /* Create a spare DMA map for mini RX buffers, ring 0. */ 997 error = bus_dmamap_create(sc->sc_rx_mini_tag, 0, 998 &sc->sc_rx_mini_sparemap); 999 if (error) { 1000 device_printf(sc->dev, 1001 "could not create spare DMA map for mini RX mbuf\n"); 1002 return (error); 1003 } 1004 1005 /* Initialize RX ring 1. */ 1006 rbd = &sc->sc_rx_data[1]; 1007 rbd->rbd_bufsize = ET_RXDMA_CTRL_RING1_2048; 1008 rbd->rbd_newbuf = et_newbuf_cluster; 1009 rbd->rbd_discard = et_rxbuf_discard; 1010 rbd->rbd_softc = sc; 1011 rbd->rbd_ring = &sc->sc_rx_ring[1]; 1012 /* Create DMA maps for standard RX buffers, ring 1. */ 1013 for (i = 0; i < ET_RX_NDESC; i++) { 1014 error = bus_dmamap_create(sc->sc_rx_tag, 0, 1015 &rbd->rbd_buf[i].rb_dmap); 1016 if (error) { 1017 device_printf(sc->dev, 1018 "could not create DMA map for mini RX mbufs\n"); 1019 return (error); 1020 } 1021 } 1022 1023 /* Create a spare DMA map for standard RX buffers, ring 1. */ 1024 error = bus_dmamap_create(sc->sc_rx_tag, 0, &sc->sc_rx_sparemap); 1025 if (error) { 1026 device_printf(sc->dev, 1027 "could not create spare DMA map for RX mbuf\n"); 1028 return (error); 1029 } 1030 1031 /* Create DMA maps for TX buffers. */ 1032 tbd = &sc->sc_tx_data; 1033 for (i = 0; i < ET_TX_NDESC; i++) { 1034 error = bus_dmamap_create(sc->sc_tx_tag, 0, 1035 &tbd->tbd_buf[i].tb_dmap); 1036 if (error) { 1037 device_printf(sc->dev, 1038 "could not create DMA map for TX mbufs\n"); 1039 return (error); 1040 } 1041 } 1042 1043 return (0); 1044 } 1045 1046 static void 1047 et_dma_free(struct et_softc *sc) 1048 { 1049 struct et_txdesc_ring *tx_ring; 1050 struct et_rxdesc_ring *rx_ring; 1051 struct et_txstatus_data *txsd; 1052 struct et_rxstat_ring *rxst_ring; 1053 struct et_rxstatus_data *rxsd; 1054 struct et_rxbuf_data *rbd; 1055 struct et_txbuf_data *tbd; 1056 int i; 1057 1058 /* Destroy DMA maps for mini RX buffers, ring 0. */ 1059 rbd = &sc->sc_rx_data[0]; 1060 for (i = 0; i < ET_RX_NDESC; i++) { 1061 if (rbd->rbd_buf[i].rb_dmap) { 1062 bus_dmamap_destroy(sc->sc_rx_mini_tag, 1063 rbd->rbd_buf[i].rb_dmap); 1064 rbd->rbd_buf[i].rb_dmap = NULL; 1065 } 1066 } 1067 if (sc->sc_rx_mini_sparemap) { 1068 bus_dmamap_destroy(sc->sc_rx_mini_tag, sc->sc_rx_mini_sparemap); 1069 sc->sc_rx_mini_sparemap = NULL; 1070 } 1071 if (sc->sc_rx_mini_tag) { 1072 bus_dma_tag_destroy(sc->sc_rx_mini_tag); 1073 sc->sc_rx_mini_tag = NULL; 1074 } 1075 1076 /* Destroy DMA maps for standard RX buffers, ring 1. */ 1077 rbd = &sc->sc_rx_data[1]; 1078 for (i = 0; i < ET_RX_NDESC; i++) { 1079 if (rbd->rbd_buf[i].rb_dmap) { 1080 bus_dmamap_destroy(sc->sc_rx_tag, 1081 rbd->rbd_buf[i].rb_dmap); 1082 rbd->rbd_buf[i].rb_dmap = NULL; 1083 } 1084 } 1085 if (sc->sc_rx_sparemap) { 1086 bus_dmamap_destroy(sc->sc_rx_tag, sc->sc_rx_sparemap); 1087 sc->sc_rx_sparemap = NULL; 1088 } 1089 if (sc->sc_rx_tag) { 1090 bus_dma_tag_destroy(sc->sc_rx_tag); 1091 sc->sc_rx_tag = NULL; 1092 } 1093 1094 /* Destroy DMA maps for TX buffers. */ 1095 tbd = &sc->sc_tx_data; 1096 for (i = 0; i < ET_TX_NDESC; i++) { 1097 if (tbd->tbd_buf[i].tb_dmap) { 1098 bus_dmamap_destroy(sc->sc_tx_tag, 1099 tbd->tbd_buf[i].tb_dmap); 1100 tbd->tbd_buf[i].tb_dmap = NULL; 1101 } 1102 } 1103 if (sc->sc_tx_tag) { 1104 bus_dma_tag_destroy(sc->sc_tx_tag); 1105 sc->sc_tx_tag = NULL; 1106 } 1107 1108 /* Destroy mini RX ring, ring 0. */ 1109 rx_ring = &sc->sc_rx_ring[0]; 1110 et_dma_ring_free(sc, &rx_ring->rr_dtag, (void *)&rx_ring->rr_desc, 1111 rx_ring->rr_dmap, &rx_ring->rr_paddr); 1112 /* Destroy standard RX ring, ring 1. */ 1113 rx_ring = &sc->sc_rx_ring[1]; 1114 et_dma_ring_free(sc, &rx_ring->rr_dtag, (void *)&rx_ring->rr_desc, 1115 rx_ring->rr_dmap, &rx_ring->rr_paddr); 1116 /* Destroy RX stat ring. */ 1117 rxst_ring = &sc->sc_rxstat_ring; 1118 et_dma_ring_free(sc, &rxst_ring->rsr_dtag, (void *)&rxst_ring->rsr_stat, 1119 rxst_ring->rsr_dmap, &rxst_ring->rsr_paddr); 1120 /* Destroy RX status block. */ 1121 rxsd = &sc->sc_rx_status; 1122 et_dma_ring_free(sc, &rxst_ring->rsr_dtag, (void *)&rxst_ring->rsr_stat, 1123 rxst_ring->rsr_dmap, &rxst_ring->rsr_paddr); 1124 /* Destroy TX ring. */ 1125 tx_ring = &sc->sc_tx_ring; 1126 et_dma_ring_free(sc, &tx_ring->tr_dtag, (void *)&tx_ring->tr_desc, 1127 tx_ring->tr_dmap, &tx_ring->tr_paddr); 1128 /* Destroy TX status block. */ 1129 txsd = &sc->sc_tx_status; 1130 et_dma_ring_free(sc, &txsd->txsd_dtag, (void *)&txsd->txsd_status, 1131 txsd->txsd_dmap, &txsd->txsd_paddr); 1132 1133 /* Destroy the parent tag. */ 1134 if (sc->sc_dtag) { 1135 bus_dma_tag_destroy(sc->sc_dtag); 1136 sc->sc_dtag = NULL; 1137 } 1138 } 1139 1140 static void 1141 et_chip_attach(struct et_softc *sc) 1142 { 1143 uint32_t val; 1144 1145 /* 1146 * Perform minimal initialization 1147 */ 1148 1149 /* Disable loopback */ 1150 CSR_WRITE_4(sc, ET_LOOPBACK, 0); 1151 1152 /* Reset MAC */ 1153 CSR_WRITE_4(sc, ET_MAC_CFG1, 1154 ET_MAC_CFG1_RST_TXFUNC | ET_MAC_CFG1_RST_RXFUNC | 1155 ET_MAC_CFG1_RST_TXMC | ET_MAC_CFG1_RST_RXMC | 1156 ET_MAC_CFG1_SIM_RST | ET_MAC_CFG1_SOFT_RST); 1157 1158 /* 1159 * Setup half duplex mode 1160 */ 1161 val = (10 << ET_MAC_HDX_ALT_BEB_TRUNC_SHIFT) | 1162 (15 << ET_MAC_HDX_REXMIT_MAX_SHIFT) | 1163 (55 << ET_MAC_HDX_COLLWIN_SHIFT) | 1164 ET_MAC_HDX_EXC_DEFER; 1165 CSR_WRITE_4(sc, ET_MAC_HDX, val); 1166 1167 /* Clear MAC control */ 1168 CSR_WRITE_4(sc, ET_MAC_CTRL, 0); 1169 1170 /* Reset MII */ 1171 CSR_WRITE_4(sc, ET_MII_CFG, ET_MII_CFG_CLKRST); 1172 1173 /* Bring MAC out of reset state */ 1174 CSR_WRITE_4(sc, ET_MAC_CFG1, 0); 1175 1176 /* Enable memory controllers */ 1177 CSR_WRITE_4(sc, ET_MMC_CTRL, ET_MMC_CTRL_ENABLE); 1178 } 1179 1180 static void 1181 et_intr(void *xsc) 1182 { 1183 struct et_softc *sc; 1184 struct ifnet *ifp; 1185 uint32_t status; 1186 1187 sc = xsc; 1188 ET_LOCK(sc); 1189 ifp = sc->ifp; 1190 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 1191 goto done; 1192 1193 status = CSR_READ_4(sc, ET_INTR_STATUS); 1194 if ((status & ET_INTRS) == 0) 1195 goto done; 1196 1197 /* Disable further interrupts. */ 1198 CSR_WRITE_4(sc, ET_INTR_MASK, 0xffffffff); 1199 1200 if (status & (ET_INTR_RXDMA_ERROR | ET_INTR_TXDMA_ERROR)) { 1201 device_printf(sc->dev, "DMA error(0x%08x) -- resetting\n", 1202 status); 1203 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1204 et_init_locked(sc); 1205 ET_UNLOCK(sc); 1206 return; 1207 } 1208 if (status & ET_INTR_RXDMA) 1209 et_rxeof(sc); 1210 if (status & (ET_INTR_TXDMA | ET_INTR_TIMER)) 1211 et_txeof(sc); 1212 if (status & ET_INTR_TIMER) 1213 CSR_WRITE_4(sc, ET_TIMER, sc->sc_timer); 1214 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1215 CSR_WRITE_4(sc, ET_INTR_MASK, ~ET_INTRS); 1216 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1217 et_start_locked(ifp); 1218 } 1219 done: 1220 ET_UNLOCK(sc); 1221 } 1222 1223 static void 1224 et_init_locked(struct et_softc *sc) 1225 { 1226 struct ifnet *ifp; 1227 int error; 1228 1229 ET_LOCK_ASSERT(sc); 1230 1231 ifp = sc->ifp; 1232 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1233 return; 1234 1235 et_stop(sc); 1236 et_reset(sc); 1237 1238 et_init_tx_ring(sc); 1239 error = et_init_rx_ring(sc); 1240 if (error) 1241 return; 1242 1243 error = et_chip_init(sc); 1244 if (error) 1245 goto fail; 1246 1247 /* 1248 * Start TX/RX DMA engine 1249 */ 1250 error = et_start_rxdma(sc); 1251 if (error) 1252 return; 1253 1254 error = et_start_txdma(sc); 1255 if (error) 1256 return; 1257 1258 /* Enable interrupts. */ 1259 CSR_WRITE_4(sc, ET_INTR_MASK, ~ET_INTRS); 1260 1261 CSR_WRITE_4(sc, ET_TIMER, sc->sc_timer); 1262 1263 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1264 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1265 1266 sc->sc_flags &= ~ET_FLAG_LINK; 1267 et_ifmedia_upd_locked(ifp); 1268 1269 callout_reset(&sc->sc_tick, hz, et_tick, sc); 1270 1271 fail: 1272 if (error) 1273 et_stop(sc); 1274 } 1275 1276 static void 1277 et_init(void *xsc) 1278 { 1279 struct et_softc *sc = xsc; 1280 1281 ET_LOCK(sc); 1282 et_init_locked(sc); 1283 ET_UNLOCK(sc); 1284 } 1285 1286 static int 1287 et_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1288 { 1289 struct et_softc *sc; 1290 struct mii_data *mii; 1291 struct ifreq *ifr; 1292 int error, mask, max_framelen; 1293 1294 sc = ifp->if_softc; 1295 ifr = (struct ifreq *)data; 1296 error = 0; 1297 1298 /* XXX LOCKSUSED */ 1299 switch (cmd) { 1300 case SIOCSIFFLAGS: 1301 ET_LOCK(sc); 1302 if (ifp->if_flags & IFF_UP) { 1303 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1304 if ((ifp->if_flags ^ sc->sc_if_flags) & 1305 (IFF_ALLMULTI | IFF_PROMISC | IFF_BROADCAST)) 1306 et_setmulti(sc); 1307 } else { 1308 et_init_locked(sc); 1309 } 1310 } else { 1311 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1312 et_stop(sc); 1313 } 1314 sc->sc_if_flags = ifp->if_flags; 1315 ET_UNLOCK(sc); 1316 break; 1317 1318 case SIOCSIFMEDIA: 1319 case SIOCGIFMEDIA: 1320 mii = device_get_softc(sc->sc_miibus); 1321 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1322 break; 1323 1324 case SIOCADDMULTI: 1325 case SIOCDELMULTI: 1326 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1327 ET_LOCK(sc); 1328 et_setmulti(sc); 1329 ET_UNLOCK(sc); 1330 } 1331 break; 1332 1333 case SIOCSIFMTU: 1334 ET_LOCK(sc); 1335 #if 0 1336 if (sc->sc_flags & ET_FLAG_JUMBO) 1337 max_framelen = ET_JUMBO_FRAMELEN; 1338 else 1339 #endif 1340 max_framelen = MCLBYTES - 1; 1341 1342 if (ET_FRAMELEN(ifr->ifr_mtu) > max_framelen) { 1343 error = EOPNOTSUPP; 1344 ET_UNLOCK(sc); 1345 break; 1346 } 1347 1348 if (ifp->if_mtu != ifr->ifr_mtu) { 1349 ifp->if_mtu = ifr->ifr_mtu; 1350 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1351 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1352 et_init_locked(sc); 1353 } 1354 } 1355 ET_UNLOCK(sc); 1356 break; 1357 1358 case SIOCSIFCAP: 1359 ET_LOCK(sc); 1360 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1361 if ((mask & IFCAP_TXCSUM) != 0 && 1362 (IFCAP_TXCSUM & ifp->if_capabilities) != 0) { 1363 ifp->if_capenable ^= IFCAP_TXCSUM; 1364 if ((IFCAP_TXCSUM & ifp->if_capenable) != 0) 1365 ifp->if_hwassist |= ET_CSUM_FEATURES; 1366 else 1367 ifp->if_hwassist &= ~ET_CSUM_FEATURES; 1368 } 1369 ET_UNLOCK(sc); 1370 break; 1371 1372 default: 1373 error = ether_ioctl(ifp, cmd, data); 1374 break; 1375 } 1376 return (error); 1377 } 1378 1379 static void 1380 et_start_locked(struct ifnet *ifp) 1381 { 1382 struct et_softc *sc; 1383 struct mbuf *m_head = NULL; 1384 struct et_txdesc_ring *tx_ring; 1385 struct et_txbuf_data *tbd; 1386 uint32_t tx_ready_pos; 1387 int enq; 1388 1389 sc = ifp->if_softc; 1390 ET_LOCK_ASSERT(sc); 1391 1392 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1393 IFF_DRV_RUNNING || 1394 (sc->sc_flags & (ET_FLAG_LINK | ET_FLAG_TXRX_ENABLED)) != 1395 (ET_FLAG_LINK | ET_FLAG_TXRX_ENABLED)) 1396 return; 1397 1398 /* 1399 * Driver does not request TX completion interrupt for every 1400 * queued frames to prevent generating excessive interrupts. 1401 * This means driver may wait for TX completion interrupt even 1402 * though some frames were successfully transmitted. Reclaiming 1403 * transmitted frames will ensure driver see all available 1404 * descriptors. 1405 */ 1406 tbd = &sc->sc_tx_data; 1407 if (tbd->tbd_used > (ET_TX_NDESC * 2) / 3) 1408 et_txeof(sc); 1409 1410 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd); ) { 1411 if (tbd->tbd_used + ET_NSEG_SPARE >= ET_TX_NDESC) { 1412 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1413 break; 1414 } 1415 1416 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1417 if (m_head == NULL) 1418 break; 1419 1420 if (et_encap(sc, &m_head)) { 1421 if (m_head == NULL) { 1422 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1423 break; 1424 } 1425 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1426 if (tbd->tbd_used > 0) 1427 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1428 break; 1429 } 1430 enq++; 1431 ETHER_BPF_MTAP(ifp, m_head); 1432 } 1433 1434 if (enq > 0) { 1435 tx_ring = &sc->sc_tx_ring; 1436 bus_dmamap_sync(tx_ring->tr_dtag, tx_ring->tr_dmap, 1437 BUS_DMASYNC_PREWRITE); 1438 tx_ready_pos = tx_ring->tr_ready_index & 1439 ET_TX_READY_POS_INDEX_MASK; 1440 if (tx_ring->tr_ready_wrap) 1441 tx_ready_pos |= ET_TX_READY_POS_WRAP; 1442 CSR_WRITE_4(sc, ET_TX_READY_POS, tx_ready_pos); 1443 sc->watchdog_timer = 5; 1444 } 1445 } 1446 1447 static void 1448 et_start(struct ifnet *ifp) 1449 { 1450 struct et_softc *sc; 1451 1452 sc = ifp->if_softc; 1453 ET_LOCK(sc); 1454 et_start_locked(ifp); 1455 ET_UNLOCK(sc); 1456 } 1457 1458 static int 1459 et_watchdog(struct et_softc *sc) 1460 { 1461 uint32_t status; 1462 1463 ET_LOCK_ASSERT(sc); 1464 1465 if (sc->watchdog_timer == 0 || --sc->watchdog_timer) 1466 return (0); 1467 1468 bus_dmamap_sync(sc->sc_tx_status.txsd_dtag, sc->sc_tx_status.txsd_dmap, 1469 BUS_DMASYNC_POSTREAD); 1470 status = le32toh(*(sc->sc_tx_status.txsd_status)); 1471 if_printf(sc->ifp, "watchdog timed out (0x%08x) -- resetting\n", 1472 status); 1473 1474 if_inc_counter(sc->ifp, IFCOUNTER_OERRORS, 1); 1475 sc->ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1476 et_init_locked(sc); 1477 return (EJUSTRETURN); 1478 } 1479 1480 static int 1481 et_stop_rxdma(struct et_softc *sc) 1482 { 1483 1484 CSR_WRITE_4(sc, ET_RXDMA_CTRL, 1485 ET_RXDMA_CTRL_HALT | ET_RXDMA_CTRL_RING1_ENABLE); 1486 1487 DELAY(5); 1488 if ((CSR_READ_4(sc, ET_RXDMA_CTRL) & ET_RXDMA_CTRL_HALTED) == 0) { 1489 if_printf(sc->ifp, "can't stop RX DMA engine\n"); 1490 return (ETIMEDOUT); 1491 } 1492 return (0); 1493 } 1494 1495 static int 1496 et_stop_txdma(struct et_softc *sc) 1497 { 1498 1499 CSR_WRITE_4(sc, ET_TXDMA_CTRL, 1500 ET_TXDMA_CTRL_HALT | ET_TXDMA_CTRL_SINGLE_EPKT); 1501 return (0); 1502 } 1503 1504 static void 1505 et_free_tx_ring(struct et_softc *sc) 1506 { 1507 struct et_txdesc_ring *tx_ring; 1508 struct et_txbuf_data *tbd; 1509 struct et_txbuf *tb; 1510 int i; 1511 1512 tbd = &sc->sc_tx_data; 1513 tx_ring = &sc->sc_tx_ring; 1514 for (i = 0; i < ET_TX_NDESC; ++i) { 1515 tb = &tbd->tbd_buf[i]; 1516 if (tb->tb_mbuf != NULL) { 1517 bus_dmamap_sync(sc->sc_tx_tag, tb->tb_dmap, 1518 BUS_DMASYNC_POSTWRITE); 1519 bus_dmamap_unload(sc->sc_mbuf_dtag, tb->tb_dmap); 1520 m_freem(tb->tb_mbuf); 1521 tb->tb_mbuf = NULL; 1522 } 1523 } 1524 } 1525 1526 static void 1527 et_free_rx_ring(struct et_softc *sc) 1528 { 1529 struct et_rxbuf_data *rbd; 1530 struct et_rxdesc_ring *rx_ring; 1531 struct et_rxbuf *rb; 1532 int i; 1533 1534 /* Ring 0 */ 1535 rx_ring = &sc->sc_rx_ring[0]; 1536 rbd = &sc->sc_rx_data[0]; 1537 for (i = 0; i < ET_RX_NDESC; ++i) { 1538 rb = &rbd->rbd_buf[i]; 1539 if (rb->rb_mbuf != NULL) { 1540 bus_dmamap_sync(sc->sc_rx_mini_tag, rx_ring->rr_dmap, 1541 BUS_DMASYNC_POSTREAD); 1542 bus_dmamap_unload(sc->sc_rx_mini_tag, rb->rb_dmap); 1543 m_freem(rb->rb_mbuf); 1544 rb->rb_mbuf = NULL; 1545 } 1546 } 1547 1548 /* Ring 1 */ 1549 rx_ring = &sc->sc_rx_ring[1]; 1550 rbd = &sc->sc_rx_data[1]; 1551 for (i = 0; i < ET_RX_NDESC; ++i) { 1552 rb = &rbd->rbd_buf[i]; 1553 if (rb->rb_mbuf != NULL) { 1554 bus_dmamap_sync(sc->sc_rx_tag, rx_ring->rr_dmap, 1555 BUS_DMASYNC_POSTREAD); 1556 bus_dmamap_unload(sc->sc_rx_tag, rb->rb_dmap); 1557 m_freem(rb->rb_mbuf); 1558 rb->rb_mbuf = NULL; 1559 } 1560 } 1561 } 1562 1563 static u_int 1564 et_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 1565 { 1566 uint32_t h, *hp, *hash = arg; 1567 1568 h = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN); 1569 h = (h & 0x3f800000) >> 23; 1570 1571 hp = &hash[0]; 1572 if (h >= 32 && h < 64) { 1573 h -= 32; 1574 hp = &hash[1]; 1575 } else if (h >= 64 && h < 96) { 1576 h -= 64; 1577 hp = &hash[2]; 1578 } else if (h >= 96) { 1579 h -= 96; 1580 hp = &hash[3]; 1581 } 1582 *hp |= (1 << h); 1583 1584 return (1); 1585 } 1586 1587 static void 1588 et_setmulti(struct et_softc *sc) 1589 { 1590 struct ifnet *ifp; 1591 uint32_t hash[4] = { 0, 0, 0, 0 }; 1592 uint32_t rxmac_ctrl, pktfilt; 1593 int i, count; 1594 1595 ET_LOCK_ASSERT(sc); 1596 ifp = sc->ifp; 1597 1598 pktfilt = CSR_READ_4(sc, ET_PKTFILT); 1599 rxmac_ctrl = CSR_READ_4(sc, ET_RXMAC_CTRL); 1600 1601 pktfilt &= ~(ET_PKTFILT_BCAST | ET_PKTFILT_MCAST | ET_PKTFILT_UCAST); 1602 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) { 1603 rxmac_ctrl |= ET_RXMAC_CTRL_NO_PKTFILT; 1604 goto back; 1605 } 1606 1607 count = if_foreach_llmaddr(ifp, et_hash_maddr, &hash); 1608 1609 for (i = 0; i < 4; ++i) 1610 CSR_WRITE_4(sc, ET_MULTI_HASH + (i * 4), hash[i]); 1611 1612 if (count > 0) 1613 pktfilt |= ET_PKTFILT_MCAST; 1614 rxmac_ctrl &= ~ET_RXMAC_CTRL_NO_PKTFILT; 1615 back: 1616 CSR_WRITE_4(sc, ET_PKTFILT, pktfilt); 1617 CSR_WRITE_4(sc, ET_RXMAC_CTRL, rxmac_ctrl); 1618 } 1619 1620 static int 1621 et_chip_init(struct et_softc *sc) 1622 { 1623 struct ifnet *ifp; 1624 uint32_t rxq_end; 1625 int error, frame_len, rxmem_size; 1626 1627 ifp = sc->ifp; 1628 /* 1629 * Split 16Kbytes internal memory between TX and RX 1630 * according to frame length. 1631 */ 1632 frame_len = ET_FRAMELEN(ifp->if_mtu); 1633 if (frame_len < 2048) { 1634 rxmem_size = ET_MEM_RXSIZE_DEFAULT; 1635 } else if (frame_len <= ET_RXMAC_CUT_THRU_FRMLEN) { 1636 rxmem_size = ET_MEM_SIZE / 2; 1637 } else { 1638 rxmem_size = ET_MEM_SIZE - 1639 roundup(frame_len + ET_MEM_TXSIZE_EX, ET_MEM_UNIT); 1640 } 1641 rxq_end = ET_QUEUE_ADDR(rxmem_size); 1642 1643 CSR_WRITE_4(sc, ET_RXQUEUE_START, ET_QUEUE_ADDR_START); 1644 CSR_WRITE_4(sc, ET_RXQUEUE_END, rxq_end); 1645 CSR_WRITE_4(sc, ET_TXQUEUE_START, rxq_end + 1); 1646 CSR_WRITE_4(sc, ET_TXQUEUE_END, ET_QUEUE_ADDR_END); 1647 1648 /* No loopback */ 1649 CSR_WRITE_4(sc, ET_LOOPBACK, 0); 1650 1651 /* Clear MSI configure */ 1652 if ((sc->sc_flags & ET_FLAG_MSI) == 0) 1653 CSR_WRITE_4(sc, ET_MSI_CFG, 0); 1654 1655 /* Disable timer */ 1656 CSR_WRITE_4(sc, ET_TIMER, 0); 1657 1658 /* Initialize MAC */ 1659 et_init_mac(sc); 1660 1661 /* Enable memory controllers */ 1662 CSR_WRITE_4(sc, ET_MMC_CTRL, ET_MMC_CTRL_ENABLE); 1663 1664 /* Initialize RX MAC */ 1665 et_init_rxmac(sc); 1666 1667 /* Initialize TX MAC */ 1668 et_init_txmac(sc); 1669 1670 /* Initialize RX DMA engine */ 1671 error = et_init_rxdma(sc); 1672 if (error) 1673 return (error); 1674 1675 /* Initialize TX DMA engine */ 1676 error = et_init_txdma(sc); 1677 if (error) 1678 return (error); 1679 1680 return (0); 1681 } 1682 1683 static void 1684 et_init_tx_ring(struct et_softc *sc) 1685 { 1686 struct et_txdesc_ring *tx_ring; 1687 struct et_txbuf_data *tbd; 1688 struct et_txstatus_data *txsd; 1689 1690 tx_ring = &sc->sc_tx_ring; 1691 bzero(tx_ring->tr_desc, ET_TX_RING_SIZE); 1692 bus_dmamap_sync(tx_ring->tr_dtag, tx_ring->tr_dmap, 1693 BUS_DMASYNC_PREWRITE); 1694 1695 tbd = &sc->sc_tx_data; 1696 tbd->tbd_start_index = 0; 1697 tbd->tbd_start_wrap = 0; 1698 tbd->tbd_used = 0; 1699 1700 txsd = &sc->sc_tx_status; 1701 bzero(txsd->txsd_status, sizeof(uint32_t)); 1702 bus_dmamap_sync(txsd->txsd_dtag, txsd->txsd_dmap, 1703 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1704 } 1705 1706 static int 1707 et_init_rx_ring(struct et_softc *sc) 1708 { 1709 struct et_rxstatus_data *rxsd; 1710 struct et_rxstat_ring *rxst_ring; 1711 struct et_rxbuf_data *rbd; 1712 int i, error, n; 1713 1714 for (n = 0; n < ET_RX_NRING; ++n) { 1715 rbd = &sc->sc_rx_data[n]; 1716 for (i = 0; i < ET_RX_NDESC; ++i) { 1717 error = rbd->rbd_newbuf(rbd, i); 1718 if (error) { 1719 if_printf(sc->ifp, "%d ring %d buf, " 1720 "newbuf failed: %d\n", n, i, error); 1721 return (error); 1722 } 1723 } 1724 } 1725 1726 rxsd = &sc->sc_rx_status; 1727 bzero(rxsd->rxsd_status, sizeof(struct et_rxstatus)); 1728 bus_dmamap_sync(rxsd->rxsd_dtag, rxsd->rxsd_dmap, 1729 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1730 1731 rxst_ring = &sc->sc_rxstat_ring; 1732 bzero(rxst_ring->rsr_stat, ET_RXSTAT_RING_SIZE); 1733 bus_dmamap_sync(rxst_ring->rsr_dtag, rxst_ring->rsr_dmap, 1734 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1735 1736 return (0); 1737 } 1738 1739 static int 1740 et_init_rxdma(struct et_softc *sc) 1741 { 1742 struct et_rxstatus_data *rxsd; 1743 struct et_rxstat_ring *rxst_ring; 1744 struct et_rxdesc_ring *rx_ring; 1745 int error; 1746 1747 error = et_stop_rxdma(sc); 1748 if (error) { 1749 if_printf(sc->ifp, "can't init RX DMA engine\n"); 1750 return (error); 1751 } 1752 1753 /* 1754 * Install RX status 1755 */ 1756 rxsd = &sc->sc_rx_status; 1757 CSR_WRITE_4(sc, ET_RX_STATUS_HI, ET_ADDR_HI(rxsd->rxsd_paddr)); 1758 CSR_WRITE_4(sc, ET_RX_STATUS_LO, ET_ADDR_LO(rxsd->rxsd_paddr)); 1759 1760 /* 1761 * Install RX stat ring 1762 */ 1763 rxst_ring = &sc->sc_rxstat_ring; 1764 CSR_WRITE_4(sc, ET_RXSTAT_HI, ET_ADDR_HI(rxst_ring->rsr_paddr)); 1765 CSR_WRITE_4(sc, ET_RXSTAT_LO, ET_ADDR_LO(rxst_ring->rsr_paddr)); 1766 CSR_WRITE_4(sc, ET_RXSTAT_CNT, ET_RX_NSTAT - 1); 1767 CSR_WRITE_4(sc, ET_RXSTAT_POS, 0); 1768 CSR_WRITE_4(sc, ET_RXSTAT_MINCNT, ((ET_RX_NSTAT * 15) / 100) - 1); 1769 1770 /* Match ET_RXSTAT_POS */ 1771 rxst_ring->rsr_index = 0; 1772 rxst_ring->rsr_wrap = 0; 1773 1774 /* 1775 * Install the 2nd RX descriptor ring 1776 */ 1777 rx_ring = &sc->sc_rx_ring[1]; 1778 CSR_WRITE_4(sc, ET_RX_RING1_HI, ET_ADDR_HI(rx_ring->rr_paddr)); 1779 CSR_WRITE_4(sc, ET_RX_RING1_LO, ET_ADDR_LO(rx_ring->rr_paddr)); 1780 CSR_WRITE_4(sc, ET_RX_RING1_CNT, ET_RX_NDESC - 1); 1781 CSR_WRITE_4(sc, ET_RX_RING1_POS, ET_RX_RING1_POS_WRAP); 1782 CSR_WRITE_4(sc, ET_RX_RING1_MINCNT, ((ET_RX_NDESC * 15) / 100) - 1); 1783 1784 /* Match ET_RX_RING1_POS */ 1785 rx_ring->rr_index = 0; 1786 rx_ring->rr_wrap = 1; 1787 1788 /* 1789 * Install the 1st RX descriptor ring 1790 */ 1791 rx_ring = &sc->sc_rx_ring[0]; 1792 CSR_WRITE_4(sc, ET_RX_RING0_HI, ET_ADDR_HI(rx_ring->rr_paddr)); 1793 CSR_WRITE_4(sc, ET_RX_RING0_LO, ET_ADDR_LO(rx_ring->rr_paddr)); 1794 CSR_WRITE_4(sc, ET_RX_RING0_CNT, ET_RX_NDESC - 1); 1795 CSR_WRITE_4(sc, ET_RX_RING0_POS, ET_RX_RING0_POS_WRAP); 1796 CSR_WRITE_4(sc, ET_RX_RING0_MINCNT, ((ET_RX_NDESC * 15) / 100) - 1); 1797 1798 /* Match ET_RX_RING0_POS */ 1799 rx_ring->rr_index = 0; 1800 rx_ring->rr_wrap = 1; 1801 1802 /* 1803 * RX intr moderation 1804 */ 1805 CSR_WRITE_4(sc, ET_RX_INTR_NPKTS, sc->sc_rx_intr_npkts); 1806 CSR_WRITE_4(sc, ET_RX_INTR_DELAY, sc->sc_rx_intr_delay); 1807 1808 return (0); 1809 } 1810 1811 static int 1812 et_init_txdma(struct et_softc *sc) 1813 { 1814 struct et_txdesc_ring *tx_ring; 1815 struct et_txstatus_data *txsd; 1816 int error; 1817 1818 error = et_stop_txdma(sc); 1819 if (error) { 1820 if_printf(sc->ifp, "can't init TX DMA engine\n"); 1821 return (error); 1822 } 1823 1824 /* 1825 * Install TX descriptor ring 1826 */ 1827 tx_ring = &sc->sc_tx_ring; 1828 CSR_WRITE_4(sc, ET_TX_RING_HI, ET_ADDR_HI(tx_ring->tr_paddr)); 1829 CSR_WRITE_4(sc, ET_TX_RING_LO, ET_ADDR_LO(tx_ring->tr_paddr)); 1830 CSR_WRITE_4(sc, ET_TX_RING_CNT, ET_TX_NDESC - 1); 1831 1832 /* 1833 * Install TX status 1834 */ 1835 txsd = &sc->sc_tx_status; 1836 CSR_WRITE_4(sc, ET_TX_STATUS_HI, ET_ADDR_HI(txsd->txsd_paddr)); 1837 CSR_WRITE_4(sc, ET_TX_STATUS_LO, ET_ADDR_LO(txsd->txsd_paddr)); 1838 1839 CSR_WRITE_4(sc, ET_TX_READY_POS, 0); 1840 1841 /* Match ET_TX_READY_POS */ 1842 tx_ring->tr_ready_index = 0; 1843 tx_ring->tr_ready_wrap = 0; 1844 1845 return (0); 1846 } 1847 1848 static void 1849 et_init_mac(struct et_softc *sc) 1850 { 1851 struct ifnet *ifp; 1852 const uint8_t *eaddr; 1853 uint32_t val; 1854 1855 /* Reset MAC */ 1856 CSR_WRITE_4(sc, ET_MAC_CFG1, 1857 ET_MAC_CFG1_RST_TXFUNC | ET_MAC_CFG1_RST_RXFUNC | 1858 ET_MAC_CFG1_RST_TXMC | ET_MAC_CFG1_RST_RXMC | 1859 ET_MAC_CFG1_SIM_RST | ET_MAC_CFG1_SOFT_RST); 1860 1861 /* 1862 * Setup inter packet gap 1863 */ 1864 val = (56 << ET_IPG_NONB2B_1_SHIFT) | 1865 (88 << ET_IPG_NONB2B_2_SHIFT) | 1866 (80 << ET_IPG_MINIFG_SHIFT) | 1867 (96 << ET_IPG_B2B_SHIFT); 1868 CSR_WRITE_4(sc, ET_IPG, val); 1869 1870 /* 1871 * Setup half duplex mode 1872 */ 1873 val = (10 << ET_MAC_HDX_ALT_BEB_TRUNC_SHIFT) | 1874 (15 << ET_MAC_HDX_REXMIT_MAX_SHIFT) | 1875 (55 << ET_MAC_HDX_COLLWIN_SHIFT) | 1876 ET_MAC_HDX_EXC_DEFER; 1877 CSR_WRITE_4(sc, ET_MAC_HDX, val); 1878 1879 /* Clear MAC control */ 1880 CSR_WRITE_4(sc, ET_MAC_CTRL, 0); 1881 1882 /* Reset MII */ 1883 CSR_WRITE_4(sc, ET_MII_CFG, ET_MII_CFG_CLKRST); 1884 1885 /* 1886 * Set MAC address 1887 */ 1888 ifp = sc->ifp; 1889 eaddr = IF_LLADDR(ifp); 1890 val = eaddr[2] | (eaddr[3] << 8) | (eaddr[4] << 16) | (eaddr[5] << 24); 1891 CSR_WRITE_4(sc, ET_MAC_ADDR1, val); 1892 val = (eaddr[0] << 16) | (eaddr[1] << 24); 1893 CSR_WRITE_4(sc, ET_MAC_ADDR2, val); 1894 1895 /* Set max frame length */ 1896 CSR_WRITE_4(sc, ET_MAX_FRMLEN, ET_FRAMELEN(ifp->if_mtu)); 1897 1898 /* Bring MAC out of reset state */ 1899 CSR_WRITE_4(sc, ET_MAC_CFG1, 0); 1900 } 1901 1902 static void 1903 et_init_rxmac(struct et_softc *sc) 1904 { 1905 struct ifnet *ifp; 1906 const uint8_t *eaddr; 1907 uint32_t val; 1908 int i; 1909 1910 /* Disable RX MAC and WOL */ 1911 CSR_WRITE_4(sc, ET_RXMAC_CTRL, ET_RXMAC_CTRL_WOL_DISABLE); 1912 1913 /* 1914 * Clear all WOL related registers 1915 */ 1916 for (i = 0; i < 3; ++i) 1917 CSR_WRITE_4(sc, ET_WOL_CRC + (i * 4), 0); 1918 for (i = 0; i < 20; ++i) 1919 CSR_WRITE_4(sc, ET_WOL_MASK + (i * 4), 0); 1920 1921 /* 1922 * Set WOL source address. XXX is this necessary? 1923 */ 1924 ifp = sc->ifp; 1925 eaddr = IF_LLADDR(ifp); 1926 val = (eaddr[2] << 24) | (eaddr[3] << 16) | (eaddr[4] << 8) | eaddr[5]; 1927 CSR_WRITE_4(sc, ET_WOL_SA_LO, val); 1928 val = (eaddr[0] << 8) | eaddr[1]; 1929 CSR_WRITE_4(sc, ET_WOL_SA_HI, val); 1930 1931 /* Clear packet filters */ 1932 CSR_WRITE_4(sc, ET_PKTFILT, 0); 1933 1934 /* No ucast filtering */ 1935 CSR_WRITE_4(sc, ET_UCAST_FILTADDR1, 0); 1936 CSR_WRITE_4(sc, ET_UCAST_FILTADDR2, 0); 1937 CSR_WRITE_4(sc, ET_UCAST_FILTADDR3, 0); 1938 1939 if (ET_FRAMELEN(ifp->if_mtu) > ET_RXMAC_CUT_THRU_FRMLEN) { 1940 /* 1941 * In order to transmit jumbo packets greater than 1942 * ET_RXMAC_CUT_THRU_FRMLEN bytes, the FIFO between 1943 * RX MAC and RX DMA needs to be reduced in size to 1944 * (ET_MEM_SIZE - ET_MEM_TXSIZE_EX - framelen). In 1945 * order to implement this, we must use "cut through" 1946 * mode in the RX MAC, which chops packets down into 1947 * segments. In this case we selected 256 bytes, 1948 * since this is the size of the PCI-Express TLP's 1949 * that the ET1310 uses. 1950 */ 1951 val = (ET_RXMAC_SEGSZ(256) & ET_RXMAC_MC_SEGSZ_MAX_MASK) | 1952 ET_RXMAC_MC_SEGSZ_ENABLE; 1953 } else { 1954 val = 0; 1955 } 1956 CSR_WRITE_4(sc, ET_RXMAC_MC_SEGSZ, val); 1957 1958 CSR_WRITE_4(sc, ET_RXMAC_MC_WATERMARK, 0); 1959 1960 /* Initialize RX MAC management register */ 1961 CSR_WRITE_4(sc, ET_RXMAC_MGT, 0); 1962 1963 CSR_WRITE_4(sc, ET_RXMAC_SPACE_AVL, 0); 1964 1965 CSR_WRITE_4(sc, ET_RXMAC_MGT, 1966 ET_RXMAC_MGT_PASS_ECRC | 1967 ET_RXMAC_MGT_PASS_ELEN | 1968 ET_RXMAC_MGT_PASS_ETRUNC | 1969 ET_RXMAC_MGT_CHECK_PKT); 1970 1971 /* 1972 * Configure runt filtering (may not work on certain chip generation) 1973 */ 1974 val = (ETHER_MIN_LEN << ET_PKTFILT_MINLEN_SHIFT) & 1975 ET_PKTFILT_MINLEN_MASK; 1976 val |= ET_PKTFILT_FRAG; 1977 CSR_WRITE_4(sc, ET_PKTFILT, val); 1978 1979 /* Enable RX MAC but leave WOL disabled */ 1980 CSR_WRITE_4(sc, ET_RXMAC_CTRL, 1981 ET_RXMAC_CTRL_WOL_DISABLE | ET_RXMAC_CTRL_ENABLE); 1982 1983 /* 1984 * Setup multicast hash and allmulti/promisc mode 1985 */ 1986 et_setmulti(sc); 1987 } 1988 1989 static void 1990 et_init_txmac(struct et_softc *sc) 1991 { 1992 1993 /* Disable TX MAC and FC(?) */ 1994 CSR_WRITE_4(sc, ET_TXMAC_CTRL, ET_TXMAC_CTRL_FC_DISABLE); 1995 1996 /* 1997 * Initialize pause time. 1998 * This register should be set before XON/XOFF frame is 1999 * sent by driver. 2000 */ 2001 CSR_WRITE_4(sc, ET_TXMAC_FLOWCTRL, 0 << ET_TXMAC_FLOWCTRL_CFPT_SHIFT); 2002 2003 /* Enable TX MAC but leave FC(?) diabled */ 2004 CSR_WRITE_4(sc, ET_TXMAC_CTRL, 2005 ET_TXMAC_CTRL_ENABLE | ET_TXMAC_CTRL_FC_DISABLE); 2006 } 2007 2008 static int 2009 et_start_rxdma(struct et_softc *sc) 2010 { 2011 uint32_t val; 2012 2013 val = (sc->sc_rx_data[0].rbd_bufsize & ET_RXDMA_CTRL_RING0_SIZE_MASK) | 2014 ET_RXDMA_CTRL_RING0_ENABLE; 2015 val |= (sc->sc_rx_data[1].rbd_bufsize & ET_RXDMA_CTRL_RING1_SIZE_MASK) | 2016 ET_RXDMA_CTRL_RING1_ENABLE; 2017 2018 CSR_WRITE_4(sc, ET_RXDMA_CTRL, val); 2019 2020 DELAY(5); 2021 2022 if (CSR_READ_4(sc, ET_RXDMA_CTRL) & ET_RXDMA_CTRL_HALTED) { 2023 if_printf(sc->ifp, "can't start RX DMA engine\n"); 2024 return (ETIMEDOUT); 2025 } 2026 return (0); 2027 } 2028 2029 static int 2030 et_start_txdma(struct et_softc *sc) 2031 { 2032 2033 CSR_WRITE_4(sc, ET_TXDMA_CTRL, ET_TXDMA_CTRL_SINGLE_EPKT); 2034 return (0); 2035 } 2036 2037 static void 2038 et_rxeof(struct et_softc *sc) 2039 { 2040 struct et_rxstatus_data *rxsd; 2041 struct et_rxstat_ring *rxst_ring; 2042 struct et_rxbuf_data *rbd; 2043 struct et_rxdesc_ring *rx_ring; 2044 struct et_rxstat *st; 2045 struct ifnet *ifp; 2046 struct mbuf *m; 2047 uint32_t rxstat_pos, rxring_pos; 2048 uint32_t rxst_info1, rxst_info2, rxs_stat_ring; 2049 int buflen, buf_idx, npost[2], ring_idx; 2050 int rxst_index, rxst_wrap; 2051 2052 ET_LOCK_ASSERT(sc); 2053 2054 ifp = sc->ifp; 2055 rxsd = &sc->sc_rx_status; 2056 rxst_ring = &sc->sc_rxstat_ring; 2057 2058 if ((sc->sc_flags & ET_FLAG_TXRX_ENABLED) == 0) 2059 return; 2060 2061 bus_dmamap_sync(rxsd->rxsd_dtag, rxsd->rxsd_dmap, 2062 BUS_DMASYNC_POSTREAD); 2063 bus_dmamap_sync(rxst_ring->rsr_dtag, rxst_ring->rsr_dmap, 2064 BUS_DMASYNC_POSTREAD); 2065 2066 npost[0] = npost[1] = 0; 2067 rxs_stat_ring = le32toh(rxsd->rxsd_status->rxs_stat_ring); 2068 rxst_wrap = (rxs_stat_ring & ET_RXS_STATRING_WRAP) ? 1 : 0; 2069 rxst_index = (rxs_stat_ring & ET_RXS_STATRING_INDEX_MASK) >> 2070 ET_RXS_STATRING_INDEX_SHIFT; 2071 2072 while (rxst_index != rxst_ring->rsr_index || 2073 rxst_wrap != rxst_ring->rsr_wrap) { 2074 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 2075 break; 2076 2077 MPASS(rxst_ring->rsr_index < ET_RX_NSTAT); 2078 st = &rxst_ring->rsr_stat[rxst_ring->rsr_index]; 2079 rxst_info1 = le32toh(st->rxst_info1); 2080 rxst_info2 = le32toh(st->rxst_info2); 2081 buflen = (rxst_info2 & ET_RXST_INFO2_LEN_MASK) >> 2082 ET_RXST_INFO2_LEN_SHIFT; 2083 buf_idx = (rxst_info2 & ET_RXST_INFO2_BUFIDX_MASK) >> 2084 ET_RXST_INFO2_BUFIDX_SHIFT; 2085 ring_idx = (rxst_info2 & ET_RXST_INFO2_RINGIDX_MASK) >> 2086 ET_RXST_INFO2_RINGIDX_SHIFT; 2087 2088 if (++rxst_ring->rsr_index == ET_RX_NSTAT) { 2089 rxst_ring->rsr_index = 0; 2090 rxst_ring->rsr_wrap ^= 1; 2091 } 2092 rxstat_pos = rxst_ring->rsr_index & ET_RXSTAT_POS_INDEX_MASK; 2093 if (rxst_ring->rsr_wrap) 2094 rxstat_pos |= ET_RXSTAT_POS_WRAP; 2095 CSR_WRITE_4(sc, ET_RXSTAT_POS, rxstat_pos); 2096 2097 if (ring_idx >= ET_RX_NRING) { 2098 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 2099 if_printf(ifp, "invalid ring index %d\n", ring_idx); 2100 continue; 2101 } 2102 if (buf_idx >= ET_RX_NDESC) { 2103 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 2104 if_printf(ifp, "invalid buf index %d\n", buf_idx); 2105 continue; 2106 } 2107 2108 rbd = &sc->sc_rx_data[ring_idx]; 2109 m = rbd->rbd_buf[buf_idx].rb_mbuf; 2110 if ((rxst_info1 & ET_RXST_INFO1_OK) == 0){ 2111 /* Discard errored frame. */ 2112 rbd->rbd_discard(rbd, buf_idx); 2113 } else if (rbd->rbd_newbuf(rbd, buf_idx) != 0) { 2114 /* No available mbufs, discard it. */ 2115 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 2116 rbd->rbd_discard(rbd, buf_idx); 2117 } else { 2118 buflen -= ETHER_CRC_LEN; 2119 if (buflen < ETHER_HDR_LEN) { 2120 m_freem(m); 2121 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 2122 } else { 2123 m->m_pkthdr.len = m->m_len = buflen; 2124 m->m_pkthdr.rcvif = ifp; 2125 ET_UNLOCK(sc); 2126 ifp->if_input(ifp, m); 2127 ET_LOCK(sc); 2128 } 2129 } 2130 2131 rx_ring = &sc->sc_rx_ring[ring_idx]; 2132 if (buf_idx != rx_ring->rr_index) { 2133 if_printf(ifp, 2134 "WARNING!! ring %d, buf_idx %d, rr_idx %d\n", 2135 ring_idx, buf_idx, rx_ring->rr_index); 2136 } 2137 2138 MPASS(rx_ring->rr_index < ET_RX_NDESC); 2139 if (++rx_ring->rr_index == ET_RX_NDESC) { 2140 rx_ring->rr_index = 0; 2141 rx_ring->rr_wrap ^= 1; 2142 } 2143 rxring_pos = rx_ring->rr_index & ET_RX_RING_POS_INDEX_MASK; 2144 if (rx_ring->rr_wrap) 2145 rxring_pos |= ET_RX_RING_POS_WRAP; 2146 CSR_WRITE_4(sc, rx_ring->rr_posreg, rxring_pos); 2147 } 2148 2149 bus_dmamap_sync(rxsd->rxsd_dtag, rxsd->rxsd_dmap, 2150 BUS_DMASYNC_PREREAD); 2151 bus_dmamap_sync(rxst_ring->rsr_dtag, rxst_ring->rsr_dmap, 2152 BUS_DMASYNC_PREREAD); 2153 } 2154 2155 static int 2156 et_encap(struct et_softc *sc, struct mbuf **m0) 2157 { 2158 struct et_txdesc_ring *tx_ring; 2159 struct et_txbuf_data *tbd; 2160 struct et_txdesc *td; 2161 struct mbuf *m; 2162 bus_dma_segment_t segs[ET_NSEG_MAX]; 2163 bus_dmamap_t map; 2164 uint32_t csum_flags, last_td_ctrl2; 2165 int error, i, idx, first_idx, last_idx, nsegs; 2166 2167 tx_ring = &sc->sc_tx_ring; 2168 MPASS(tx_ring->tr_ready_index < ET_TX_NDESC); 2169 tbd = &sc->sc_tx_data; 2170 first_idx = tx_ring->tr_ready_index; 2171 map = tbd->tbd_buf[first_idx].tb_dmap; 2172 2173 error = bus_dmamap_load_mbuf_sg(sc->sc_tx_tag, map, *m0, segs, &nsegs, 2174 0); 2175 if (error == EFBIG) { 2176 m = m_collapse(*m0, M_NOWAIT, ET_NSEG_MAX); 2177 if (m == NULL) { 2178 m_freem(*m0); 2179 *m0 = NULL; 2180 return (ENOMEM); 2181 } 2182 *m0 = m; 2183 error = bus_dmamap_load_mbuf_sg(sc->sc_tx_tag, map, *m0, segs, 2184 &nsegs, 0); 2185 if (error != 0) { 2186 m_freem(*m0); 2187 *m0 = NULL; 2188 return (error); 2189 } 2190 } else if (error != 0) 2191 return (error); 2192 2193 /* Check for descriptor overruns. */ 2194 if (tbd->tbd_used + nsegs > ET_TX_NDESC - 1) { 2195 bus_dmamap_unload(sc->sc_tx_tag, map); 2196 return (ENOBUFS); 2197 } 2198 bus_dmamap_sync(sc->sc_tx_tag, map, BUS_DMASYNC_PREWRITE); 2199 2200 last_td_ctrl2 = ET_TDCTRL2_LAST_FRAG; 2201 sc->sc_tx += nsegs; 2202 if (sc->sc_tx / sc->sc_tx_intr_nsegs != sc->sc_tx_intr) { 2203 sc->sc_tx_intr = sc->sc_tx / sc->sc_tx_intr_nsegs; 2204 last_td_ctrl2 |= ET_TDCTRL2_INTR; 2205 } 2206 2207 m = *m0; 2208 csum_flags = 0; 2209 if ((m->m_pkthdr.csum_flags & ET_CSUM_FEATURES) != 0) { 2210 if ((m->m_pkthdr.csum_flags & CSUM_IP) != 0) 2211 csum_flags |= ET_TDCTRL2_CSUM_IP; 2212 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) 2213 csum_flags |= ET_TDCTRL2_CSUM_UDP; 2214 else if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0) 2215 csum_flags |= ET_TDCTRL2_CSUM_TCP; 2216 } 2217 last_idx = -1; 2218 for (i = 0; i < nsegs; ++i) { 2219 idx = (first_idx + i) % ET_TX_NDESC; 2220 td = &tx_ring->tr_desc[idx]; 2221 td->td_addr_hi = htole32(ET_ADDR_HI(segs[i].ds_addr)); 2222 td->td_addr_lo = htole32(ET_ADDR_LO(segs[i].ds_addr)); 2223 td->td_ctrl1 = htole32(segs[i].ds_len & ET_TDCTRL1_LEN_MASK); 2224 if (i == nsegs - 1) { 2225 /* Last frag */ 2226 td->td_ctrl2 = htole32(last_td_ctrl2 | csum_flags); 2227 last_idx = idx; 2228 } else 2229 td->td_ctrl2 = htole32(csum_flags); 2230 2231 MPASS(tx_ring->tr_ready_index < ET_TX_NDESC); 2232 if (++tx_ring->tr_ready_index == ET_TX_NDESC) { 2233 tx_ring->tr_ready_index = 0; 2234 tx_ring->tr_ready_wrap ^= 1; 2235 } 2236 } 2237 td = &tx_ring->tr_desc[first_idx]; 2238 /* First frag */ 2239 td->td_ctrl2 |= htole32(ET_TDCTRL2_FIRST_FRAG); 2240 2241 MPASS(last_idx >= 0); 2242 tbd->tbd_buf[first_idx].tb_dmap = tbd->tbd_buf[last_idx].tb_dmap; 2243 tbd->tbd_buf[last_idx].tb_dmap = map; 2244 tbd->tbd_buf[last_idx].tb_mbuf = m; 2245 2246 tbd->tbd_used += nsegs; 2247 MPASS(tbd->tbd_used <= ET_TX_NDESC); 2248 2249 return (0); 2250 } 2251 2252 static void 2253 et_txeof(struct et_softc *sc) 2254 { 2255 struct et_txdesc_ring *tx_ring; 2256 struct et_txbuf_data *tbd; 2257 struct et_txbuf *tb; 2258 struct ifnet *ifp; 2259 uint32_t tx_done; 2260 int end, wrap; 2261 2262 ET_LOCK_ASSERT(sc); 2263 2264 ifp = sc->ifp; 2265 tx_ring = &sc->sc_tx_ring; 2266 tbd = &sc->sc_tx_data; 2267 2268 if ((sc->sc_flags & ET_FLAG_TXRX_ENABLED) == 0) 2269 return; 2270 2271 if (tbd->tbd_used == 0) 2272 return; 2273 2274 bus_dmamap_sync(tx_ring->tr_dtag, tx_ring->tr_dmap, 2275 BUS_DMASYNC_POSTWRITE); 2276 2277 tx_done = CSR_READ_4(sc, ET_TX_DONE_POS); 2278 end = tx_done & ET_TX_DONE_POS_INDEX_MASK; 2279 wrap = (tx_done & ET_TX_DONE_POS_WRAP) ? 1 : 0; 2280 2281 while (tbd->tbd_start_index != end || tbd->tbd_start_wrap != wrap) { 2282 MPASS(tbd->tbd_start_index < ET_TX_NDESC); 2283 tb = &tbd->tbd_buf[tbd->tbd_start_index]; 2284 if (tb->tb_mbuf != NULL) { 2285 bus_dmamap_sync(sc->sc_tx_tag, tb->tb_dmap, 2286 BUS_DMASYNC_POSTWRITE); 2287 bus_dmamap_unload(sc->sc_tx_tag, tb->tb_dmap); 2288 m_freem(tb->tb_mbuf); 2289 tb->tb_mbuf = NULL; 2290 } 2291 2292 if (++tbd->tbd_start_index == ET_TX_NDESC) { 2293 tbd->tbd_start_index = 0; 2294 tbd->tbd_start_wrap ^= 1; 2295 } 2296 2297 MPASS(tbd->tbd_used > 0); 2298 tbd->tbd_used--; 2299 } 2300 2301 if (tbd->tbd_used == 0) 2302 sc->watchdog_timer = 0; 2303 if (tbd->tbd_used + ET_NSEG_SPARE < ET_TX_NDESC) 2304 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2305 } 2306 2307 static void 2308 et_tick(void *xsc) 2309 { 2310 struct et_softc *sc; 2311 struct ifnet *ifp; 2312 struct mii_data *mii; 2313 2314 sc = xsc; 2315 ET_LOCK_ASSERT(sc); 2316 ifp = sc->ifp; 2317 mii = device_get_softc(sc->sc_miibus); 2318 2319 mii_tick(mii); 2320 et_stats_update(sc); 2321 if (et_watchdog(sc) == EJUSTRETURN) 2322 return; 2323 callout_reset(&sc->sc_tick, hz, et_tick, sc); 2324 } 2325 2326 static int 2327 et_newbuf_cluster(struct et_rxbuf_data *rbd, int buf_idx) 2328 { 2329 struct et_softc *sc; 2330 struct et_rxdesc *desc; 2331 struct et_rxbuf *rb; 2332 struct mbuf *m; 2333 bus_dma_segment_t segs[1]; 2334 bus_dmamap_t dmap; 2335 int nsegs; 2336 2337 MPASS(buf_idx < ET_RX_NDESC); 2338 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 2339 if (m == NULL) 2340 return (ENOBUFS); 2341 m->m_len = m->m_pkthdr.len = MCLBYTES; 2342 m_adj(m, ETHER_ALIGN); 2343 2344 sc = rbd->rbd_softc; 2345 rb = &rbd->rbd_buf[buf_idx]; 2346 2347 if (bus_dmamap_load_mbuf_sg(sc->sc_rx_tag, sc->sc_rx_sparemap, m, 2348 segs, &nsegs, 0) != 0) { 2349 m_freem(m); 2350 return (ENOBUFS); 2351 } 2352 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 2353 2354 if (rb->rb_mbuf != NULL) { 2355 bus_dmamap_sync(sc->sc_rx_tag, rb->rb_dmap, 2356 BUS_DMASYNC_POSTREAD); 2357 bus_dmamap_unload(sc->sc_rx_tag, rb->rb_dmap); 2358 } 2359 dmap = rb->rb_dmap; 2360 rb->rb_dmap = sc->sc_rx_sparemap; 2361 sc->sc_rx_sparemap = dmap; 2362 bus_dmamap_sync(sc->sc_rx_tag, rb->rb_dmap, BUS_DMASYNC_PREREAD); 2363 2364 rb->rb_mbuf = m; 2365 desc = &rbd->rbd_ring->rr_desc[buf_idx]; 2366 desc->rd_addr_hi = htole32(ET_ADDR_HI(segs[0].ds_addr)); 2367 desc->rd_addr_lo = htole32(ET_ADDR_LO(segs[0].ds_addr)); 2368 desc->rd_ctrl = htole32(buf_idx & ET_RDCTRL_BUFIDX_MASK); 2369 bus_dmamap_sync(rbd->rbd_ring->rr_dtag, rbd->rbd_ring->rr_dmap, 2370 BUS_DMASYNC_PREWRITE); 2371 return (0); 2372 } 2373 2374 static void 2375 et_rxbuf_discard(struct et_rxbuf_data *rbd, int buf_idx) 2376 { 2377 struct et_rxdesc *desc; 2378 2379 desc = &rbd->rbd_ring->rr_desc[buf_idx]; 2380 desc->rd_ctrl = htole32(buf_idx & ET_RDCTRL_BUFIDX_MASK); 2381 bus_dmamap_sync(rbd->rbd_ring->rr_dtag, rbd->rbd_ring->rr_dmap, 2382 BUS_DMASYNC_PREWRITE); 2383 } 2384 2385 static int 2386 et_newbuf_hdr(struct et_rxbuf_data *rbd, int buf_idx) 2387 { 2388 struct et_softc *sc; 2389 struct et_rxdesc *desc; 2390 struct et_rxbuf *rb; 2391 struct mbuf *m; 2392 bus_dma_segment_t segs[1]; 2393 bus_dmamap_t dmap; 2394 int nsegs; 2395 2396 MPASS(buf_idx < ET_RX_NDESC); 2397 MGETHDR(m, M_NOWAIT, MT_DATA); 2398 if (m == NULL) 2399 return (ENOBUFS); 2400 m->m_len = m->m_pkthdr.len = MHLEN; 2401 m_adj(m, ETHER_ALIGN); 2402 2403 sc = rbd->rbd_softc; 2404 rb = &rbd->rbd_buf[buf_idx]; 2405 2406 if (bus_dmamap_load_mbuf_sg(sc->sc_rx_mini_tag, sc->sc_rx_mini_sparemap, 2407 m, segs, &nsegs, 0) != 0) { 2408 m_freem(m); 2409 return (ENOBUFS); 2410 } 2411 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 2412 2413 if (rb->rb_mbuf != NULL) { 2414 bus_dmamap_sync(sc->sc_rx_mini_tag, rb->rb_dmap, 2415 BUS_DMASYNC_POSTREAD); 2416 bus_dmamap_unload(sc->sc_rx_mini_tag, rb->rb_dmap); 2417 } 2418 dmap = rb->rb_dmap; 2419 rb->rb_dmap = sc->sc_rx_mini_sparemap; 2420 sc->sc_rx_mini_sparemap = dmap; 2421 bus_dmamap_sync(sc->sc_rx_mini_tag, rb->rb_dmap, BUS_DMASYNC_PREREAD); 2422 2423 rb->rb_mbuf = m; 2424 desc = &rbd->rbd_ring->rr_desc[buf_idx]; 2425 desc->rd_addr_hi = htole32(ET_ADDR_HI(segs[0].ds_addr)); 2426 desc->rd_addr_lo = htole32(ET_ADDR_LO(segs[0].ds_addr)); 2427 desc->rd_ctrl = htole32(buf_idx & ET_RDCTRL_BUFIDX_MASK); 2428 bus_dmamap_sync(rbd->rbd_ring->rr_dtag, rbd->rbd_ring->rr_dmap, 2429 BUS_DMASYNC_PREWRITE); 2430 return (0); 2431 } 2432 2433 #define ET_SYSCTL_STAT_ADD32(c, h, n, p, d) \ 2434 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) 2435 #define ET_SYSCTL_STAT_ADD64(c, h, n, p, d) \ 2436 SYSCTL_ADD_UQUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d) 2437 2438 /* 2439 * Create sysctl tree 2440 */ 2441 static void 2442 et_add_sysctls(struct et_softc * sc) 2443 { 2444 struct sysctl_ctx_list *ctx; 2445 struct sysctl_oid_list *children, *parent; 2446 struct sysctl_oid *tree; 2447 struct et_hw_stats *stats; 2448 2449 ctx = device_get_sysctl_ctx(sc->dev); 2450 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)); 2451 2452 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_intr_npkts", 2453 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 2454 et_sysctl_rx_intr_npkts, "I", "RX IM, # packets per RX interrupt"); 2455 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_intr_delay", 2456 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 2457 et_sysctl_rx_intr_delay, "I", 2458 "RX IM, RX interrupt delay (x10 usec)"); 2459 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_intr_nsegs", 2460 CTLFLAG_RW, &sc->sc_tx_intr_nsegs, 0, 2461 "TX IM, # segments per TX interrupt"); 2462 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "timer", 2463 CTLFLAG_RW, &sc->sc_timer, 0, "TX timer"); 2464 2465 tree = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats", 2466 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "ET statistics"); 2467 parent = SYSCTL_CHILDREN(tree); 2468 2469 /* TX/RX statistics. */ 2470 stats = &sc->sc_stats; 2471 ET_SYSCTL_STAT_ADD64(ctx, parent, "frames_64", &stats->pkts_64, 2472 "0 to 64 bytes frames"); 2473 ET_SYSCTL_STAT_ADD64(ctx, parent, "frames_65_127", &stats->pkts_65, 2474 "65 to 127 bytes frames"); 2475 ET_SYSCTL_STAT_ADD64(ctx, parent, "frames_128_255", &stats->pkts_128, 2476 "128 to 255 bytes frames"); 2477 ET_SYSCTL_STAT_ADD64(ctx, parent, "frames_256_511", &stats->pkts_256, 2478 "256 to 511 bytes frames"); 2479 ET_SYSCTL_STAT_ADD64(ctx, parent, "frames_512_1023", &stats->pkts_512, 2480 "512 to 1023 bytes frames"); 2481 ET_SYSCTL_STAT_ADD64(ctx, parent, "frames_1024_1518", &stats->pkts_1024, 2482 "1024 to 1518 bytes frames"); 2483 ET_SYSCTL_STAT_ADD64(ctx, parent, "frames_1519_1522", &stats->pkts_1519, 2484 "1519 to 1522 bytes frames"); 2485 2486 /* RX statistics. */ 2487 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", 2488 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "RX MAC statistics"); 2489 children = SYSCTL_CHILDREN(tree); 2490 ET_SYSCTL_STAT_ADD64(ctx, children, "bytes", 2491 &stats->rx_bytes, "Good bytes"); 2492 ET_SYSCTL_STAT_ADD64(ctx, children, "frames", 2493 &stats->rx_frames, "Good frames"); 2494 ET_SYSCTL_STAT_ADD32(ctx, children, "crc_errs", 2495 &stats->rx_crcerrs, "CRC errors"); 2496 ET_SYSCTL_STAT_ADD64(ctx, children, "mcast_frames", 2497 &stats->rx_mcast, "Multicast frames"); 2498 ET_SYSCTL_STAT_ADD64(ctx, children, "bcast_frames", 2499 &stats->rx_bcast, "Broadcast frames"); 2500 ET_SYSCTL_STAT_ADD32(ctx, children, "control", 2501 &stats->rx_control, "Control frames"); 2502 ET_SYSCTL_STAT_ADD32(ctx, children, "pause", 2503 &stats->rx_pause, "Pause frames"); 2504 ET_SYSCTL_STAT_ADD32(ctx, children, "unknown_control", 2505 &stats->rx_unknown_control, "Unknown control frames"); 2506 ET_SYSCTL_STAT_ADD32(ctx, children, "align_errs", 2507 &stats->rx_alignerrs, "Alignment errors"); 2508 ET_SYSCTL_STAT_ADD32(ctx, children, "len_errs", 2509 &stats->rx_lenerrs, "Frames with length mismatched"); 2510 ET_SYSCTL_STAT_ADD32(ctx, children, "code_errs", 2511 &stats->rx_codeerrs, "Frames with code error"); 2512 ET_SYSCTL_STAT_ADD32(ctx, children, "cs_errs", 2513 &stats->rx_cserrs, "Frames with carrier sense error"); 2514 ET_SYSCTL_STAT_ADD32(ctx, children, "runts", 2515 &stats->rx_runts, "Too short frames"); 2516 ET_SYSCTL_STAT_ADD64(ctx, children, "oversize", 2517 &stats->rx_oversize, "Oversized frames"); 2518 ET_SYSCTL_STAT_ADD32(ctx, children, "fragments", 2519 &stats->rx_fragments, "Fragmented frames"); 2520 ET_SYSCTL_STAT_ADD32(ctx, children, "jabbers", 2521 &stats->rx_jabbers, "Frames with jabber error"); 2522 ET_SYSCTL_STAT_ADD32(ctx, children, "drop", 2523 &stats->rx_drop, "Dropped frames"); 2524 2525 /* TX statistics. */ 2526 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", 2527 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "TX MAC statistics"); 2528 children = SYSCTL_CHILDREN(tree); 2529 ET_SYSCTL_STAT_ADD64(ctx, children, "bytes", 2530 &stats->tx_bytes, "Good bytes"); 2531 ET_SYSCTL_STAT_ADD64(ctx, children, "frames", 2532 &stats->tx_frames, "Good frames"); 2533 ET_SYSCTL_STAT_ADD64(ctx, children, "mcast_frames", 2534 &stats->tx_mcast, "Multicast frames"); 2535 ET_SYSCTL_STAT_ADD64(ctx, children, "bcast_frames", 2536 &stats->tx_bcast, "Broadcast frames"); 2537 ET_SYSCTL_STAT_ADD32(ctx, children, "pause", 2538 &stats->tx_pause, "Pause frames"); 2539 ET_SYSCTL_STAT_ADD32(ctx, children, "deferred", 2540 &stats->tx_deferred, "Deferred frames"); 2541 ET_SYSCTL_STAT_ADD32(ctx, children, "excess_deferred", 2542 &stats->tx_excess_deferred, "Excessively deferred frames"); 2543 ET_SYSCTL_STAT_ADD32(ctx, children, "single_colls", 2544 &stats->tx_single_colls, "Single collisions"); 2545 ET_SYSCTL_STAT_ADD32(ctx, children, "multi_colls", 2546 &stats->tx_multi_colls, "Multiple collisions"); 2547 ET_SYSCTL_STAT_ADD32(ctx, children, "late_colls", 2548 &stats->tx_late_colls, "Late collisions"); 2549 ET_SYSCTL_STAT_ADD32(ctx, children, "excess_colls", 2550 &stats->tx_excess_colls, "Excess collisions"); 2551 ET_SYSCTL_STAT_ADD32(ctx, children, "total_colls", 2552 &stats->tx_total_colls, "Total collisions"); 2553 ET_SYSCTL_STAT_ADD32(ctx, children, "pause_honored", 2554 &stats->tx_pause_honored, "Honored pause frames"); 2555 ET_SYSCTL_STAT_ADD32(ctx, children, "drop", 2556 &stats->tx_drop, "Dropped frames"); 2557 ET_SYSCTL_STAT_ADD32(ctx, children, "jabbers", 2558 &stats->tx_jabbers, "Frames with jabber errors"); 2559 ET_SYSCTL_STAT_ADD32(ctx, children, "crc_errs", 2560 &stats->tx_crcerrs, "Frames with CRC errors"); 2561 ET_SYSCTL_STAT_ADD32(ctx, children, "control", 2562 &stats->tx_control, "Control frames"); 2563 ET_SYSCTL_STAT_ADD64(ctx, children, "oversize", 2564 &stats->tx_oversize, "Oversized frames"); 2565 ET_SYSCTL_STAT_ADD32(ctx, children, "undersize", 2566 &stats->tx_undersize, "Undersized frames"); 2567 ET_SYSCTL_STAT_ADD32(ctx, children, "fragments", 2568 &stats->tx_fragments, "Fragmented frames"); 2569 } 2570 2571 #undef ET_SYSCTL_STAT_ADD32 2572 #undef ET_SYSCTL_STAT_ADD64 2573 2574 static int 2575 et_sysctl_rx_intr_npkts(SYSCTL_HANDLER_ARGS) 2576 { 2577 struct et_softc *sc; 2578 struct ifnet *ifp; 2579 int error, v; 2580 2581 sc = arg1; 2582 ifp = sc->ifp; 2583 v = sc->sc_rx_intr_npkts; 2584 error = sysctl_handle_int(oidp, &v, 0, req); 2585 if (error || req->newptr == NULL) 2586 goto back; 2587 if (v <= 0) { 2588 error = EINVAL; 2589 goto back; 2590 } 2591 2592 if (sc->sc_rx_intr_npkts != v) { 2593 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2594 CSR_WRITE_4(sc, ET_RX_INTR_NPKTS, v); 2595 sc->sc_rx_intr_npkts = v; 2596 } 2597 back: 2598 return (error); 2599 } 2600 2601 static int 2602 et_sysctl_rx_intr_delay(SYSCTL_HANDLER_ARGS) 2603 { 2604 struct et_softc *sc; 2605 struct ifnet *ifp; 2606 int error, v; 2607 2608 sc = arg1; 2609 ifp = sc->ifp; 2610 v = sc->sc_rx_intr_delay; 2611 error = sysctl_handle_int(oidp, &v, 0, req); 2612 if (error || req->newptr == NULL) 2613 goto back; 2614 if (v <= 0) { 2615 error = EINVAL; 2616 goto back; 2617 } 2618 2619 if (sc->sc_rx_intr_delay != v) { 2620 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2621 CSR_WRITE_4(sc, ET_RX_INTR_DELAY, v); 2622 sc->sc_rx_intr_delay = v; 2623 } 2624 back: 2625 return (error); 2626 } 2627 2628 static void 2629 et_stats_update(struct et_softc *sc) 2630 { 2631 struct et_hw_stats *stats; 2632 2633 stats = &sc->sc_stats; 2634 stats->pkts_64 += CSR_READ_4(sc, ET_STAT_PKTS_64); 2635 stats->pkts_65 += CSR_READ_4(sc, ET_STAT_PKTS_65_127); 2636 stats->pkts_128 += CSR_READ_4(sc, ET_STAT_PKTS_128_255); 2637 stats->pkts_256 += CSR_READ_4(sc, ET_STAT_PKTS_256_511); 2638 stats->pkts_512 += CSR_READ_4(sc, ET_STAT_PKTS_512_1023); 2639 stats->pkts_1024 += CSR_READ_4(sc, ET_STAT_PKTS_1024_1518); 2640 stats->pkts_1519 += CSR_READ_4(sc, ET_STAT_PKTS_1519_1522); 2641 2642 stats->rx_bytes += CSR_READ_4(sc, ET_STAT_RX_BYTES); 2643 stats->rx_frames += CSR_READ_4(sc, ET_STAT_RX_FRAMES); 2644 stats->rx_crcerrs += CSR_READ_4(sc, ET_STAT_RX_CRC_ERR); 2645 stats->rx_mcast += CSR_READ_4(sc, ET_STAT_RX_MCAST); 2646 stats->rx_bcast += CSR_READ_4(sc, ET_STAT_RX_BCAST); 2647 stats->rx_control += CSR_READ_4(sc, ET_STAT_RX_CTL); 2648 stats->rx_pause += CSR_READ_4(sc, ET_STAT_RX_PAUSE); 2649 stats->rx_unknown_control += CSR_READ_4(sc, ET_STAT_RX_UNKNOWN_CTL); 2650 stats->rx_alignerrs += CSR_READ_4(sc, ET_STAT_RX_ALIGN_ERR); 2651 stats->rx_lenerrs += CSR_READ_4(sc, ET_STAT_RX_LEN_ERR); 2652 stats->rx_codeerrs += CSR_READ_4(sc, ET_STAT_RX_CODE_ERR); 2653 stats->rx_cserrs += CSR_READ_4(sc, ET_STAT_RX_CS_ERR); 2654 stats->rx_runts += CSR_READ_4(sc, ET_STAT_RX_RUNT); 2655 stats->rx_oversize += CSR_READ_4(sc, ET_STAT_RX_OVERSIZE); 2656 stats->rx_fragments += CSR_READ_4(sc, ET_STAT_RX_FRAG); 2657 stats->rx_jabbers += CSR_READ_4(sc, ET_STAT_RX_JABBER); 2658 stats->rx_drop += CSR_READ_4(sc, ET_STAT_RX_DROP); 2659 2660 stats->tx_bytes += CSR_READ_4(sc, ET_STAT_TX_BYTES); 2661 stats->tx_frames += CSR_READ_4(sc, ET_STAT_TX_FRAMES); 2662 stats->tx_mcast += CSR_READ_4(sc, ET_STAT_TX_MCAST); 2663 stats->tx_bcast += CSR_READ_4(sc, ET_STAT_TX_BCAST); 2664 stats->tx_pause += CSR_READ_4(sc, ET_STAT_TX_PAUSE); 2665 stats->tx_deferred += CSR_READ_4(sc, ET_STAT_TX_DEFER); 2666 stats->tx_excess_deferred += CSR_READ_4(sc, ET_STAT_TX_EXCESS_DEFER); 2667 stats->tx_single_colls += CSR_READ_4(sc, ET_STAT_TX_SINGLE_COL); 2668 stats->tx_multi_colls += CSR_READ_4(sc, ET_STAT_TX_MULTI_COL); 2669 stats->tx_late_colls += CSR_READ_4(sc, ET_STAT_TX_LATE_COL); 2670 stats->tx_excess_colls += CSR_READ_4(sc, ET_STAT_TX_EXCESS_COL); 2671 stats->tx_total_colls += CSR_READ_4(sc, ET_STAT_TX_TOTAL_COL); 2672 stats->tx_pause_honored += CSR_READ_4(sc, ET_STAT_TX_PAUSE_HONOR); 2673 stats->tx_drop += CSR_READ_4(sc, ET_STAT_TX_DROP); 2674 stats->tx_jabbers += CSR_READ_4(sc, ET_STAT_TX_JABBER); 2675 stats->tx_crcerrs += CSR_READ_4(sc, ET_STAT_TX_CRC_ERR); 2676 stats->tx_control += CSR_READ_4(sc, ET_STAT_TX_CTL); 2677 stats->tx_oversize += CSR_READ_4(sc, ET_STAT_TX_OVERSIZE); 2678 stats->tx_undersize += CSR_READ_4(sc, ET_STAT_TX_UNDERSIZE); 2679 stats->tx_fragments += CSR_READ_4(sc, ET_STAT_TX_FRAG); 2680 } 2681 2682 static uint64_t 2683 et_get_counter(struct ifnet *ifp, ift_counter cnt) 2684 { 2685 struct et_softc *sc; 2686 struct et_hw_stats *stats; 2687 2688 sc = if_getsoftc(ifp); 2689 stats = &sc->sc_stats; 2690 2691 switch (cnt) { 2692 case IFCOUNTER_OPACKETS: 2693 return (stats->tx_frames); 2694 case IFCOUNTER_COLLISIONS: 2695 return (stats->tx_total_colls); 2696 case IFCOUNTER_OERRORS: 2697 return (stats->tx_drop + stats->tx_jabbers + 2698 stats->tx_crcerrs + stats->tx_excess_deferred + 2699 stats->tx_late_colls); 2700 case IFCOUNTER_IPACKETS: 2701 return (stats->rx_frames); 2702 case IFCOUNTER_IERRORS: 2703 return (stats->rx_crcerrs + stats->rx_alignerrs + 2704 stats->rx_lenerrs + stats->rx_codeerrs + stats->rx_cserrs + 2705 stats->rx_runts + stats->rx_jabbers + stats->rx_drop); 2706 default: 2707 return (if_get_counter_default(ifp, cnt)); 2708 } 2709 } 2710 2711 static int 2712 et_suspend(device_t dev) 2713 { 2714 struct et_softc *sc; 2715 uint32_t pmcfg; 2716 2717 sc = device_get_softc(dev); 2718 ET_LOCK(sc); 2719 if ((sc->ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2720 et_stop(sc); 2721 /* Diable all clocks and put PHY into COMA. */ 2722 pmcfg = CSR_READ_4(sc, ET_PM); 2723 pmcfg &= ~(EM_PM_GIGEPHY_ENB | ET_PM_SYSCLK_GATE | ET_PM_TXCLK_GATE | 2724 ET_PM_RXCLK_GATE); 2725 pmcfg |= ET_PM_PHY_SW_COMA; 2726 CSR_WRITE_4(sc, ET_PM, pmcfg); 2727 ET_UNLOCK(sc); 2728 return (0); 2729 } 2730 2731 static int 2732 et_resume(device_t dev) 2733 { 2734 struct et_softc *sc; 2735 uint32_t pmcfg; 2736 2737 sc = device_get_softc(dev); 2738 ET_LOCK(sc); 2739 /* Take PHY out of COMA and enable clocks. */ 2740 pmcfg = ET_PM_SYSCLK_GATE | ET_PM_TXCLK_GATE | ET_PM_RXCLK_GATE; 2741 if ((sc->sc_flags & ET_FLAG_FASTETHER) == 0) 2742 pmcfg |= EM_PM_GIGEPHY_ENB; 2743 CSR_WRITE_4(sc, ET_PM, pmcfg); 2744 if ((sc->ifp->if_flags & IFF_UP) != 0) 2745 et_init_locked(sc); 2746 ET_UNLOCK(sc); 2747 return (0); 2748 }
Cache object: 0e640209817ac4e445abcd295d718219
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