Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/dev/et/if_etreg.h
Version:
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1 /*- 2 * SPDX-License-Identifier: BSD-3-Clause 3 * 4 * Copyright (c) 2007 Sepherosa Ziehau. All rights reserved. 5 * 6 * This code is derived from software contributed to The DragonFly Project 7 * by Sepherosa Ziehau <sepherosa@gmail.com> 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in 17 * the documentation and/or other materials provided with the 18 * distribution. 19 * 3. Neither the name of The DragonFly Project nor the names of its 20 * contributors may be used to endorse or promote products derived 21 * from this software without specific, prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 24 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 25 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 26 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 27 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 28 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 29 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 30 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 31 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 33 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * $DragonFly: src/sys/dev/netif/et/if_etreg.h,v 1.3 2007/10/23 14:28:42 sephe Exp $ 37 * $FreeBSD$ 38 */ 39 40 #ifndef _IF_ETREG_H 41 #define _IF_ETREG_H 42 43 #define ET_MEM_TXSIZE_EX 182 44 #define ET_MEM_RXSIZE_MIN 608 45 #define ET_MEM_RXSIZE_DEFAULT 11216 46 #define ET_MEM_SIZE 16384 47 #define ET_MEM_UNIT 16 48 49 /* 50 * PCI registers 51 * 52 * ET_PCIV_ACK_LATENCY_{128,256} are from 53 * PCI EXPRESS BASE SPECIFICATION, REV. 1.0a, Table 3-5 54 * 55 * ET_PCIV_REPLAY_TIMER_{128,256} are from 56 * PCI EXPRESS BASE SPECIFICATION, REV. 1.0a, Table 3-4 57 */ 58 #define ET_PCIR_DEVICE_CAPS 0x4C 59 #define ET_PCIM_DEVICE_CAPS_MAX_PLSZ 0x7 /* Max playload size */ 60 #define ET_PCIV_DEVICE_CAPS_PLSZ_128 0x0 61 #define ET_PCIV_DEVICE_CAPS_PLSZ_256 0x1 62 63 #define ET_PCIR_DEVICE_CTRL 0x50 64 #define ET_PCIM_DEVICE_CTRL_MAX_RRSZ 0x7000 /* Max read request size */ 65 #define ET_PCIV_DEVICE_CTRL_RRSZ_2K 0x4000 66 67 #define ET_PCIR_MAC_ADDR0 0xA4 68 #define ET_PCIR_MAC_ADDR1 0xA8 69 70 #define ET_PCIR_EEPROM_STATUS 0xB2 /* XXX undocumented */ 71 #define ET_PCIM_EEPROM_STATUS_ERROR 0x4C 72 73 #define ET_PCIR_ACK_LATENCY 0xC0 74 #define ET_PCIV_ACK_LATENCY_128 237 75 #define ET_PCIV_ACK_LATENCY_256 416 76 77 #define ET_PCIR_REPLAY_TIMER 0xC2 78 #define ET_REPLAY_TIMER_RX_L0S_ADJ 250 /* XXX inferred from default */ 79 #define ET_PCIV_REPLAY_TIMER_128 (711 + ET_REPLAY_TIMER_RX_L0S_ADJ) 80 #define ET_PCIV_REPLAY_TIMER_256 (1248 + ET_REPLAY_TIMER_RX_L0S_ADJ) 81 82 #define ET_PCIR_L0S_L1_LATENCY 0xCF 83 84 /* 85 * CSR 86 */ 87 #define ET_TXQUEUE_START 0x0000 88 #define ET_TXQUEUE_END 0x0004 89 #define ET_RXQUEUE_START 0x0008 90 #define ET_RXQUEUE_END 0x000C 91 #define ET_QUEUE_ADDR(addr) (((addr) / ET_MEM_UNIT) - 1) 92 #define ET_QUEUE_ADDR_START 0 93 #define ET_QUEUE_ADDR_END ET_QUEUE_ADDR(ET_MEM_SIZE) 94 95 #define ET_PM 0x0010 96 #define EM_PM_GIGEPHY_ENB 0x00000001 97 #define ET_PM_SYSCLK_GATE 0x00000008 98 #define ET_PM_TXCLK_GATE 0x00000010 99 #define ET_PM_RXCLK_GATE 0x00000020 100 #define ET_PM_PHY_SW_COMA 0x00000040 101 102 #define ET_INTR_STATUS 0x0018 103 #define ET_INTR_MASK 0x001C 104 105 #define ET_SWRST 0x0028 106 #define ET_SWRST_TXDMA 0x00000001 107 #define ET_SWRST_RXDMA 0x00000002 108 #define ET_SWRST_TXMAC 0x00000004 109 #define ET_SWRST_RXMAC 0x00000008 110 #define ET_SWRST_MAC 0x00000010 111 #define ET_SWRST_MAC_STAT 0x00000020 112 #define ET_SWRST_MMC 0x00000040 113 #define ET_SWRST_SELFCLR_DISABLE 0x80000000 114 115 #define ET_MSI_CFG 0x0030 116 117 #define ET_LOOPBACK 0x0034 118 119 #define ET_TIMER 0x0038 120 121 #define ET_TXDMA_CTRL 0x1000 122 #define ET_TXDMA_CTRL_HALT 0x00000001 123 #define ET_TXDMA_CTRL_CACHE_THR_MASK 0x000000F0 124 #define ET_TXDMA_CTRL_SINGLE_EPKT 0x00000100 /* ??? */ 125 126 #define ET_TX_RING_HI 0x1004 127 #define ET_TX_RING_LO 0x1008 128 #define ET_TX_RING_CNT 0x100C 129 130 #define ET_TX_STATUS_HI 0x101C 131 #define ET_TX_STATUS_LO 0x1020 132 133 #define ET_TX_READY_POS 0x1024 134 #define ET_TX_READY_POS_INDEX_MASK 0x000003FF 135 #define ET_TX_READY_POS_WRAP 0x00000400 136 137 #define ET_TX_DONE_POS 0x1060 138 #define ET_TX_DONE_POS_INDEX_MASK 0x0000003FF 139 #define ET_TX_DONE_POS_WRAP 0x000000400 140 141 #define ET_RXDMA_CTRL 0x2000 142 #define ET_RXDMA_CTRL_HALT 0x00000001 143 #define ET_RXDMA_CTRL_RING0_SIZE_MASK 0x00000300 144 #define ET_RXDMA_CTRL_RING0_128 0x00000000 /* 127 */ 145 #define ET_RXDMA_CTRL_RING0_256 0x00000100 /* 255 */ 146 #define ET_RXDMA_CTRL_RING0_512 0x00000200 /* 511 */ 147 #define ET_RXDMA_CTRL_RING0_1024 0x00000300 /* 1023 */ 148 #define ET_RXDMA_CTRL_RING0_ENABLE 0x00000400 149 #define ET_RXDMA_CTRL_RING1_SIZE_MASK 0x00001800 150 #define ET_RXDMA_CTRL_RING1_2048 0x00000000 /* 2047 */ 151 #define ET_RXDMA_CTRL_RING1_4096 0x00000800 /* 4095 */ 152 #define ET_RXDMA_CTRL_RING1_8192 0x00001000 /* 8191 */ 153 #define ET_RXDMA_CTRL_RING1_16384 0x00001800 /* 16383 (9022?) */ 154 #define ET_RXDMA_CTRL_RING1_ENABLE 0x00002000 155 #define ET_RXDMA_CTRL_HALTED 0x00020000 156 157 #define ET_RX_STATUS_LO 0x2004 158 #define ET_RX_STATUS_HI 0x2008 159 160 #define ET_RX_INTR_NPKTS 0x200C 161 #define ET_RX_INTR_DELAY 0x2010 162 163 #define ET_RXSTAT_LO 0x2020 164 #define ET_RXSTAT_HI 0x2024 165 #define ET_RXSTAT_CNT 0x2028 166 167 #define ET_RXSTAT_POS 0x2030 168 #define ET_RXSTAT_POS_INDEX_MASK 0x00000FFF 169 #define ET_RXSTAT_POS_WRAP 0x00001000 170 171 #define ET_RXSTAT_MINCNT 0x2038 172 173 #define ET_RX_RING0_LO 0x203C 174 #define ET_RX_RING0_HI 0x2040 175 #define ET_RX_RING0_CNT 0x2044 176 177 #define ET_RX_RING0_POS 0x204C 178 #define ET_RX_RING0_POS_INDEX_MASK 0x000003FF 179 #define ET_RX_RING0_POS_WRAP 0x00000400 180 181 #define ET_RX_RING0_MINCNT 0x2054 182 183 #define ET_RX_RING1_LO 0x2058 184 #define ET_RX_RING1_HI 0x205C 185 #define ET_RX_RING1_CNT 0x2060 186 187 #define ET_RX_RING1_POS 0x2068 188 #define ET_RX_RING1_POS_INDEX 0x000003FF 189 #define ET_RX_RING1_POS_WRAP 0x00000400 190 191 #define ET_RX_RING1_MINCNT 0x2070 192 193 #define ET_TXMAC_CTRL 0x3000 194 #define ET_TXMAC_CTRL_ENABLE 0x00000001 195 #define ET_TXMAC_CTRL_FC_DISABLE 0x00000008 196 197 #define ET_TXMAC_FLOWCTRL 0x3010 198 #define ET_TXMAC_FLOWCTRL_CFPT_MASK 0x0000FFFF 199 #define ET_TXMAC_FLOWCTRL_CFEP_MASK 0xFFFF0000 200 #define ET_TXMAC_FLOWCTRL_CFPT_SHIFT 0 201 202 #define ET_TXMAC_BP_CTRL 0x3020 203 #define ET_TXMAC_BP_CTRL_XONXOFF 0x00000001 204 #define ET_TXMAC_BP_CTRL_REQ 0x00000002 205 206 #define ET_RXMAC_CTRL 0x4000 207 #define ET_RXMAC_CTRL_ENABLE 0x00000001 208 #define ET_RXMAC_CTRL_NO_PKTFILT 0x00000004 209 #define ET_RXMAC_CTRL_WOL_DISABLE 0x00000008 210 211 #define ET_WOL_CRC 0x4004 212 #define ET_WOL_SA_LO 0x4010 213 #define ET_WOL_SA_HI 0x4014 214 #define ET_WOL_MASK 0x4018 215 216 #define ET_UCAST_FILTADDR1 0x4068 217 #define ET_UCAST_FILTADDR2 0x406C 218 #define ET_UCAST_FILTADDR3 0x4070 219 220 #define ET_MULTI_HASH 0x4074 221 222 #define ET_PKTFILT 0x4084 223 #define ET_PKTFILT_BCAST 0x00000001 224 #define ET_PKTFILT_MCAST 0x00000002 225 #define ET_PKTFILT_UCAST 0x00000004 226 #define ET_PKTFILT_FRAG 0x00000008 227 #define ET_PKTFILT_MINLEN_MASK 0x007F0000 228 #define ET_PKTFILT_MINLEN_SHIFT 16 229 230 #define ET_RXMAC_MC_SEGSZ 0x4088 231 #define ET_RXMAC_MC_SEGSZ_ENABLE 0x00000001 232 #define ET_RXMAC_MC_SEGSZ_FC 0x00000002 233 #define ET_RXMAC_MC_SEGSZ_MAX_MASK 0x000003FC 234 #define ET_RXMAC_SEGSZ(segsz) ((segsz) / ET_MEM_UNIT) 235 #define ET_RXMAC_CUT_THRU_FRMLEN 8074 236 237 #define ET_RXMAC_MC_WATERMARK 0x408C 238 #define ET_RXMAC_SPACE_AVL 0x4094 239 240 #define ET_RXMAC_MGT 0x4098 241 #define ET_RXMAC_MGT_PASS_ECRC 0x00000010 242 #define ET_RXMAC_MGT_PASS_ELEN 0x00000020 243 #define ET_RXMAC_MGT_PASS_ETRUNC 0x00010000 244 #define ET_RXMAC_MGT_CHECK_PKT 0x00020000 245 246 #define ET_MAC_CFG1 0x5000 247 #define ET_MAC_CFG1_TXEN 0x00000001 248 #define ET_MAC_CFG1_SYNC_TXEN 0x00000002 249 #define ET_MAC_CFG1_RXEN 0x00000004 250 #define ET_MAC_CFG1_SYNC_RXEN 0x00000008 251 #define ET_MAC_CFG1_TXFLOW 0x00000010 252 #define ET_MAC_CFG1_RXFLOW 0x00000020 253 #define ET_MAC_CFG1_LOOPBACK 0x00000100 254 #define ET_MAC_CFG1_RST_TXFUNC 0x00010000 255 #define ET_MAC_CFG1_RST_RXFUNC 0x00020000 256 #define ET_MAC_CFG1_RST_TXMC 0x00040000 257 #define ET_MAC_CFG1_RST_RXMC 0x00080000 258 #define ET_MAC_CFG1_SIM_RST 0x40000000 259 #define ET_MAC_CFG1_SOFT_RST 0x80000000 260 261 #define ET_MAC_CFG2 0x5004 262 #define ET_MAC_CFG2_FDX 0x00000001 263 #define ET_MAC_CFG2_CRC 0x00000002 264 #define ET_MAC_CFG2_PADCRC 0x00000004 265 #define ET_MAC_CFG2_LENCHK 0x00000010 266 #define ET_MAC_CFG2_BIGFRM 0x00000020 267 #define ET_MAC_CFG2_MODE_MII 0x00000100 268 #define ET_MAC_CFG2_MODE_GMII 0x00000200 269 #define ET_MAC_CFG2_PREAMBLE_LEN_MASK 0x0000F000 270 #define ET_MAC_CFG2_PREAMBLE_LEN_SHIFT 12 271 272 #define ET_IPG 0x5008 273 #define ET_IPG_B2B_MASK 0x0000007F 274 #define ET_IPG_MINIFG_MASK 0x0000FF00 275 #define ET_IPG_NONB2B_2_MASK 0x007F0000 276 #define ET_IPG_NONB2B_1_MASK 0x7F000000 277 #define ET_IPG_B2B_SHIFT 0 278 #define ET_IPG_MINIFG_SHIFT 8 279 #define ET_IPG_NONB2B_2_SHIFT 16 280 #define ET_IPG_NONB2B_1_SHIFT 24 281 282 #define ET_MAC_HDX 0x500C 283 #define ET_MAC_HDX_COLLWIN_MASK 0x000003FF 284 #define ET_MAC_HDX_REXMIT_MAX_MASK 0x0000F000 285 #define ET_MAC_HDX_EXC_DEFER 0x00010000 286 #define ET_MAC_HDX_NOBACKOFF 0x00020000 287 #define ET_MAC_HDX_BP_NOBACKOFF 0x00040000 288 #define ET_MAC_HDX_ALT_BEB 0x00080000 289 #define ET_MAC_HDX_ALT_BEB_TRUNC_MASK 0x00F00000 290 #define ET_MAC_HDX_COLLWIN_SHIFT 0 291 #define ET_MAC_HDX_REXMIT_MAX_SHIFT 12 292 #define ET_MAC_HDX_ALT_BEB_TRUNC_SHIFT 20 293 294 #define ET_MAX_FRMLEN 0x5010 295 296 #define ET_MII_CFG 0x5020 297 #define ET_MII_CFG_CLKRST 0x00000007 298 #define ET_MII_CFG_PREAMBLE_SUP 0x00000010 299 #define ET_MII_CFG_SCAN_AUTOINC 0x00000020 300 #define ET_MII_CFG_RST 0x80000000 301 302 #define ET_MII_CMD 0x5024 303 #define ET_MII_CMD_READ 0x00000001 304 305 #define ET_MII_ADDR 0x5028 306 #define ET_MII_ADDR_REG_MASK 0x0000001F 307 #define ET_MII_ADDR_PHY_MASK 0x00001F00 308 #define ET_MII_ADDR_REG_SHIFT 0 309 #define ET_MII_ADDR_PHY_SHIFT 8 310 311 #define ET_MII_CTRL 0x502C 312 #define ET_MII_CTRL_VALUE_MASK 0x0000FFFF 313 #define ET_MII_CTRL_VALUE_SHIFT 0 314 315 #define ET_MII_STAT 0x5030 316 #define ET_MII_STAT_VALUE_MASK 0x0000FFFF 317 318 #define ET_MII_IND 0x5034 319 #define ET_MII_IND_BUSY 0x00000001 320 #define ET_MII_IND_INVALID 0x00000004 321 322 #define ET_MAC_CTRL 0x5038 323 #define ET_MAC_CTRL_MODE_MII 0x01000000 324 #define ET_MAC_CTRL_LHDX 0x02000000 325 #define ET_MAC_CTRL_GHDX 0x04000000 326 327 #define ET_MAC_ADDR1 0x5040 328 #define ET_MAC_ADDR2 0x5044 329 330 /* MAC statistics counters. */ 331 #define ET_STAT_PKTS_64 0x6080 332 #define ET_STAT_PKTS_65_127 0x6084 333 #define ET_STAT_PKTS_128_255 0x6088 334 #define ET_STAT_PKTS_256_511 0x608C 335 #define ET_STAT_PKTS_512_1023 0x6090 336 #define ET_STAT_PKTS_1024_1518 0x6094 337 #define ET_STAT_PKTS_1519_1522 0x6098 338 #define ET_STAT_RX_BYTES 0x609C 339 #define ET_STAT_RX_FRAMES 0x60A0 340 #define ET_STAT_RX_CRC_ERR 0x60A4 341 #define ET_STAT_RX_MCAST 0x60A8 342 #define ET_STAT_RX_BCAST 0x60AC 343 #define ET_STAT_RX_CTL 0x60B0 344 #define ET_STAT_RX_PAUSE 0x60B4 345 #define ET_STAT_RX_UNKNOWN_CTL 0x60B8 346 #define ET_STAT_RX_ALIGN_ERR 0x60BC 347 #define ET_STAT_RX_LEN_ERR 0x60C0 348 #define ET_STAT_RX_CODE_ERR 0x60C4 349 #define ET_STAT_RX_CS_ERR 0x60C8 350 #define ET_STAT_RX_RUNT 0x60CC 351 #define ET_STAT_RX_OVERSIZE 0x60D0 352 #define ET_STAT_RX_FRAG 0x60D4 353 #define ET_STAT_RX_JABBER 0x60D8 354 #define ET_STAT_RX_DROP 0x60DC 355 #define ET_STAT_TX_BYTES 0x60E0 356 #define ET_STAT_TX_FRAMES 0x60E4 357 #define ET_STAT_TX_MCAST 0x60E8 358 #define ET_STAT_TX_BCAST 0x60EC 359 #define ET_STAT_TX_PAUSE 0x60F0 360 #define ET_STAT_TX_DEFER 0x60F4 361 #define ET_STAT_TX_EXCESS_DEFER 0x60F8 362 #define ET_STAT_TX_SINGLE_COL 0x60FC 363 #define ET_STAT_TX_MULTI_COL 0x6100 364 #define ET_STAT_TX_LATE_COL 0x6104 365 #define ET_STAT_TX_EXCESS_COL 0x6108 366 #define ET_STAT_TX_TOTAL_COL 0x610C 367 #define ET_STAT_TX_PAUSE_HONOR 0x6110 368 #define ET_STAT_TX_DROP 0x6114 369 #define ET_STAT_TX_JABBER 0x6118 370 #define ET_STAT_TX_CRC_ERR 0x611C 371 #define ET_STAT_TX_CTL 0x6120 372 #define ET_STAT_TX_OVERSIZE 0x6124 373 #define ET_STAT_TX_UNDERSIZE 0x6128 374 #define ET_STAT_TX_FRAG 0x612C 375 376 #define ET_MMC_CTRL 0x7000 377 #define ET_MMC_CTRL_ENABLE 0x00000001 378 #define ET_MMC_CTRL_ARB_DISABLE 0x00000002 379 #define ET_MMC_CTRL_RXMAC_DISABLE 0x00000004 380 #define ET_MMC_CTRL_TXMAC_DISABLE 0x00000008 381 #define ET_MMC_CTRL_TXDMA_DISABLE 0x00000010 382 #define ET_MMC_CTRL_RXDMA_DISABLE 0x00000020 383 #define ET_MMC_CTRL_FORCE_CE 0x00000040 384 385 /* 386 * Interrupts 387 */ 388 #define ET_INTR_TXDMA 0x00000008 389 #define ET_INTR_TXDMA_ERROR 0x00000010 390 #define ET_INTR_RXDMA 0x00000020 391 #define ET_INTR_RXRING0_LOW 0x00000040 392 #define ET_INTR_RXRING1_LOW 0x00000080 393 #define ET_INTR_RXSTAT_LOW 0x00000100 394 #define ET_INTR_RXDMA_ERROR 0x00000200 395 #define ET_INTR_TIMER 0x00004000 396 #define ET_INTR_WOL 0x00008000 397 #define ET_INTR_PHY 0x00010000 398 #define ET_INTR_TXMAC 0x00020000 399 #define ET_INTR_RXMAC 0x00040000 400 #define ET_INTR_MAC_STATS 0x00080000 401 #define ET_INTR_SLAVE_TO 0x00100000 402 403 #define ET_INTRS \ 404 (ET_INTR_TXDMA | ET_INTR_RXDMA | ET_INTR_TIMER | \ 405 ET_INTR_TXDMA_ERROR | ET_INTR_RXDMA_ERROR) 406 407 /* 408 * RX ring position uses same layout 409 */ 410 #define ET_RX_RING_POS_INDEX_MASK 0x000003FF 411 #define ET_RX_RING_POS_WRAP 0x00000400 412 413 /* 414 * PCI IDs 415 */ 416 #define PCI_VENDOR_LUCENT 0x11C1 417 #define PCI_PRODUCT_LUCENT_ET1310 0xED00 /* ET1310 10/100/1000M Ethernet */ 418 #define PCI_PRODUCT_LUCENT_ET1310_FAST 0xED01 /* ET1310 10/100M Ethernet */ 419 420 #endif /* !_IF_ETREG_H */
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