The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/dev/ex/if_exreg.h

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    1 /*-
    2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
    3  *
    4  * Copyright (c) 1996, Javier Martín Rueda (jmrueda@diatel.upm.es)
    5  * All rights reserved.
    6  *
    7  * Redistribution and use in source and binary forms, with or without
    8  * modification, are permitted provided that the following conditions
    9  * are met:
   10  * 1. Redistributions of source code must retain the above copyright
   11  *    notice unmodified, this list of conditions, and the following
   12  *    disclaimer.
   13  * 2. Redistributions in binary form must reproduce the above copyright
   14  *    notice, this list of conditions and the following disclaimer in the
   15  *    documentation and/or other materials provided with the distribution.
   16  *
   17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   18  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   19  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   20  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   21  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   22  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   23  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   24  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   25  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   26  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   27  * SUCH DAMAGE.
   28  *
   29  * $FreeBSD: head/sys/dev/ex/if_exreg.h 326255 2017-11-27 14:52:40Z pfg $
   30  */
   31 
   32 /*
   33  * Intel EtherExpress Pro/10 Ethernet driver
   34  */
   35 
   36 /*
   37  * Several constants.
   38  */
   39 
   40 #define CARD_TYPE_EX_10         1
   41 #define CARD_TYPE_EX_10_PLUS    2
   42 
   43 /* Length of an ethernet address. */
   44 #define ETHER_ADDR_LEN  6
   45 /* Default RAM size in board. */
   46 #define CARD_RAM_SIZE   0x8000
   47 /* Number of I/O ports used. */
   48 #define EX_IOSIZE       16
   49 
   50 /*
   51  * Intel EtherExpress Pro (i82595 based) registers
   52  */
   53 
   54 /* Common registers to all banks. */
   55 
   56 #define CMD_REG         0
   57 #define REG1            1
   58 #define REG2            2
   59 #define REG3            3
   60 #define REG4            4
   61 #define REG5            5
   62 #define REG6            6
   63 #define REG7            7
   64 #define REG8            8
   65 #define REG9            9
   66 #define REG10           10
   67 #define REG11           11
   68 #define REG12           12
   69 #define REG13           13
   70 #define REG14           14
   71 #define REG15           15
   72 
   73 /* Definitions for command register (CMD_REG). */
   74 
   75 #define Switch_Bank_CMD 0
   76 #define MC_Setup_CMD    3
   77 #define Transmit_CMD    4
   78 #define Diagnose_CMD    7
   79 #define Rcv_Enable_CMD  8
   80 #define Rcv_Stop        11
   81 #define Reset_CMD       14
   82 #define Resume_XMT_List_CMD 28
   83 #define Sel_Reset_CMD   30
   84 #define Abort           0x20
   85 #define Bank0_Sel       0x00
   86 #define Bank1_Sel       0x40
   87 #define Bank2_Sel       0x80
   88 
   89 /* Bank 0 specific registers. */
   90 
   91 #define STATUS_REG      1
   92 #define ID_REG          2
   93 #define Id_Mask         0x2c
   94 #define Id_Sig          0x24
   95 #define Counter_bits    0xc0
   96 #define MASK_REG        3
   97 #define Exec_Int        0x08
   98 #define Tx_Int          0x04
   99 #define Rx_Int          0x02
  100 #define Rx_Stp_Int      0x01
  101 #define All_Int         0x0f
  102 #define RCV_BAR         4
  103 #define RCV_BAR_Lo      4
  104 #define RCV_BAR_Hi      5
  105 #define RCV_STOP_REG    6
  106 #define XMT_BAR         10
  107 #define HOST_ADDR_REG   12      /* 16-bit register */
  108 #define IO_PORT_REG     14      /* 16-bit register */
  109 
  110 /* Bank 1 specific registers. */
  111 
  112 #define TriST_INT               0x80
  113 #define INT_NO_REG              2
  114 #define RCV_LOWER_LIMIT_REG     8
  115 #define RCV_UPPER_LIMIT_REG     9
  116 #define XMT_LOWER_LIMIT_REG     10
  117 #define XMT_UPPER_LIMIT_REG     11
  118 
  119 /* Bank 2 specific registers. */
  120 
  121 #define Disc_Bad_Fr             0x80
  122 #define Tx_Chn_ErStp            0x40
  123 #define Tx_Chn_Int_Md           0x20
  124 #define Multi_IA                0x20
  125 #define No_SA_Ins               0x10
  126 #define RX_CRC_InMem            0x04
  127 #define Promisc_Mode            0x01
  128 #define BNC_bit                 0x20
  129 #define TPE_bit                 0x04
  130 #define I_ADDR_REG0             4
  131 #define EEPROM_REG              10
  132 #define Trnoff_Enable           0x10
  133 
  134 /* EEPROM memory positions (16-bit wide). */
  135 
  136 #define EE_W0                   0x00
  137 # define EE_W0_PNP              0x0001
  138 # define EE_W0_BUS16            0x0004
  139 # define EE_W0_FLASH_ADDR_MASK  0x0038
  140 # define EE_W0_FLASH_ADDR_SHIFT 3
  141 # define EE_W0_AUTO_IO          0x0040
  142 # define EE_W0_FLASH            0x0100
  143 # define EE_W0_AUTO_NEG         0x0200
  144 # define EE_W0_IO_MASK          0xFC00
  145 # define EE_W0_IO_SHIFT         10
  146 
  147 #define EE_IRQ_No               1
  148 #define IRQ_No_Mask             0x07
  149 
  150 #define EE_W1                   0x01
  151 # define EE_W1_INT_SEL          0x0007
  152 # define EE_W1_NO_LINK_INT      0x0008  /* Link Integrity Off           */
  153 # define EE_W1_NO_POLARITY      0x0010  /* Polarity Correction Off      */
  154 # define EE_W1_TPE_AUI          0x0020  /* 1 = TPE, 0 = AUI             */
  155 # define EE_W1_NO_JABBER_PREV   0x0040  /* Jabber prevention Off        */
  156 # define EE_W1_NO_AUTO_SELECT   0x0080  /* Auto Port Selection Off      */
  157 # define EE_W1_SMOUT            0x0100  /* SMout Pin Control 0= Input   */
  158 # define EE_W1_PROM             0x0200  /* Flash = 0, PROM = 1          */
  159 # define EE_W1_ALT_READY        0x2000  /* Alternate Ready, 0=normal    */
  160 # define EE_W1_FULL_DUPLEX      0x8000
  161 
  162 #define EE_W2                   0x02
  163 #define EE_W3                   0x03
  164 #define EE_W4                   0x04
  165 
  166 #define EE_Eth_Addr_Lo          2
  167 #define EE_Eth_Addr_Mid         3
  168 #define EE_Eth_Addr_Hi          4
  169 
  170 #define EE_W5                   0x05
  171 # define EE_W5_BNC_TPE          0x0001  /* 0 = TPE, 1 = BNC             */
  172 # define EE_W5_BOOT_IPX         0x0002
  173 # define EE_W5_BOOT_ODI         0x0004
  174 # define EE_W5_BOOT_NDIS        (EE_W5_BOOT_IPX|EE_W5_BOOT_ODI)
  175 # define EE_W5_NUM_CONN         0x0008  /* 0 = 2, 1 = 3                 */
  176 # define EE_W5_NOFLASH          0x0010  /* No flash socket present      */
  177 # define EE_W5_PORT_TPE         0x0020  /* TPE present                  */
  178 # define EE_W5_PORT_BNC         0x0040  /* BNC present                  */
  179 # define EE_W5_PORT_AUI         0x0080  /* AUI present                  */
  180 # define EE_W5_PWR_MGT          0x0100  /* Power Management             */
  181 # define EE_W5_CP               0x0200  /* COncurrent Processing        */
  182 
  183 #define EE_W6                   0x05
  184 # define EE_W6_STEP_MASK        0x000F
  185 # define EE_W6_BOARD_MASK       0xFFF0
  186 # define EE_W6_BOARD_SHIFT      4
  187 
  188 /* EEPROM serial interface. */
  189 
  190 #define EESK                    0x01
  191 #define EECS                    0x02
  192 #define EEDI                    0x04
  193 #define EEDO                    0x08
  194 #define EE_READ_CMD             (6 << 6)
  195 
  196 /* Frame chain constants. */
  197 
  198 /* Transmit header length (in board's ring buffer). */
  199 #define XMT_HEADER_LEN          8
  200 #define XMT_Chain_Point         4
  201 #define XMT_Byte_Count          6
  202 #define Done_bit                0x0080
  203 #define Ch_bit                  0x8000
  204 
  205 /* Transmit result bits. */
  206 #define No_Collisions_bits      0x000f
  207 #define TX_OK_bit               0x2000
  208 
  209 /* Receive result bits. */
  210 #define RCV_Done                8
  211 #define RCV_OK_bit              0x2000

Cache object: b25c691306477c285bea9176fad144cf


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