The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/dev/ex/if_exreg.h

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    1 /*-
    2  * Copyright (c) 1996, Javier Martín Rueda (jmrueda@diatel.upm.es)
    3  * All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice unmodified, this list of conditions, and the following
   10  *    disclaimer.
   11  * 2. Redistributions in binary form must reproduce the above copyright
   12  *    notice, this list of conditions and the following disclaimer in the
   13  *    documentation and/or other materials provided with the distribution.
   14  *
   15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   25  * SUCH DAMAGE.
   26  *
   27  * $FreeBSD: releng/11.2/sys/dev/ex/if_exreg.h 331722 2018-03-29 02:50:57Z eadler $
   28  */
   29 
   30 /*
   31  * Intel EtherExpress Pro/10 Ethernet driver
   32  */
   33 
   34 /*
   35  * Several constants.
   36  */
   37 
   38 #define CARD_TYPE_EX_10         1
   39 #define CARD_TYPE_EX_10_PLUS    2
   40 
   41 /* Length of an ethernet address. */
   42 #define ETHER_ADDR_LEN  6
   43 /* Default RAM size in board. */
   44 #define CARD_RAM_SIZE   0x8000
   45 /* Number of I/O ports used. */
   46 #define EX_IOSIZE       16
   47 
   48 /*
   49  * Intel EtherExpress Pro (i82595 based) registers
   50  */
   51 
   52 /* Common registers to all banks. */
   53 
   54 #define CMD_REG         0
   55 #define REG1            1
   56 #define REG2            2
   57 #define REG3            3
   58 #define REG4            4
   59 #define REG5            5
   60 #define REG6            6
   61 #define REG7            7
   62 #define REG8            8
   63 #define REG9            9
   64 #define REG10           10
   65 #define REG11           11
   66 #define REG12           12
   67 #define REG13           13
   68 #define REG14           14
   69 #define REG15           15
   70 
   71 /* Definitions for command register (CMD_REG). */
   72 
   73 #define Switch_Bank_CMD 0
   74 #define MC_Setup_CMD    3
   75 #define Transmit_CMD    4
   76 #define Diagnose_CMD    7
   77 #define Rcv_Enable_CMD  8
   78 #define Rcv_Stop        11
   79 #define Reset_CMD       14
   80 #define Resume_XMT_List_CMD 28
   81 #define Sel_Reset_CMD   30
   82 #define Abort           0x20
   83 #define Bank0_Sel       0x00
   84 #define Bank1_Sel       0x40
   85 #define Bank2_Sel       0x80
   86 
   87 /* Bank 0 specific registers. */
   88 
   89 #define STATUS_REG      1
   90 #define ID_REG          2
   91 #define Id_Mask         0x2c
   92 #define Id_Sig          0x24
   93 #define Counter_bits    0xc0
   94 #define MASK_REG        3
   95 #define Exec_Int        0x08
   96 #define Tx_Int          0x04
   97 #define Rx_Int          0x02
   98 #define Rx_Stp_Int      0x01
   99 #define All_Int         0x0f
  100 #define RCV_BAR         4
  101 #define RCV_BAR_Lo      4
  102 #define RCV_BAR_Hi      5
  103 #define RCV_STOP_REG    6
  104 #define XMT_BAR         10
  105 #define HOST_ADDR_REG   12      /* 16-bit register */
  106 #define IO_PORT_REG     14      /* 16-bit register */
  107 
  108 /* Bank 1 specific registers. */
  109 
  110 #define TriST_INT               0x80
  111 #define INT_NO_REG              2
  112 #define RCV_LOWER_LIMIT_REG     8
  113 #define RCV_UPPER_LIMIT_REG     9
  114 #define XMT_LOWER_LIMIT_REG     10
  115 #define XMT_UPPER_LIMIT_REG     11
  116 
  117 /* Bank 2 specific registers. */
  118 
  119 #define Disc_Bad_Fr             0x80
  120 #define Tx_Chn_ErStp            0x40
  121 #define Tx_Chn_Int_Md           0x20
  122 #define Multi_IA                0x20
  123 #define No_SA_Ins               0x10
  124 #define RX_CRC_InMem            0x04
  125 #define Promisc_Mode            0x01
  126 #define BNC_bit                 0x20
  127 #define TPE_bit                 0x04
  128 #define I_ADDR_REG0             4
  129 #define EEPROM_REG              10
  130 #define Trnoff_Enable           0x10
  131 
  132 /* EEPROM memory positions (16-bit wide). */
  133 
  134 #define EE_W0                   0x00
  135 # define EE_W0_PNP              0x0001
  136 # define EE_W0_BUS16            0x0004
  137 # define EE_W0_FLASH_ADDR_MASK  0x0038
  138 # define EE_W0_FLASH_ADDR_SHIFT 3
  139 # define EE_W0_AUTO_IO          0x0040
  140 # define EE_W0_FLASH            0x0100
  141 # define EE_W0_AUTO_NEG         0x0200
  142 # define EE_W0_IO_MASK          0xFC00
  143 # define EE_W0_IO_SHIFT         10
  144 
  145 #define EE_IRQ_No               1
  146 #define IRQ_No_Mask             0x07
  147 
  148 #define EE_W1                   0x01
  149 # define EE_W1_INT_SEL          0x0007
  150 # define EE_W1_NO_LINK_INT      0x0008  /* Link Integrity Off           */
  151 # define EE_W1_NO_POLARITY      0x0010  /* Polarity Correction Off      */
  152 # define EE_W1_TPE_AUI          0x0020  /* 1 = TPE, 0 = AUI             */
  153 # define EE_W1_NO_JABBER_PREV   0x0040  /* Jabber prevention Off        */
  154 # define EE_W1_NO_AUTO_SELECT   0x0080  /* Auto Port Selection Off      */
  155 # define EE_W1_SMOUT            0x0100  /* SMout Pin Control 0= Input   */
  156 # define EE_W1_PROM             0x0200  /* Flash = 0, PROM = 1          */
  157 # define EE_W1_ALT_READY        0x2000  /* Alternate Ready, 0=normal    */
  158 # define EE_W1_FULL_DUPLEX      0x8000
  159 
  160 #define EE_W2                   0x02
  161 #define EE_W3                   0x03
  162 #define EE_W4                   0x04
  163 
  164 #define EE_Eth_Addr_Lo          2
  165 #define EE_Eth_Addr_Mid         3
  166 #define EE_Eth_Addr_Hi          4
  167 
  168 #define EE_W5                   0x05
  169 # define EE_W5_BNC_TPE          0x0001  /* 0 = TPE, 1 = BNC             */
  170 # define EE_W5_BOOT_IPX         0x0002
  171 # define EE_W5_BOOT_ODI         0x0004
  172 # define EE_W5_BOOT_NDIS        (EE_W5_BOOT_IPX|EE_W5_BOOT_ODI)
  173 # define EE_W5_NUM_CONN         0x0008  /* 0 = 2, 1 = 3                 */
  174 # define EE_W5_NOFLASH          0x0010  /* No flash socket present      */
  175 # define EE_W5_PORT_TPE         0x0020  /* TPE present                  */
  176 # define EE_W5_PORT_BNC         0x0040  /* BNC present                  */
  177 # define EE_W5_PORT_AUI         0x0080  /* AUI present                  */
  178 # define EE_W5_PWR_MGT          0x0100  /* Power Management             */
  179 # define EE_W5_CP               0x0200  /* COncurrent Processing        */
  180 
  181 #define EE_W6                   0x05
  182 # define EE_W6_STEP_MASK        0x000F
  183 # define EE_W6_BOARD_MASK       0xFFF0
  184 # define EE_W6_BOARD_SHIFT      4
  185 
  186 /* EEPROM serial interface. */
  187 
  188 #define EESK                    0x01
  189 #define EECS                    0x02
  190 #define EEDI                    0x04
  191 #define EEDO                    0x08
  192 #define EE_READ_CMD             (6 << 6)
  193 
  194 /* Frame chain constants. */
  195 
  196 /* Transmit header length (in board's ring buffer). */
  197 #define XMT_HEADER_LEN          8
  198 #define XMT_Chain_Point         4
  199 #define XMT_Byte_Count          6
  200 #define Done_bit                0x0080
  201 #define Ch_bit                  0x8000
  202 
  203 /* Transmit result bits. */
  204 #define No_Collisions_bits      0x000f
  205 #define TX_OK_bit               0x2000
  206 
  207 /* Receive result bits. */
  208 #define RCV_Done                8
  209 #define RCV_OK_bit              0x2000

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