The Design and Implementation of the FreeBSD Operating System, Second Edition
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FreeBSD/Linux Kernel Cross Reference
sys/dev/fb/machfbreg.h

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    1 /*-
    2  * Copyright 1992,1993,1994,1995,1996,1997 by Kevin E. Martin, Chapel Hill, North Carolina.
    3  *
    4  * Permission to use, copy, modify, distribute, and sell this software and
    5  * its documentation for any purpose is hereby granted without fee,
    6  * provided that the above copyright notice appear in all copies and that
    7  * both that copyright notice and this permission notice appear in
    8  * supporting documentation, and that the name of Kevin E. Martin not be
    9  * used in advertising or publicity pertaining to distribution of the
   10  * software without specific, written prior permission.  Kevin E. Martin
   11  * makes no representations about the suitability of this software for any
   12  * purpose.  It is provided "as is" without express or implied warranty.
   13  *
   14  * KEVIN E. MARTIN, RICKARD E. FAITH, AND TIAGO GONS DISCLAIM ALL
   15  * WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING ALL IMPLIED
   16  * WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO EVENT SHALL THE
   17  * AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR
   18  * ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS,
   19  * WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION,
   20  * ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS
   21  * SOFTWARE.
   22  *
   23  * Modified for the Mach-8 by Rickard E. Faith (faith@cs.unc.edu)
   24  * Modified for the Mach32 by Kevin E. Martin (martin@cs.unc.edu)
   25  * Modified for the Mach64 by Kevin E. Martin (martin@cs.unc.edu)
   26  *
   27  *      from: NetBSD: machfbreg.h,v 1.1 2002/10/24 18:15:57 junyoung Exp
   28  *
   29  * $FreeBSD: releng/11.1/sys/dev/fb/machfbreg.h 146482 2005-05-21 20:47:38Z marius $
   30  */
   31 
   32 #ifndef _DEV_FB_MACHFB_H_
   33 #define _DEV_FB_MACHFB_H_
   34 
   35 /* NON-GUI MEMORY MAPPED Registers - expressed in BYTE offsets */
   36 
   37 #define CRTC_H_TOTAL_DISP       0x0000  /* Dword offset 00 */
   38 #define CRTC_H_SYNC_STRT_WID    0x0004  /* Dword offset 01 */
   39 #define CRTC_V_TOTAL_DISP       0x0008  /* Dword offset 02 */
   40 #define CRTC_V_SYNC_STRT_WID    0x000C  /* Dword offset 03 */
   41 #define CRTC_VLINE_CRNT_VLINE   0x0010  /* Dword offset 04 */
   42 #define CRTC_OFF_PITCH          0x0014  /* Dword offset 05 */
   43 #define CRTC_INT_CNTL           0x0018  /* Dword offset 06 */
   44 #define CRTC_GEN_CNTL           0x001C  /* Dword offset 07 */
   45 
   46 #define DSP_CONFIG              0x0020  /* Dword offset 08 */
   47 #define DSP_ON_OFF              0x0024  /* Dword offset 09 */
   48 
   49 #define SHARED_CNTL             0x0038  /* Dword offset 0E */
   50 
   51 #define OVR_CLR                 0x0040  /* Dword offset 10 */
   52 #define OVR_WID_LEFT_RIGHT      0x0044  /* Dword offset 11 */
   53 #define OVR_WID_TOP_BOTTOM      0x0048  /* Dword offset 12 */
   54 
   55 #define CUR_CLR0                0x0060  /* Dword offset 18 */
   56 #define CUR_CLR1                0x0064  /* Dword offset 19 */
   57 #define CUR_OFFSET              0x0068  /* Dword offset 1A */
   58 #define CUR_HORZ_VERT_POSN      0x006C  /* Dword offset 1B */
   59 #define CUR_HORZ_VERT_OFF       0x0070  /* Dword offset 1C */
   60 
   61 #define HW_DEBUG                0x007C  /* Dword offset 1F */
   62 
   63 #define SCRATCH_REG0            0x0080  /* Dword offset 20 */
   64 #define SCRATCH_REG1            0x0084  /* Dword offset 21 */
   65 
   66 #define CLOCK_CNTL              0x0090  /* Dword offset 24 */
   67 
   68 #define BUS_CNTL                0x00A0  /* Dword offset 28 */
   69 
   70 #define LCD_INDEX               0x00A4  /* Dword offset 29 (LTPro) */
   71 #define LCD_DATA                0x00A8  /* Dword offset 2A (LTPro) */
   72 
   73 #define MEM_CNTL                0x00B0  /* Dword offset 2C */
   74 
   75 #define MEM_VGA_WP_SEL          0x00B4  /* Dword offset 2D */
   76 #define MEM_VGA_RP_SEL          0x00B8  /* Dword offset 2E */
   77 
   78 #define DAC_REGS                0x00C0  /* Dword offset 30 */
   79 #define DAC_WINDEX              0x00C0  /* Dword offset 30 */
   80 #define DAC_DATA                0x00C1  /* Dword offset 30 */
   81 #define DAC_MASK                0x00C2  /* Dword offset 30 */
   82 #define DAC_RINDEX              0x00C3  /* Dword offset 30 */
   83 #define DAC_CNTL                0x00C4  /* Dword offset 31 */
   84 
   85 #define HORZ_STRETCHING         0x00C8  /* Dword offset 32 (LT) */
   86 #define VERT_STRETCHING         0x00CC  /* Dword offset 33 (LT) */
   87 
   88 #define GEN_TEST_CNTL           0x00D0  /* Dword offset 34 */
   89 
   90 #define LCD_GEN_CNTL            0x00D4  /* Dword offset 35 (LT) */
   91 #define POWER_MANAGEMENT        0x00D8  /* Dword offset 36 (LT) */
   92 
   93 #define CONFIG_CNTL             0x00DC  /* Dword offset 37 (CT, ET, VT) */
   94 #define CONFIG_CHIP_ID          0x00E0  /* Dword offset 38 */
   95 #define CONFIG_STAT0            0x00E4  /* Dword offset 39 */
   96 #define CONFIG_STAT1            0x00E8  /* Dword offset 3A */
   97 
   98 
   99 /* GUI MEMORY MAPPED Registers */
  100 
  101 #define DST_OFF_PITCH           0x0100  /* Dword offset 40 */
  102 #define DST_X                   0x0104  /* Dword offset 41 */
  103 #define DST_Y                   0x0108  /* Dword offset 42 */
  104 #define DST_Y_X                 0x010C  /* Dword offset 43 */
  105 #define DST_WIDTH               0x0110  /* Dword offset 44 */
  106 #define DST_HEIGHT              0x0114  /* Dword offset 45 */
  107 #define DST_HEIGHT_WIDTH        0x0118  /* Dword offset 46 */
  108 #define DST_X_WIDTH             0x011C  /* Dword offset 47 */
  109 #define DST_BRES_LNTH           0x0120  /* Dword offset 48 */
  110 #define DST_BRES_ERR            0x0124  /* Dword offset 49 */
  111 #define DST_BRES_INC            0x0128  /* Dword offset 4A */
  112 #define DST_BRES_DEC            0x012C  /* Dword offset 4B */
  113 #define DST_CNTL                0x0130  /* Dword offset 4C */
  114 
  115 #define SRC_OFF_PITCH           0x0180  /* Dword offset 60 */
  116 #define SRC_X                   0x0184  /* Dword offset 61 */
  117 #define SRC_Y                   0x0188  /* Dword offset 62 */
  118 #define SRC_Y_X                 0x018C  /* Dword offset 63 */
  119 #define SRC_WIDTH1              0x0190  /* Dword offset 64 */
  120 #define SRC_HEIGHT1             0x0194  /* Dword offset 65 */
  121 #define SRC_HEIGHT1_WIDTH1      0x0198  /* Dword offset 66 */
  122 #define SRC_X_START             0x019C  /* Dword offset 67 */
  123 #define SRC_Y_START             0x01A0  /* Dword offset 68 */
  124 #define SRC_Y_X_START           0x01A4  /* Dword offset 69 */
  125 #define SRC_WIDTH2              0x01A8  /* Dword offset 6A */
  126 #define SRC_HEIGHT2             0x01AC  /* Dword offset 6B */
  127 #define SRC_HEIGHT2_WIDTH2      0x01B0  /* Dword offset 6C */
  128 #define SRC_CNTL                0x01B4  /* Dword offset 6D */
  129 
  130 #define HOST_DATA0              0x0200  /* Dword offset 80 */
  131 #define HOST_DATA1              0x0204  /* Dword offset 81 */
  132 #define HOST_DATA2              0x0208  /* Dword offset 82 */
  133 #define HOST_DATA3              0x020C  /* Dword offset 83 */
  134 #define HOST_DATA4              0x0210  /* Dword offset 84 */
  135 #define HOST_DATA5              0x0214  /* Dword offset 85 */
  136 #define HOST_DATA6              0x0218  /* Dword offset 86 */
  137 #define HOST_DATA7              0x021C  /* Dword offset 87 */
  138 #define HOST_DATA8              0x0220  /* Dword offset 88 */
  139 #define HOST_DATA9              0x0224  /* Dword offset 89 */
  140 #define HOST_DATAA              0x0228  /* Dword offset 8A */
  141 #define HOST_DATAB              0x022C  /* Dword offset 8B */
  142 #define HOST_DATAC              0x0230  /* Dword offset 8C */
  143 #define HOST_DATAD              0x0234  /* Dword offset 8D */
  144 #define HOST_DATAE              0x0238  /* Dword offset 8E */
  145 #define HOST_DATAF              0x023C  /* Dword offset 8F */
  146 #define HOST_CNTL               0x0240  /* Dword offset 90 */
  147 
  148 #define PAT_REG0                0x0280  /* Dword offset A0 */
  149 #define PAT_REG1                0x0284  /* Dword offset A1 */
  150 #define PAT_CNTL                0x0288  /* Dword offset A2 */
  151 
  152 #define SC_LEFT                 0x02A0  /* Dword offset A8 */
  153 #define SC_RIGHT                0x02A4  /* Dword offset A9 */
  154 #define SC_LEFT_RIGHT           0x02A8  /* Dword offset AA */
  155 #define SC_TOP                  0x02AC  /* Dword offset AB */
  156 #define SC_BOTTOM               0x02B0  /* Dword offset AC */
  157 #define SC_TOP_BOTTOM           0x02B4  /* Dword offset AD */
  158 
  159 #define DP_BKGD_CLR             0x02C0  /* Dword offset B0 */
  160 #define DP_FRGD_CLR             0x02C4  /* Dword offset B1 */
  161 #define DP_WRITE_MASK           0x02C8  /* Dword offset B2 */
  162 #define DP_CHAIN_MASK           0x02CC  /* Dword offset B3 */
  163 #define DP_PIX_WIDTH            0x02D0  /* Dword offset B4 */
  164 #define DP_MIX                  0x02D4  /* Dword offset B5 */
  165 #define DP_SRC                  0x02D8  /* Dword offset B6 */
  166 
  167 #define CLR_CMP_CLR             0x0300  /* Dword offset C0 */
  168 #define CLR_CMP_MASK            0x0304  /* Dword offset C1 */
  169 #define CLR_CMP_CNTL            0x0308  /* Dword offset C2 */
  170 
  171 #define FIFO_STAT               0x0310  /* Dword offset C4 */
  172 
  173 #define CONTEXT_MASK            0x0320  /* Dword offset C8 */
  174 #define CONTEXT_LOAD_CNTL       0x032C  /* Dword offset CB */
  175 
  176 #define GUI_TRAJ_CNTL           0x0330  /* Dword offset CC */
  177 #define GUI_STAT                0x0338  /* Dword offset CE */
  178 
  179 
  180 /* CRTC control values */
  181 
  182 #define CRTC_HSYNC_NEG          0x00200000
  183 #define CRTC_VSYNC_NEG          0x00200000
  184 
  185 #define CRTC_DBL_SCAN_EN        0x00000001
  186 #define CRTC_INTERLACE_EN       0x00000002
  187 #define CRTC_HSYNC_DIS          0x00000004
  188 #define CRTC_VSYNC_DIS          0x00000008
  189 #define CRTC_CSYNC_EN           0x00000010
  190 #define CRTC_PIX_BY_2_EN        0x00000020
  191 #define CRTC_DISPLAY_DIS        0x00000040
  192 #define CRTC_VGA_XOVERSCAN      0x00000080
  193 
  194 #define CRTC_PIX_WIDTH          0x00000700
  195 #define CRTC_PIX_WIDTH_4BPP     0x00000100
  196 #define CRTC_PIX_WIDTH_8BPP     0x00000200
  197 #define CRTC_PIX_WIDTH_15BPP    0x00000300
  198 #define CRTC_PIX_WIDTH_16BPP    0x00000400
  199 #define CRTC_PIX_WIDTH_24BPP    0x00000500
  200 #define CRTC_PIX_WIDTH_32BPP    0x00000600
  201 
  202 #define CRTC_BYTE_PIX_ORDER     0x00000800
  203 #define CRTC_PIX_ORDER_MSN_LSN  0x00000000
  204 #define CRTC_PIX_ORDER_LSN_MSN  0x00000800
  205 
  206 #define CRTC_FIFO_LWM           0x000f0000
  207 #define CRTC_LOCK_REGS          0x00400000
  208 #define CRTC_EXT_DISP_EN        0x01000000
  209 #define CRTC_EN                 0x02000000
  210 #define CRTC_DISP_REQ_EN        0x04000000
  211 #define CRTC_VGA_LINEAR         0x08000000
  212 #define CRTC_VSYNC_FALL_EDGE    0x10000000
  213 #define CRTC_VGA_TEXT_132       0x20000000
  214 #define CRTC_CNT_EN             0x40000000
  215 #define CRTC_CUR_B_TEST         0x80000000
  216 
  217 #define CRTC_CRNT_VLINE         0x07f00000
  218 #define CRTC_VBLANK             0x00000001
  219 
  220 /* DAC control values */
  221 
  222 #define DAC_EXT_SEL_RS2         0x01
  223 #define DAC_EXT_SEL_RS3         0x02
  224 #define DAC_8BIT_EN             0x00000100
  225 #define DAC_PIX_DLY_MASK        0x00000600
  226 #define DAC_PIX_DLY_0NS         0x00000000
  227 #define DAC_PIX_DLY_2NS         0x00000200
  228 #define DAC_PIX_DLY_4NS         0x00000400
  229 #define DAC_BLANK_ADJ_MASK      0x00001800
  230 #define DAC_BLANK_ADJ_0         0x00000000
  231 #define DAC_BLANK_ADJ_1         0x00000800
  232 #define DAC_BLANK_ADJ_2         0x00001000
  233 
  234 
  235 /* Mix control values */
  236 
  237 #define MIX_NOT_DST             0x0000
  238 #define MIX_0                   0x0001
  239 #define MIX_1                   0x0002
  240 #define MIX_DST                 0x0003
  241 #define MIX_NOT_SRC             0x0004
  242 #define MIX_XOR                 0x0005
  243 #define MIX_XNOR                0x0006
  244 #define MIX_SRC                 0x0007
  245 #define MIX_NAND                0x0008
  246 #define MIX_NOT_SRC_OR_DST      0x0009
  247 #define MIX_SRC_OR_NOT_DST      0x000a
  248 #define MIX_OR                  0x000b
  249 #define MIX_AND                 0x000c
  250 #define MIX_SRC_AND_NOT_DST     0x000d
  251 #define MIX_NOT_SRC_AND_DST     0x000e
  252 #define MIX_NOR                 0x000f
  253 
  254 /* Maximum engine dimensions */
  255 #define ENGINE_MIN_X            0
  256 #define ENGINE_MIN_Y            0
  257 #define ENGINE_MAX_X            4095
  258 #define ENGINE_MAX_Y            16383
  259 
  260 /* Mach64 engine bit constants - these are typically ORed together */
  261 
  262 /* HW_DEBUG register constants */
  263 /* For RagePro only... */
  264 #define AUTO_FF_DIS             0x000001000
  265 #define AUTO_BLKWRT_DIS         0x000002000
  266 
  267 /* BUS_CNTL register constants */
  268 #define BUS_FIFO_ERR_ACK        0x00200000
  269 #define BUS_HOST_ERR_ACK        0x00800000
  270 #define BUS_APER_REG_DIS        0x00000010
  271 
  272 /* GEN_TEST_CNTL register constants */
  273 #define GEN_OVR_OUTPUT_EN       0x20
  274 #define HWCURSOR_ENABLE         0x80
  275 #define GUI_ENGINE_ENABLE       0x100
  276 #define BLOCK_WRITE_ENABLE      0x200
  277 
  278 /* DSP_CONFIG register constants */
  279 #define DSP_XCLKS_PER_QW        0x00003fff
  280 #define DSP_LOOP_LATENCY        0x000f0000
  281 #define DSP_PRECISION           0x00700000
  282 
  283 /* DSP_ON_OFF register constants */
  284 #define DSP_OFF                 0x000007ff
  285 #define DSP_ON                  0x07ff0000
  286 
  287 /* SHARED_CNTL register constants */
  288 #define CTD_FIFO5               0x01000000
  289 
  290 /* CLOCK_CNTL register constants */
  291 #define CLOCK_SEL               0x0f
  292 #define CLOCK_DIV               0x30
  293 #define CLOCK_DIV1              0x00
  294 #define CLOCK_DIV2              0x10
  295 #define CLOCK_DIV4              0x20
  296 #define CLOCK_STROBE            0x40
  297 #define PLL_WR_EN               0x02
  298 
  299 /* PLL registers */
  300 #define PLL_MACRO_CNTL          0x01
  301 #define PLL_REF_DIV             0x02
  302 #define PLL_GEN_CNTL            0x03
  303 #define MCLK_FB_DIV             0x04
  304 #define PLL_VCLK_CNTL           0x05
  305 #define VCLK_POST_DIV           0x06
  306 #define VCLK0_FB_DIV            0x07
  307 #define VCLK1_FB_DIV            0x08
  308 #define VCLK2_FB_DIV            0x09
  309 #define VCLK3_FB_DIV            0x0A
  310 #define PLL_XCLK_CNTL           0x0B
  311 #define PLL_TEST_CTRL           0x0E
  312 #define PLL_TEST_COUNT          0x0F
  313 
  314 /* Memory types for CT, ET, VT, GT */
  315 #define DRAM                    1
  316 #define EDO_DRAM                2
  317 #define PSEUDO_EDO              3
  318 #define SDRAM                   4
  319 #define SGRAM                   5
  320 #define SGRAM32                 6
  321 
  322 #define DAC_INTERNAL            0x00
  323 #define DAC_IBMRGB514           0x01
  324 #define DAC_ATI68875            0x02
  325 #define DAC_TVP3026_A           0x72
  326 #define DAC_BT476               0x03
  327 #define DAC_BT481               0x04
  328 #define DAC_ATT20C491           0x14
  329 #define DAC_SC15026             0x24
  330 #define DAC_MU9C1880            0x34
  331 #define DAC_IMSG174             0x44
  332 #define DAC_ATI68860_B          0x05
  333 #define DAC_ATI68860_C          0x15
  334 #define DAC_TVP3026_B           0x75
  335 #define DAC_STG1700             0x06
  336 #define DAC_ATT498              0x16
  337 #define DAC_STG1702             0x07
  338 #define DAC_SC15021             0x17
  339 #define DAC_ATT21C498           0x27
  340 #define DAC_STG1703             0x37
  341 #define DAC_CH8398              0x47
  342 #define DAC_ATT20C408           0x57
  343 
  344 #define CLK_ATI18818_0          0
  345 #define CLK_ATI18818_1          1
  346 #define CLK_STG1703             2
  347 #define CLK_CH8398              3
  348 #define CLK_INTERNAL            4
  349 #define CLK_ATT20C408           5
  350 #define CLK_IBMRGB514           6
  351 
  352 /* DST_CNTL register constants */
  353 #define DST_X_RIGHT_TO_LEFT     0
  354 #define DST_X_LEFT_TO_RIGHT     1
  355 #define DST_Y_BOTTOM_TO_TOP     0
  356 #define DST_Y_TOP_TO_BOTTOM     2
  357 #define DST_X_MAJOR             0
  358 #define DST_Y_MAJOR             4
  359 #define DST_X_TILE              8
  360 #define DST_Y_TILE              0x10
  361 #define DST_LAST_PEL            0x20
  362 #define DST_POLYGON_ENABLE      0x40
  363 #define DST_24_ROTATION_ENABLE  0x80
  364 
  365 /* SRC_CNTL register constants */
  366 #define SRC_PATTERN_ENABLE      1
  367 #define SRC_ROTATION_ENABLE     2
  368 #define SRC_LINEAR_ENABLE       4
  369 #define SRC_BYTE_ALIGN          8
  370 #define SRC_LINE_X_RIGHT_TO_LEFT        0
  371 #define SRC_LINE_X_LEFT_TO_RIGHT        0x10
  372 
  373 /* HOST_CNTL register constants */
  374 #define HOST_BYTE_ALIGN         1
  375 
  376 /* DP_CHAIN_MASK register constants */
  377 #define DP_CHAIN_4BPP           0x8888
  378 #define DP_CHAIN_7BPP           0xD2D2
  379 #define DP_CHAIN_8BPP           0x8080
  380 #define DP_CHAIN_8BPP_RGB       0x9292
  381 #define DP_CHAIN_15BPP          0x4210
  382 #define DP_CHAIN_16BPP          0x8410
  383 #define DP_CHAIN_24BPP          0x8080
  384 #define DP_CHAIN_32BPP          0x8080
  385 
  386 /* DP_PIX_WIDTH register constants */
  387 #define DST_1BPP                0
  388 #define DST_4BPP                1
  389 #define DST_8BPP                2
  390 #define DST_15BPP               3
  391 #define DST_16BPP               4
  392 #define DST_32BPP               6
  393 #define SRC_1BPP                0
  394 #define SRC_4BPP                0x100
  395 #define SRC_8BPP                0x200
  396 #define SRC_15BPP               0x300
  397 #define SRC_16BPP               0x400
  398 #define SRC_32BPP               0x600
  399 #define HOST_1BPP               0
  400 #define HOST_4BPP               0x10000
  401 #define HOST_8BPP               0x20000
  402 #define HOST_15BPP              0x30000
  403 #define HOST_16BPP              0x40000
  404 #define HOST_32BPP              0x60000
  405 #define BYTE_ORDER_MSB_TO_LSB   0
  406 #define BYTE_ORDER_LSB_TO_MSB   0x1000000
  407 
  408 /* DP_SRC register constants */
  409 #define BKGD_SRC_BKGD_CLR       0
  410 #define BKGD_SRC_FRGD_CLR       1
  411 #define BKGD_SRC_HOST           2
  412 #define BKGD_SRC_BLIT           3
  413 #define BKGD_SRC_PATTERN        4
  414 #define FRGD_SRC_BKGD_CLR       0
  415 #define FRGD_SRC_FRGD_CLR       0x100
  416 #define FRGD_SRC_HOST           0x200
  417 #define FRGD_SRC_BLIT           0x300
  418 #define FRGD_SRC_PATTERN        0x400
  419 #define MONO_SRC_ONE            0
  420 #define MONO_SRC_PATTERN        0x10000
  421 #define MONO_SRC_HOST           0x20000
  422 #define MONO_SRC_BLIT           0x30000
  423 
  424 /* PCI IDs */
  425 #define ATI_VENDOR              0x1002
  426 #define ATI_MACH64_CT           0x4354  /* Mach64 CT */
  427 #define ATI_RAGE_PRO_AGP        0x4742  /* 3D Rage Pro (AGP) */
  428 #define ATI_RAGE_PRO_AGP1X      0x4744  /* 3D Rage Pro (AGP 1x) */
  429 #define ATI_RAGE_PRO_PCI_B      0x4749  /* 3D Rage Pro Turbo */
  430 #define ATI_RAGE_XC_PCI66       0x474c  /* Rage XC (PCI66) */
  431 #define ATI_RAGE_XL_AGP         0x474d  /* Rage XL (AGP) */
  432 #define ATI_RAGE_XC_AGP         0x474e  /* Rage XC (AGP) */
  433 #define ATI_RAGE_XL_PCI66       0x474f  /* Rage XL (PCI66) */
  434 #define ATI_RAGE_PRO_PCI_P      0x4750  /* 3D Rage Pro */
  435 #define ATI_RAGE_PRO_PCI_L      0x4751  /* 3D Rage Pro (limited 3D) */
  436 #define ATI_RAGE_XL_PCI         0x4752  /* Rage XL */
  437 #define ATI_RAGE_XC_PCI         0x4753  /* Rage XC */
  438 #define ATI_RAGE_II             0x4754  /* 3D Rage I/II */
  439 #define ATI_RAGE_IIP            0x4755  /* 3D Rage II+ */
  440 #define ATI_RAGE_IIC_PCI        0x4756  /* 3D Rage IIC */
  441 #define ATI_RAGE_IIC_AGP_B      0x4757  /* 3D Rage IIC (AGP) */
  442 #define ATI_RAGE_IIC_AGP_P      0x475a  /* 3D Rage IIC (AGP) */
  443 #define ATI_RAGE_LT_PRO_AGP     0x4c42  /* 3D Rage LT Pro (AGP 133MHz) */
  444 #define ATI_RAGE_MOB_M3_PCI     0x4c45  /* Rage Mobility M3 */
  445 #define ATI_RAGE_MOB_M3_AGP     0x4c46  /* Rage Mobility M3 (AGP) */
  446 #define ATI_RAGE_LT             0x4c47  /* 3D Rage LT */
  447 #define ATI_RAGE_LT_PRO_PCI     0x4c49  /* 3D Rage LT Pro */
  448 #define ATI_RAGE_MOBILITY       0x4c4d  /* Rage Mobility */
  449 #define ATI_RAGE_L_MOBILITY     0x4c4e  /* Rage L Mobility */
  450 #define ATI_RAGE_LT_PRO         0x4c50  /* 3D Rage LT Pro */
  451 #define ATI_RAGE_LT_PRO2        0x4c51  /* 3D Rage LT Pro */
  452 #define ATI_RAGE_MOB_M1_PCI     0x4c52  /* Rage Mobility M1 (PCI) */
  453 #define ATI_RAGE_L_MOB_M1_PCI   0x4c53  /* Rage L Mobility (PCI) */
  454 #define ATI_MACH64_VT           0x5654  /* Mach64 VT */
  455 #define ATI_MACH64_VTB          0x5655  /* Mach64 VTB */
  456 #define ATI_MACH64_VT4          0x5656  /* Mach64 VT4 */
  457 
  458 #endif /* !_DEV_FB_MACHFB_H_ */

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