FreeBSD/Linux Kernel Cross Reference
sys/dev/ffec/if_ffec.c
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2013 Ian Lepore <ian@freebsd.org>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 *
28 */
29
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
32
33 /*
34 * Driver for Freescale Fast Ethernet Controller, found on imx-series SoCs among
35 * others. Also works for the ENET Gigibit controller found on imx6 and imx28,
36 * but the driver doesn't currently use any of the ENET advanced features other
37 * than enabling gigabit.
38 *
39 * The interface name 'fec' is already taken by netgraph's Fast Etherchannel
40 * (netgraph/ng_fec.c), so we use 'ffec'.
41 *
42 * Requires an FDT entry with at least these properties:
43 * fec: ethernet@02188000 {
44 * compatible = "fsl,imxNN-fec";
45 * reg = <0x02188000 0x4000>;
46 * interrupts = <150 151>;
47 * phy-mode = "rgmii";
48 * phy-disable-preamble; // optional
49 * };
50 * The second interrupt number is for IEEE-1588, and is not currently used; it
51 * need not be present. phy-mode must be one of: "mii", "rmii", "rgmii".
52 * There is also an optional property, phy-disable-preamble, which if present
53 * will disable the preamble bits, cutting the size of each mdio transaction
54 * (and thus the busy-wait time) in half.
55 */
56
57 #include <sys/param.h>
58 #include <sys/systm.h>
59 #include <sys/bus.h>
60 #include <sys/endian.h>
61 #include <sys/kernel.h>
62 #include <sys/lock.h>
63 #include <sys/malloc.h>
64 #include <sys/mbuf.h>
65 #include <sys/module.h>
66 #include <sys/mutex.h>
67 #include <sys/rman.h>
68 #include <sys/socket.h>
69 #include <sys/sockio.h>
70 #include <sys/sysctl.h>
71
72 #include <machine/bus.h>
73
74 #include <net/bpf.h>
75 #include <net/if.h>
76 #include <net/ethernet.h>
77 #include <net/if_dl.h>
78 #include <net/if_media.h>
79 #include <net/if_types.h>
80 #include <net/if_var.h>
81 #include <net/if_vlan_var.h>
82
83 #include <dev/fdt/fdt_common.h>
84 #include <dev/ffec/if_ffecreg.h>
85 #include <dev/ofw/ofw_bus.h>
86 #include <dev/ofw/ofw_bus_subr.h>
87 #include <dev/mii/mii.h>
88 #include <dev/mii/miivar.h>
89 #include <dev/mii/mii_fdt.h>
90 #include "miibus_if.h"
91
92 /*
93 * There are small differences in the hardware on various SoCs. Not every SoC
94 * we support has its own FECTYPE; most work as GENERIC and only the ones that
95 * need different handling get their own entry. In addition to the types in
96 * this list, there are some flags below that can be ORed into the upper bits.
97 */
98 enum {
99 FECTYPE_NONE,
100 FECTYPE_GENERIC,
101 FECTYPE_IMX53,
102 FECTYPE_IMX6, /* imx6 and imx7 */
103 FECTYPE_MVF,
104 };
105
106 /*
107 * Flags that describe general differences between the FEC hardware in various
108 * SoCs. These are ORed into the FECTYPE enum values in the ofw_compat_data, so
109 * the low 8 bits are reserved for the type enum. In the softc, the type and
110 * flags are put into separate members, so that you don't need to mask the flags
111 * out of the type to compare it.
112 */
113 #define FECTYPE_MASK 0x000000ff
114 #define FECFLAG_GBE (1 << 8)
115 #define FECFLAG_AVB (1 << 9)
116 #define FECFLAG_RACC (1 << 10)
117
118 /*
119 * Table of supported FDT compat strings and their associated FECTYPE values.
120 */
121 static struct ofw_compat_data compat_data[] = {
122 {"fsl,imx51-fec", FECTYPE_GENERIC},
123 {"fsl,imx53-fec", FECTYPE_IMX53},
124 {"fsl,imx6q-fec", FECTYPE_IMX6 | FECFLAG_RACC | FECFLAG_GBE },
125 {"fsl,imx6ul-fec", FECTYPE_IMX6 | FECFLAG_RACC },
126 {"fsl,imx6sx-fec", FECTYPE_IMX6 | FECFLAG_RACC },
127 {"fsl,imx7d-fec", FECTYPE_IMX6 | FECFLAG_RACC | FECFLAG_GBE |
128 FECFLAG_AVB },
129 {"fsl,mvf600-fec", FECTYPE_MVF | FECFLAG_RACC },
130 {"fsl,mvf-fec", FECTYPE_MVF},
131 {NULL, FECTYPE_NONE},
132 };
133
134 /*
135 * Driver data and defines.
136 */
137 #define RX_DESC_COUNT 64
138 #define RX_DESC_SIZE (sizeof(struct ffec_hwdesc) * RX_DESC_COUNT)
139 #define TX_DESC_COUNT 64
140 #define TX_DESC_SIZE (sizeof(struct ffec_hwdesc) * TX_DESC_COUNT)
141
142 #define WATCHDOG_TIMEOUT_SECS 5
143
144 #define MAX_IRQ_COUNT 3
145
146 struct ffec_bufmap {
147 struct mbuf *mbuf;
148 bus_dmamap_t map;
149 };
150
151 struct ffec_softc {
152 device_t dev;
153 device_t miibus;
154 struct mii_data * mii_softc;
155 struct ifnet *ifp;
156 int if_flags;
157 struct mtx mtx;
158 struct resource *irq_res[MAX_IRQ_COUNT];
159 struct resource *mem_res;
160 void * intr_cookie[MAX_IRQ_COUNT];
161 struct callout ffec_callout;
162 mii_contype_t phy_conn_type;
163 uint32_t fecflags;
164 uint8_t fectype;
165 boolean_t link_is_up;
166 boolean_t is_attached;
167 boolean_t is_detaching;
168 int tx_watchdog_count;
169 int rxbuf_align;
170 int txbuf_align;
171
172 bus_dma_tag_t rxdesc_tag;
173 bus_dmamap_t rxdesc_map;
174 struct ffec_hwdesc *rxdesc_ring;
175 bus_addr_t rxdesc_ring_paddr;
176 bus_dma_tag_t rxbuf_tag;
177 struct ffec_bufmap rxbuf_map[RX_DESC_COUNT];
178 uint32_t rx_idx;
179
180 bus_dma_tag_t txdesc_tag;
181 bus_dmamap_t txdesc_map;
182 struct ffec_hwdesc *txdesc_ring;
183 bus_addr_t txdesc_ring_paddr;
184 bus_dma_tag_t txbuf_tag;
185 struct ffec_bufmap txbuf_map[TX_DESC_COUNT];
186 uint32_t tx_idx_head;
187 uint32_t tx_idx_tail;
188 int txcount;
189 };
190
191 static struct resource_spec irq_res_spec[MAX_IRQ_COUNT + 1] = {
192 { SYS_RES_IRQ, 0, RF_ACTIVE },
193 { SYS_RES_IRQ, 1, RF_ACTIVE | RF_OPTIONAL },
194 { SYS_RES_IRQ, 2, RF_ACTIVE | RF_OPTIONAL },
195 RESOURCE_SPEC_END
196 };
197
198 #define FFEC_LOCK(sc) mtx_lock(&(sc)->mtx)
199 #define FFEC_UNLOCK(sc) mtx_unlock(&(sc)->mtx)
200 #define FFEC_LOCK_INIT(sc) mtx_init(&(sc)->mtx, \
201 device_get_nameunit((sc)->dev), MTX_NETWORK_LOCK, MTX_DEF)
202 #define FFEC_LOCK_DESTROY(sc) mtx_destroy(&(sc)->mtx);
203 #define FFEC_ASSERT_LOCKED(sc) mtx_assert(&(sc)->mtx, MA_OWNED);
204 #define FFEC_ASSERT_UNLOCKED(sc) mtx_assert(&(sc)->mtx, MA_NOTOWNED);
205
206 static void ffec_init_locked(struct ffec_softc *sc);
207 static void ffec_stop_locked(struct ffec_softc *sc);
208 static void ffec_txstart_locked(struct ffec_softc *sc);
209 static void ffec_txfinish_locked(struct ffec_softc *sc);
210
211 static inline uint16_t
212 RD2(struct ffec_softc *sc, bus_size_t off)
213 {
214
215 return (bus_read_2(sc->mem_res, off));
216 }
217
218 static inline void
219 WR2(struct ffec_softc *sc, bus_size_t off, uint16_t val)
220 {
221
222 bus_write_2(sc->mem_res, off, val);
223 }
224
225 static inline uint32_t
226 RD4(struct ffec_softc *sc, bus_size_t off)
227 {
228
229 return (bus_read_4(sc->mem_res, off));
230 }
231
232 static inline void
233 WR4(struct ffec_softc *sc, bus_size_t off, uint32_t val)
234 {
235
236 bus_write_4(sc->mem_res, off, val);
237 }
238
239 static inline uint32_t
240 next_rxidx(struct ffec_softc *sc, uint32_t curidx)
241 {
242
243 return ((curidx == RX_DESC_COUNT - 1) ? 0 : curidx + 1);
244 }
245
246 static inline uint32_t
247 next_txidx(struct ffec_softc *sc, uint32_t curidx)
248 {
249
250 return ((curidx == TX_DESC_COUNT - 1) ? 0 : curidx + 1);
251 }
252
253 static void
254 ffec_get1paddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
255 {
256
257 if (error != 0)
258 return;
259 *(bus_addr_t *)arg = segs[0].ds_addr;
260 }
261
262 static void
263 ffec_miigasket_setup(struct ffec_softc *sc)
264 {
265 uint32_t ifmode;
266
267 /*
268 * We only need the gasket for MII and RMII connections on certain SoCs.
269 */
270
271 switch (sc->fectype)
272 {
273 case FECTYPE_IMX53:
274 break;
275 default:
276 return;
277 }
278
279 switch (sc->phy_conn_type)
280 {
281 case MII_CONTYPE_MII:
282 ifmode = 0;
283 break;
284 case MII_CONTYPE_RMII:
285 ifmode = FEC_MIIGSK_CFGR_IF_MODE_RMII;
286 break;
287 default:
288 return;
289 }
290
291 /*
292 * Disable the gasket, configure for either MII or RMII, then enable.
293 */
294
295 WR2(sc, FEC_MIIGSK_ENR, 0);
296 while (RD2(sc, FEC_MIIGSK_ENR) & FEC_MIIGSK_ENR_READY)
297 continue;
298
299 WR2(sc, FEC_MIIGSK_CFGR, ifmode);
300
301 WR2(sc, FEC_MIIGSK_ENR, FEC_MIIGSK_ENR_EN);
302 while (!(RD2(sc, FEC_MIIGSK_ENR) & FEC_MIIGSK_ENR_READY))
303 continue;
304 }
305
306 static boolean_t
307 ffec_miibus_iowait(struct ffec_softc *sc)
308 {
309 uint32_t timeout;
310
311 for (timeout = 10000; timeout != 0; --timeout)
312 if (RD4(sc, FEC_IER_REG) & FEC_IER_MII)
313 return (true);
314
315 return (false);
316 }
317
318 static int
319 ffec_miibus_readreg(device_t dev, int phy, int reg)
320 {
321 struct ffec_softc *sc;
322 int val;
323
324 sc = device_get_softc(dev);
325
326 WR4(sc, FEC_IER_REG, FEC_IER_MII);
327
328 WR4(sc, FEC_MMFR_REG, FEC_MMFR_OP_READ |
329 FEC_MMFR_ST_VALUE | FEC_MMFR_TA_VALUE |
330 ((phy << FEC_MMFR_PA_SHIFT) & FEC_MMFR_PA_MASK) |
331 ((reg << FEC_MMFR_RA_SHIFT) & FEC_MMFR_RA_MASK));
332
333 if (!ffec_miibus_iowait(sc)) {
334 device_printf(dev, "timeout waiting for mii read\n");
335 return (-1); /* All-ones is a symptom of bad mdio. */
336 }
337
338 val = RD4(sc, FEC_MMFR_REG) & FEC_MMFR_DATA_MASK;
339
340 return (val);
341 }
342
343 static int
344 ffec_miibus_writereg(device_t dev, int phy, int reg, int val)
345 {
346 struct ffec_softc *sc;
347
348 sc = device_get_softc(dev);
349
350 WR4(sc, FEC_IER_REG, FEC_IER_MII);
351
352 WR4(sc, FEC_MMFR_REG, FEC_MMFR_OP_WRITE |
353 FEC_MMFR_ST_VALUE | FEC_MMFR_TA_VALUE |
354 ((phy << FEC_MMFR_PA_SHIFT) & FEC_MMFR_PA_MASK) |
355 ((reg << FEC_MMFR_RA_SHIFT) & FEC_MMFR_RA_MASK) |
356 (val & FEC_MMFR_DATA_MASK));
357
358 if (!ffec_miibus_iowait(sc)) {
359 device_printf(dev, "timeout waiting for mii write\n");
360 return (-1);
361 }
362
363 return (0);
364 }
365
366 static void
367 ffec_miibus_statchg(device_t dev)
368 {
369 struct ffec_softc *sc;
370 struct mii_data *mii;
371 uint32_t ecr, rcr, tcr;
372
373 /*
374 * Called by the MII bus driver when the PHY establishes link to set the
375 * MAC interface registers.
376 */
377
378 sc = device_get_softc(dev);
379
380 FFEC_ASSERT_LOCKED(sc);
381
382 mii = sc->mii_softc;
383
384 if (mii->mii_media_status & IFM_ACTIVE)
385 sc->link_is_up = true;
386 else
387 sc->link_is_up = false;
388
389 ecr = RD4(sc, FEC_ECR_REG) & ~FEC_ECR_SPEED;
390 rcr = RD4(sc, FEC_RCR_REG) & ~(FEC_RCR_RMII_10T | FEC_RCR_RMII_MODE |
391 FEC_RCR_RGMII_EN | FEC_RCR_DRT | FEC_RCR_FCE);
392 tcr = RD4(sc, FEC_TCR_REG) & ~FEC_TCR_FDEN;
393
394 rcr |= FEC_RCR_MII_MODE; /* Must always be on even for R[G]MII. */
395 switch (sc->phy_conn_type) {
396 case MII_CONTYPE_RMII:
397 rcr |= FEC_RCR_RMII_MODE;
398 break;
399 case MII_CONTYPE_RGMII:
400 case MII_CONTYPE_RGMII_ID:
401 case MII_CONTYPE_RGMII_RXID:
402 case MII_CONTYPE_RGMII_TXID:
403 rcr |= FEC_RCR_RGMII_EN;
404 break;
405 default:
406 break;
407 }
408
409 switch (IFM_SUBTYPE(mii->mii_media_active)) {
410 case IFM_1000_T:
411 case IFM_1000_SX:
412 ecr |= FEC_ECR_SPEED;
413 break;
414 case IFM_100_TX:
415 /* Not-FEC_ECR_SPEED + not-FEC_RCR_RMII_10T means 100TX */
416 break;
417 case IFM_10_T:
418 rcr |= FEC_RCR_RMII_10T;
419 break;
420 case IFM_NONE:
421 sc->link_is_up = false;
422 return;
423 default:
424 sc->link_is_up = false;
425 device_printf(dev, "Unsupported media %u\n",
426 IFM_SUBTYPE(mii->mii_media_active));
427 return;
428 }
429
430 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0)
431 tcr |= FEC_TCR_FDEN;
432 else
433 rcr |= FEC_RCR_DRT;
434
435 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FLOW) != 0)
436 rcr |= FEC_RCR_FCE;
437
438 WR4(sc, FEC_RCR_REG, rcr);
439 WR4(sc, FEC_TCR_REG, tcr);
440 WR4(sc, FEC_ECR_REG, ecr);
441 }
442
443 static void
444 ffec_media_status(struct ifnet * ifp, struct ifmediareq *ifmr)
445 {
446 struct ffec_softc *sc;
447 struct mii_data *mii;
448
449
450 sc = ifp->if_softc;
451 mii = sc->mii_softc;
452 FFEC_LOCK(sc);
453 mii_pollstat(mii);
454 ifmr->ifm_active = mii->mii_media_active;
455 ifmr->ifm_status = mii->mii_media_status;
456 FFEC_UNLOCK(sc);
457 }
458
459 static int
460 ffec_media_change_locked(struct ffec_softc *sc)
461 {
462
463 return (mii_mediachg(sc->mii_softc));
464 }
465
466 static int
467 ffec_media_change(struct ifnet * ifp)
468 {
469 struct ffec_softc *sc;
470 int error;
471
472 sc = ifp->if_softc;
473
474 FFEC_LOCK(sc);
475 error = ffec_media_change_locked(sc);
476 FFEC_UNLOCK(sc);
477 return (error);
478 }
479
480 static void ffec_clear_stats(struct ffec_softc *sc)
481 {
482 uint32_t mibc;
483
484 mibc = RD4(sc, FEC_MIBC_REG);
485
486 /*
487 * On newer hardware the statistic regs are cleared by toggling a bit in
488 * the mib control register. On older hardware the clear procedure is
489 * to disable statistics collection, zero the regs, then re-enable.
490 */
491 if (sc->fectype == FECTYPE_IMX6 || sc->fectype == FECTYPE_MVF) {
492 WR4(sc, FEC_MIBC_REG, mibc | FEC_MIBC_CLEAR);
493 WR4(sc, FEC_MIBC_REG, mibc & ~FEC_MIBC_CLEAR);
494 } else {
495 WR4(sc, FEC_MIBC_REG, mibc | FEC_MIBC_DIS);
496
497 WR4(sc, FEC_IEEE_R_DROP, 0);
498 WR4(sc, FEC_IEEE_R_MACERR, 0);
499 WR4(sc, FEC_RMON_R_CRC_ALIGN, 0);
500 WR4(sc, FEC_RMON_R_FRAG, 0);
501 WR4(sc, FEC_RMON_R_JAB, 0);
502 WR4(sc, FEC_RMON_R_MC_PKT, 0);
503 WR4(sc, FEC_RMON_R_OVERSIZE, 0);
504 WR4(sc, FEC_RMON_R_PACKETS, 0);
505 WR4(sc, FEC_RMON_R_UNDERSIZE, 0);
506 WR4(sc, FEC_RMON_T_COL, 0);
507 WR4(sc, FEC_RMON_T_CRC_ALIGN, 0);
508 WR4(sc, FEC_RMON_T_FRAG, 0);
509 WR4(sc, FEC_RMON_T_JAB, 0);
510 WR4(sc, FEC_RMON_T_MC_PKT, 0);
511 WR4(sc, FEC_RMON_T_OVERSIZE , 0);
512 WR4(sc, FEC_RMON_T_PACKETS, 0);
513 WR4(sc, FEC_RMON_T_UNDERSIZE, 0);
514
515 WR4(sc, FEC_MIBC_REG, mibc);
516 }
517 }
518
519 static void
520 ffec_harvest_stats(struct ffec_softc *sc)
521 {
522 struct ifnet *ifp;
523
524 ifp = sc->ifp;
525
526 /*
527 * - FEC_IEEE_R_DROP is "dropped due to invalid start frame delimiter"
528 * so it's really just another type of input error.
529 * - FEC_IEEE_R_MACERR is "no receive fifo space"; count as input drops.
530 */
531 if_inc_counter(ifp, IFCOUNTER_IPACKETS, RD4(sc, FEC_RMON_R_PACKETS));
532 if_inc_counter(ifp, IFCOUNTER_IMCASTS, RD4(sc, FEC_RMON_R_MC_PKT));
533 if_inc_counter(ifp, IFCOUNTER_IERRORS,
534 RD4(sc, FEC_RMON_R_CRC_ALIGN) + RD4(sc, FEC_RMON_R_UNDERSIZE) +
535 RD4(sc, FEC_RMON_R_OVERSIZE) + RD4(sc, FEC_RMON_R_FRAG) +
536 RD4(sc, FEC_RMON_R_JAB) + RD4(sc, FEC_IEEE_R_DROP));
537
538 if_inc_counter(ifp, IFCOUNTER_IQDROPS, RD4(sc, FEC_IEEE_R_MACERR));
539
540 if_inc_counter(ifp, IFCOUNTER_OPACKETS, RD4(sc, FEC_RMON_T_PACKETS));
541 if_inc_counter(ifp, IFCOUNTER_OMCASTS, RD4(sc, FEC_RMON_T_MC_PKT));
542 if_inc_counter(ifp, IFCOUNTER_OERRORS,
543 RD4(sc, FEC_RMON_T_CRC_ALIGN) + RD4(sc, FEC_RMON_T_UNDERSIZE) +
544 RD4(sc, FEC_RMON_T_OVERSIZE) + RD4(sc, FEC_RMON_T_FRAG) +
545 RD4(sc, FEC_RMON_T_JAB));
546
547 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, RD4(sc, FEC_RMON_T_COL));
548
549 ffec_clear_stats(sc);
550 }
551
552 static void
553 ffec_tick(void *arg)
554 {
555 struct ffec_softc *sc;
556 struct ifnet *ifp;
557 int link_was_up;
558
559 sc = arg;
560
561 FFEC_ASSERT_LOCKED(sc);
562
563 ifp = sc->ifp;
564
565 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
566 return;
567
568 /*
569 * Typical tx watchdog. If this fires it indicates that we enqueued
570 * packets for output and never got a txdone interrupt for them. Maybe
571 * it's a missed interrupt somehow, just pretend we got one.
572 */
573 if (sc->tx_watchdog_count > 0) {
574 if (--sc->tx_watchdog_count == 0) {
575 ffec_txfinish_locked(sc);
576 }
577 }
578
579 /* Gather stats from hardware counters. */
580 ffec_harvest_stats(sc);
581
582 /* Check the media status. */
583 link_was_up = sc->link_is_up;
584 mii_tick(sc->mii_softc);
585 if (sc->link_is_up && !link_was_up)
586 ffec_txstart_locked(sc);
587
588 /* Schedule another check one second from now. */
589 callout_reset(&sc->ffec_callout, hz, ffec_tick, sc);
590 }
591
592 inline static uint32_t
593 ffec_setup_txdesc(struct ffec_softc *sc, int idx, bus_addr_t paddr,
594 uint32_t len)
595 {
596 uint32_t nidx;
597 uint32_t flags;
598
599 nidx = next_txidx(sc, idx);
600
601 /* Addr/len 0 means we're clearing the descriptor after xmit done. */
602 if (paddr == 0 || len == 0) {
603 flags = 0;
604 --sc->txcount;
605 } else {
606 flags = FEC_TXDESC_READY | FEC_TXDESC_L | FEC_TXDESC_TC;
607 ++sc->txcount;
608 }
609 if (nidx == 0)
610 flags |= FEC_TXDESC_WRAP;
611
612 /*
613 * The hardware requires 32-bit physical addresses. We set up the dma
614 * tag to indicate that, so the cast to uint32_t should never lose
615 * significant bits.
616 */
617 sc->txdesc_ring[idx].buf_paddr = (uint32_t)paddr;
618 sc->txdesc_ring[idx].flags_len = flags | len; /* Must be set last! */
619
620 return (nidx);
621 }
622
623 static int
624 ffec_setup_txbuf(struct ffec_softc *sc, int idx, struct mbuf **mp)
625 {
626 struct mbuf * m;
627 int error, nsegs;
628 struct bus_dma_segment seg;
629
630 if ((m = m_defrag(*mp, M_NOWAIT)) == NULL)
631 return (ENOMEM);
632 *mp = m;
633
634 error = bus_dmamap_load_mbuf_sg(sc->txbuf_tag, sc->txbuf_map[idx].map,
635 m, &seg, &nsegs, 0);
636 if (error != 0) {
637 return (ENOMEM);
638 }
639 bus_dmamap_sync(sc->txbuf_tag, sc->txbuf_map[idx].map,
640 BUS_DMASYNC_PREWRITE);
641
642 sc->txbuf_map[idx].mbuf = m;
643 ffec_setup_txdesc(sc, idx, seg.ds_addr, seg.ds_len);
644
645 return (0);
646
647 }
648
649 static void
650 ffec_txstart_locked(struct ffec_softc *sc)
651 {
652 struct ifnet *ifp;
653 struct mbuf *m;
654 int enqueued;
655
656 FFEC_ASSERT_LOCKED(sc);
657
658 if (!sc->link_is_up)
659 return;
660
661 ifp = sc->ifp;
662
663 if (ifp->if_drv_flags & IFF_DRV_OACTIVE)
664 return;
665
666 enqueued = 0;
667
668 for (;;) {
669 if (sc->txcount == (TX_DESC_COUNT-1)) {
670 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
671 break;
672 }
673 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
674 if (m == NULL)
675 break;
676 if (ffec_setup_txbuf(sc, sc->tx_idx_head, &m) != 0) {
677 IFQ_DRV_PREPEND(&ifp->if_snd, m);
678 break;
679 }
680 BPF_MTAP(ifp, m);
681 sc->tx_idx_head = next_txidx(sc, sc->tx_idx_head);
682 ++enqueued;
683 }
684
685 if (enqueued != 0) {
686 bus_dmamap_sync(sc->txdesc_tag, sc->txdesc_map, BUS_DMASYNC_PREWRITE);
687 WR4(sc, FEC_TDAR_REG, FEC_TDAR_TDAR);
688 bus_dmamap_sync(sc->txdesc_tag, sc->txdesc_map, BUS_DMASYNC_POSTWRITE);
689 sc->tx_watchdog_count = WATCHDOG_TIMEOUT_SECS;
690 }
691 }
692
693 static void
694 ffec_txstart(struct ifnet *ifp)
695 {
696 struct ffec_softc *sc = ifp->if_softc;
697
698 FFEC_LOCK(sc);
699 ffec_txstart_locked(sc);
700 FFEC_UNLOCK(sc);
701 }
702
703 static void
704 ffec_txfinish_locked(struct ffec_softc *sc)
705 {
706 struct ifnet *ifp;
707 struct ffec_hwdesc *desc;
708 struct ffec_bufmap *bmap;
709 boolean_t retired_buffer;
710
711 FFEC_ASSERT_LOCKED(sc);
712
713 /* XXX Can't set PRE|POST right now, but we need both. */
714 bus_dmamap_sync(sc->txdesc_tag, sc->txdesc_map, BUS_DMASYNC_PREREAD);
715 bus_dmamap_sync(sc->txdesc_tag, sc->txdesc_map, BUS_DMASYNC_POSTREAD);
716 ifp = sc->ifp;
717 retired_buffer = false;
718 while (sc->tx_idx_tail != sc->tx_idx_head) {
719 desc = &sc->txdesc_ring[sc->tx_idx_tail];
720 if (desc->flags_len & FEC_TXDESC_READY)
721 break;
722 retired_buffer = true;
723 bmap = &sc->txbuf_map[sc->tx_idx_tail];
724 bus_dmamap_sync(sc->txbuf_tag, bmap->map,
725 BUS_DMASYNC_POSTWRITE);
726 bus_dmamap_unload(sc->txbuf_tag, bmap->map);
727 m_freem(bmap->mbuf);
728 bmap->mbuf = NULL;
729 ffec_setup_txdesc(sc, sc->tx_idx_tail, 0, 0);
730 sc->tx_idx_tail = next_txidx(sc, sc->tx_idx_tail);
731 }
732
733 /*
734 * If we retired any buffers, there will be open tx slots available in
735 * the descriptor ring, go try to start some new output.
736 */
737 if (retired_buffer) {
738 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
739 ffec_txstart_locked(sc);
740 }
741
742 /* If there are no buffers outstanding, muzzle the watchdog. */
743 if (sc->tx_idx_tail == sc->tx_idx_head) {
744 sc->tx_watchdog_count = 0;
745 }
746 }
747
748 inline static uint32_t
749 ffec_setup_rxdesc(struct ffec_softc *sc, int idx, bus_addr_t paddr)
750 {
751 uint32_t nidx;
752
753 /*
754 * The hardware requires 32-bit physical addresses. We set up the dma
755 * tag to indicate that, so the cast to uint32_t should never lose
756 * significant bits.
757 */
758 nidx = next_rxidx(sc, idx);
759 sc->rxdesc_ring[idx].buf_paddr = (uint32_t)paddr;
760 sc->rxdesc_ring[idx].flags_len = FEC_RXDESC_EMPTY |
761 ((nidx == 0) ? FEC_RXDESC_WRAP : 0);
762
763 return (nidx);
764 }
765
766 static int
767 ffec_setup_rxbuf(struct ffec_softc *sc, int idx, struct mbuf * m)
768 {
769 int error, nsegs;
770 struct bus_dma_segment seg;
771
772 if (!(sc->fecflags & FECFLAG_RACC)) {
773 /*
774 * The RACC[SHIFT16] feature is not available. So, we need to
775 * leave at least ETHER_ALIGN bytes free at the beginning of the
776 * buffer to allow the data to be re-aligned after receiving it
777 * (by copying it backwards ETHER_ALIGN bytes in the same
778 * buffer). We also have to ensure that the beginning of the
779 * buffer is aligned to the hardware's requirements.
780 */
781 m_adj(m, roundup(ETHER_ALIGN, sc->rxbuf_align));
782 }
783
784 error = bus_dmamap_load_mbuf_sg(sc->rxbuf_tag, sc->rxbuf_map[idx].map,
785 m, &seg, &nsegs, 0);
786 if (error != 0) {
787 return (error);
788 }
789
790 bus_dmamap_sync(sc->rxbuf_tag, sc->rxbuf_map[idx].map,
791 BUS_DMASYNC_PREREAD);
792
793 sc->rxbuf_map[idx].mbuf = m;
794 ffec_setup_rxdesc(sc, idx, seg.ds_addr);
795
796 return (0);
797 }
798
799 static struct mbuf *
800 ffec_alloc_mbufcl(struct ffec_softc *sc)
801 {
802 struct mbuf *m;
803
804 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
805 if (m != NULL)
806 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size;
807
808 return (m);
809 }
810
811 static void
812 ffec_rxfinish_onebuf(struct ffec_softc *sc, int len)
813 {
814 struct mbuf *m, *newmbuf;
815 struct ffec_bufmap *bmap;
816 uint8_t *dst, *src;
817 int error;
818
819 /*
820 * First try to get a new mbuf to plug into this slot in the rx ring.
821 * If that fails, drop the current packet and recycle the current
822 * mbuf, which is still mapped and loaded.
823 */
824 if ((newmbuf = ffec_alloc_mbufcl(sc)) == NULL) {
825 if_inc_counter(sc->ifp, IFCOUNTER_IQDROPS, 1);
826 ffec_setup_rxdesc(sc, sc->rx_idx,
827 sc->rxdesc_ring[sc->rx_idx].buf_paddr);
828 return;
829 }
830
831 FFEC_UNLOCK(sc);
832
833 bmap = &sc->rxbuf_map[sc->rx_idx];
834 len -= ETHER_CRC_LEN;
835 bus_dmamap_sync(sc->rxbuf_tag, bmap->map, BUS_DMASYNC_POSTREAD);
836 bus_dmamap_unload(sc->rxbuf_tag, bmap->map);
837 m = bmap->mbuf;
838 bmap->mbuf = NULL;
839 m->m_len = len;
840 m->m_pkthdr.len = len;
841 m->m_pkthdr.rcvif = sc->ifp;
842
843 /*
844 * Align the protocol headers in the receive buffer on a 32-bit
845 * boundary. Newer hardware does the alignment for us. On hardware
846 * that doesn't support this feature, we have to copy-align the data.
847 *
848 * XXX for older hardware, could we speed this up by copying just the
849 * protocol headers into their own small mbuf then chaining the cluster
850 * to it? That way we'd only need to copy like 64 bytes or whatever the
851 * biggest header is, instead of the whole 1530ish-byte frame.
852 */
853 if (sc->fecflags & FECFLAG_RACC) {
854 m->m_data = mtod(m, uint8_t *) + 2;
855 } else {
856 src = mtod(m, uint8_t*);
857 dst = src - ETHER_ALIGN;
858 bcopy(src, dst, len);
859 m->m_data = dst;
860 }
861 sc->ifp->if_input(sc->ifp, m);
862
863 FFEC_LOCK(sc);
864
865 if ((error = ffec_setup_rxbuf(sc, sc->rx_idx, newmbuf)) != 0) {
866 device_printf(sc->dev, "ffec_setup_rxbuf error %d\n", error);
867 /* XXX Now what? We've got a hole in the rx ring. */
868 }
869
870 }
871
872 static void
873 ffec_rxfinish_locked(struct ffec_softc *sc)
874 {
875 struct ffec_hwdesc *desc;
876 int len;
877 boolean_t produced_empty_buffer;
878
879 FFEC_ASSERT_LOCKED(sc);
880
881 /* XXX Can't set PRE|POST right now, but we need both. */
882 bus_dmamap_sync(sc->rxdesc_tag, sc->rxdesc_map, BUS_DMASYNC_PREREAD);
883 bus_dmamap_sync(sc->rxdesc_tag, sc->rxdesc_map, BUS_DMASYNC_POSTREAD);
884 produced_empty_buffer = false;
885 for (;;) {
886 desc = &sc->rxdesc_ring[sc->rx_idx];
887 if (desc->flags_len & FEC_RXDESC_EMPTY)
888 break;
889 produced_empty_buffer = true;
890 len = (desc->flags_len & FEC_RXDESC_LEN_MASK);
891 if (len < 64) {
892 /*
893 * Just recycle the descriptor and continue. .
894 */
895 ffec_setup_rxdesc(sc, sc->rx_idx,
896 sc->rxdesc_ring[sc->rx_idx].buf_paddr);
897 } else if ((desc->flags_len & FEC_RXDESC_L) == 0) {
898 /*
899 * The entire frame is not in this buffer. Impossible.
900 * Recycle the descriptor and continue.
901 *
902 * XXX what's the right way to handle this? Probably we
903 * should stop/init the hardware because this should
904 * just really never happen when we have buffers bigger
905 * than the maximum frame size.
906 */
907 device_printf(sc->dev,
908 "fec_rxfinish: received frame without LAST bit set");
909 ffec_setup_rxdesc(sc, sc->rx_idx,
910 sc->rxdesc_ring[sc->rx_idx].buf_paddr);
911 } else if (desc->flags_len & FEC_RXDESC_ERROR_BITS) {
912 /*
913 * Something went wrong with receiving the frame, we
914 * don't care what (the hardware has counted the error
915 * in the stats registers already), we just reuse the
916 * same mbuf, which is still dma-mapped, by resetting
917 * the rx descriptor.
918 */
919 ffec_setup_rxdesc(sc, sc->rx_idx,
920 sc->rxdesc_ring[sc->rx_idx].buf_paddr);
921 } else {
922 /*
923 * Normal case: a good frame all in one buffer.
924 */
925 ffec_rxfinish_onebuf(sc, len);
926 }
927 sc->rx_idx = next_rxidx(sc, sc->rx_idx);
928 }
929
930 if (produced_empty_buffer) {
931 bus_dmamap_sync(sc->rxdesc_tag, sc->rxdesc_map, BUS_DMASYNC_PREWRITE);
932 WR4(sc, FEC_RDAR_REG, FEC_RDAR_RDAR);
933 bus_dmamap_sync(sc->rxdesc_tag, sc->rxdesc_map, BUS_DMASYNC_POSTWRITE);
934 }
935 }
936
937 static void
938 ffec_get_hwaddr(struct ffec_softc *sc, uint8_t *hwaddr)
939 {
940 uint32_t palr, paur, rnd;
941
942 /*
943 * Try to recover a MAC address from the running hardware. If there's
944 * something non-zero there, assume the bootloader did the right thing
945 * and just use it.
946 *
947 * Otherwise, set the address to a convenient locally assigned address,
948 * 'bsd' + random 24 low-order bits. 'b' is 0x62, which has the locally
949 * assigned bit set, and the broadcast/multicast bit clear.
950 */
951 palr = RD4(sc, FEC_PALR_REG);
952 paur = RD4(sc, FEC_PAUR_REG) & FEC_PAUR_PADDR2_MASK;
953 if ((palr | paur) != 0) {
954 hwaddr[0] = palr >> 24;
955 hwaddr[1] = palr >> 16;
956 hwaddr[2] = palr >> 8;
957 hwaddr[3] = palr >> 0;
958 hwaddr[4] = paur >> 24;
959 hwaddr[5] = paur >> 16;
960 } else {
961 rnd = arc4random() & 0x00ffffff;
962 hwaddr[0] = 'b';
963 hwaddr[1] = 's';
964 hwaddr[2] = 'd';
965 hwaddr[3] = rnd >> 16;
966 hwaddr[4] = rnd >> 8;
967 hwaddr[5] = rnd >> 0;
968 }
969
970 if (bootverbose) {
971 device_printf(sc->dev,
972 "MAC address %02x:%02x:%02x:%02x:%02x:%02x:\n",
973 hwaddr[0], hwaddr[1], hwaddr[2],
974 hwaddr[3], hwaddr[4], hwaddr[5]);
975 }
976 }
977
978 static u_int
979 ffec_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt)
980 {
981 uint64_t *ghash = arg;
982 uint32_t crc;
983
984 /* 6 bits from MSB in LE CRC32 are used for hash. */
985 crc = ether_crc32_le(LLADDR(sdl), ETHER_ADDR_LEN);
986 *ghash |= 1LLU << (((uint8_t *)&crc)[3] >> 2);
987
988 return (1);
989 }
990
991 static void
992 ffec_setup_rxfilter(struct ffec_softc *sc)
993 {
994 struct ifnet *ifp;
995 uint8_t *eaddr;
996 uint64_t ghash, ihash;
997
998 FFEC_ASSERT_LOCKED(sc);
999
1000 ifp = sc->ifp;
1001
1002 /*
1003 * Set the multicast (group) filter hash.
1004 */
1005 if ((ifp->if_flags & IFF_ALLMULTI))
1006 ghash = 0xffffffffffffffffLLU;
1007 else {
1008 ghash = 0;
1009 if_foreach_llmaddr(ifp, ffec_hash_maddr, &ghash);
1010 }
1011 WR4(sc, FEC_GAUR_REG, (uint32_t)(ghash >> 32));
1012 WR4(sc, FEC_GALR_REG, (uint32_t)ghash);
1013
1014 /*
1015 * Set the individual address filter hash.
1016 *
1017 * XXX Is 0 the right value when promiscuous is off? This hw feature
1018 * seems to support the concept of MAC address aliases, does such a
1019 * thing even exist?
1020 */
1021 if ((ifp->if_flags & IFF_PROMISC))
1022 ihash = 0xffffffffffffffffLLU;
1023 else {
1024 ihash = 0;
1025 }
1026 WR4(sc, FEC_IAUR_REG, (uint32_t)(ihash >> 32));
1027 WR4(sc, FEC_IALR_REG, (uint32_t)ihash);
1028
1029 /*
1030 * Set the primary address.
1031 */
1032 eaddr = IF_LLADDR(ifp);
1033 WR4(sc, FEC_PALR_REG, (eaddr[0] << 24) | (eaddr[1] << 16) |
1034 (eaddr[2] << 8) | eaddr[3]);
1035 WR4(sc, FEC_PAUR_REG, (eaddr[4] << 24) | (eaddr[5] << 16));
1036 }
1037
1038 static void
1039 ffec_stop_locked(struct ffec_softc *sc)
1040 {
1041 struct ifnet *ifp;
1042 struct ffec_hwdesc *desc;
1043 struct ffec_bufmap *bmap;
1044 int idx;
1045
1046 FFEC_ASSERT_LOCKED(sc);
1047
1048 ifp = sc->ifp;
1049 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1050 sc->tx_watchdog_count = 0;
1051
1052 /*
1053 * Stop the hardware, mask all interrupts, and clear all current
1054 * interrupt status bits.
1055 */
1056 WR4(sc, FEC_ECR_REG, RD4(sc, FEC_ECR_REG) & ~FEC_ECR_ETHEREN);
1057 WR4(sc, FEC_IEM_REG, 0x00000000);
1058 WR4(sc, FEC_IER_REG, 0xffffffff);
1059
1060 /*
1061 * Stop the media-check callout. Do not use callout_drain() because
1062 * we're holding a mutex the callout acquires, and if it's currently
1063 * waiting to acquire it, we'd deadlock. If it is waiting now, the
1064 * ffec_tick() routine will return without doing anything when it sees
1065 * that IFF_DRV_RUNNING is not set, so avoiding callout_drain() is safe.
1066 */
1067 callout_stop(&sc->ffec_callout);
1068
1069 /*
1070 * Discard all untransmitted buffers. Each buffer is simply freed;
1071 * it's as if the bits were transmitted and then lost on the wire.
1072 *
1073 * XXX Is this right? Or should we use IFQ_DRV_PREPEND() to put them
1074 * back on the queue for when we get restarted later?
1075 */
1076 idx = sc->tx_idx_tail;
1077 while (idx != sc->tx_idx_head) {
1078 desc = &sc->txdesc_ring[idx];
1079 bmap = &sc->txbuf_map[idx];
1080 if (desc->buf_paddr != 0) {
1081 bus_dmamap_unload(sc->txbuf_tag, bmap->map);
1082 m_freem(bmap->mbuf);
1083 bmap->mbuf = NULL;
1084 ffec_setup_txdesc(sc, idx, 0, 0);
1085 }
1086 idx = next_txidx(sc, idx);
1087 }
1088
1089 /*
1090 * Discard all unprocessed receive buffers. This amounts to just
1091 * pretending that nothing ever got received into them. We reuse the
1092 * mbuf already mapped for each desc, simply turning the EMPTY flags
1093 * back on so they'll get reused when we start up again.
1094 */
1095 for (idx = 0; idx < RX_DESC_COUNT; ++idx) {
1096 desc = &sc->rxdesc_ring[idx];
1097 ffec_setup_rxdesc(sc, idx, desc->buf_paddr);
1098 }
1099 }
1100
1101 static void
1102 ffec_init_locked(struct ffec_softc *sc)
1103 {
1104 struct ifnet *ifp = sc->ifp;
1105 uint32_t maxbuf, maxfl, regval;
1106
1107 FFEC_ASSERT_LOCKED(sc);
1108
1109 /*
1110 * The hardware has a limit of 0x7ff as the max frame length (see
1111 * comments for MRBR below), and we use mbuf clusters as receive
1112 * buffers, and we currently are designed to receive an entire frame
1113 * into a single buffer.
1114 *
1115 * We start with a MCLBYTES-sized cluster, but we have to offset into
1116 * the buffer by ETHER_ALIGN to make room for post-receive re-alignment,
1117 * and then that value has to be rounded up to the hardware's DMA
1118 * alignment requirements, so all in all our buffer is that much smaller
1119 * than MCLBYTES.
1120 *
1121 * The resulting value is used as the frame truncation length and the
1122 * max buffer receive buffer size for now. It'll become more complex
1123 * when we support jumbo frames and receiving fragments of them into
1124 * separate buffers.
1125 */
1126 maxbuf = MCLBYTES - roundup(ETHER_ALIGN, sc->rxbuf_align);
1127 maxfl = min(maxbuf, 0x7ff);
1128
1129 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1130 return;
1131
1132 /* Mask all interrupts and clear all current interrupt status bits. */
1133 WR4(sc, FEC_IEM_REG, 0x00000000);
1134 WR4(sc, FEC_IER_REG, 0xffffffff);
1135
1136 /*
1137 * Go set up palr/puar, galr/gaur, ialr/iaur.
1138 */
1139 ffec_setup_rxfilter(sc);
1140
1141 /*
1142 * TFWR - Transmit FIFO watermark register.
1143 *
1144 * Set the transmit fifo watermark register to "store and forward" mode
1145 * and also set a threshold of 128 bytes in the fifo before transmission
1146 * of a frame begins (to avoid dma underruns). Recent FEC hardware
1147 * supports STRFWD and when that bit is set, the watermark level in the
1148 * low bits is ignored. Older hardware doesn't have STRFWD, but writing
1149 * to that bit is innocuous, and the TWFR bits get used instead.
1150 */
1151 WR4(sc, FEC_TFWR_REG, FEC_TFWR_STRFWD | FEC_TFWR_TWFR_128BYTE);
1152
1153 /* RCR - Receive control register.
1154 *
1155 * Set max frame length + clean out anything left from u-boot.
1156 */
1157 WR4(sc, FEC_RCR_REG, (maxfl << FEC_RCR_MAX_FL_SHIFT));
1158
1159 /*
1160 * TCR - Transmit control register.
1161 *
1162 * Clean out anything left from u-boot. Any necessary values are set in
1163 * ffec_miibus_statchg() based on the media type.
1164 */
1165 WR4(sc, FEC_TCR_REG, 0);
1166
1167 /*
1168 * OPD - Opcode/pause duration.
1169 *
1170 * XXX These magic numbers come from u-boot.
1171 */
1172 WR4(sc, FEC_OPD_REG, 0x00010020);
1173
1174 /*
1175 * FRSR - Fifo receive start register.
1176 *
1177 * This register does not exist on imx6, it is present on earlier
1178 * hardware. The u-boot code sets this to a non-default value that's 32
1179 * bytes larger than the default, with no clue as to why. The default
1180 * value should work fine, so there's no code to init it here.
1181 */
1182
1183 /*
1184 * MRBR - Max RX buffer size.
1185 *
1186 * Note: For hardware prior to imx6 this value cannot exceed 0x07ff,
1187 * but the datasheet says no such thing for imx6. On the imx6, setting
1188 * this to 2K without setting EN1588 resulted in a crazy runaway
1189 * receive loop in the hardware, where every rx descriptor in the ring
1190 * had its EMPTY flag cleared, no completion or error flags set, and a
1191 * length of zero. I think maybe you can only exceed it when EN1588 is
1192 * set, like maybe that's what enables jumbo frames, because in general
1193 * the EN1588 flag seems to be the "enable new stuff" vs. "be legacy-
1194 * compatible" flag.
1195 */
1196 WR4(sc, FEC_MRBR_REG, maxfl << FEC_MRBR_R_BUF_SIZE_SHIFT);
1197
1198 /*
1199 * FTRL - Frame truncation length.
1200 *
1201 * Must be greater than or equal to the value set in FEC_RCR_MAXFL.
1202 */
1203 WR4(sc, FEC_FTRL_REG, maxfl);
1204
1205 /*
1206 * RDSR / TDSR descriptor ring pointers.
1207 *
1208 * When we turn on ECR_ETHEREN at the end, the hardware zeroes its
1209 * internal current descriptor index values for both rings, so we zero
1210 * our index values as well.
1211 */
1212 sc->rx_idx = 0;
1213 sc->tx_idx_head = sc->tx_idx_tail = 0;
1214 sc->txcount = 0;
1215 WR4(sc, FEC_RDSR_REG, sc->rxdesc_ring_paddr);
1216 WR4(sc, FEC_TDSR_REG, sc->txdesc_ring_paddr);
1217
1218 /*
1219 * EIM - interrupt mask register.
1220 *
1221 * We always enable the same set of interrupts while running; unlike
1222 * some drivers there's no need to change the mask on the fly depending
1223 * on what operations are in progress.
1224 */
1225 WR4(sc, FEC_IEM_REG, FEC_IER_TXF | FEC_IER_RXF | FEC_IER_EBERR);
1226
1227 /*
1228 * MIBC - MIB control (hardware stats); clear all statistics regs, then
1229 * enable collection of statistics.
1230 */
1231 regval = RD4(sc, FEC_MIBC_REG);
1232 WR4(sc, FEC_MIBC_REG, regval | FEC_MIBC_DIS);
1233 ffec_clear_stats(sc);
1234 WR4(sc, FEC_MIBC_REG, regval & ~FEC_MIBC_DIS);
1235
1236 if (sc->fecflags & FECFLAG_RACC) {
1237 /*
1238 * RACC - Receive Accelerator Function Configuration.
1239 */
1240 regval = RD4(sc, FEC_RACC_REG);
1241 WR4(sc, FEC_RACC_REG, regval | FEC_RACC_SHIFT16);
1242 }
1243
1244 /*
1245 * ECR - Ethernet control register.
1246 *
1247 * This must happen after all the other config registers are set. If
1248 * we're running on little-endian hardware, also set the flag for byte-
1249 * swapping descriptor ring entries. This flag doesn't exist on older
1250 * hardware, but it can be safely set -- the bit position it occupies
1251 * was unused.
1252 */
1253 regval = RD4(sc, FEC_ECR_REG);
1254 #if _BYTE_ORDER == _LITTLE_ENDIAN
1255 regval |= FEC_ECR_DBSWP;
1256 #endif
1257 regval |= FEC_ECR_ETHEREN;
1258 WR4(sc, FEC_ECR_REG, regval);
1259
1260 ifp->if_drv_flags |= IFF_DRV_RUNNING;
1261
1262 /*
1263 * Call mii_mediachg() which will call back into ffec_miibus_statchg() to
1264 * set up the remaining config registers based on the current media.
1265 */
1266 mii_mediachg(sc->mii_softc);
1267 callout_reset(&sc->ffec_callout, hz, ffec_tick, sc);
1268
1269 /*
1270 * Tell the hardware that receive buffers are available. They were made
1271 * available in ffec_attach() or ffec_stop().
1272 */
1273 WR4(sc, FEC_RDAR_REG, FEC_RDAR_RDAR);
1274 }
1275
1276 static void
1277 ffec_init(void *if_softc)
1278 {
1279 struct ffec_softc *sc = if_softc;
1280
1281 FFEC_LOCK(sc);
1282 ffec_init_locked(sc);
1283 FFEC_UNLOCK(sc);
1284 }
1285
1286 static void
1287 ffec_intr(void *arg)
1288 {
1289 struct ffec_softc *sc;
1290 uint32_t ier;
1291
1292 sc = arg;
1293
1294 FFEC_LOCK(sc);
1295
1296 ier = RD4(sc, FEC_IER_REG);
1297
1298 if (ier & FEC_IER_TXF) {
1299 WR4(sc, FEC_IER_REG, FEC_IER_TXF);
1300 ffec_txfinish_locked(sc);
1301 }
1302
1303 if (ier & FEC_IER_RXF) {
1304 WR4(sc, FEC_IER_REG, FEC_IER_RXF);
1305 ffec_rxfinish_locked(sc);
1306 }
1307
1308 /*
1309 * We actually don't care about most errors, because the hardware copes
1310 * with them just fine, discarding the incoming bad frame, or forcing a
1311 * bad CRC onto an outgoing bad frame, and counting the errors in the
1312 * stats registers. The one that really matters is EBERR (DMA bus
1313 * error) because the hardware automatically clears ECR[ETHEREN] and we
1314 * have to restart it here. It should never happen.
1315 */
1316 if (ier & FEC_IER_EBERR) {
1317 WR4(sc, FEC_IER_REG, FEC_IER_EBERR);
1318 device_printf(sc->dev,
1319 "Ethernet DMA error, restarting controller.\n");
1320 ffec_stop_locked(sc);
1321 ffec_init_locked(sc);
1322 }
1323
1324 FFEC_UNLOCK(sc);
1325
1326 }
1327
1328 static int
1329 ffec_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
1330 {
1331 struct ffec_softc *sc;
1332 struct mii_data *mii;
1333 struct ifreq *ifr;
1334 int mask, error;
1335
1336 sc = ifp->if_softc;
1337 ifr = (struct ifreq *)data;
1338
1339 error = 0;
1340 switch (cmd) {
1341 case SIOCSIFFLAGS:
1342 FFEC_LOCK(sc);
1343 if (ifp->if_flags & IFF_UP) {
1344 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1345 if ((ifp->if_flags ^ sc->if_flags) &
1346 (IFF_PROMISC | IFF_ALLMULTI))
1347 ffec_setup_rxfilter(sc);
1348 } else {
1349 if (!sc->is_detaching)
1350 ffec_init_locked(sc);
1351 }
1352 } else {
1353 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1354 ffec_stop_locked(sc);
1355 }
1356 sc->if_flags = ifp->if_flags;
1357 FFEC_UNLOCK(sc);
1358 break;
1359
1360 case SIOCADDMULTI:
1361 case SIOCDELMULTI:
1362 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1363 FFEC_LOCK(sc);
1364 ffec_setup_rxfilter(sc);
1365 FFEC_UNLOCK(sc);
1366 }
1367 break;
1368
1369 case SIOCSIFMEDIA:
1370 case SIOCGIFMEDIA:
1371 mii = sc->mii_softc;
1372 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
1373 break;
1374
1375 case SIOCSIFCAP:
1376 mask = ifp->if_capenable ^ ifr->ifr_reqcap;
1377 if (mask & IFCAP_VLAN_MTU) {
1378 /* No work to do except acknowledge the change took. */
1379 ifp->if_capenable ^= IFCAP_VLAN_MTU;
1380 }
1381 break;
1382
1383 default:
1384 error = ether_ioctl(ifp, cmd, data);
1385 break;
1386 }
1387
1388 return (error);
1389 }
1390
1391 static int
1392 ffec_detach(device_t dev)
1393 {
1394 struct ffec_softc *sc;
1395 bus_dmamap_t map;
1396 int idx, irq;
1397
1398 /*
1399 * NB: This function can be called internally to unwind a failure to
1400 * attach. Make sure a resource got allocated/created before destroying.
1401 */
1402
1403 sc = device_get_softc(dev);
1404
1405 if (sc->is_attached) {
1406 FFEC_LOCK(sc);
1407 sc->is_detaching = true;
1408 ffec_stop_locked(sc);
1409 FFEC_UNLOCK(sc);
1410 callout_drain(&sc->ffec_callout);
1411 ether_ifdetach(sc->ifp);
1412 }
1413
1414 /* XXX no miibus detach? */
1415
1416 /* Clean up RX DMA resources and free mbufs. */
1417 for (idx = 0; idx < RX_DESC_COUNT; ++idx) {
1418 if ((map = sc->rxbuf_map[idx].map) != NULL) {
1419 bus_dmamap_unload(sc->rxbuf_tag, map);
1420 bus_dmamap_destroy(sc->rxbuf_tag, map);
1421 m_freem(sc->rxbuf_map[idx].mbuf);
1422 }
1423 }
1424 if (sc->rxbuf_tag != NULL)
1425 bus_dma_tag_destroy(sc->rxbuf_tag);
1426 if (sc->rxdesc_map != NULL) {
1427 bus_dmamap_unload(sc->rxdesc_tag, sc->rxdesc_map);
1428 bus_dmamem_free(sc->rxdesc_tag, sc->rxdesc_ring,
1429 sc->rxdesc_map);
1430 }
1431 if (sc->rxdesc_tag != NULL)
1432 bus_dma_tag_destroy(sc->rxdesc_tag);
1433
1434 /* Clean up TX DMA resources. */
1435 for (idx = 0; idx < TX_DESC_COUNT; ++idx) {
1436 if ((map = sc->txbuf_map[idx].map) != NULL) {
1437 /* TX maps are already unloaded. */
1438 bus_dmamap_destroy(sc->txbuf_tag, map);
1439 }
1440 }
1441 if (sc->txbuf_tag != NULL)
1442 bus_dma_tag_destroy(sc->txbuf_tag);
1443 if (sc->txdesc_map != NULL) {
1444 bus_dmamap_unload(sc->txdesc_tag, sc->txdesc_map);
1445 bus_dmamem_free(sc->txdesc_tag, sc->txdesc_ring,
1446 sc->txdesc_map);
1447 }
1448 if (sc->txdesc_tag != NULL)
1449 bus_dma_tag_destroy(sc->txdesc_tag);
1450
1451 /* Release bus resources. */
1452 for (irq = 0; irq < MAX_IRQ_COUNT; ++irq) {
1453 if (sc->intr_cookie[irq] != NULL) {
1454 bus_teardown_intr(dev, sc->irq_res[irq],
1455 sc->intr_cookie[irq]);
1456 }
1457 }
1458 bus_release_resources(dev, irq_res_spec, sc->irq_res);
1459
1460 if (sc->mem_res != NULL)
1461 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->mem_res);
1462
1463 FFEC_LOCK_DESTROY(sc);
1464 return (0);
1465 }
1466
1467 static int
1468 ffec_attach(device_t dev)
1469 {
1470 struct ffec_softc *sc;
1471 struct ifnet *ifp = NULL;
1472 struct mbuf *m;
1473 void *dummy;
1474 uintptr_t typeflags;
1475 phandle_t ofw_node;
1476 uint32_t idx, mscr;
1477 int error, phynum, rid, irq;
1478 uint8_t eaddr[ETHER_ADDR_LEN];
1479
1480 sc = device_get_softc(dev);
1481 sc->dev = dev;
1482
1483 FFEC_LOCK_INIT(sc);
1484
1485 /*
1486 * There are differences in the implementation and features of the FEC
1487 * hardware on different SoCs, so figure out what type we are.
1488 */
1489 typeflags = ofw_bus_search_compatible(dev, compat_data)->ocd_data;
1490 sc->fectype = (uint8_t)(typeflags & FECTYPE_MASK);
1491 sc->fecflags = (uint32_t)(typeflags & ~FECTYPE_MASK);
1492
1493 if (sc->fecflags & FECFLAG_AVB) {
1494 sc->rxbuf_align = 64;
1495 sc->txbuf_align = 1;
1496 } else {
1497 sc->rxbuf_align = 16;
1498 sc->txbuf_align = 16;
1499 }
1500
1501 /*
1502 * We have to be told what kind of electrical connection exists between
1503 * the MAC and PHY or we can't operate correctly.
1504 */
1505 if ((ofw_node = ofw_bus_get_node(dev)) == -1) {
1506 device_printf(dev, "Impossible: Can't find ofw bus node\n");
1507 error = ENXIO;
1508 goto out;
1509 }
1510 sc->phy_conn_type = mii_fdt_get_contype(ofw_node);
1511 if (sc->phy_conn_type == MII_CONTYPE_UNKNOWN) {
1512 device_printf(sc->dev, "No valid 'phy-mode' "
1513 "property found in FDT data for device.\n");
1514 error = ENOATTR;
1515 goto out;
1516 }
1517
1518 callout_init_mtx(&sc->ffec_callout, &sc->mtx, 0);
1519
1520 /* Allocate bus resources for accessing the hardware. */
1521 rid = 0;
1522 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1523 RF_ACTIVE);
1524 if (sc->mem_res == NULL) {
1525 device_printf(dev, "could not allocate memory resources.\n");
1526 error = ENOMEM;
1527 goto out;
1528 }
1529
1530 error = bus_alloc_resources(dev, irq_res_spec, sc->irq_res);
1531 if (error != 0) {
1532 device_printf(dev, "could not allocate interrupt resources\n");
1533 goto out;
1534 }
1535
1536 /*
1537 * Set up TX descriptor ring, descriptors, and dma maps.
1538 */
1539 error = bus_dma_tag_create(
1540 bus_get_dma_tag(dev), /* Parent tag. */
1541 FEC_DESC_RING_ALIGN, 0, /* alignment, boundary */
1542 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
1543 BUS_SPACE_MAXADDR, /* highaddr */
1544 NULL, NULL, /* filter, filterarg */
1545 TX_DESC_SIZE, 1, /* maxsize, nsegments */
1546 TX_DESC_SIZE, /* maxsegsize */
1547 0, /* flags */
1548 NULL, NULL, /* lockfunc, lockarg */
1549 &sc->txdesc_tag);
1550 if (error != 0) {
1551 device_printf(sc->dev,
1552 "could not create TX ring DMA tag.\n");
1553 goto out;
1554 }
1555
1556 error = bus_dmamem_alloc(sc->txdesc_tag, (void**)&sc->txdesc_ring,
1557 BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO, &sc->txdesc_map);
1558 if (error != 0) {
1559 device_printf(sc->dev,
1560 "could not allocate TX descriptor ring.\n");
1561 goto out;
1562 }
1563
1564 error = bus_dmamap_load(sc->txdesc_tag, sc->txdesc_map, sc->txdesc_ring,
1565 TX_DESC_SIZE, ffec_get1paddr, &sc->txdesc_ring_paddr, 0);
1566 if (error != 0) {
1567 device_printf(sc->dev,
1568 "could not load TX descriptor ring map.\n");
1569 goto out;
1570 }
1571
1572 error = bus_dma_tag_create(
1573 bus_get_dma_tag(dev), /* Parent tag. */
1574 sc->txbuf_align, 0, /* alignment, boundary */
1575 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
1576 BUS_SPACE_MAXADDR, /* highaddr */
1577 NULL, NULL, /* filter, filterarg */
1578 MCLBYTES, 1, /* maxsize, nsegments */
1579 MCLBYTES, /* maxsegsize */
1580 0, /* flags */
1581 NULL, NULL, /* lockfunc, lockarg */
1582 &sc->txbuf_tag);
1583 if (error != 0) {
1584 device_printf(sc->dev,
1585 "could not create TX ring DMA tag.\n");
1586 goto out;
1587 }
1588
1589 for (idx = 0; idx < TX_DESC_COUNT; ++idx) {
1590 error = bus_dmamap_create(sc->txbuf_tag, 0,
1591 &sc->txbuf_map[idx].map);
1592 if (error != 0) {
1593 device_printf(sc->dev,
1594 "could not create TX buffer DMA map.\n");
1595 goto out;
1596 }
1597 ffec_setup_txdesc(sc, idx, 0, 0);
1598 }
1599
1600 /*
1601 * Set up RX descriptor ring, descriptors, dma maps, and mbufs.
1602 */
1603 error = bus_dma_tag_create(
1604 bus_get_dma_tag(dev), /* Parent tag. */
1605 FEC_DESC_RING_ALIGN, 0, /* alignment, boundary */
1606 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
1607 BUS_SPACE_MAXADDR, /* highaddr */
1608 NULL, NULL, /* filter, filterarg */
1609 RX_DESC_SIZE, 1, /* maxsize, nsegments */
1610 RX_DESC_SIZE, /* maxsegsize */
1611 0, /* flags */
1612 NULL, NULL, /* lockfunc, lockarg */
1613 &sc->rxdesc_tag);
1614 if (error != 0) {
1615 device_printf(sc->dev,
1616 "could not create RX ring DMA tag.\n");
1617 goto out;
1618 }
1619
1620 error = bus_dmamem_alloc(sc->rxdesc_tag, (void **)&sc->rxdesc_ring,
1621 BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO, &sc->rxdesc_map);
1622 if (error != 0) {
1623 device_printf(sc->dev,
1624 "could not allocate RX descriptor ring.\n");
1625 goto out;
1626 }
1627
1628 error = bus_dmamap_load(sc->rxdesc_tag, sc->rxdesc_map, sc->rxdesc_ring,
1629 RX_DESC_SIZE, ffec_get1paddr, &sc->rxdesc_ring_paddr, 0);
1630 if (error != 0) {
1631 device_printf(sc->dev,
1632 "could not load RX descriptor ring map.\n");
1633 goto out;
1634 }
1635
1636 error = bus_dma_tag_create(
1637 bus_get_dma_tag(dev), /* Parent tag. */
1638 1, 0, /* alignment, boundary */
1639 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
1640 BUS_SPACE_MAXADDR, /* highaddr */
1641 NULL, NULL, /* filter, filterarg */
1642 MCLBYTES, 1, /* maxsize, nsegments */
1643 MCLBYTES, /* maxsegsize */
1644 0, /* flags */
1645 NULL, NULL, /* lockfunc, lockarg */
1646 &sc->rxbuf_tag);
1647 if (error != 0) {
1648 device_printf(sc->dev,
1649 "could not create RX buf DMA tag.\n");
1650 goto out;
1651 }
1652
1653 for (idx = 0; idx < RX_DESC_COUNT; ++idx) {
1654 error = bus_dmamap_create(sc->rxbuf_tag, 0,
1655 &sc->rxbuf_map[idx].map);
1656 if (error != 0) {
1657 device_printf(sc->dev,
1658 "could not create RX buffer DMA map.\n");
1659 goto out;
1660 }
1661 if ((m = ffec_alloc_mbufcl(sc)) == NULL) {
1662 device_printf(dev, "Could not alloc mbuf\n");
1663 error = ENOMEM;
1664 goto out;
1665 }
1666 if ((error = ffec_setup_rxbuf(sc, idx, m)) != 0) {
1667 device_printf(sc->dev,
1668 "could not create new RX buffer.\n");
1669 goto out;
1670 }
1671 }
1672
1673 /* Try to get the MAC address from the hardware before resetting it. */
1674 ffec_get_hwaddr(sc, eaddr);
1675
1676 /*
1677 * Reset the hardware. Disables all interrupts.
1678 *
1679 * When the FEC is connected to the AXI bus (indicated by AVB flag), a
1680 * MAC reset while a bus transaction is pending can hang the bus.
1681 * Instead of resetting, turn off the ENABLE bit, which allows the
1682 * hardware to complete any in-progress transfers (appending a bad CRC
1683 * to any partial packet) and release the AXI bus. This could probably
1684 * be done unconditionally for all hardware variants, but that hasn't
1685 * been tested.
1686 */
1687 if (sc->fecflags & FECFLAG_AVB)
1688 WR4(sc, FEC_ECR_REG, 0);
1689 else
1690 WR4(sc, FEC_ECR_REG, FEC_ECR_RESET);
1691
1692 /* Setup interrupt handler. */
1693 for (irq = 0; irq < MAX_IRQ_COUNT; ++irq) {
1694 if (sc->irq_res[irq] != NULL) {
1695 error = bus_setup_intr(dev, sc->irq_res[irq],
1696 INTR_TYPE_NET | INTR_MPSAFE, NULL, ffec_intr, sc,
1697 &sc->intr_cookie[irq]);
1698 if (error != 0) {
1699 device_printf(dev,
1700 "could not setup interrupt handler.\n");
1701 goto out;
1702 }
1703 }
1704 }
1705
1706 /*
1707 * Set up the PHY control register.
1708 *
1709 * Speed formula for ENET is md_clock = mac_clock / ((N + 1) * 2).
1710 * Speed formula for FEC is md_clock = mac_clock / (N * 2)
1711 *
1712 * XXX - Revisit this...
1713 *
1714 * For a Wandboard imx6 (ENET) I was originally using 4, but the uboot
1715 * code uses 10. Both values seem to work, but I suspect many modern
1716 * PHY parts can do mdio at speeds far above the standard 2.5 MHz.
1717 *
1718 * Different imx manuals use confusingly different terminology (things
1719 * like "system clock" and "internal module clock") with examples that
1720 * use frequencies that have nothing to do with ethernet, giving the
1721 * vague impression that maybe the clock in question is the periphclock
1722 * or something. In fact, on an imx53 development board (FEC),
1723 * measuring the mdio clock at the pin on the PHY and playing with
1724 * various divisors showed that the root speed was 66 MHz (clk_ipg_root
1725 * aka periphclock) and 13 was the right divisor.
1726 *
1727 * All in all, it seems likely that 13 is a safe divisor for now,
1728 * because if we really do need to base it on the peripheral clock
1729 * speed, then we need a platform-independent get-clock-freq API.
1730 */
1731 mscr = 13 << FEC_MSCR_MII_SPEED_SHIFT;
1732 if (OF_hasprop(ofw_node, "phy-disable-preamble")) {
1733 mscr |= FEC_MSCR_DIS_PRE;
1734 if (bootverbose)
1735 device_printf(dev, "PHY preamble disabled\n");
1736 }
1737 WR4(sc, FEC_MSCR_REG, mscr);
1738
1739 /* Set up the ethernet interface. */
1740 sc->ifp = ifp = if_alloc(IFT_ETHER);
1741
1742 ifp->if_softc = sc;
1743 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1744 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1745 ifp->if_capabilities = IFCAP_VLAN_MTU;
1746 ifp->if_capenable = ifp->if_capabilities;
1747 ifp->if_start = ffec_txstart;
1748 ifp->if_ioctl = ffec_ioctl;
1749 ifp->if_init = ffec_init;
1750 IFQ_SET_MAXLEN(&ifp->if_snd, TX_DESC_COUNT - 1);
1751 ifp->if_snd.ifq_drv_maxlen = TX_DESC_COUNT - 1;
1752 IFQ_SET_READY(&ifp->if_snd);
1753 ifp->if_hdrlen = sizeof(struct ether_vlan_header);
1754
1755 #if 0 /* XXX The hardware keeps stats we could use for these. */
1756 ifp->if_linkmib = &sc->mibdata;
1757 ifp->if_linkmiblen = sizeof(sc->mibdata);
1758 #endif
1759
1760 /* Set up the miigasket hardware (if any). */
1761 ffec_miigasket_setup(sc);
1762
1763 /* Attach the mii driver. */
1764 if (fdt_get_phyaddr(ofw_node, dev, &phynum, &dummy) != 0) {
1765 phynum = MII_PHY_ANY;
1766 }
1767 error = mii_attach(dev, &sc->miibus, ifp, ffec_media_change,
1768 ffec_media_status, BMSR_DEFCAPMASK, phynum, MII_OFFSET_ANY,
1769 (sc->fecflags & FECTYPE_MVF) ? MIIF_FORCEANEG : 0);
1770 if (error != 0) {
1771 device_printf(dev, "PHY attach failed\n");
1772 goto out;
1773 }
1774 sc->mii_softc = device_get_softc(sc->miibus);
1775
1776 /* All ready to run, attach the ethernet interface. */
1777 ether_ifattach(ifp, eaddr);
1778 sc->is_attached = true;
1779
1780 error = 0;
1781 out:
1782
1783 if (error != 0)
1784 ffec_detach(dev);
1785
1786 return (error);
1787 }
1788
1789 static int
1790 ffec_probe(device_t dev)
1791 {
1792 uintptr_t fectype;
1793
1794 if (!ofw_bus_status_okay(dev))
1795 return (ENXIO);
1796
1797 fectype = ofw_bus_search_compatible(dev, compat_data)->ocd_data;
1798 if (fectype == FECTYPE_NONE)
1799 return (ENXIO);
1800
1801 device_set_desc(dev, (fectype & FECFLAG_GBE) ?
1802 "Freescale Gigabit Ethernet Controller" :
1803 "Freescale Fast Ethernet Controller");
1804
1805 return (BUS_PROBE_DEFAULT);
1806 }
1807
1808
1809 static device_method_t ffec_methods[] = {
1810 /* Device interface. */
1811 DEVMETHOD(device_probe, ffec_probe),
1812 DEVMETHOD(device_attach, ffec_attach),
1813 DEVMETHOD(device_detach, ffec_detach),
1814
1815 /*
1816 DEVMETHOD(device_shutdown, ffec_shutdown),
1817 DEVMETHOD(device_suspend, ffec_suspend),
1818 DEVMETHOD(device_resume, ffec_resume),
1819 */
1820
1821 /* MII interface. */
1822 DEVMETHOD(miibus_readreg, ffec_miibus_readreg),
1823 DEVMETHOD(miibus_writereg, ffec_miibus_writereg),
1824 DEVMETHOD(miibus_statchg, ffec_miibus_statchg),
1825
1826 DEVMETHOD_END
1827 };
1828
1829 static driver_t ffec_driver = {
1830 "ffec",
1831 ffec_methods,
1832 sizeof(struct ffec_softc)
1833 };
1834
1835 DRIVER_MODULE(ffec, simplebus, ffec_driver, 0, 0);
1836 DRIVER_MODULE(miibus, ffec, miibus_driver, 0, 0);
1837
1838 MODULE_DEPEND(ffec, ether, 1, 1, 1);
1839 MODULE_DEPEND(ffec, miibus, 1, 1, 1);
Cache object: 313c1bb2e55561a88b9f57e70f4ccb3b
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