flex_spi.c

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    1 /*-
    2  * Copyright (c) 2021 Alstom Group.
    3  * Copyright (c) 2021 Semihalf.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice, this list of conditions and the following disclaimer.
   10  * 2. Redistributions in binary form must reproduce the above copyright
   11  *    notice, this list of conditions and the following disclaimer in the
   12  *    documentation and/or other materials provided with the distribution.
   13  *
   14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
   15  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
   16  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
   17  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
   18  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
   19  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
   20  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
   21  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
   22  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
   23  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   24  */
   25 
   26 #include <sys/cdefs.h>
   27 __FBSDID("$FreeBSD$");
   28 
   29 #include "opt_platform.h"
   30 
   31 #include <sys/param.h>
   32 #include <sys/systm.h>
   33 #include <sys/bio.h>
   34 #include <sys/endian.h>
   35 #include <sys/kernel.h>
   36 #include <sys/kthread.h>
   37 #include <sys/lock.h>
   38 #include <sys/malloc.h>
   39 #include <sys/module.h>
   40 #include <sys/mutex.h>
   41 #include <sys/rman.h>
   42 
   43 #include <geom/geom_disk.h>
   44 
   45 #include <machine/bus.h>
   46 
   47 #include <dev/extres/clk/clk.h>
   48 #include <dev/fdt/fdt_common.h>
   49 #include <dev/ofw/ofw_bus_subr.h>
   50 
   51 #include <vm/pmap.h>
   52 
   53 #include "flex_spi.h"
   54 
   55 static MALLOC_DEFINE(SECTOR_BUFFER, "flex_spi", "FSL QSPI sector buffer memory");
   56 
   57 #define AHB_LUT_ID      31
   58 #define MHZ(x)                  ((x)*1000*1000)
   59 #define SPI_DEFAULT_CLK_RATE    (MHZ(10))
   60 
   61 static int driver_flags = 0;
   62 SYSCTL_NODE(_hw, OID_AUTO, flex_spi, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
   63     "FlexSPI driver parameters");
   64 SYSCTL_INT(_hw_flex_spi, OID_AUTO, driver_flags, CTLFLAG_RDTUN, &driver_flags, 0,
   65     "Configuration flags and quirks");
   66 
   67 static struct ofw_compat_data flex_spi_compat_data[] = {
   68         {"nxp,lx2160a-fspi",  true},
   69         {NULL,               false}
   70 };
   71 
   72 struct flex_spi_flash_info {
   73         char*           name;
   74         uint32_t        jedecid;
   75         uint32_t        sectorsize;
   76         uint32_t        sectorcount;
   77         uint32_t        erasesize;
   78         uint32_t        maxclk;
   79 };
   80 
   81 /* Add information about supported Flashes. TODO: use SFDP instead */
   82 static struct flex_spi_flash_info flex_spi_flash_info[] = {
   83                 {"W25Q128JW", 0x001860ef, 64*1024, 256, 4096, MHZ(100)},
   84                 {NULL, 0, 0, 0, 0, 0}
   85 };
   86 
   87 struct flex_spi_softc
   88 {
   89         device_t                dev;
   90         unsigned int            flags;
   91 
   92         struct bio_queue_head   bio_queue;
   93         struct mtx              disk_mtx;
   94         struct disk             *disk;
   95         struct proc             *p;
   96         unsigned int            taskstate;
   97         uint8_t                 *buf;
   98 
   99         struct resource         *ahb_mem_res;
  100         struct resource         *mem_res;
  101 
  102         clk_t                   fspi_clk_en;
  103         clk_t                   fspi_clk;
  104         uint64_t                fspi_clk_en_hz;
  105         uint64_t                fspi_clk_hz;
  106 
  107         /* TODO: support more than one Flash per bus */
  108         uint64_t                fspi_max_clk;
  109         uint32_t                quirks;
  110 
  111         /* Flash parameters */
  112         uint32_t                sectorsize;
  113         uint32_t                sectorcount;
  114         uint32_t                erasesize;
  115 };
  116 
  117 static int flex_spi_read(struct flex_spi_softc *sc, off_t offset, caddr_t data,
  118     size_t count);
  119 static int flex_spi_write(struct flex_spi_softc *sc, off_t offset,
  120     uint8_t *data, size_t size);
  121 
  122 static int flex_spi_attach(device_t dev);
  123 static int flex_spi_probe(device_t dev);
  124 static int flex_spi_detach(device_t dev);
  125 
  126 /* disk routines */
  127 static int flex_spi_open(struct disk *dp);
  128 static int flex_spi_close(struct disk *dp);
  129 static int flex_spi_ioctl(struct disk *, u_long, void *, int, struct thread *);
  130 static void flex_spi_strategy(struct bio *bp);
  131 static int flex_spi_getattr(struct bio *bp);
  132 static void flex_spi_task(void *arg);
  133 
  134 static uint32_t
  135 read_reg(struct flex_spi_softc *sc, uint32_t offset)
  136 {
  137 
  138         return ((bus_read_4(sc->mem_res, offset)));
  139 }
  140 
  141 static void
  142 write_reg(struct flex_spi_softc *sc, uint32_t offset, uint32_t value)
  143 {
  144 
  145         bus_write_4(sc->mem_res, offset, (value));
  146 }
  147 
  148 static int
  149 reg_read_poll_tout(struct flex_spi_softc *sc, uint32_t offset, uint32_t mask,
  150     uint32_t delay_us, uint32_t iterations, bool positive)
  151 {
  152         uint32_t reg;
  153         uint32_t condition = 0;
  154 
  155         do {
  156                 reg = read_reg(sc, offset);
  157                 if (positive)
  158                         condition = ((reg & mask) == 0);
  159                 else
  160                         condition = ((reg & mask) != 0);
  161 
  162                 if (condition == 0)
  163                         break;
  164 
  165                 DELAY(delay_us);
  166         } while (condition && (--iterations > 0));
  167 
  168         return (condition != 0);
  169 }
  170 
  171 static int
  172 flex_spi_clk_setup(struct flex_spi_softc *sc, uint32_t rate)
  173 {
  174         int ret = 0;
  175 
  176         /* disable to avoid glitching */
  177         ret |= clk_disable(sc->fspi_clk_en);
  178         ret |= clk_disable(sc->fspi_clk);
  179 
  180         ret |= clk_set_freq(sc->fspi_clk, rate, 0);
  181         sc->fspi_clk_hz = rate;
  182 
  183         /* enable clocks back */
  184         ret |= clk_enable(sc->fspi_clk_en);
  185         ret |= clk_enable(sc->fspi_clk);
  186 
  187         if (ret)
  188                 return (EINVAL);
  189 
  190         return (0);
  191 }
  192 
  193 static void
  194 flex_spi_prepare_lut(struct flex_spi_softc *sc, uint8_t op)
  195 {
  196         uint32_t lut_id;
  197         uint32_t lut;
  198 
  199         /* unlock LUT */
  200         write_reg(sc, FSPI_LUTKEY, FSPI_LUTKEY_VALUE);
  201         write_reg(sc, FSPI_LCKCR, FSPI_LCKER_UNLOCK);
  202 
  203         /* Read JEDEC ID */
  204         lut_id = 0;
  205 
  206         switch (op) {
  207         case LUT_FLASH_CMD_JEDECID:
  208                 lut = LUT_DEF(0, LUT_CMD, LUT_PAD(1), FSPI_CMD_READ_IDENT);
  209                 lut |= LUT_DEF(1, LUT_NXP_READ, LUT_PAD(1), 0);
  210                 write_reg(sc, FSPI_LUT_REG(lut_id), lut);
  211                 write_reg(sc, FSPI_LUT_REG(lut_id) + 4, 0);
  212                 break;
  213         case LUT_FLASH_CMD_READ:
  214                 lut = LUT_DEF(0, LUT_CMD, LUT_PAD(1), FSPI_CMD_FAST_READ);
  215                 lut |= LUT_DEF(1, LUT_ADDR, LUT_PAD(1), 3*8);
  216                 write_reg(sc, FSPI_LUT_REG(lut_id), lut);
  217                 lut = LUT_DEF(0, LUT_DUMMY, LUT_PAD(1), 1*8);
  218                 lut |= LUT_DEF(1, LUT_NXP_READ, LUT_PAD(1), 0);
  219                 write_reg(sc, FSPI_LUT_REG(lut_id) + 4, lut);
  220                 write_reg(sc, FSPI_LUT_REG(lut_id) + 8, 0);
  221                 break;
  222         case LUT_FLASH_CMD_STATUS_READ:
  223                 lut = LUT_DEF(0, LUT_CMD, LUT_PAD(1), FSPI_CMD_READ_STATUS);
  224                 lut |= LUT_DEF(1, LUT_NXP_READ, LUT_PAD(1), 0);
  225                 write_reg(sc, FSPI_LUT_REG(lut_id), lut);
  226                 write_reg(sc, FSPI_LUT_REG(lut_id) + 4, 0);
  227                 break;
  228         case LUT_FLASH_CMD_PAGE_PROGRAM:
  229                 lut = LUT_DEF(0, LUT_CMD, LUT_PAD(1), FSPI_CMD_PAGE_PROGRAM);
  230                 lut |= LUT_DEF(1, LUT_ADDR, LUT_PAD(1), 3*8);
  231                 write_reg(sc, FSPI_LUT_REG(lut_id), lut);
  232                 lut = LUT_DEF(0, LUT_NXP_WRITE, LUT_PAD(1), 0);
  233                 write_reg(sc, FSPI_LUT_REG(lut_id) + 4, lut);
  234                 write_reg(sc, FSPI_LUT_REG(lut_id) + 8, 0);
  235                 break;
  236         case LUT_FLASH_CMD_WRITE_ENABLE:
  237                 lut = LUT_DEF(0, LUT_CMD, LUT_PAD(1), FSPI_CMD_WRITE_ENABLE);
  238                 write_reg(sc, FSPI_LUT_REG(lut_id), lut);
  239                 write_reg(sc, FSPI_LUT_REG(lut_id) + 4, 0);
  240                 break;
  241         case LUT_FLASH_CMD_WRITE_DISABLE:
  242                 lut = LUT_DEF(0, LUT_CMD, LUT_PAD(1), FSPI_CMD_WRITE_DISABLE);
  243                 write_reg(sc, FSPI_LUT_REG(lut_id), lut);
  244                 write_reg(sc, FSPI_LUT_REG(lut_id) + 4, 0);
  245                 break;
  246         case LUT_FLASH_CMD_SECTOR_ERASE:
  247                 lut = LUT_DEF(0, LUT_CMD, LUT_PAD(1), FSPI_CMD_SECTOR_ERASE);
  248                 lut |= LUT_DEF(1, LUT_ADDR, LUT_PAD(1), 3*8);
  249                 write_reg(sc, FSPI_LUT_REG(lut_id), lut);
  250                 write_reg(sc, FSPI_LUT_REG(lut_id) + 4, 0);
  251                 break;
  252         default:
  253                 write_reg(sc, FSPI_LUT_REG(lut_id), 0);
  254         }
  255 
  256         /* lock LUT */
  257         write_reg(sc, FSPI_LUTKEY, FSPI_LUTKEY_VALUE);
  258         write_reg(sc, FSPI_LCKCR, FSPI_LCKER_LOCK);
  259 }
  260 
  261 static void
  262 flex_spi_prepare_ahb_lut(struct flex_spi_softc *sc)
  263 {
  264         uint32_t lut_id;
  265         uint32_t lut;
  266 
  267         /* unlock LUT */
  268         write_reg(sc, FSPI_LUTKEY, FSPI_LUTKEY_VALUE);
  269         write_reg(sc, FSPI_LCKCR, FSPI_LCKER_UNLOCK);
  270 
  271         lut_id = AHB_LUT_ID;
  272         lut = LUT_DEF(0, LUT_CMD, LUT_PAD(1), FSPI_CMD_FAST_READ);
  273         lut |= LUT_DEF(1, LUT_ADDR, LUT_PAD(1), 3*8);
  274         write_reg(sc, FSPI_LUT_REG(lut_id), lut);
  275         lut = LUT_DEF(0, LUT_DUMMY, LUT_PAD(1), 1*8);
  276         lut |= LUT_DEF(1, LUT_NXP_READ, LUT_PAD(1), 0);
  277         write_reg(sc, FSPI_LUT_REG(lut_id) + 4, lut);
  278         write_reg(sc, FSPI_LUT_REG(lut_id) + 8, 0);
  279 
  280         /* lock LUT */
  281         write_reg(sc, FSPI_LUTKEY, FSPI_LUTKEY_VALUE);
  282         write_reg(sc, FSPI_LCKCR, FSPI_LCKER_LOCK);
  283 }
  284 
  285 #define DIR_READ        0
  286 #define DIR_WRITE       1
  287 
  288 static void
  289 flex_spi_read_rxfifo(struct flex_spi_softc *sc, uint8_t *buf, uint8_t size)
  290 {
  291         int i, ret, reg;
  292 
  293         /*
  294          * Default value of water mark level is 8 bytes, hence in single
  295          * read request controller can read max 8 bytes of data.
  296          */
  297         for (i = 0; i < size; i += 4) {
  298                 /* Wait for RXFIFO available */
  299                 if (i % 8 == 0) {
  300                         ret = reg_read_poll_tout(sc, FSPI_INTR, FSPI_INTR_IPRXWA,
  301                             1, 50000, 1);
  302                         if (ret)
  303                                 device_printf(sc->dev,
  304                                     "timed out waiting for FSPI_INTR_IPRXWA\n");
  305                 }
  306 
  307                 if (i % 8 == 0)
  308                         reg = read_reg(sc, FSPI_RFDR);
  309                 else
  310                         reg = read_reg(sc, FSPI_RFDR + 4);
  311 
  312                 if (size  >= (i + 4))
  313                         *(uint32_t *)(buf + i) = reg;
  314                 else
  315                         memcpy(buf + i, &reg, size - i);
  316 
  317                 /* move the FIFO pointer */
  318                 if (i % 8 != 0)
  319                         write_reg(sc, FSPI_INTR, FSPI_INTR_IPRXWA);
  320         }
  321 
  322         /* invalid the RXFIFO */
  323         write_reg(sc, FSPI_IPRXFCR, FSPI_IPRXFCR_CLR);
  324         /* move the FIFO pointer */
  325         write_reg(sc, FSPI_INTR, FSPI_INTR_IPRXWA);
  326 }
  327 
  328 static void
  329 flex_spi_write_txfifo(struct flex_spi_softc *sc, uint8_t *buf, uint8_t size)
  330 {
  331         int i, ret, reg;
  332 
  333         /* invalid the TXFIFO */
  334         write_reg(sc, FSPI_IPRXFCR, FSPI_IPTXFCR_CLR);
  335 
  336         /*
  337          * Default value of water mark level is 8 bytes, hence in single
  338          * read request controller can read max 8 bytes of data.
  339          */
  340         for (i = 0; i < size; i += 4) {
  341                 /* Wait for RXFIFO available */
  342                 if (i % 8 == 0) {
  343                         ret = reg_read_poll_tout(sc, FSPI_INTR, FSPI_INTR_IPTXWE,
  344                             1, 50000, 1);
  345                         if (ret)
  346                                 device_printf(sc->dev,
  347                                     "timed out waiting for FSPI_INTR_IPRXWA\n");
  348                 }
  349 
  350                 if (size  >= (i + 4))
  351                         reg = *(uint32_t *)(buf + i);
  352                 else {
  353                         reg = 0;
  354                         memcpy(&reg, buf + i, size - i);
  355                 }
  356 
  357                 if (i % 8 == 0)
  358                         write_reg(sc, FSPI_TFDR, reg);
  359                 else
  360                         write_reg(sc, FSPI_TFDR + 4, reg);
  361 
  362                 /* move the FIFO pointer */
  363                 if (i % 8 != 0)
  364                         write_reg(sc, FSPI_INTR, FSPI_INTR_IPTXWE);
  365         }
  366 
  367         /* move the FIFO pointer */
  368         write_reg(sc, FSPI_INTR, FSPI_INTR_IPTXWE);
  369 }
  370 
  371 static int
  372 flex_spi_do_op(struct flex_spi_softc *sc, uint32_t op, uint32_t addr,
  373     uint8_t *buf, uint8_t size, uint8_t dir)
  374 {
  375 
  376         uint32_t cnt = 1000, reg;
  377 
  378         reg = read_reg(sc, FSPI_IPRXFCR);
  379         /* invalidate RXFIFO first */
  380         reg &= ~FSPI_IPRXFCR_DMA_EN;
  381         reg |= FSPI_IPRXFCR_CLR;
  382         write_reg(sc, FSPI_IPRXFCR, reg);
  383 
  384         /* Prepare LUT */
  385         flex_spi_prepare_lut(sc, op);
  386 
  387         write_reg(sc, FSPI_IPCR0, addr);
  388         /*
  389          * Always start the sequence at the same index since we update
  390          * the LUT at each BIO operation. And also specify the DATA
  391          * length, since it's has not been specified in the LUT.
  392          */
  393         write_reg(sc, FSPI_IPCR1, size |
  394             (0 << FSPI_IPCR1_SEQID_SHIFT) | (0 << FSPI_IPCR1_SEQNUM_SHIFT));
  395 
  396         if ((size != 0) && (dir == DIR_WRITE))
  397                 flex_spi_write_txfifo(sc, buf, size);
  398 
  399         /* Trigger the LUT now. */
  400         write_reg(sc, FSPI_IPCMD, FSPI_IPCMD_TRG);
  401 
  402 
  403         /* Wait for completion. */
  404         do {
  405                 reg = read_reg(sc, FSPI_INTR);
  406                 if (reg & FSPI_INTR_IPCMDDONE) {
  407                         write_reg(sc, FSPI_INTR, FSPI_INTR_IPCMDDONE);
  408                         break;
  409                 }
  410                 DELAY(1);
  411         } while (--cnt);
  412         if (cnt == 0) {
  413                 device_printf(sc->dev, "timed out waiting for command completion\n");
  414                 return (ETIMEDOUT);
  415         }
  416 
  417         /* Invoke IP data read, if request is of data read. */
  418         if ((size != 0) && (dir == DIR_READ))
  419                 flex_spi_read_rxfifo(sc, buf, size);
  420 
  421         return (0);
  422 }
  423 
  424 static int
  425 flex_spi_wait_for_controller(struct flex_spi_softc *sc)
  426 {
  427         int err;
  428 
  429         /* Wait for controller being ready. */
  430         err = reg_read_poll_tout(sc, FSPI_STS0,
  431            FSPI_STS0_ARB_IDLE, 1, POLL_TOUT, 1);
  432 
  433         return (err);
  434 }
  435 
  436 static int
  437 flex_spi_wait_for_flash(struct flex_spi_softc *sc)
  438 {
  439         int ret;
  440         uint32_t status = 0;
  441 
  442         ret = flex_spi_wait_for_controller(sc);
  443         if (ret != 0) {
  444                 device_printf(sc->dev, "%s: timed out waiting for controller", __func__);
  445                 return (ret);
  446         }
  447 
  448         do {
  449                 ret = flex_spi_do_op(sc, LUT_FLASH_CMD_STATUS_READ, 0, (void*)&status,
  450                     1, DIR_READ);
  451                 if (ret != 0) {
  452                         device_printf(sc->dev, "ERROR: failed to get flash status\n");
  453                         return (ret);
  454                 }
  455 
  456         } while (status & STATUS_WIP);
  457 
  458         return (0);
  459 }
  460 
  461 static int
  462 flex_spi_identify(struct flex_spi_softc *sc)
  463 {
  464         int ret;
  465         uint32_t id = 0;
  466         struct flex_spi_flash_info *finfo = flex_spi_flash_info;
  467 
  468         ret = flex_spi_do_op(sc, LUT_FLASH_CMD_JEDECID, 0, (void*)&id, sizeof(id), DIR_READ);
  469         if (ret != 0) {
  470                 device_printf(sc->dev, "ERROR: failed to identify device\n");
  471                 return (ret);
  472         }
  473 
  474         /* XXX TODO: SFDP to be implemented */
  475         while (finfo->jedecid != 0) {
  476                 if (id == finfo->jedecid) {
  477                         device_printf(sc->dev, "found %s Flash\n", finfo->name);
  478                         sc->sectorsize = finfo->sectorsize;
  479                         sc->sectorcount = finfo->sectorcount;
  480                         sc->erasesize = finfo->erasesize;
  481                         sc->fspi_max_clk = finfo->maxclk;
  482                         return (0);
  483                 }
  484                 finfo++;
  485         }
  486 
  487         return (EINVAL);
  488 }
  489 
  490 static inline int
  491 flex_spi_force_ip_mode(struct flex_spi_softc *sc)
  492 {
  493 
  494         if (sc->quirks & FSPI_QUIRK_USE_IP_ONLY)
  495                 return (1);
  496         if (driver_flags & FSPI_QUIRK_USE_IP_ONLY)
  497                 return (1);
  498 
  499         return (0);
  500 }
  501 
  502 static int
  503 flex_spi_read(struct flex_spi_softc *sc, off_t offset, caddr_t data,
  504     size_t count)
  505 {
  506         int err;
  507         size_t len;
  508 
  509         /* Wait for controller being ready. */
  510         err = flex_spi_wait_for_controller(sc);
  511         if (err)
  512                 device_printf(sc->dev,
  513                     "warning: spi_read, timed out waiting for controller");
  514 
  515         /* Use AHB access whenever we can */
  516         if (flex_spi_force_ip_mode(sc) != 0) {
  517                 do {
  518                         if (((offset % 4) != 0) || (count < 4)) {
  519                                 *(uint8_t*)data = bus_read_1(sc->ahb_mem_res, offset);
  520                                 data++;
  521                                 count--;
  522                                 offset++;
  523                         } else {
  524                                 *(uint32_t*)data = bus_read_4(sc->ahb_mem_res, offset);
  525                                 data += 4;
  526                                 count -= 4;
  527                                 offset += 4;
  528                         }
  529                 } while (count);
  530 
  531                 return (0);
  532         }
  533 
  534         do {
  535                 len = min(64, count);
  536                 err = flex_spi_do_op(sc, LUT_FLASH_CMD_READ, offset, (void*)data,
  537                                 len, DIR_READ);
  538                 if (err)
  539                         return (err);
  540                 offset += len;
  541                 data += len;
  542                 count -= len;
  543         } while (count);
  544 
  545         return (0);
  546 }
  547 
  548 static int
  549 flex_spi_write(struct flex_spi_softc *sc, off_t offset, uint8_t *data,
  550     size_t size)
  551 {
  552         int ret = 0;
  553         size_t ptr;
  554 
  555         flex_spi_wait_for_flash(sc);
  556         ret = flex_spi_do_op(sc, LUT_FLASH_CMD_WRITE_ENABLE, offset, NULL,
  557                                 0, DIR_READ);
  558         if (ret != 0) {
  559                 device_printf(sc->dev, "ERROR: failed to enable writes\n");
  560                 return (ret);
  561         }
  562         flex_spi_wait_for_flash(sc);
  563 
  564         /* per-sector write */
  565         while (size > 0) {
  566                 uint32_t sector_base = rounddown2(offset, sc->erasesize);
  567                 size_t size_in_sector = size;
  568 
  569                 if (size_in_sector + offset > sector_base + sc->erasesize)
  570                         size_in_sector = sector_base + sc->erasesize - offset;
  571 
  572                 /* Read sector */
  573                 ret = flex_spi_read(sc, sector_base, sc->buf, sc->erasesize);
  574                 if (ret != 0) {
  575                         device_printf(sc->dev, "ERROR: failed to read sector %d\n",
  576                             sector_base);
  577                         goto exit;
  578                 }
  579 
  580                 /* Erase sector */
  581                 flex_spi_wait_for_flash(sc);
  582                 ret = flex_spi_do_op(sc, LUT_FLASH_CMD_SECTOR_ERASE, offset, NULL,
  583                                 0, DIR_READ);
  584                 if (ret != 0) {
  585                         device_printf(sc->dev, "ERROR: failed to erase sector %d\n",
  586                             sector_base);
  587                         goto exit;
  588                 }
  589 
  590                 /* Update buffer with input data */
  591                 memcpy(sc->buf + (offset - sector_base), data, size_in_sector);
  592 
  593                 /* Write buffer back to the flash
  594                  * Up to 32 bytes per single request, request cannot spread
  595                  * across 256-byte page boundary
  596                  */
  597                 for (ptr = 0; ptr < sc->erasesize; ptr += 32) {
  598                         flex_spi_wait_for_flash(sc);
  599                         ret = flex_spi_do_op(sc, LUT_FLASH_CMD_PAGE_PROGRAM,
  600                             sector_base + ptr, (void*)(sc->buf + ptr), 32, DIR_WRITE);
  601                         if (ret != 0) {
  602                                 device_printf(sc->dev, "ERROR: failed to write address %ld\n",
  603                                    sector_base + ptr);
  604                                 goto exit;
  605                         }
  606                 }
  607 
  608                 /* update pointers */
  609                 size = size - size_in_sector;
  610                 offset = offset + size;
  611         }
  612 
  613         flex_spi_wait_for_flash(sc);
  614         ret = flex_spi_do_op(sc, LUT_FLASH_CMD_WRITE_DISABLE, offset, (void*)sc->buf,
  615                                 0, DIR_READ);
  616         if (ret != 0) {
  617                 device_printf(sc->dev, "ERROR: failed to disable writes\n");
  618                 goto exit;
  619         }
  620         flex_spi_wait_for_flash(sc);
  621 
  622 exit:
  623 
  624         return (ret);
  625 }
  626 
  627 static int
  628 flex_spi_default_setup(struct flex_spi_softc *sc)
  629 {
  630         int ret, i;
  631         uint32_t reg;
  632 
  633         /* Default clock speed */
  634         ret = flex_spi_clk_setup(sc, SPI_DEFAULT_CLK_RATE);
  635         if (ret)
  636                 return (ret);
  637 
  638         /* Reset the module */
  639         /* w1c register, wait unit clear */
  640         reg = read_reg(sc, FSPI_MCR0);
  641         reg |= FSPI_MCR0_SWRST;
  642         write_reg(sc, FSPI_MCR0, reg);
  643         ret = reg_read_poll_tout(sc, FSPI_MCR0, FSPI_MCR0_SWRST, 1000, POLL_TOUT, 0);
  644         if (ret != 0) {
  645                 device_printf(sc->dev, "time out waiting for reset");
  646                 return (ret);
  647         }
  648 
  649         /* Disable the module */
  650         write_reg(sc, FSPI_MCR0, FSPI_MCR0_MDIS);
  651 
  652         /* Reset the DLL register to default value */
  653         write_reg(sc, FSPI_DLLACR, FSPI_DLLACR_OVRDEN);
  654         write_reg(sc, FSPI_DLLBCR, FSPI_DLLBCR_OVRDEN);
  655 
  656         /* enable module */
  657         write_reg(sc, FSPI_MCR0, FSPI_MCR0_AHB_TIMEOUT(0xFF) |
  658                     FSPI_MCR0_IP_TIMEOUT(0xFF) | (uint32_t) FSPI_MCR0_OCTCOMB_EN);
  659 
  660         /*
  661          * Disable same device enable bit and configure all slave devices
  662          * independently.
  663          */
  664         reg = read_reg(sc, FSPI_MCR2);
  665         reg = reg & ~(FSPI_MCR2_SAMEDEVICEEN);
  666         write_reg(sc, FSPI_MCR2, reg);
  667 
  668         /* AHB configuration for access buffer 0~7. */
  669         for (i = 0; i < 7; i++)
  670                 write_reg(sc, FSPI_AHBRX_BUF0CR0 + 4 * i, 0);
  671 
  672         /*
  673          * Set ADATSZ with the maximum AHB buffer size to improve the read
  674          * performance.
  675          */
  676         write_reg(sc, FSPI_AHBRX_BUF7CR0, (2048 / 8 |
  677                   FSPI_AHBRXBUF0CR7_PREF));
  678 
  679         /* prefetch and no start address alignment limitation */
  680         write_reg(sc, FSPI_AHBCR, FSPI_AHBCR_PREF_EN | FSPI_AHBCR_RDADDROPT);
  681 
  682         /* AHB Read - Set lut sequence ID for all CS. */
  683         flex_spi_prepare_ahb_lut(sc);
  684         write_reg(sc, FSPI_FLSHA1CR2, AHB_LUT_ID);
  685         write_reg(sc, FSPI_FLSHA2CR2, AHB_LUT_ID);
  686         write_reg(sc, FSPI_FLSHB1CR2, AHB_LUT_ID);
  687         write_reg(sc, FSPI_FLSHB2CR2, AHB_LUT_ID);
  688 
  689         /* disable interrupts */
  690         write_reg(sc, FSPI_INTEN, 0);
  691 
  692         return (0);
  693 }
  694 
  695 static int
  696 flex_spi_probe(device_t dev)
  697 {
  698 
  699         if (!ofw_bus_status_okay(dev))
  700                 return (ENXIO);
  701 
  702         if (!ofw_bus_search_compatible(dev, flex_spi_compat_data)->ocd_data)
  703                 return (ENXIO);
  704 
  705         device_set_desc(dev, "NXP FlexSPI Flash");
  706         return (BUS_PROBE_SPECIFIC);
  707 }
  708 
  709 static int
  710 flex_spi_attach(device_t dev)
  711 {
  712         struct flex_spi_softc *sc;
  713         phandle_t node;
  714         int rid;
  715         uint32_t reg;
  716 
  717         node = ofw_bus_get_node(dev);
  718         sc = device_get_softc(dev);
  719         sc->dev = dev;
  720 
  721         mtx_init(&sc->disk_mtx, "flex_spi_DISK", "QSPI disk mtx", MTX_DEF);
  722 
  723         /* Get memory resources. */
  724         rid = 0;
  725         sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
  726             RF_ACTIVE);
  727 
  728         rid = 1;
  729         sc->ahb_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
  730             RF_ACTIVE | RF_SHAREABLE);
  731 
  732         if (sc->mem_res == NULL || sc->ahb_mem_res == NULL) {
  733                 device_printf(dev, "could not allocate resources\n");
  734                 flex_spi_detach(dev);
  735                 return (ENOMEM);
  736         }
  737 
  738         /* Get clocks */
  739         if ((clk_get_by_ofw_name(dev, node, "fspi_en", &sc->fspi_clk_en) != 0)
  740             || (clk_get_freq(sc->fspi_clk_en, &sc->fspi_clk_en_hz) != 0)) {
  741                 device_printf(dev, "could not get fspi_en clock\n");
  742                 flex_spi_detach(dev);
  743                 return (EINVAL);
  744         }
  745         if ((clk_get_by_ofw_name(dev, node, "fspi", &sc->fspi_clk) != 0)
  746             || (clk_get_freq(sc->fspi_clk, &sc->fspi_clk_hz) != 0)) {
  747                 device_printf(dev, "could not get fspi clock\n");
  748                 flex_spi_detach(dev);
  749                 return (EINVAL);
  750         }
  751 
  752         /* Enable clocks */
  753         if (clk_enable(sc->fspi_clk_en) != 0 ||
  754             clk_enable(sc->fspi_clk) != 0) {
  755                 device_printf(dev, "could not enable clocks\n");
  756                 flex_spi_detach(dev);
  757                 return (EINVAL);
  758         }
  759 
  760         /* Clear potential interrupts */
  761         reg = read_reg(sc, FSPI_INTR);
  762         if (reg)
  763                 write_reg(sc, FSPI_INTR, reg);
  764 
  765         /* Default setup */
  766         if (flex_spi_default_setup(sc) != 0) {
  767                 device_printf(sc->dev, "Unable to initialize defaults\n");
  768                 flex_spi_detach(dev);
  769                 return (ENXIO);
  770         }
  771 
  772         /* Identify attached Flash */
  773         if(flex_spi_identify(sc) != 0) {
  774                 device_printf(sc->dev, "Unable to identify Flash\n");
  775                 flex_spi_detach(dev);
  776                 return (ENXIO);
  777         }
  778 
  779         if (flex_spi_clk_setup(sc, sc->fspi_max_clk) != 0) {
  780                 device_printf(sc->dev, "Unable to set up SPI max clock\n");
  781                 flex_spi_detach(dev);
  782                 return (ENXIO);
  783         }
  784 
  785         sc->buf = malloc(sc->erasesize, SECTOR_BUFFER, M_WAITOK);
  786         if (sc->buf == NULL) {
  787                 device_printf(sc->dev, "Unable to set up allocate internal buffer\n");
  788                 flex_spi_detach(dev);
  789                 return (ENOMEM);
  790         }
  791 
  792         /* Move it to per-flash */
  793         sc->disk = disk_alloc();
  794         sc->disk->d_open = flex_spi_open;
  795         sc->disk->d_close = flex_spi_close;
  796         sc->disk->d_strategy = flex_spi_strategy;
  797         sc->disk->d_getattr = flex_spi_getattr;
  798         sc->disk->d_ioctl = flex_spi_ioctl;
  799         sc->disk->d_name = "flash/qspi";
  800         sc->disk->d_drv1 = sc;
  801         /* the most that can fit in a single spi transaction */
  802         sc->disk->d_maxsize = DFLTPHYS;
  803         sc->disk->d_sectorsize = FLASH_SECTORSIZE;
  804         sc->disk->d_unit = device_get_unit(sc->dev);
  805         sc->disk->d_dump = NULL;
  806 
  807         sc->disk->d_mediasize = sc->sectorsize * sc->sectorcount;
  808         sc->disk->d_stripesize = sc->erasesize;
  809 
  810         bioq_init(&sc->bio_queue);
  811         sc->taskstate = TSTATE_RUNNING;
  812         kproc_create(&flex_spi_task, sc, &sc->p, 0, 0, "task: qspi flash");
  813         disk_create(sc->disk, DISK_VERSION);
  814 
  815         return (0);
  816 }
  817 
  818 static int
  819 flex_spi_detach(device_t dev)
  820 {
  821         struct flex_spi_softc *sc;
  822         int err;
  823 
  824         sc = device_get_softc(dev);
  825         err = 0;
  826 
  827         if (!device_is_attached(dev))
  828                 goto free_resources;
  829 
  830         mtx_lock(&sc->disk_mtx);
  831         if (sc->taskstate == TSTATE_RUNNING) {
  832                 sc->taskstate = TSTATE_STOPPING;
  833                 wakeup(sc->disk);
  834                 while (err == 0 && sc->taskstate != TSTATE_STOPPED) {
  835                         err = mtx_sleep(sc->disk, &sc->disk_mtx, 0, "flex_spi",
  836                             hz * 3);
  837                         if (err != 0) {
  838                                 sc->taskstate = TSTATE_RUNNING;
  839                                 device_printf(sc->dev,
  840                                     "Failed to stop queue task\n");
  841                         }
  842                 }
  843         }
  844 
  845         mtx_unlock(&sc->disk_mtx);
  846         mtx_destroy(&sc->disk_mtx);
  847 
  848         if (err == 0 && sc->taskstate == TSTATE_STOPPED) {
  849                 disk_destroy(sc->disk);
  850                 bioq_flush(&sc->bio_queue, NULL, ENXIO);
  851         }
  852 
  853         /* Disable hardware. */
  854 free_resources:
  855         /* Release memory resource. */
  856         if (sc->mem_res != NULL)
  857                 bus_release_resource(dev, SYS_RES_MEMORY,
  858                     rman_get_rid(sc->mem_res), sc->mem_res);
  859 
  860         if (sc->ahb_mem_res != NULL)
  861                 bus_release_resource(dev, SYS_RES_MEMORY,
  862                     rman_get_rid(sc->ahb_mem_res), sc->ahb_mem_res);
  863 
  864         /* Disable clocks */
  865         if (sc->fspi_clk_en_hz)
  866                 clk_disable(sc->fspi_clk_en);
  867         if (sc->fspi_clk_hz)
  868                 clk_disable(sc->fspi_clk);
  869 
  870         free(sc->buf, SECTOR_BUFFER);
  871 
  872         return (err);
  873 }
  874 
  875 static int
  876 flex_spi_open(struct disk *dp)
  877 {
  878 
  879         return (0);
  880 }
  881 
  882 static int
  883 flex_spi_close(struct disk *dp)
  884 {
  885 
  886         return (0);
  887 }
  888 
  889 static int
  890 flex_spi_ioctl(struct disk *dp, u_long cmd, void *data, int fflag,
  891     struct thread *td)
  892 {
  893 
  894         return (ENOTSUP);
  895 }
  896 
  897 static void
  898 flex_spi_strategy(struct bio *bp)
  899 {
  900         struct flex_spi_softc *sc;
  901 
  902         sc = (struct flex_spi_softc *)bp->bio_disk->d_drv1;
  903         mtx_lock(&sc->disk_mtx);
  904         bioq_disksort(&sc->bio_queue, bp);
  905         mtx_unlock(&sc->disk_mtx);
  906         wakeup(sc->disk);
  907 }
  908 
  909 static int
  910 flex_spi_getattr(struct bio *bp)
  911 {
  912         struct flex_spi_softc *sc;
  913         device_t dev;
  914 
  915         if (bp->bio_disk == NULL || bp->bio_disk->d_drv1 == NULL) {
  916                 return (ENXIO);
  917         }
  918 
  919         sc = bp->bio_disk->d_drv1;
  920         dev = sc->dev;
  921 
  922         if (strcmp(bp->bio_attribute, "SPI::device") != 0) {
  923                 return (-1);
  924         }
  925 
  926         if (bp->bio_length != sizeof(dev)) {
  927                 return (EFAULT);
  928         }
  929 
  930         bcopy(&dev, bp->bio_data, sizeof(dev));
  931 
  932         return (0);
  933 }
  934 
  935 static void
  936 flex_spi_task(void *arg)
  937 {
  938         struct flex_spi_softc *sc;
  939         struct bio *bp;
  940 
  941         sc = (struct flex_spi_softc *)arg;
  942         for (;;) {
  943                 mtx_lock(&sc->disk_mtx);
  944                 do {
  945                         if (sc->taskstate == TSTATE_STOPPING) {
  946                                 sc->taskstate = TSTATE_STOPPED;
  947                                 mtx_unlock(&sc->disk_mtx);
  948                                 wakeup(sc->disk);
  949                                 kproc_exit(0);
  950                         }
  951                         bp = bioq_first(&sc->bio_queue);
  952                         if (bp == NULL)
  953                                 mtx_sleep(sc->disk, &sc->disk_mtx, PRIBIO,
  954                                     "flex_spi", 0);
  955                 } while (bp == NULL);
  956                 bioq_remove(&sc->bio_queue, bp);
  957                 mtx_unlock(&sc->disk_mtx);
  958 
  959                 switch (bp->bio_cmd) {
  960                 case BIO_READ:
  961                         bp->bio_error = flex_spi_read(sc, bp->bio_offset,
  962                             bp->bio_data, bp->bio_bcount);
  963                         break;
  964                 case BIO_WRITE:
  965                         bp->bio_error = flex_spi_write(sc, bp->bio_offset,
  966                             bp->bio_data, bp->bio_bcount);
  967                         break;
  968                 default:
  969                         bp->bio_error = EINVAL;
  970                 }
  971                 biodone(bp);
  972         }
  973 }
  974 
  975 static device_method_t flex_spi_methods[] = {
  976         /* Device interface */
  977         DEVMETHOD(device_probe,         flex_spi_probe),
  978         DEVMETHOD(device_attach,        flex_spi_attach),
  979         DEVMETHOD(device_detach,        flex_spi_detach),
  980 
  981         { 0, 0 }
  982 };
  983 
  984 static driver_t flex_spi_driver = {
  985         "flex_spi",
  986         flex_spi_methods,
  987         sizeof(struct flex_spi_softc),
  988 };
  989 
  990 DRIVER_MODULE(flex_spi, simplebus, flex_spi_driver, 0, 0);
  991 SIMPLEBUS_PNP_INFO(flex_spi_compat_data);
Cache object: c63f020b55d259a165ed0012d28c4906
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FreeBSD/Linux Kernel Cross Reference sys/dev/flash/flexspi/flex_spi.c

FreeBSD/Linux Kernel Cross Reference
sys/dev/flash/flexspi/flex_spi.c
