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sys/dev/fxp/if_fxp.c
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1 /*- 2 * Copyright (c) 1995, David Greenman 3 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD: releng/5.0/sys/dev/fxp/if_fxp.c 106937 2002-11-14 23:54:55Z sam $ 29 */ 30 31 /* 32 * Intel EtherExpress Pro/100B PCI Fast Ethernet driver 33 */ 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/mbuf.h> 38 #include <sys/malloc.h> 39 /* #include <sys/mutex.h> */ 40 #include <sys/kernel.h> 41 #include <sys/socket.h> 42 #include <sys/sysctl.h> 43 44 #include <net/if.h> 45 #include <net/if_dl.h> 46 #include <net/if_media.h> 47 48 #ifdef NS 49 #include <netns/ns.h> 50 #include <netns/ns_if.h> 51 #endif 52 53 #include <net/bpf.h> 54 #include <sys/sockio.h> 55 #include <sys/bus.h> 56 #include <machine/bus.h> 57 #include <sys/rman.h> 58 #include <machine/resource.h> 59 60 #include <net/ethernet.h> 61 #include <net/if_arp.h> 62 63 #include <vm/vm.h> /* for vtophys */ 64 #include <vm/pmap.h> /* for vtophys */ 65 #include <machine/clock.h> /* for DELAY */ 66 67 #include <net/if_types.h> 68 #include <net/if_vlan_var.h> 69 70 #include <pci/pcivar.h> 71 #include <pci/pcireg.h> /* for PCIM_CMD_xxx */ 72 73 #include <dev/mii/mii.h> 74 #include <dev/mii/miivar.h> 75 76 #include <dev/fxp/if_fxpreg.h> 77 #include <dev/fxp/if_fxpvar.h> 78 #include <dev/fxp/rcvbundl.h> 79 80 MODULE_DEPEND(fxp, miibus, 1, 1, 1); 81 #include "miibus_if.h" 82 83 /* 84 * NOTE! On the Alpha, we have an alignment constraint. The 85 * card DMAs the packet immediately following the RFA. However, 86 * the first thing in the packet is a 14-byte Ethernet header. 87 * This means that the packet is misaligned. To compensate, 88 * we actually offset the RFA 2 bytes into the cluster. This 89 * alignes the packet after the Ethernet header at a 32-bit 90 * boundary. HOWEVER! This means that the RFA is misaligned! 91 */ 92 #define RFA_ALIGNMENT_FUDGE 2 93 94 /* 95 * Set initial transmit threshold at 64 (512 bytes). This is 96 * increased by 64 (512 bytes) at a time, to maximum of 192 97 * (1536 bytes), if an underrun occurs. 98 */ 99 static int tx_threshold = 64; 100 101 /* 102 * The configuration byte map has several undefined fields which 103 * must be one or must be zero. Set up a template for these bits 104 * only, (assuming a 82557 chip) leaving the actual configuration 105 * to fxp_init. 106 * 107 * See struct fxp_cb_config for the bit definitions. 108 */ 109 static u_char fxp_cb_config_template[] = { 110 0x0, 0x0, /* cb_status */ 111 0x0, 0x0, /* cb_command */ 112 0x0, 0x0, 0x0, 0x0, /* link_addr */ 113 0x0, /* 0 */ 114 0x0, /* 1 */ 115 0x0, /* 2 */ 116 0x0, /* 3 */ 117 0x0, /* 4 */ 118 0x0, /* 5 */ 119 0x32, /* 6 */ 120 0x0, /* 7 */ 121 0x0, /* 8 */ 122 0x0, /* 9 */ 123 0x6, /* 10 */ 124 0x0, /* 11 */ 125 0x0, /* 12 */ 126 0x0, /* 13 */ 127 0xf2, /* 14 */ 128 0x48, /* 15 */ 129 0x0, /* 16 */ 130 0x40, /* 17 */ 131 0xf0, /* 18 */ 132 0x0, /* 19 */ 133 0x3f, /* 20 */ 134 0x5 /* 21 */ 135 }; 136 137 struct fxp_ident { 138 u_int16_t devid; 139 char *name; 140 }; 141 142 /* 143 * Claim various Intel PCI device identifiers for this driver. The 144 * sub-vendor and sub-device field are extensively used to identify 145 * particular variants, but we don't currently differentiate between 146 * them. 147 */ 148 static struct fxp_ident fxp_ident_table[] = { 149 { 0x1229, "Intel Pro 10/100B/100+ Ethernet" }, 150 { 0x2449, "Intel Pro/100 Ethernet" }, 151 { 0x1209, "Intel Embedded 10/100 Ethernet" }, 152 { 0x1029, "Intel Pro/100 Ethernet" }, 153 { 0x1030, "Intel Pro/100 Ethernet" }, 154 { 0x1031, "Intel Pro/100 Ethernet" }, 155 { 0x1032, "Intel Pro/100 Ethernet" }, 156 { 0x1033, "Intel Pro/100 Ethernet" }, 157 { 0x1034, "Intel Pro/100 Ethernet" }, 158 { 0x1035, "Intel Pro/100 Ethernet" }, 159 { 0x1036, "Intel Pro/100 Ethernet" }, 160 { 0x1037, "Intel Pro/100 Ethernet" }, 161 { 0x1038, "Intel Pro/100 Ethernet" }, 162 { 0x1039, "Intel Pro/100 Ethernet" }, 163 { 0x103A, "Intel Pro/100 Ethernet" }, 164 { 0x103B, "Intel Pro/100 Ethernet" }, 165 { 0x103C, "Intel Pro/100 Ethernet" }, 166 { 0x103D, "Intel Pro/100 Ethernet" }, 167 { 0x103E, "Intel Pro/100 Ethernet" }, 168 { 0, NULL }, 169 }; 170 171 static int fxp_probe(device_t dev); 172 static int fxp_attach(device_t dev); 173 static int fxp_detach(device_t dev); 174 static int fxp_shutdown(device_t dev); 175 static int fxp_suspend(device_t dev); 176 static int fxp_resume(device_t dev); 177 178 static void fxp_intr(void *xsc); 179 static void fxp_init(void *xsc); 180 static void fxp_tick(void *xsc); 181 static void fxp_powerstate_d0(device_t dev); 182 static void fxp_start(struct ifnet *ifp); 183 static void fxp_stop(struct fxp_softc *sc); 184 static void fxp_release(struct fxp_softc *sc); 185 static int fxp_ioctl(struct ifnet *ifp, u_long command, 186 caddr_t data); 187 static void fxp_watchdog(struct ifnet *ifp); 188 static int fxp_add_rfabuf(struct fxp_softc *sc, struct mbuf *oldm); 189 static int fxp_mc_addrs(struct fxp_softc *sc); 190 static void fxp_mc_setup(struct fxp_softc *sc); 191 static u_int16_t fxp_eeprom_getword(struct fxp_softc *sc, int offset, 192 int autosize); 193 static void fxp_eeprom_putword(struct fxp_softc *sc, int offset, 194 u_int16_t data); 195 static void fxp_autosize_eeprom(struct fxp_softc *sc); 196 static void fxp_read_eeprom(struct fxp_softc *sc, u_short *data, 197 int offset, int words); 198 static void fxp_write_eeprom(struct fxp_softc *sc, u_short *data, 199 int offset, int words); 200 static int fxp_ifmedia_upd(struct ifnet *ifp); 201 static void fxp_ifmedia_sts(struct ifnet *ifp, 202 struct ifmediareq *ifmr); 203 static int fxp_serial_ifmedia_upd(struct ifnet *ifp); 204 static void fxp_serial_ifmedia_sts(struct ifnet *ifp, 205 struct ifmediareq *ifmr); 206 static volatile int fxp_miibus_readreg(device_t dev, int phy, int reg); 207 static void fxp_miibus_writereg(device_t dev, int phy, int reg, 208 int value); 209 static void fxp_load_ucode(struct fxp_softc *sc); 210 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, 211 int low, int high); 212 static int sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS); 213 static int sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS); 214 static __inline void fxp_lwcopy(volatile u_int32_t *src, 215 volatile u_int32_t *dst); 216 static __inline void fxp_scb_wait(struct fxp_softc *sc); 217 static __inline void fxp_scb_cmd(struct fxp_softc *sc, int cmd); 218 static __inline void fxp_dma_wait(volatile u_int16_t *status, 219 struct fxp_softc *sc); 220 221 static device_method_t fxp_methods[] = { 222 /* Device interface */ 223 DEVMETHOD(device_probe, fxp_probe), 224 DEVMETHOD(device_attach, fxp_attach), 225 DEVMETHOD(device_detach, fxp_detach), 226 DEVMETHOD(device_shutdown, fxp_shutdown), 227 DEVMETHOD(device_suspend, fxp_suspend), 228 DEVMETHOD(device_resume, fxp_resume), 229 230 /* MII interface */ 231 DEVMETHOD(miibus_readreg, fxp_miibus_readreg), 232 DEVMETHOD(miibus_writereg, fxp_miibus_writereg), 233 234 { 0, 0 } 235 }; 236 237 static driver_t fxp_driver = { 238 "fxp", 239 fxp_methods, 240 sizeof(struct fxp_softc), 241 }; 242 243 static devclass_t fxp_devclass; 244 245 DRIVER_MODULE(if_fxp, pci, fxp_driver, fxp_devclass, 0, 0); 246 DRIVER_MODULE(if_fxp, cardbus, fxp_driver, fxp_devclass, 0, 0); 247 DRIVER_MODULE(miibus, fxp, miibus_driver, miibus_devclass, 0, 0); 248 249 static int fxp_rnr; 250 SYSCTL_INT(_hw, OID_AUTO, fxp_rnr, CTLFLAG_RW, &fxp_rnr, 0, "fxp rnr events"); 251 252 /* 253 * Inline function to copy a 16-bit aligned 32-bit quantity. 254 */ 255 static __inline void 256 fxp_lwcopy(volatile u_int32_t *src, volatile u_int32_t *dst) 257 { 258 #ifdef __i386__ 259 *dst = *src; 260 #else 261 volatile u_int16_t *a = (volatile u_int16_t *)src; 262 volatile u_int16_t *b = (volatile u_int16_t *)dst; 263 264 b[0] = a[0]; 265 b[1] = a[1]; 266 #endif 267 } 268 269 /* 270 * Wait for the previous command to be accepted (but not necessarily 271 * completed). 272 */ 273 static __inline void 274 fxp_scb_wait(struct fxp_softc *sc) 275 { 276 int i = 10000; 277 278 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i) 279 DELAY(2); 280 if (i == 0) 281 device_printf(sc->dev, "SCB timeout: 0x%x 0x%x 0x%x 0x%x\n", 282 CSR_READ_1(sc, FXP_CSR_SCB_COMMAND), 283 CSR_READ_1(sc, FXP_CSR_SCB_STATACK), 284 CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS), 285 CSR_READ_2(sc, FXP_CSR_FLOWCONTROL)); 286 } 287 288 static __inline void 289 fxp_scb_cmd(struct fxp_softc *sc, int cmd) 290 { 291 292 if (cmd == FXP_SCB_COMMAND_CU_RESUME && sc->cu_resume_bug) { 293 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP); 294 fxp_scb_wait(sc); 295 } 296 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); 297 } 298 299 static __inline void 300 fxp_dma_wait(volatile u_int16_t *status, struct fxp_softc *sc) 301 { 302 int i = 10000; 303 304 while (!(*status & FXP_CB_STATUS_C) && --i) 305 DELAY(2); 306 if (i == 0) 307 device_printf(sc->dev, "DMA timeout\n"); 308 } 309 310 /* 311 * Return identification string if this is device is ours. 312 */ 313 static int 314 fxp_probe(device_t dev) 315 { 316 u_int16_t devid; 317 struct fxp_ident *ident; 318 319 if (pci_get_vendor(dev) == FXP_VENDORID_INTEL) { 320 devid = pci_get_device(dev); 321 for (ident = fxp_ident_table; ident->name != NULL; ident++) { 322 if (ident->devid == devid) { 323 device_set_desc(dev, ident->name); 324 return (0); 325 } 326 } 327 } 328 return (ENXIO); 329 } 330 331 static void 332 fxp_powerstate_d0(device_t dev) 333 { 334 #if __FreeBSD_version >= 430002 335 u_int32_t iobase, membase, irq; 336 337 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 338 /* Save important PCI config data. */ 339 iobase = pci_read_config(dev, FXP_PCI_IOBA, 4); 340 membase = pci_read_config(dev, FXP_PCI_MMBA, 4); 341 irq = pci_read_config(dev, PCIR_INTLINE, 4); 342 343 /* Reset the power state. */ 344 device_printf(dev, "chip is in D%d power mode " 345 "-- setting to D0\n", pci_get_powerstate(dev)); 346 347 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 348 349 /* Restore PCI config data. */ 350 pci_write_config(dev, FXP_PCI_IOBA, iobase, 4); 351 pci_write_config(dev, FXP_PCI_MMBA, membase, 4); 352 pci_write_config(dev, PCIR_INTLINE, irq, 4); 353 } 354 #endif 355 } 356 357 static int 358 fxp_attach(device_t dev) 359 { 360 int error = 0; 361 struct fxp_softc *sc = device_get_softc(dev); 362 struct ifnet *ifp; 363 u_int32_t val; 364 u_int16_t data; 365 int i, rid, m1, m2, prefer_iomap; 366 int s; 367 368 bzero(sc, sizeof(*sc)); 369 sc->dev = dev; 370 callout_handle_init(&sc->stat_ch); 371 sysctl_ctx_init(&sc->sysctl_ctx); 372 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 373 MTX_DEF | MTX_RECURSE); 374 375 s = splimp(); 376 377 /* 378 * Enable bus mastering. Enable memory space too, in case 379 * BIOS/Prom forgot about it. 380 */ 381 val = pci_read_config(dev, PCIR_COMMAND, 2); 382 val |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 383 pci_write_config(dev, PCIR_COMMAND, val, 2); 384 val = pci_read_config(dev, PCIR_COMMAND, 2); 385 386 fxp_powerstate_d0(dev); 387 388 /* 389 * Figure out which we should try first - memory mapping or i/o mapping? 390 * We default to memory mapping. Then we accept an override from the 391 * command line. Then we check to see which one is enabled. 392 */ 393 m1 = PCIM_CMD_MEMEN; 394 m2 = PCIM_CMD_PORTEN; 395 prefer_iomap = 0; 396 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 397 "prefer_iomap", &prefer_iomap) == 0 && prefer_iomap != 0) { 398 m1 = PCIM_CMD_PORTEN; 399 m2 = PCIM_CMD_MEMEN; 400 } 401 402 if (val & m1) { 403 sc->rtp = 404 (m1 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 405 sc->rgd = (m1 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 406 sc->mem = bus_alloc_resource(dev, sc->rtp, &sc->rgd, 407 0, ~0, 1, RF_ACTIVE); 408 } 409 if (sc->mem == NULL && (val & m2)) { 410 sc->rtp = 411 (m2 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT; 412 sc->rgd = (m2 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA; 413 sc->mem = bus_alloc_resource(dev, sc->rtp, &sc->rgd, 414 0, ~0, 1, RF_ACTIVE); 415 } 416 417 if (!sc->mem) { 418 device_printf(dev, "could not map device registers\n"); 419 error = ENXIO; 420 goto fail; 421 } 422 if (bootverbose) { 423 device_printf(dev, "using %s space register mapping\n", 424 sc->rtp == SYS_RES_MEMORY? "memory" : "I/O"); 425 } 426 427 sc->sc_st = rman_get_bustag(sc->mem); 428 sc->sc_sh = rman_get_bushandle(sc->mem); 429 430 /* 431 * Allocate our interrupt. 432 */ 433 rid = 0; 434 sc->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 435 RF_SHAREABLE | RF_ACTIVE); 436 if (sc->irq == NULL) { 437 device_printf(dev, "could not map interrupt\n"); 438 error = ENXIO; 439 goto fail; 440 } 441 442 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET, 443 fxp_intr, sc, &sc->ih); 444 if (error) { 445 device_printf(dev, "could not setup irq\n"); 446 goto fail; 447 } 448 449 /* 450 * Reset to a stable state. 451 */ 452 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 453 DELAY(10); 454 455 sc->cbl_base = malloc(sizeof(struct fxp_cb_tx) * FXP_NTXCB, 456 M_DEVBUF, M_NOWAIT | M_ZERO); 457 if (sc->cbl_base == NULL) 458 goto failmem; 459 460 sc->fxp_stats = malloc(sizeof(struct fxp_stats), M_DEVBUF, 461 M_NOWAIT | M_ZERO); 462 if (sc->fxp_stats == NULL) 463 goto failmem; 464 465 sc->mcsp = malloc(sizeof(struct fxp_cb_mcs), M_DEVBUF, M_NOWAIT); 466 if (sc->mcsp == NULL) 467 goto failmem; 468 469 /* 470 * Pre-allocate our receive buffers. 471 */ 472 for (i = 0; i < FXP_NRFABUFS; i++) { 473 if (fxp_add_rfabuf(sc, NULL) != 0) { 474 goto failmem; 475 } 476 } 477 478 /* 479 * Find out how large of an SEEPROM we have. 480 */ 481 fxp_autosize_eeprom(sc); 482 483 /* 484 * Determine whether we must use the 503 serial interface. 485 */ 486 fxp_read_eeprom(sc, &data, 6, 1); 487 if ((data & FXP_PHY_DEVICE_MASK) != 0 && 488 (data & FXP_PHY_SERIAL_ONLY)) 489 sc->flags |= FXP_FLAG_SERIAL_MEDIA; 490 491 /* 492 * Create the sysctl tree 493 */ 494 sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx, 495 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO, 496 device_get_nameunit(dev), CTLFLAG_RD, 0, ""); 497 if (sc->sysctl_tree == NULL) 498 goto fail; 499 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 500 OID_AUTO, "int_delay", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON, 501 &sc->tunable_int_delay, 0, sysctl_hw_fxp_int_delay, "I", 502 "FXP driver receive interrupt microcode bundling delay"); 503 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree), 504 OID_AUTO, "bundle_max", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON, 505 &sc->tunable_bundle_max, 0, sysctl_hw_fxp_bundle_max, "I", 506 "FXP driver receive interrupt microcode bundle size limit"); 507 508 /* 509 * Pull in device tunables. 510 */ 511 sc->tunable_int_delay = TUNABLE_INT_DELAY; 512 sc->tunable_bundle_max = TUNABLE_BUNDLE_MAX; 513 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 514 "int_delay", &sc->tunable_int_delay); 515 (void) resource_int_value(device_get_name(dev), device_get_unit(dev), 516 "bundle_max", &sc->tunable_bundle_max); 517 518 /* 519 * Find out the chip revision; lump all 82557 revs together. 520 */ 521 fxp_read_eeprom(sc, &data, 5, 1); 522 if ((data >> 8) == 1) 523 sc->revision = FXP_REV_82557; 524 else 525 sc->revision = pci_get_revid(dev); 526 527 /* 528 * Enable workarounds for certain chip revision deficiencies. 529 * 530 * Systems based on the ICH2/ICH2-M chip from Intel, and possibly 531 * some systems based a normal 82559 design, have a defect where 532 * the chip can cause a PCI protocol violation if it receives 533 * a CU_RESUME command when it is entering the IDLE state. The 534 * workaround is to disable Dynamic Standby Mode, so the chip never 535 * deasserts CLKRUN#, and always remains in an active state. 536 * 537 * See Intel 82801BA/82801BAM Specification Update, Errata #30. 538 */ 539 i = pci_get_device(dev); 540 if (i == 0x2449 || (i > 0x1030 && i < 0x1039) || 541 sc->revision >= FXP_REV_82559_A0) { 542 fxp_read_eeprom(sc, &data, 10, 1); 543 if (data & 0x02) { /* STB enable */ 544 u_int16_t cksum; 545 int i; 546 547 device_printf(dev, 548 "Disabling dynamic standby mode in EEPROM\n"); 549 data &= ~0x02; 550 fxp_write_eeprom(sc, &data, 10, 1); 551 device_printf(dev, "New EEPROM ID: 0x%x\n", data); 552 cksum = 0; 553 for (i = 0; i < (1 << sc->eeprom_size) - 1; i++) { 554 fxp_read_eeprom(sc, &data, i, 1); 555 cksum += data; 556 } 557 i = (1 << sc->eeprom_size) - 1; 558 cksum = 0xBABA - cksum; 559 fxp_read_eeprom(sc, &data, i, 1); 560 fxp_write_eeprom(sc, &cksum, i, 1); 561 device_printf(dev, 562 "EEPROM checksum @ 0x%x: 0x%x -> 0x%x\n", 563 i, data, cksum); 564 #if 1 565 /* 566 * If the user elects to continue, try the software 567 * workaround, as it is better than nothing. 568 */ 569 sc->flags |= FXP_FLAG_CU_RESUME_BUG; 570 #endif 571 } 572 } 573 574 /* 575 * If we are not a 82557 chip, we can enable extended features. 576 */ 577 if (sc->revision != FXP_REV_82557) { 578 /* 579 * If MWI is enabled in the PCI configuration, and there 580 * is a valid cacheline size (8 or 16 dwords), then tell 581 * the board to turn on MWI. 582 */ 583 if (val & PCIM_CMD_MWRICEN && 584 pci_read_config(dev, PCIR_CACHELNSZ, 1) != 0) 585 sc->flags |= FXP_FLAG_MWI_ENABLE; 586 587 /* turn on the extended TxCB feature */ 588 sc->flags |= FXP_FLAG_EXT_TXCB; 589 590 /* enable reception of long frames for VLAN */ 591 sc->flags |= FXP_FLAG_LONG_PKT_EN; 592 } 593 594 /* 595 * Read MAC address. 596 */ 597 fxp_read_eeprom(sc, (u_int16_t *)sc->arpcom.ac_enaddr, 0, 3); 598 device_printf(dev, "Ethernet address %6D%s\n", 599 sc->arpcom.ac_enaddr, ":", 600 sc->flags & FXP_FLAG_SERIAL_MEDIA ? ", 10Mbps" : ""); 601 if (bootverbose) { 602 device_printf(dev, "PCI IDs: %04x %04x %04x %04x %04x\n", 603 pci_get_vendor(dev), pci_get_device(dev), 604 pci_get_subvendor(dev), pci_get_subdevice(dev), 605 pci_get_revid(dev)); 606 fxp_read_eeprom(sc, &data, 10, 1); 607 device_printf(dev, "Dynamic Standby mode is %s\n", 608 data & 0x02 ? "enabled" : "disabled"); 609 } 610 611 /* 612 * If this is only a 10Mbps device, then there is no MII, and 613 * the PHY will use a serial interface instead. 614 * 615 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter 616 * doesn't have a programming interface of any sort. The 617 * media is sensed automatically based on how the link partner 618 * is configured. This is, in essence, manual configuration. 619 */ 620 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) { 621 ifmedia_init(&sc->sc_media, 0, fxp_serial_ifmedia_upd, 622 fxp_serial_ifmedia_sts); 623 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 624 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 625 } else { 626 if (mii_phy_probe(dev, &sc->miibus, fxp_ifmedia_upd, 627 fxp_ifmedia_sts)) { 628 device_printf(dev, "MII without any PHY!\n"); 629 error = ENXIO; 630 goto fail; 631 } 632 } 633 634 ifp = &sc->arpcom.ac_if; 635 ifp->if_unit = device_get_unit(dev); 636 ifp->if_name = "fxp"; 637 ifp->if_output = ether_output; 638 ifp->if_baudrate = 100000000; 639 ifp->if_init = fxp_init; 640 ifp->if_softc = sc; 641 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 642 ifp->if_ioctl = fxp_ioctl; 643 ifp->if_start = fxp_start; 644 ifp->if_watchdog = fxp_watchdog; 645 646 /* 647 * Attach the interface. 648 */ 649 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 650 651 /* 652 * Tell the upper layer(s) we support long frames. 653 */ 654 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 655 ifp->if_capabilities |= IFCAP_VLAN_MTU; 656 657 /* 658 * Let the system queue as many packets as we have available 659 * TX descriptors. 660 */ 661 ifp->if_snd.ifq_maxlen = FXP_NTXCB - 1; 662 663 splx(s); 664 return (0); 665 666 failmem: 667 device_printf(dev, "Failed to malloc memory\n"); 668 error = ENOMEM; 669 fail: 670 splx(s); 671 fxp_release(sc); 672 return (error); 673 } 674 675 /* 676 * release all resources 677 */ 678 static void 679 fxp_release(struct fxp_softc *sc) 680 { 681 682 bus_generic_detach(sc->dev); 683 if (sc->miibus) 684 device_delete_child(sc->dev, sc->miibus); 685 686 if (sc->cbl_base) 687 free(sc->cbl_base, M_DEVBUF); 688 if (sc->fxp_stats) 689 free(sc->fxp_stats, M_DEVBUF); 690 if (sc->mcsp) 691 free(sc->mcsp, M_DEVBUF); 692 if (sc->rfa_headm) 693 m_freem(sc->rfa_headm); 694 695 if (sc->ih) 696 bus_teardown_intr(sc->dev, sc->irq, sc->ih); 697 if (sc->irq) 698 bus_release_resource(sc->dev, SYS_RES_IRQ, 0, sc->irq); 699 if (sc->mem) 700 bus_release_resource(sc->dev, sc->rtp, sc->rgd, sc->mem); 701 702 sysctl_ctx_free(&sc->sysctl_ctx); 703 704 mtx_destroy(&sc->sc_mtx); 705 } 706 707 /* 708 * Detach interface. 709 */ 710 static int 711 fxp_detach(device_t dev) 712 { 713 struct fxp_softc *sc = device_get_softc(dev); 714 int s; 715 716 /* disable interrupts */ 717 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 718 719 s = splimp(); 720 721 /* 722 * Stop DMA and drop transmit queue. 723 */ 724 fxp_stop(sc); 725 726 /* 727 * Close down routes etc. 728 */ 729 ether_ifdetach(&sc->arpcom.ac_if); 730 731 /* 732 * Free all media structures. 733 */ 734 ifmedia_removeall(&sc->sc_media); 735 736 splx(s); 737 738 /* Release our allocated resources. */ 739 fxp_release(sc); 740 741 return (0); 742 } 743 744 /* 745 * Device shutdown routine. Called at system shutdown after sync. The 746 * main purpose of this routine is to shut off receiver DMA so that 747 * kernel memory doesn't get clobbered during warmboot. 748 */ 749 static int 750 fxp_shutdown(device_t dev) 751 { 752 /* 753 * Make sure that DMA is disabled prior to reboot. Not doing 754 * do could allow DMA to corrupt kernel memory during the 755 * reboot before the driver initializes. 756 */ 757 fxp_stop((struct fxp_softc *) device_get_softc(dev)); 758 return (0); 759 } 760 761 /* 762 * Device suspend routine. Stop the interface and save some PCI 763 * settings in case the BIOS doesn't restore them properly on 764 * resume. 765 */ 766 static int 767 fxp_suspend(device_t dev) 768 { 769 struct fxp_softc *sc = device_get_softc(dev); 770 int i, s; 771 772 s = splimp(); 773 774 fxp_stop(sc); 775 776 for (i = 0; i < 5; i++) 777 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4); 778 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 779 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 780 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 781 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 782 783 sc->suspended = 1; 784 785 splx(s); 786 return (0); 787 } 788 789 /* 790 * Device resume routine. Restore some PCI settings in case the BIOS 791 * doesn't, re-enable busmastering, and restart the interface if 792 * appropriate. 793 */ 794 static int 795 fxp_resume(device_t dev) 796 { 797 struct fxp_softc *sc = device_get_softc(dev); 798 struct ifnet *ifp = &sc->sc_if; 799 u_int16_t pci_command; 800 int i, s; 801 802 s = splimp(); 803 804 fxp_powerstate_d0(dev); 805 806 /* better way to do this? */ 807 for (i = 0; i < 5; i++) 808 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4); 809 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 810 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 811 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 812 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 813 814 /* reenable busmastering */ 815 pci_command = pci_read_config(dev, PCIR_COMMAND, 2); 816 pci_command |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 817 pci_write_config(dev, PCIR_COMMAND, pci_command, 2); 818 819 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET); 820 DELAY(10); 821 822 /* reinitialize interface if necessary */ 823 if (ifp->if_flags & IFF_UP) 824 fxp_init(sc); 825 826 sc->suspended = 0; 827 828 splx(s); 829 return (0); 830 } 831 832 static void 833 fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int length) 834 { 835 u_int16_t reg; 836 int x; 837 838 /* 839 * Shift in data. 840 */ 841 for (x = 1 << (length - 1); x; x >>= 1) { 842 if (data & x) 843 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 844 else 845 reg = FXP_EEPROM_EECS; 846 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 847 DELAY(1); 848 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 849 DELAY(1); 850 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 851 DELAY(1); 852 } 853 } 854 855 /* 856 * Read from the serial EEPROM. Basically, you manually shift in 857 * the read opcode (one bit at a time) and then shift in the address, 858 * and then you shift out the data (all of this one bit at a time). 859 * The word size is 16 bits, so you have to provide the address for 860 * every 16 bits of data. 861 */ 862 static u_int16_t 863 fxp_eeprom_getword(struct fxp_softc *sc, int offset, int autosize) 864 { 865 u_int16_t reg, data; 866 int x; 867 868 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 869 /* 870 * Shift in read opcode. 871 */ 872 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3); 873 /* 874 * Shift in address. 875 */ 876 data = 0; 877 for (x = 1 << (sc->eeprom_size - 1); x; x >>= 1) { 878 if (offset & x) 879 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI; 880 else 881 reg = FXP_EEPROM_EECS; 882 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 883 DELAY(1); 884 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 885 DELAY(1); 886 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 887 DELAY(1); 888 reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO; 889 data++; 890 if (autosize && reg == 0) { 891 sc->eeprom_size = data; 892 break; 893 } 894 } 895 /* 896 * Shift out data. 897 */ 898 data = 0; 899 reg = FXP_EEPROM_EECS; 900 for (x = 1 << 15; x; x >>= 1) { 901 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); 902 DELAY(1); 903 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 904 data |= x; 905 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); 906 DELAY(1); 907 } 908 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 909 DELAY(1); 910 911 return (data); 912 } 913 914 static void 915 fxp_eeprom_putword(struct fxp_softc *sc, int offset, u_int16_t data) 916 { 917 int i; 918 919 /* 920 * Erase/write enable. 921 */ 922 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 923 fxp_eeprom_shiftin(sc, 0x4, 3); 924 fxp_eeprom_shiftin(sc, 0x03 << (sc->eeprom_size - 2), sc->eeprom_size); 925 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 926 DELAY(1); 927 /* 928 * Shift in write opcode, address, data. 929 */ 930 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 931 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3); 932 fxp_eeprom_shiftin(sc, offset, sc->eeprom_size); 933 fxp_eeprom_shiftin(sc, data, 16); 934 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 935 DELAY(1); 936 /* 937 * Wait for EEPROM to finish up. 938 */ 939 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 940 DELAY(1); 941 for (i = 0; i < 1000; i++) { 942 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO) 943 break; 944 DELAY(50); 945 } 946 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 947 DELAY(1); 948 /* 949 * Erase/write disable. 950 */ 951 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); 952 fxp_eeprom_shiftin(sc, 0x4, 3); 953 fxp_eeprom_shiftin(sc, 0, sc->eeprom_size); 954 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); 955 DELAY(1); 956 } 957 958 /* 959 * From NetBSD: 960 * 961 * Figure out EEPROM size. 962 * 963 * 559's can have either 64-word or 256-word EEPROMs, the 558 964 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet 965 * talks about the existance of 16 to 256 word EEPROMs. 966 * 967 * The only known sizes are 64 and 256, where the 256 version is used 968 * by CardBus cards to store CIS information. 969 * 970 * The address is shifted in msb-to-lsb, and after the last 971 * address-bit the EEPROM is supposed to output a `dummy zero' bit, 972 * after which follows the actual data. We try to detect this zero, by 973 * probing the data-out bit in the EEPROM control register just after 974 * having shifted in a bit. If the bit is zero, we assume we've 975 * shifted enough address bits. The data-out should be tri-state, 976 * before this, which should translate to a logical one. 977 */ 978 static void 979 fxp_autosize_eeprom(struct fxp_softc *sc) 980 { 981 982 /* guess maximum size of 256 words */ 983 sc->eeprom_size = 8; 984 985 /* autosize */ 986 (void) fxp_eeprom_getword(sc, 0, 1); 987 } 988 989 static void 990 fxp_read_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 991 { 992 int i; 993 994 for (i = 0; i < words; i++) 995 data[i] = fxp_eeprom_getword(sc, offset + i, 0); 996 } 997 998 static void 999 fxp_write_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words) 1000 { 1001 int i; 1002 1003 for (i = 0; i < words; i++) 1004 fxp_eeprom_putword(sc, offset + i, data[i]); 1005 } 1006 1007 /* 1008 * Start packet transmission on the interface. 1009 */ 1010 static void 1011 fxp_start(struct ifnet *ifp) 1012 { 1013 struct fxp_softc *sc = ifp->if_softc; 1014 struct fxp_cb_tx *txp; 1015 1016 /* 1017 * See if we need to suspend xmit until the multicast filter 1018 * has been reprogrammed (which can only be done at the head 1019 * of the command chain). 1020 */ 1021 if (sc->need_mcsetup) { 1022 return; 1023 } 1024 1025 txp = NULL; 1026 1027 /* 1028 * We're finished if there is nothing more to add to the list or if 1029 * we're all filled up with buffers to transmit. 1030 * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add 1031 * a NOP command when needed. 1032 */ 1033 while (ifp->if_snd.ifq_head != NULL && sc->tx_queued < FXP_NTXCB - 1) { 1034 struct mbuf *m, *mb_head; 1035 int segment; 1036 1037 /* 1038 * Grab a packet to transmit. 1039 */ 1040 IF_DEQUEUE(&ifp->if_snd, mb_head); 1041 1042 /* 1043 * Get pointer to next available tx desc. 1044 */ 1045 txp = sc->cbl_last->next; 1046 1047 /* 1048 * Go through each of the mbufs in the chain and initialize 1049 * the transmit buffer descriptors with the physical address 1050 * and size of the mbuf. 1051 */ 1052 tbdinit: 1053 for (m = mb_head, segment = 0; m != NULL; m = m->m_next) { 1054 if (m->m_len != 0) { 1055 if (segment == FXP_NTXSEG) 1056 break; 1057 txp->tbd[segment].tb_addr = 1058 vtophys(mtod(m, vm_offset_t)); 1059 txp->tbd[segment].tb_size = m->m_len; 1060 segment++; 1061 } 1062 } 1063 if (m != NULL) { 1064 struct mbuf *mn; 1065 1066 /* 1067 * We ran out of segments. We have to recopy this 1068 * mbuf chain first. Bail out if we can't get the 1069 * new buffers. 1070 */ 1071 MGETHDR(mn, M_DONTWAIT, MT_DATA); 1072 if (mn == NULL) { 1073 m_freem(mb_head); 1074 break; 1075 } 1076 if (mb_head->m_pkthdr.len > MHLEN) { 1077 MCLGET(mn, M_DONTWAIT); 1078 if ((mn->m_flags & M_EXT) == 0) { 1079 m_freem(mn); 1080 m_freem(mb_head); 1081 break; 1082 } 1083 } 1084 m_copydata(mb_head, 0, mb_head->m_pkthdr.len, 1085 mtod(mn, caddr_t)); 1086 mn->m_pkthdr.len = mn->m_len = mb_head->m_pkthdr.len; 1087 m_freem(mb_head); 1088 mb_head = mn; 1089 goto tbdinit; 1090 } 1091 1092 txp->tbd_number = segment; 1093 txp->mb_head = mb_head; 1094 txp->cb_status = 0; 1095 if (sc->tx_queued != FXP_CXINT_THRESH - 1) { 1096 txp->cb_command = 1097 FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF | 1098 FXP_CB_COMMAND_S; 1099 } else { 1100 txp->cb_command = 1101 FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF | 1102 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; 1103 /* 1104 * Set a 5 second timer just in case we don't hear 1105 * from the card again. 1106 */ 1107 ifp->if_timer = 5; 1108 } 1109 txp->tx_threshold = tx_threshold; 1110 1111 /* 1112 * Advance the end of list forward. 1113 */ 1114 1115 #ifdef __alpha__ 1116 /* 1117 * On platforms which can't access memory in 16-bit 1118 * granularities, we must prevent the card from DMA'ing 1119 * up the status while we update the command field. 1120 * This could cause us to overwrite the completion status. 1121 */ 1122 atomic_clear_short(&sc->cbl_last->cb_command, 1123 FXP_CB_COMMAND_S); 1124 #else 1125 sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S; 1126 #endif /*__alpha__*/ 1127 sc->cbl_last = txp; 1128 1129 /* 1130 * Advance the beginning of the list forward if there are 1131 * no other packets queued (when nothing is queued, cbl_first 1132 * sits on the last TxCB that was sent out). 1133 */ 1134 if (sc->tx_queued == 0) 1135 sc->cbl_first = txp; 1136 1137 sc->tx_queued++; 1138 1139 /* 1140 * Pass packet to bpf if there is a listener. 1141 */ 1142 BPF_MTAP(ifp, mb_head); 1143 } 1144 1145 /* 1146 * We're finished. If we added to the list, issue a RESUME to get DMA 1147 * going again if suspended. 1148 */ 1149 if (txp != NULL) { 1150 fxp_scb_wait(sc); 1151 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 1152 } 1153 } 1154 1155 static void fxp_intr_body(struct fxp_softc *sc, u_int8_t statack, int count); 1156 1157 #ifdef DEVICE_POLLING 1158 static poll_handler_t fxp_poll; 1159 1160 static void 1161 fxp_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1162 { 1163 struct fxp_softc *sc = ifp->if_softc; 1164 u_int8_t statack; 1165 1166 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1167 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 1168 return; 1169 } 1170 statack = FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA | 1171 FXP_SCB_STATACK_FR; 1172 if (cmd == POLL_AND_CHECK_STATUS) { 1173 u_int8_t tmp; 1174 1175 tmp = CSR_READ_1(sc, FXP_CSR_SCB_STATACK); 1176 if (tmp == 0xff || tmp == 0) 1177 return; /* nothing to do */ 1178 tmp &= ~statack; 1179 /* ack what we can */ 1180 if (tmp != 0) 1181 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, tmp); 1182 statack |= tmp; 1183 } 1184 fxp_intr_body(sc, statack, count); 1185 } 1186 #endif /* DEVICE_POLLING */ 1187 1188 /* 1189 * Process interface interrupts. 1190 */ 1191 static void 1192 fxp_intr(void *xsc) 1193 { 1194 struct fxp_softc *sc = xsc; 1195 u_int8_t statack; 1196 1197 #ifdef DEVICE_POLLING 1198 struct ifnet *ifp = &sc->sc_if; 1199 1200 if (ifp->if_flags & IFF_POLLING) 1201 return; 1202 if (ether_poll_register(fxp_poll, ifp)) { 1203 /* disable interrupts */ 1204 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 1205 fxp_poll(ifp, 0, 1); 1206 return; 1207 } 1208 #endif 1209 1210 if (sc->suspended) { 1211 return; 1212 } 1213 1214 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) { 1215 /* 1216 * It should not be possible to have all bits set; the 1217 * FXP_SCB_INTR_SWI bit always returns 0 on a read. If 1218 * all bits are set, this may indicate that the card has 1219 * been physically ejected, so ignore it. 1220 */ 1221 if (statack == 0xff) 1222 return; 1223 1224 /* 1225 * First ACK all the interrupts in this pass. 1226 */ 1227 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); 1228 fxp_intr_body(sc, statack, -1); 1229 } 1230 } 1231 1232 static void 1233 fxp_intr_body(struct fxp_softc *sc, u_int8_t statack, int count) 1234 { 1235 struct ifnet *ifp = &sc->sc_if; 1236 struct mbuf *m; 1237 struct fxp_rfa *rfa; 1238 int rnr = (statack & FXP_SCB_STATACK_RNR) ? 1 : 0; 1239 1240 if (rnr) 1241 fxp_rnr++; 1242 #ifdef DEVICE_POLLING 1243 /* Pick up a deferred RNR condition if `count' ran out last time. */ 1244 if (sc->flags & FXP_FLAG_DEFERRED_RNR) { 1245 sc->flags &= ~FXP_FLAG_DEFERRED_RNR; 1246 rnr = 1; 1247 } 1248 #endif 1249 1250 /* 1251 * Free any finished transmit mbuf chains. 1252 * 1253 * Handle the CNA event likt a CXTNO event. It used to 1254 * be that this event (control unit not ready) was not 1255 * encountered, but it is now with the SMPng modifications. 1256 * The exact sequence of events that occur when the interface 1257 * is brought up are different now, and if this event 1258 * goes unhandled, the configuration/rxfilter setup sequence 1259 * can stall for several seconds. The result is that no 1260 * packets go out onto the wire for about 5 to 10 seconds 1261 * after the interface is ifconfig'ed for the first time. 1262 */ 1263 if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA)) { 1264 struct fxp_cb_tx *txp; 1265 1266 for (txp = sc->cbl_first; sc->tx_queued && 1267 (txp->cb_status & FXP_CB_STATUS_C) != 0; 1268 txp = txp->next) { 1269 if (txp->mb_head != NULL) { 1270 m_freem(txp->mb_head); 1271 txp->mb_head = NULL; 1272 } 1273 sc->tx_queued--; 1274 } 1275 sc->cbl_first = txp; 1276 ifp->if_timer = 0; 1277 if (sc->tx_queued == 0) { 1278 if (sc->need_mcsetup) 1279 fxp_mc_setup(sc); 1280 } 1281 /* 1282 * Try to start more packets transmitting. 1283 */ 1284 if (ifp->if_snd.ifq_head != NULL) 1285 fxp_start(ifp); 1286 } 1287 1288 /* 1289 * Just return if nothing happened on the receive side. 1290 */ 1291 if (!rnr && (statack & FXP_SCB_STATACK_FR) == 0) 1292 return; 1293 1294 /* 1295 * Process receiver interrupts. If a no-resource (RNR) 1296 * condition exists, get whatever packets we can and 1297 * re-start the receiver. 1298 * 1299 * When using polling, we do not process the list to completion, 1300 * so when we get an RNR interrupt we must defer the restart 1301 * until we hit the last buffer with the C bit set. 1302 * If we run out of cycles and rfa_headm has the C bit set, 1303 * record the pending RNR in the FXP_FLAG_DEFERRED_RNR flag so 1304 * that the info will be used in the subsequent polling cycle. 1305 */ 1306 for (;;) { 1307 m = sc->rfa_headm; 1308 rfa = (struct fxp_rfa *)(m->m_ext.ext_buf + 1309 RFA_ALIGNMENT_FUDGE); 1310 1311 #ifdef DEVICE_POLLING /* loop at most count times if count >=0 */ 1312 if (count >= 0 && count-- == 0) { 1313 if (rnr) { 1314 /* Defer RNR processing until the next time. */ 1315 sc->flags |= FXP_FLAG_DEFERRED_RNR; 1316 rnr = 0; 1317 } 1318 break; 1319 } 1320 #endif /* DEVICE_POLLING */ 1321 1322 if ( (rfa->rfa_status & FXP_RFA_STATUS_C) == 0) 1323 break; 1324 1325 /* 1326 * Remove first packet from the chain. 1327 */ 1328 sc->rfa_headm = m->m_next; 1329 m->m_next = NULL; 1330 1331 /* 1332 * Add a new buffer to the receive chain. 1333 * If this fails, the old buffer is recycled 1334 * instead. 1335 */ 1336 if (fxp_add_rfabuf(sc, m) == 0) { 1337 int total_len; 1338 1339 /* 1340 * Fetch packet length (the top 2 bits of 1341 * actual_size are flags set by the controller 1342 * upon completion), and drop the packet in case 1343 * of bogus length or CRC errors. 1344 */ 1345 total_len = rfa->actual_size & 0x3fff; 1346 if (total_len < sizeof(struct ether_header) || 1347 total_len > MCLBYTES - RFA_ALIGNMENT_FUDGE - 1348 sizeof(struct fxp_rfa) || 1349 rfa->rfa_status & FXP_RFA_STATUS_CRC) { 1350 m_freem(m); 1351 continue; 1352 } 1353 1354 m->m_pkthdr.len = m->m_len = total_len; 1355 m->m_pkthdr.rcvif = ifp; 1356 1357 (*ifp->if_input)(ifp, m); 1358 } 1359 } 1360 if (rnr) { 1361 fxp_scb_wait(sc); 1362 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1363 vtophys(sc->rfa_headm->m_ext.ext_buf) + 1364 RFA_ALIGNMENT_FUDGE); 1365 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1366 } 1367 } 1368 1369 /* 1370 * Update packet in/out/collision statistics. The i82557 doesn't 1371 * allow you to access these counters without doing a fairly 1372 * expensive DMA to get _all_ of the statistics it maintains, so 1373 * we do this operation here only once per second. The statistics 1374 * counters in the kernel are updated from the previous dump-stats 1375 * DMA and then a new dump-stats DMA is started. The on-chip 1376 * counters are zeroed when the DMA completes. If we can't start 1377 * the DMA immediately, we don't wait - we just prepare to read 1378 * them again next time. 1379 */ 1380 static void 1381 fxp_tick(void *xsc) 1382 { 1383 struct fxp_softc *sc = xsc; 1384 struct ifnet *ifp = &sc->sc_if; 1385 struct fxp_stats *sp = sc->fxp_stats; 1386 struct fxp_cb_tx *txp; 1387 int s; 1388 1389 ifp->if_opackets += sp->tx_good; 1390 ifp->if_collisions += sp->tx_total_collisions; 1391 if (sp->rx_good) { 1392 ifp->if_ipackets += sp->rx_good; 1393 sc->rx_idle_secs = 0; 1394 } else { 1395 /* 1396 * Receiver's been idle for another second. 1397 */ 1398 sc->rx_idle_secs++; 1399 } 1400 ifp->if_ierrors += 1401 sp->rx_crc_errors + 1402 sp->rx_alignment_errors + 1403 sp->rx_rnr_errors + 1404 sp->rx_overrun_errors; 1405 /* 1406 * If any transmit underruns occured, bump up the transmit 1407 * threshold by another 512 bytes (64 * 8). 1408 */ 1409 if (sp->tx_underruns) { 1410 ifp->if_oerrors += sp->tx_underruns; 1411 if (tx_threshold < 192) 1412 tx_threshold += 64; 1413 } 1414 s = splimp(); 1415 /* 1416 * Release any xmit buffers that have completed DMA. This isn't 1417 * strictly necessary to do here, but it's advantagous for mbufs 1418 * with external storage to be released in a timely manner rather 1419 * than being defered for a potentially long time. This limits 1420 * the delay to a maximum of one second. 1421 */ 1422 for (txp = sc->cbl_first; sc->tx_queued && 1423 (txp->cb_status & FXP_CB_STATUS_C) != 0; 1424 txp = txp->next) { 1425 if (txp->mb_head != NULL) { 1426 m_freem(txp->mb_head); 1427 txp->mb_head = NULL; 1428 } 1429 sc->tx_queued--; 1430 } 1431 sc->cbl_first = txp; 1432 /* 1433 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds, 1434 * then assume the receiver has locked up and attempt to clear 1435 * the condition by reprogramming the multicast filter. This is 1436 * a work-around for a bug in the 82557 where the receiver locks 1437 * up if it gets certain types of garbage in the syncronization 1438 * bits prior to the packet header. This bug is supposed to only 1439 * occur in 10Mbps mode, but has been seen to occur in 100Mbps 1440 * mode as well (perhaps due to a 10/100 speed transition). 1441 */ 1442 if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) { 1443 sc->rx_idle_secs = 0; 1444 fxp_mc_setup(sc); 1445 } 1446 /* 1447 * If there is no pending command, start another stats 1448 * dump. Otherwise punt for now. 1449 */ 1450 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) { 1451 /* 1452 * Start another stats dump. 1453 */ 1454 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET); 1455 } else { 1456 /* 1457 * A previous command is still waiting to be accepted. 1458 * Just zero our copy of the stats and wait for the 1459 * next timer event to update them. 1460 */ 1461 sp->tx_good = 0; 1462 sp->tx_underruns = 0; 1463 sp->tx_total_collisions = 0; 1464 1465 sp->rx_good = 0; 1466 sp->rx_crc_errors = 0; 1467 sp->rx_alignment_errors = 0; 1468 sp->rx_rnr_errors = 0; 1469 sp->rx_overrun_errors = 0; 1470 } 1471 if (sc->miibus != NULL) 1472 mii_tick(device_get_softc(sc->miibus)); 1473 splx(s); 1474 /* 1475 * Schedule another timeout one second from now. 1476 */ 1477 sc->stat_ch = timeout(fxp_tick, sc, hz); 1478 } 1479 1480 /* 1481 * Stop the interface. Cancels the statistics updater and resets 1482 * the interface. 1483 */ 1484 static void 1485 fxp_stop(struct fxp_softc *sc) 1486 { 1487 struct ifnet *ifp = &sc->sc_if; 1488 struct fxp_cb_tx *txp; 1489 int i; 1490 1491 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1492 ifp->if_timer = 0; 1493 1494 #ifdef DEVICE_POLLING 1495 ether_poll_deregister(ifp); 1496 #endif 1497 /* 1498 * Cancel stats updater. 1499 */ 1500 untimeout(fxp_tick, sc, sc->stat_ch); 1501 1502 /* 1503 * Issue software reset, which also unloads the microcode. 1504 */ 1505 sc->flags &= ~FXP_FLAG_UCODE; 1506 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET); 1507 DELAY(50); 1508 1509 /* 1510 * Release any xmit buffers. 1511 */ 1512 txp = sc->cbl_base; 1513 if (txp != NULL) { 1514 for (i = 0; i < FXP_NTXCB; i++) { 1515 if (txp[i].mb_head != NULL) { 1516 m_freem(txp[i].mb_head); 1517 txp[i].mb_head = NULL; 1518 } 1519 } 1520 } 1521 sc->tx_queued = 0; 1522 1523 /* 1524 * Free all the receive buffers then reallocate/reinitialize 1525 */ 1526 if (sc->rfa_headm != NULL) 1527 m_freem(sc->rfa_headm); 1528 sc->rfa_headm = NULL; 1529 sc->rfa_tailm = NULL; 1530 for (i = 0; i < FXP_NRFABUFS; i++) { 1531 if (fxp_add_rfabuf(sc, NULL) != 0) { 1532 /* 1533 * This "can't happen" - we're at splimp() 1534 * and we just freed all the buffers we need 1535 * above. 1536 */ 1537 panic("fxp_stop: no buffers!"); 1538 } 1539 } 1540 } 1541 1542 /* 1543 * Watchdog/transmission transmit timeout handler. Called when a 1544 * transmission is started on the interface, but no interrupt is 1545 * received before the timeout. This usually indicates that the 1546 * card has wedged for some reason. 1547 */ 1548 static void 1549 fxp_watchdog(struct ifnet *ifp) 1550 { 1551 struct fxp_softc *sc = ifp->if_softc; 1552 1553 device_printf(sc->dev, "device timeout\n"); 1554 ifp->if_oerrors++; 1555 1556 fxp_init(sc); 1557 } 1558 1559 static void 1560 fxp_init(void *xsc) 1561 { 1562 struct fxp_softc *sc = xsc; 1563 struct ifnet *ifp = &sc->sc_if; 1564 struct fxp_cb_config *cbp; 1565 struct fxp_cb_ias *cb_ias; 1566 struct fxp_cb_tx *txp; 1567 struct fxp_cb_mcs *mcsp; 1568 int i, prm, s; 1569 1570 s = splimp(); 1571 /* 1572 * Cancel any pending I/O 1573 */ 1574 fxp_stop(sc); 1575 1576 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0; 1577 1578 /* 1579 * Initialize base of CBL and RFA memory. Loading with zero 1580 * sets it up for regular linear addressing. 1581 */ 1582 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0); 1583 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE); 1584 1585 fxp_scb_wait(sc); 1586 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE); 1587 1588 /* 1589 * Initialize base of dump-stats buffer. 1590 */ 1591 fxp_scb_wait(sc); 1592 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(sc->fxp_stats)); 1593 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR); 1594 1595 /* 1596 * Attempt to load microcode if requested. 1597 */ 1598 if (ifp->if_flags & IFF_LINK0 && (sc->flags & FXP_FLAG_UCODE) == 0) 1599 fxp_load_ucode(sc); 1600 1601 /* 1602 * Initialize the multicast address list. 1603 */ 1604 if (fxp_mc_addrs(sc)) { 1605 mcsp = sc->mcsp; 1606 mcsp->cb_status = 0; 1607 mcsp->cb_command = FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL; 1608 mcsp->link_addr = -1; 1609 /* 1610 * Start the multicast setup command. 1611 */ 1612 fxp_scb_wait(sc); 1613 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&mcsp->cb_status)); 1614 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1615 /* ...and wait for it to complete. */ 1616 fxp_dma_wait(&mcsp->cb_status, sc); 1617 } 1618 1619 /* 1620 * We temporarily use memory that contains the TxCB list to 1621 * construct the config CB. The TxCB list memory is rebuilt 1622 * later. 1623 */ 1624 cbp = (struct fxp_cb_config *) sc->cbl_base; 1625 1626 /* 1627 * This bcopy is kind of disgusting, but there are a bunch of must be 1628 * zero and must be one bits in this structure and this is the easiest 1629 * way to initialize them all to proper values. 1630 */ 1631 bcopy(fxp_cb_config_template, 1632 (void *)(uintptr_t)(volatile void *)&cbp->cb_status, 1633 sizeof(fxp_cb_config_template)); 1634 1635 cbp->cb_status = 0; 1636 cbp->cb_command = FXP_CB_COMMAND_CONFIG | FXP_CB_COMMAND_EL; 1637 cbp->link_addr = -1; /* (no) next command */ 1638 cbp->byte_count = 22; /* (22) bytes to config */ 1639 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */ 1640 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */ 1641 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */ 1642 cbp->mwi_enable = sc->flags & FXP_FLAG_MWI_ENABLE ? 1 : 0; 1643 cbp->type_enable = 0; /* actually reserved */ 1644 cbp->read_align_en = sc->flags & FXP_FLAG_READ_ALIGN ? 1 : 0; 1645 cbp->end_wr_on_cl = sc->flags & FXP_FLAG_WRITE_ALIGN ? 1 : 0; 1646 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */ 1647 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */ 1648 cbp->dma_mbce = 0; /* (disable) dma max counters */ 1649 cbp->late_scb = 0; /* (don't) defer SCB update */ 1650 cbp->direct_dma_dis = 1; /* disable direct rcv dma mode */ 1651 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */ 1652 cbp->ci_int = 1; /* interrupt on CU idle */ 1653 cbp->ext_txcb_dis = sc->flags & FXP_FLAG_EXT_TXCB ? 0 : 1; 1654 cbp->ext_stats_dis = 1; /* disable extended counters */ 1655 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */ 1656 cbp->save_bf = sc->revision == FXP_REV_82557 ? 1 : prm; 1657 cbp->disc_short_rx = !prm; /* discard short packets */ 1658 cbp->underrun_retry = 1; /* retry mode (once) on DMA underrun */ 1659 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */ 1660 cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */ 1661 cbp->mediatype = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 0 : 1; 1662 cbp->csma_dis = 0; /* (don't) disable link */ 1663 cbp->tcp_udp_cksum = 0; /* (don't) enable checksum */ 1664 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */ 1665 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */ 1666 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */ 1667 cbp->mc_wake_en = 0; /* (don't) enable PME# on mcmatch */ 1668 cbp->nsai = 1; /* (don't) disable source addr insert */ 1669 cbp->preamble_length = 2; /* (7 byte) preamble */ 1670 cbp->loopback = 0; /* (don't) loopback */ 1671 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */ 1672 cbp->linear_pri_mode = 0; /* (wait after xmit only) */ 1673 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */ 1674 cbp->promiscuous = prm; /* promiscuous mode */ 1675 cbp->bcast_disable = 0; /* (don't) disable broadcasts */ 1676 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/ 1677 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */ 1678 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */ 1679 cbp->crscdt = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 1 : 0; 1680 1681 cbp->stripping = !prm; /* truncate rx packet to byte count */ 1682 cbp->padding = 1; /* (do) pad short tx packets */ 1683 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */ 1684 cbp->long_rx_en = sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0; 1685 cbp->ia_wake_en = 0; /* (don't) wake up on address match */ 1686 cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */ 1687 /* must set wake_en in PMCSR also */ 1688 cbp->force_fdx = 0; /* (don't) force full duplex */ 1689 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */ 1690 cbp->multi_ia = 0; /* (don't) accept multiple IAs */ 1691 cbp->mc_all = sc->flags & FXP_FLAG_ALL_MCAST ? 1 : 0; 1692 1693 if (sc->revision == FXP_REV_82557) { 1694 /* 1695 * The 82557 has no hardware flow control, the values 1696 * below are the defaults for the chip. 1697 */ 1698 cbp->fc_delay_lsb = 0; 1699 cbp->fc_delay_msb = 0x40; 1700 cbp->pri_fc_thresh = 3; 1701 cbp->tx_fc_dis = 0; 1702 cbp->rx_fc_restop = 0; 1703 cbp->rx_fc_restart = 0; 1704 cbp->fc_filter = 0; 1705 cbp->pri_fc_loc = 1; 1706 } else { 1707 cbp->fc_delay_lsb = 0x1f; 1708 cbp->fc_delay_msb = 0x01; 1709 cbp->pri_fc_thresh = 3; 1710 cbp->tx_fc_dis = 0; /* enable transmit FC */ 1711 cbp->rx_fc_restop = 1; /* enable FC restop frames */ 1712 cbp->rx_fc_restart = 1; /* enable FC restart frames */ 1713 cbp->fc_filter = !prm; /* drop FC frames to host */ 1714 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */ 1715 } 1716 1717 /* 1718 * Start the config command/DMA. 1719 */ 1720 fxp_scb_wait(sc); 1721 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&cbp->cb_status)); 1722 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1723 /* ...and wait for it to complete. */ 1724 fxp_dma_wait(&cbp->cb_status, sc); 1725 1726 /* 1727 * Now initialize the station address. Temporarily use the TxCB 1728 * memory area like we did above for the config CB. 1729 */ 1730 cb_ias = (struct fxp_cb_ias *) sc->cbl_base; 1731 cb_ias->cb_status = 0; 1732 cb_ias->cb_command = FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL; 1733 cb_ias->link_addr = -1; 1734 bcopy(sc->arpcom.ac_enaddr, 1735 (void *)(uintptr_t)(volatile void *)cb_ias->macaddr, 1736 sizeof(sc->arpcom.ac_enaddr)); 1737 1738 /* 1739 * Start the IAS (Individual Address Setup) command/DMA. 1740 */ 1741 fxp_scb_wait(sc); 1742 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1743 /* ...and wait for it to complete. */ 1744 fxp_dma_wait(&cb_ias->cb_status, sc); 1745 1746 /* 1747 * Initialize transmit control block (TxCB) list. 1748 */ 1749 1750 txp = sc->cbl_base; 1751 bzero(txp, sizeof(struct fxp_cb_tx) * FXP_NTXCB); 1752 for (i = 0; i < FXP_NTXCB; i++) { 1753 txp[i].cb_status = FXP_CB_STATUS_C | FXP_CB_STATUS_OK; 1754 txp[i].cb_command = FXP_CB_COMMAND_NOP; 1755 txp[i].link_addr = 1756 vtophys(&txp[(i + 1) & FXP_TXCB_MASK].cb_status); 1757 if (sc->flags & FXP_FLAG_EXT_TXCB) 1758 txp[i].tbd_array_addr = vtophys(&txp[i].tbd[2]); 1759 else 1760 txp[i].tbd_array_addr = vtophys(&txp[i].tbd[0]); 1761 txp[i].next = &txp[(i + 1) & FXP_TXCB_MASK]; 1762 } 1763 /* 1764 * Set the suspend flag on the first TxCB and start the control 1765 * unit. It will execute the NOP and then suspend. 1766 */ 1767 txp->cb_command = FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S; 1768 sc->cbl_first = sc->cbl_last = txp; 1769 sc->tx_queued = 1; 1770 1771 fxp_scb_wait(sc); 1772 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 1773 1774 /* 1775 * Initialize receiver buffer area - RFA. 1776 */ 1777 fxp_scb_wait(sc); 1778 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 1779 vtophys(sc->rfa_headm->m_ext.ext_buf) + RFA_ALIGNMENT_FUDGE); 1780 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START); 1781 1782 /* 1783 * Set current media. 1784 */ 1785 if (sc->miibus != NULL) 1786 mii_mediachg(device_get_softc(sc->miibus)); 1787 1788 ifp->if_flags |= IFF_RUNNING; 1789 ifp->if_flags &= ~IFF_OACTIVE; 1790 1791 /* 1792 * Enable interrupts. 1793 */ 1794 #ifdef DEVICE_POLLING 1795 /* 1796 * ... but only do that if we are not polling. And because (presumably) 1797 * the default is interrupts on, we need to disable them explicitly! 1798 */ 1799 if ( ifp->if_flags & IFF_POLLING ) 1800 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); 1801 else 1802 #endif /* DEVICE_POLLING */ 1803 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0); 1804 splx(s); 1805 1806 /* 1807 * Start stats updater. 1808 */ 1809 sc->stat_ch = timeout(fxp_tick, sc, hz); 1810 } 1811 1812 static int 1813 fxp_serial_ifmedia_upd(struct ifnet *ifp) 1814 { 1815 1816 return (0); 1817 } 1818 1819 static void 1820 fxp_serial_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1821 { 1822 1823 ifmr->ifm_active = IFM_ETHER|IFM_MANUAL; 1824 } 1825 1826 /* 1827 * Change media according to request. 1828 */ 1829 static int 1830 fxp_ifmedia_upd(struct ifnet *ifp) 1831 { 1832 struct fxp_softc *sc = ifp->if_softc; 1833 struct mii_data *mii; 1834 1835 mii = device_get_softc(sc->miibus); 1836 mii_mediachg(mii); 1837 return (0); 1838 } 1839 1840 /* 1841 * Notify the world which media we're using. 1842 */ 1843 static void 1844 fxp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1845 { 1846 struct fxp_softc *sc = ifp->if_softc; 1847 struct mii_data *mii; 1848 1849 mii = device_get_softc(sc->miibus); 1850 mii_pollstat(mii); 1851 ifmr->ifm_active = mii->mii_media_active; 1852 ifmr->ifm_status = mii->mii_media_status; 1853 1854 if (ifmr->ifm_status & IFM_10_T && sc->flags & FXP_FLAG_CU_RESUME_BUG) 1855 sc->cu_resume_bug = 1; 1856 else 1857 sc->cu_resume_bug = 0; 1858 } 1859 1860 /* 1861 * Add a buffer to the end of the RFA buffer list. 1862 * Return 0 if successful, 1 for failure. A failure results in 1863 * adding the 'oldm' (if non-NULL) on to the end of the list - 1864 * tossing out its old contents and recycling it. 1865 * The RFA struct is stuck at the beginning of mbuf cluster and the 1866 * data pointer is fixed up to point just past it. 1867 */ 1868 static int 1869 fxp_add_rfabuf(struct fxp_softc *sc, struct mbuf *oldm) 1870 { 1871 u_int32_t v; 1872 struct mbuf *m; 1873 struct fxp_rfa *rfa, *p_rfa; 1874 1875 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1876 if (m == NULL) { /* try to recycle the old mbuf instead */ 1877 if (oldm == NULL) 1878 return 1; 1879 m = oldm; 1880 m->m_data = m->m_ext.ext_buf; 1881 } 1882 1883 /* 1884 * Move the data pointer up so that the incoming data packet 1885 * will be 32-bit aligned. 1886 */ 1887 m->m_data += RFA_ALIGNMENT_FUDGE; 1888 1889 /* 1890 * Get a pointer to the base of the mbuf cluster and move 1891 * data start past it. 1892 */ 1893 rfa = mtod(m, struct fxp_rfa *); 1894 m->m_data += sizeof(struct fxp_rfa); 1895 rfa->size = (u_int16_t)(MCLBYTES - sizeof(struct fxp_rfa) - RFA_ALIGNMENT_FUDGE); 1896 1897 /* 1898 * Initialize the rest of the RFA. Note that since the RFA 1899 * is misaligned, we cannot store values directly. Instead, 1900 * we use an optimized, inline copy. 1901 */ 1902 1903 rfa->rfa_status = 0; 1904 rfa->rfa_control = FXP_RFA_CONTROL_EL; 1905 rfa->actual_size = 0; 1906 1907 v = -1; 1908 fxp_lwcopy(&v, (volatile u_int32_t *) rfa->link_addr); 1909 fxp_lwcopy(&v, (volatile u_int32_t *) rfa->rbd_addr); 1910 1911 /* 1912 * If there are other buffers already on the list, attach this 1913 * one to the end by fixing up the tail to point to this one. 1914 */ 1915 if (sc->rfa_headm != NULL) { 1916 p_rfa = (struct fxp_rfa *) (sc->rfa_tailm->m_ext.ext_buf + 1917 RFA_ALIGNMENT_FUDGE); 1918 sc->rfa_tailm->m_next = m; 1919 v = vtophys(rfa); 1920 fxp_lwcopy(&v, (volatile u_int32_t *) p_rfa->link_addr); 1921 p_rfa->rfa_control = 0; 1922 } else { 1923 sc->rfa_headm = m; 1924 } 1925 sc->rfa_tailm = m; 1926 1927 return (m == oldm); 1928 } 1929 1930 static volatile int 1931 fxp_miibus_readreg(device_t dev, int phy, int reg) 1932 { 1933 struct fxp_softc *sc = device_get_softc(dev); 1934 int count = 10000; 1935 int value; 1936 1937 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 1938 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21)); 1939 1940 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0 1941 && count--) 1942 DELAY(10); 1943 1944 if (count <= 0) 1945 device_printf(dev, "fxp_miibus_readreg: timed out\n"); 1946 1947 return (value & 0xffff); 1948 } 1949 1950 static void 1951 fxp_miibus_writereg(device_t dev, int phy, int reg, int value) 1952 { 1953 struct fxp_softc *sc = device_get_softc(dev); 1954 int count = 10000; 1955 1956 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL, 1957 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) | 1958 (value & 0xffff)); 1959 1960 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 && 1961 count--) 1962 DELAY(10); 1963 1964 if (count <= 0) 1965 device_printf(dev, "fxp_miibus_writereg: timed out\n"); 1966 } 1967 1968 static int 1969 fxp_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1970 { 1971 struct fxp_softc *sc = ifp->if_softc; 1972 struct ifreq *ifr = (struct ifreq *)data; 1973 struct mii_data *mii; 1974 int s, error = 0; 1975 1976 s = splimp(); 1977 1978 switch (command) { 1979 case SIOCSIFFLAGS: 1980 if (ifp->if_flags & IFF_ALLMULTI) 1981 sc->flags |= FXP_FLAG_ALL_MCAST; 1982 else 1983 sc->flags &= ~FXP_FLAG_ALL_MCAST; 1984 1985 /* 1986 * If interface is marked up and not running, then start it. 1987 * If it is marked down and running, stop it. 1988 * XXX If it's up then re-initialize it. This is so flags 1989 * such as IFF_PROMISC are handled. 1990 */ 1991 if (ifp->if_flags & IFF_UP) { 1992 fxp_init(sc); 1993 } else { 1994 if (ifp->if_flags & IFF_RUNNING) 1995 fxp_stop(sc); 1996 } 1997 break; 1998 1999 case SIOCADDMULTI: 2000 case SIOCDELMULTI: 2001 if (ifp->if_flags & IFF_ALLMULTI) 2002 sc->flags |= FXP_FLAG_ALL_MCAST; 2003 else 2004 sc->flags &= ~FXP_FLAG_ALL_MCAST; 2005 /* 2006 * Multicast list has changed; set the hardware filter 2007 * accordingly. 2008 */ 2009 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) 2010 fxp_mc_setup(sc); 2011 /* 2012 * fxp_mc_setup() can set FXP_FLAG_ALL_MCAST, so check it 2013 * again rather than else {}. 2014 */ 2015 if (sc->flags & FXP_FLAG_ALL_MCAST) 2016 fxp_init(sc); 2017 error = 0; 2018 break; 2019 2020 case SIOCSIFMEDIA: 2021 case SIOCGIFMEDIA: 2022 if (sc->miibus != NULL) { 2023 mii = device_get_softc(sc->miibus); 2024 error = ifmedia_ioctl(ifp, ifr, 2025 &mii->mii_media, command); 2026 } else { 2027 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command); 2028 } 2029 break; 2030 2031 default: 2032 error = ether_ioctl(ifp, command, data); 2033 } 2034 splx(s); 2035 return (error); 2036 } 2037 2038 /* 2039 * Fill in the multicast address list and return number of entries. 2040 */ 2041 static int 2042 fxp_mc_addrs(struct fxp_softc *sc) 2043 { 2044 struct fxp_cb_mcs *mcsp = sc->mcsp; 2045 struct ifnet *ifp = &sc->sc_if; 2046 struct ifmultiaddr *ifma; 2047 int nmcasts; 2048 2049 nmcasts = 0; 2050 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) { 2051 #if __FreeBSD_version < 500000 2052 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2053 #else 2054 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2055 #endif 2056 if (ifma->ifma_addr->sa_family != AF_LINK) 2057 continue; 2058 if (nmcasts >= MAXMCADDR) { 2059 sc->flags |= FXP_FLAG_ALL_MCAST; 2060 nmcasts = 0; 2061 break; 2062 } 2063 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 2064 (void *)(uintptr_t)(volatile void *) 2065 &sc->mcsp->mc_addr[nmcasts][0], 6); 2066 nmcasts++; 2067 } 2068 } 2069 mcsp->mc_cnt = nmcasts * 6; 2070 return (nmcasts); 2071 } 2072 2073 /* 2074 * Program the multicast filter. 2075 * 2076 * We have an artificial restriction that the multicast setup command 2077 * must be the first command in the chain, so we take steps to ensure 2078 * this. By requiring this, it allows us to keep up the performance of 2079 * the pre-initialized command ring (esp. link pointers) by not actually 2080 * inserting the mcsetup command in the ring - i.e. its link pointer 2081 * points to the TxCB ring, but the mcsetup descriptor itself is not part 2082 * of it. We then can do 'CU_START' on the mcsetup descriptor and have it 2083 * lead into the regular TxCB ring when it completes. 2084 * 2085 * This function must be called at splimp. 2086 */ 2087 static void 2088 fxp_mc_setup(struct fxp_softc *sc) 2089 { 2090 struct fxp_cb_mcs *mcsp = sc->mcsp; 2091 struct ifnet *ifp = &sc->sc_if; 2092 int count; 2093 2094 /* 2095 * If there are queued commands, we must wait until they are all 2096 * completed. If we are already waiting, then add a NOP command 2097 * with interrupt option so that we're notified when all commands 2098 * have been completed - fxp_start() ensures that no additional 2099 * TX commands will be added when need_mcsetup is true. 2100 */ 2101 if (sc->tx_queued) { 2102 struct fxp_cb_tx *txp; 2103 2104 /* 2105 * need_mcsetup will be true if we are already waiting for the 2106 * NOP command to be completed (see below). In this case, bail. 2107 */ 2108 if (sc->need_mcsetup) 2109 return; 2110 sc->need_mcsetup = 1; 2111 2112 /* 2113 * Add a NOP command with interrupt so that we are notified 2114 * when all TX commands have been processed. 2115 */ 2116 txp = sc->cbl_last->next; 2117 txp->mb_head = NULL; 2118 txp->cb_status = 0; 2119 txp->cb_command = FXP_CB_COMMAND_NOP | 2120 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; 2121 /* 2122 * Advance the end of list forward. 2123 */ 2124 sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S; 2125 sc->cbl_last = txp; 2126 sc->tx_queued++; 2127 /* 2128 * Issue a resume in case the CU has just suspended. 2129 */ 2130 fxp_scb_wait(sc); 2131 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME); 2132 /* 2133 * Set a 5 second timer just in case we don't hear from the 2134 * card again. 2135 */ 2136 ifp->if_timer = 5; 2137 2138 return; 2139 } 2140 sc->need_mcsetup = 0; 2141 2142 /* 2143 * Initialize multicast setup descriptor. 2144 */ 2145 mcsp->next = sc->cbl_base; 2146 mcsp->mb_head = NULL; 2147 mcsp->cb_status = 0; 2148 mcsp->cb_command = FXP_CB_COMMAND_MCAS | 2149 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I; 2150 mcsp->link_addr = vtophys(&sc->cbl_base->cb_status); 2151 (void) fxp_mc_addrs(sc); 2152 sc->cbl_first = sc->cbl_last = (struct fxp_cb_tx *) mcsp; 2153 sc->tx_queued = 1; 2154 2155 /* 2156 * Wait until command unit is not active. This should never 2157 * be the case when nothing is queued, but make sure anyway. 2158 */ 2159 count = 100; 2160 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) == 2161 FXP_SCB_CUS_ACTIVE && --count) 2162 DELAY(10); 2163 if (count == 0) { 2164 device_printf(sc->dev, "command queue timeout\n"); 2165 return; 2166 } 2167 2168 /* 2169 * Start the multicast setup command. 2170 */ 2171 fxp_scb_wait(sc); 2172 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&mcsp->cb_status)); 2173 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2174 2175 ifp->if_timer = 2; 2176 return; 2177 } 2178 2179 static u_int32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE; 2180 static u_int32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE; 2181 static u_int32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE; 2182 static u_int32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE; 2183 static u_int32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE; 2184 static u_int32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE; 2185 2186 #define UCODE(x) x, sizeof(x) 2187 2188 struct ucode { 2189 u_int32_t revision; 2190 u_int32_t *ucode; 2191 int length; 2192 u_short int_delay_offset; 2193 u_short bundle_max_offset; 2194 } ucode_table[] = { 2195 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), D101_CPUSAVER_DWORD, 0 }, 2196 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), D101_CPUSAVER_DWORD, 0 }, 2197 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma), 2198 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD }, 2199 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s), 2200 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD }, 2201 { FXP_REV_82550, UCODE(fxp_ucode_d102), 2202 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD }, 2203 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c), 2204 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD }, 2205 { 0, NULL, 0, 0, 0 } 2206 }; 2207 2208 static void 2209 fxp_load_ucode(struct fxp_softc *sc) 2210 { 2211 struct ucode *uc; 2212 struct fxp_cb_ucode *cbp; 2213 2214 for (uc = ucode_table; uc->ucode != NULL; uc++) 2215 if (sc->revision == uc->revision) 2216 break; 2217 if (uc->ucode == NULL) 2218 return; 2219 cbp = (struct fxp_cb_ucode *)sc->cbl_base; 2220 cbp->cb_status = 0; 2221 cbp->cb_command = FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL; 2222 cbp->link_addr = -1; /* (no) next command */ 2223 memcpy(cbp->ucode, uc->ucode, uc->length); 2224 if (uc->int_delay_offset) 2225 *(u_short *)&cbp->ucode[uc->int_delay_offset] = 2226 sc->tunable_int_delay + sc->tunable_int_delay / 2; 2227 if (uc->bundle_max_offset) 2228 *(u_short *)&cbp->ucode[uc->bundle_max_offset] = 2229 sc->tunable_bundle_max; 2230 /* 2231 * Download the ucode to the chip. 2232 */ 2233 fxp_scb_wait(sc); 2234 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&cbp->cb_status)); 2235 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START); 2236 /* ...and wait for it to complete. */ 2237 fxp_dma_wait(&cbp->cb_status, sc); 2238 device_printf(sc->dev, 2239 "Microcode loaded, int_delay: %d usec bundle_max: %d\n", 2240 sc->tunable_int_delay, 2241 uc->bundle_max_offset == 0 ? 0 : sc->tunable_bundle_max); 2242 sc->flags |= FXP_FLAG_UCODE; 2243 } 2244 2245 static int 2246 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 2247 { 2248 int error, value; 2249 2250 value = *(int *)arg1; 2251 error = sysctl_handle_int(oidp, &value, 0, req); 2252 if (error || !req->newptr) 2253 return (error); 2254 if (value < low || value > high) 2255 return (EINVAL); 2256 *(int *)arg1 = value; 2257 return (0); 2258 } 2259 2260 /* 2261 * Interrupt delay is expressed in microseconds, a multiplier is used 2262 * to convert this to the appropriate clock ticks before using. 2263 */ 2264 static int 2265 sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS) 2266 { 2267 return (sysctl_int_range(oidp, arg1, arg2, req, 300, 3000)); 2268 } 2269 2270 static int 2271 sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS) 2272 { 2273 return (sysctl_int_range(oidp, arg1, arg2, req, 1, 0xffff)); 2274 }
Cache object: 43346e1e3724cbe5636a4c14f4ef36c3
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