1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause-NetBSD
3 *
4 * Copyright (C) 2001 Eduardo Horvath.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 *
28 * from: NetBSD: gemvar.h,v 1.8 2002/05/15 02:36:12 matt Exp
29 *
30 * $FreeBSD$
31 */
32
33 #ifndef _IF_GEMVAR_H
34 #define _IF_GEMVAR_H
35
36 #include <sys/queue.h>
37 #include <sys/callout.h>
38
39 /*
40 * Transmit descriptor ring size - this is arbitrary, but allocate
41 * enough descriptors for 64 pending transmissions and 16 segments
42 * per packet. This limit is not actually enforced (packets with
43 * more segments can be sent, depending on the busdma backend); it
44 * is however used as an estimate for the TX window size.
45 */
46 #define GEM_NTXSEGS 16
47
48 #define GEM_TXQUEUELEN 64
49 #define GEM_NTXDESC (GEM_TXQUEUELEN * GEM_NTXSEGS)
50 #define GEM_MAXTXFREE (GEM_NTXDESC - 1)
51 #define GEM_NTXDESC_MASK (GEM_NTXDESC - 1)
52 #define GEM_NEXTTX(x) ((x + 1) & GEM_NTXDESC_MASK)
53
54 /*
55 * Receive descriptor ring size - we have one RX buffer per incoming
56 * packet, so this logic is a little simpler.
57 */
58 #define GEM_NRXDESC 256
59 #define GEM_NRXDESC_MASK (GEM_NRXDESC - 1)
60 #define GEM_NEXTRX(x) ((x + 1) & GEM_NRXDESC_MASK)
61
62 /*
63 * How many ticks to wait until to retry on a RX descriptor that is
64 * still owned by the hardware.
65 */
66 #define GEM_RXOWN_TICKS (hz / 50)
67
68 /*
69 * Control structures are DMA'd to the chip. We allocate them
70 * in a single clump that maps to a single DMA segment to make
71 * several things easier.
72 */
73 struct gem_control_data {
74 struct gem_desc gcd_txdescs[GEM_NTXDESC]; /* TX descriptors */
75 struct gem_desc gcd_rxdescs[GEM_NRXDESC]; /* RX descriptors */
76 };
77
78 #define GEM_CDOFF(x) offsetof(struct gem_control_data, x)
79 #define GEM_CDTXOFF(x) GEM_CDOFF(gcd_txdescs[(x)])
80 #define GEM_CDRXOFF(x) GEM_CDOFF(gcd_rxdescs[(x)])
81
82 /*
83 * software state for transmit job mbufs (may be elements of mbuf chains)
84 */
85 struct gem_txsoft {
86 struct mbuf *txs_mbuf; /* head of our mbuf chain */
87 bus_dmamap_t txs_dmamap; /* our DMA map */
88 u_int txs_firstdesc; /* first descriptor in packet */
89 u_int txs_lastdesc; /* last descriptor in packet */
90 u_int txs_ndescs; /* number of descriptors */
91 STAILQ_ENTRY(gem_txsoft) txs_q;
92 };
93
94 STAILQ_HEAD(gem_txsq, gem_txsoft);
95
96 /*
97 * software state for receive jobs
98 */
99 struct gem_rxsoft {
100 struct mbuf *rxs_mbuf; /* head of our mbuf chain */
101 bus_dmamap_t rxs_dmamap; /* our DMA map */
102 bus_addr_t rxs_paddr; /* physical address of the segment */
103 };
104
105 /*
106 * software state per device
107 */
108 struct gem_softc {
109 struct ifnet *sc_ifp;
110 struct mtx sc_mtx;
111 device_t sc_miibus;
112 struct mii_data *sc_mii; /* MII media control */
113 device_t sc_dev; /* generic device information */
114 u_char sc_enaddr[ETHER_ADDR_LEN];
115 struct callout sc_tick_ch; /* tick callout */
116 struct callout sc_rx_ch; /* delayed RX callout */
117 u_int sc_wdog_timer; /* watchdog timer */
118
119 void *sc_ih;
120 struct resource *sc_res[3];
121 #define GEM_RES_INTR 0
122 #define GEM_RES_BANK1 1
123 #define GEM_RES_BANK2 2
124
125 bus_dma_tag_t sc_pdmatag; /* parent bus DMA tag */
126 bus_dma_tag_t sc_rdmatag; /* RX bus DMA tag */
127 bus_dma_tag_t sc_tdmatag; /* TX bus DMA tag */
128 bus_dma_tag_t sc_cdmatag; /* control data bus DMA tag */
129 bus_dmamap_t sc_dmamap; /* bus DMA handle */
130
131 u_int sc_variant;
132 #define GEM_UNKNOWN 0 /* don't know */
133 #define GEM_SUN_GEM 1 /* Sun GEM */
134 #define GEM_SUN_ERI 2 /* Sun ERI */
135 #define GEM_APPLE_GMAC 3 /* Apple GMAC */
136 #define GEM_APPLE_K2_GMAC 4 /* Apple K2 GMAC */
137
138 #define GEM_IS_APPLE(sc) \
139 ((sc)->sc_variant == GEM_APPLE_GMAC || \
140 (sc)->sc_variant == GEM_APPLE_K2_GMAC)
141
142 u_int sc_flags;
143 #define GEM_INITED (1 << 0) /* reset persistent regs init'ed */
144 #define GEM_LINK (1 << 1) /* link is up */
145 #define GEM_PCI (1 << 2) /* PCI busses are little-endian */
146 #define GEM_PCI66 (1 << 3) /* PCI bus runs at 66MHz */
147 #define GEM_SERDES (1 << 4) /* use the SERDES */
148
149 /*
150 * ring buffer DMA stuff
151 */
152 bus_dmamap_t sc_cddmamap; /* control data DMA map */
153 bus_addr_t sc_cddma;
154
155 /*
156 * software state for transmit and receive descriptors
157 */
158 struct gem_txsoft sc_txsoft[GEM_TXQUEUELEN];
159 struct gem_rxsoft sc_rxsoft[GEM_NRXDESC];
160
161 /*
162 * control data structures
163 */
164 struct gem_control_data *sc_control_data;
165 #define sc_txdescs sc_control_data->gcd_txdescs
166 #define sc_rxdescs sc_control_data->gcd_rxdescs
167
168 u_int sc_txfree; /* number of free TX descriptors */
169 u_int sc_txnext; /* next ready TX descriptor */
170 u_int sc_txwin; /* TX desc. since last TX intr. */
171
172 struct gem_txsq sc_txfreeq; /* free TX descsofts */
173 struct gem_txsq sc_txdirtyq; /* dirty TX descsofts */
174
175 u_int sc_rxptr; /* next ready RX descriptor/state */
176 u_int sc_rxfifosize; /* RX FIFO size (bytes) */
177
178 uint32_t sc_mac_rxcfg; /* RX MAC conf. % GEM_MAC_RX_ENABLE */
179
180 int sc_ifflags;
181 u_long sc_csum_features;
182 };
183
184 #define GEM_BANKN_BARRIER(n, sc, offs, len, flags) \
185 bus_barrier((sc)->sc_res[(n)], (offs), (len), (flags))
186 #define GEM_BANK1_BARRIER(sc, offs, len, flags) \
187 GEM_BANKN_BARRIER(GEM_RES_BANK1, (sc), (offs), (len), (flags))
188 #define GEM_BANK2_BARRIER(sc, offs, len, flags) \
189 GEM_BANKN_BARRIER(GEM_RES_BANK2, (sc), (offs), (len), (flags))
190
191 #define GEM_BANKN_READ_M(n, m, sc, offs) \
192 bus_read_ ## m((sc)->sc_res[(n)], (offs))
193 #define GEM_BANK1_READ_1(sc, offs) \
194 GEM_BANKN_READ_M(GEM_RES_BANK1, 1, (sc), (offs))
195 #define GEM_BANK1_READ_2(sc, offs) \
196 GEM_BANKN_READ_M(GEM_RES_BANK1, 2, (sc), (offs))
197 #define GEM_BANK1_READ_4(sc, offs) \
198 GEM_BANKN_READ_M(GEM_RES_BANK1, 4, (sc), (offs))
199 #define GEM_BANK2_READ_1(sc, offs) \
200 GEM_BANKN_READ_M(GEM_RES_BANK2, 1, (sc), (offs))
201 #define GEM_BANK2_READ_2(sc, offs) \
202 GEM_BANKN_READ_M(GEM_RES_BANK2, 2, (sc), (offs))
203 #define GEM_BANK2_READ_4(sc, offs) \
204 GEM_BANKN_READ_M(GEM_RES_BANK2, 4, (sc), (offs))
205
206 #define GEM_BANKN_WRITE_M(n, m, sc, offs, v) \
207 bus_write_ ## m((sc)->sc_res[n], (offs), (v))
208 #define GEM_BANK1_WRITE_1(sc, offs, v) \
209 GEM_BANKN_WRITE_M(GEM_RES_BANK1, 1, (sc), (offs), (v))
210 #define GEM_BANK1_WRITE_2(sc, offs, v) \
211 GEM_BANKN_WRITE_M(GEM_RES_BANK1, 2, (sc), (offs), (v))
212 #define GEM_BANK1_WRITE_4(sc, offs, v) \
213 GEM_BANKN_WRITE_M(GEM_RES_BANK1, 4, (sc), (offs), (v))
214 #define GEM_BANK2_WRITE_1(sc, offs, v) \
215 GEM_BANKN_WRITE_M(GEM_RES_BANK2, 1, (sc), (offs), (v))
216 #define GEM_BANK2_WRITE_2(sc, offs, v) \
217 GEM_BANKN_WRITE_M(GEM_RES_BANK2, 2, (sc), (offs), (v))
218 #define GEM_BANK2_WRITE_4(sc, offs, v) \
219 GEM_BANKN_WRITE_M(GEM_RES_BANK2, 4, (sc), (offs), (v))
220
221 /* XXX this should be handled by bus_dma(9). */
222 #define GEM_DMA_READ(sc, v) \
223 ((((sc)->sc_flags & GEM_PCI) != 0) ? le64toh(v) : be64toh(v))
224 #define GEM_DMA_WRITE(sc, v) \
225 ((((sc)->sc_flags & GEM_PCI) != 0) ? htole64(v) : htobe64(v))
226
227 #define GEM_CDTXADDR(sc, x) ((sc)->sc_cddma + GEM_CDTXOFF((x)))
228 #define GEM_CDRXADDR(sc, x) ((sc)->sc_cddma + GEM_CDRXOFF((x)))
229
230 #define GEM_CDSYNC(sc, ops) \
231 bus_dmamap_sync((sc)->sc_cdmatag, (sc)->sc_cddmamap, (ops));
232
233 #define GEM_INIT_RXDESC(sc, x) \
234 do { \
235 struct gem_rxsoft *__rxs = &sc->sc_rxsoft[(x)]; \
236 struct gem_desc *__rxd = &sc->sc_rxdescs[(x)]; \
237 struct mbuf *__m = __rxs->rxs_mbuf; \
238 \
239 __m->m_data = __m->m_ext.ext_buf; \
240 __rxd->gd_addr = \
241 GEM_DMA_WRITE((sc), __rxs->rxs_paddr); \
242 __rxd->gd_flags = GEM_DMA_WRITE((sc), \
243 (((__m->m_ext.ext_size) << GEM_RD_BUFSHIFT) & \
244 GEM_RD_BUFSIZE) | GEM_RD_OWN); \
245 } while (0)
246
247 #define GEM_UPDATE_RXDESC(sc, x) \
248 do { \
249 struct gem_rxsoft *__rxs = &sc->sc_rxsoft[(x)]; \
250 struct gem_desc *__rxd = &sc->sc_rxdescs[(x)]; \
251 struct mbuf *__m = __rxs->rxs_mbuf; \
252 \
253 __rxd->gd_flags = GEM_DMA_WRITE((sc), \
254 (((__m->m_ext.ext_size) << GEM_RD_BUFSHIFT) & \
255 GEM_RD_BUFSIZE) | GEM_RD_OWN); \
256 } while (0)
257
258 #define GEM_LOCK_INIT(_sc, _name) \
259 mtx_init(&(_sc)->sc_mtx, _name, MTX_NETWORK_LOCK, MTX_DEF)
260 #define GEM_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
261 #define GEM_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
262 #define GEM_LOCK_ASSERT(_sc, _what) mtx_assert(&(_sc)->sc_mtx, (_what))
263 #define GEM_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx)
264
265 #ifdef _KERNEL
266 extern devclass_t gem_devclass;
267
268 int gem_attach(struct gem_softc *sc);
269 void gem_detach(struct gem_softc *sc);
270 void gem_intr(void *v);
271 void gem_resume(struct gem_softc *sc);
272 void gem_suspend(struct gem_softc *sc);
273
274 int gem_mediachange(struct ifnet *ifp);
275 void gem_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr);
276
277 /* MII methods & callbacks */
278 int gem_mii_readreg(device_t dev, int phy, int reg);
279 void gem_mii_statchg(device_t dev);
280 int gem_mii_writereg(device_t dev, int phy, int reg, int val);
281
282 #endif /* _KERNEL */
283
284 #endif
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