chvgpio_reg.h

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    1 /*-
    2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
    3  *
    4  * Copyright (c) 2017 Tom Jones <tj@enoti.me>
    5  * All rights reserved.
    6  *
    7  * Redistribution and use in source and binary forms, with or without
    8  * modification, are permitted provided that the following conditions
    9  * are met:
   10  * 1. Redistributions of source code must retain the above copyright
   11  *    notice, this list of conditions and the following disclaimer.
   12  * 2. Redistributions in binary form must reproduce the above copyright
   13  *    notice, this list of conditions and the following disclaimer in the
   14  *    documentation and/or other materials provided with the distribution.
   15  *
   16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   19  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   26  * SUCH DAMAGE.
   27  *
   28  * $FreeBSD$
   29  */
   30 
   31 /*
   32  * Copyright (c) 2016 Mark Kettenis
   33  *
   34  * Permission to use, copy, modify, and distribute this software for any
   35  * purpose with or without fee is hereby granted, provided that the above
   36  * copyright notice and this permission notice appear in all copies.
   37  *
   38  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   39  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
   40  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
   41  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
   42  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
   43  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
   44  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
   45  *
   46  */
   47 
   48 
   49 #define CHVGPIO_INTERRUPT_STATUS                0x0300
   50 #define CHVGPIO_INTERRUPT_MASK                  0x0380
   51 #define CHVGPIO_PAD_CFG0                        0x4400
   52 #define CHVGPIO_PAD_CFG1                        0x4404
   53 
   54 #define CHVGPIO_PAD_CFG0_GPIORXSTATE            0x00000001
   55 #define CHVGPIO_PAD_CFG0_GPIOTXSTATE            0x00000002
   56 #define CHVGPIO_PAD_CFG0_INTSEL_MASK            0xf0000000
   57 #define CHVGPIO_PAD_CFG0_INTSEL_SHIFT           28
   58 
   59 #define CHVGPIO_PAD_CFG0_GPIOCFG_SHIFT          8
   60 #define CHVGPIO_PAD_CFG0_GPIOCFG_MASK           (7 << CHVGPIO_PAD_CFG0_GPIOCFG_SHIFT)
   61 #define CHVGPIO_PAD_CFG0_GPIOCFG_GPIO           0
   62 #define CHVGPIO_PAD_CFG0_GPIOCFG_GPO            1
   63 #define CHVGPIO_PAD_CFG0_GPIOCFG_GPI            2
   64 #define CHVGPIO_PAD_CFG0_GPIOCFG_HIZ            3
   65 
   66 #define CHVGPIO_PAD_CFG1_INTWAKECFG_MASK        0x00000007
   67 #define CHVGPIO_PAD_CFG1_INTWAKECFG_FALLING     0x00000001
   68 #define CHVGPIO_PAD_CFG1_INTWAKECFG_RISING      0x00000002
   69 #define CHVGPIO_PAD_CFG1_INTWAKECFG_BOTH        0x00000003
   70 #define CHVGPIO_PAD_CFG1_INTWAKECFG_LEVEL       0x00000004
   71 #define CHVGPIO_PAD_CFG1_INVRXTX_MASK           0x000000f0
   72 #define CHVGPIO_PAD_CFG1_INVRXTX_RXDATA         0x00000040
   73 
   74 /*
   75  * The pads for the pins are arranged in groups of maximal 15 pins.
   76  * The arrays below give the number of pins per group, such that we
   77  * can validate the (untrusted) pin numbers from ACPI.
   78  */
   79 #define E_UID           3
   80 #define E_BANK_PREFIX   "eastbank"
   81 
   82 const int chv_east_pins[] = {
   83         12, 12, -1
   84 };
   85 
   86 const char *chv_east_pin_names[] = {
   87                 "PMU_SLP_S3_B",
   88                 "PMU_BATLOW_B",
   89                 "SUS_STAT_B",
   90                 "PMU_SLP_S0IX_B",
   91                 "PMU_AC_PRESENT",
   92                 "PMU_PLTRST_B",
   93                 "PMU_SUSCLK",
   94                 "PMU_SLP_LAN_B",
   95                 "PMU_PWRBTN_B",
   96                 "PMU_SLP_S4_B",
   97                 "PMU_WAKE_B",
   98                 "PMU_WAKE_LAN_B"
   99 
  100                 "MF_ISH_GPIO_3",
  101                 "MF_ISH_GPIO_7",
  102                 "MF_ISH_I2C1_SCL",
  103                 "MF_ISH_GPIO_1",
  104                 "MF_ISH_GPIO_5",
  105                 "MF_ISH_GPIO_9",
  106                 "MF_ISH_GPIO_0",
  107                 "MF_ISH_GPIO_4",
  108                 "MF_ISH_GPIO_8",
  109                 "MF_ISH_GPIO_2",
  110                 "MF_ISH_GPIO_6",
  111                 "MF_ISH_I2C1_SDA"
  112 };
  113 
  114 #define N_UID           2
  115 #define N_BANK_PREFIX   "northbank"
  116 
  117 const int chv_north_pins[] = {
  118         9, 13, 12, 12, 13, -1
  119 };
  120 
  121 const char *chv_north_pin_names[] = {
  122         "GPIO_DFX0_PAD",
  123         "GPIO_DFX3_PAD",
  124         "GPIO_DFX7_PAD",
  125         "GPIO_DFX1_PAD",
  126         "GPIO_DFX5_PAD",
  127         "GPIO_DFX4_PAD",
  128         "GPIO_DFX8_PAD",
  129         "GPIO_DFX2_PAD",
  130         "GPIO_DFX6_PAD",
  131 
  132         "GPIO_SUS0_PAD",
  133         "SEC_GPIO_SUS10_PAD",
  134         "GPIO_SUS3_PAD",
  135         "GPIO_SUS7_PAD",
  136         "GPIO_SUS1_PAD",
  137         "GPIO_SUS5_PAD",
  138         "SEC_GPIO_SUS11_PAD",
  139         "GPIO_SUS4_PAD",
  140         "SEC_GPIO_SUS8_PAD",
  141         "GPIO_SUS2_PAD",
  142         "GPIO_SUS6_PAD",
  143         "CX_PREQ_B_PAD",
  144         "SEC_GPIO_SUS9_PAD",
  145 
  146         "TRST_B_PAD",
  147         "TCK_PAD",
  148         "PROCHOT_B_PAD",
  149         "SVID0_DATA_PAD",
  150         "TMS_PAD",
  151         "CX_PRDY_B_2_PAD",
  152         "TDO_2_PAD",
  153         "CX_PRDY_B_PAD",
  154         "SVID0_ALERT_B_PAD",
  155         "TDO_PAD",
  156         "SVID0_CLK_PAD",
  157         "TDI_PAD",
  158 
  159         "GP_CAMERASB05_PAD",
  160         "GP_CAMERASB02_PAD",
  161         "GP_CAMERASB08_PAD",
  162         "GP_CAMERASB00_PAD",
  163         "GP_CAMERASB06_PAD",
  164         "GP_CAMERASB10_PAD",
  165         "GP_CAMERASB03_PAD",
  166         "GP_CAMERASB09_PAD",
  167         "GP_CAMERASB01_PAD",
  168         "GP_CAMERASB07_PAD",
  169         "GP_CAMERASB11_PAD",
  170         "GP_CAMERASB04_PAD",
  171 
  172         "PANEL0_BKLTEN_PAD",
  173         "HV_DDI0_HPD_PAD",
  174         "HV_DDI2_DDC_SDA_PAD",
  175         "PANEL1_BKLTCTL_PAD",
  176         "HV_DDI1_HPD_PAD",
  177         "PANEL0_BKLTCTL_PAD",
  178         "HV_DDI0_DDC_SDA_PAD",
  179         "HV_DDI2_DDC_SCL_PAD",
  180         "HV_DDI2_HPD_PAD",
  181         "PANEL1_VDDEN_PAD",
  182         "PANEL1_BKLTEN_PAD",
  183         "HV_DDI0_DDC_SCL_PAD",
  184         "PANEL0_VDDEN_PAD",
  185 };
  186 
  187 
  188 #define SE_UID          4
  189 #define SE_BANK_PREFIX  "southeastbank"
  190 
  191 const int chv_southeast_pins[] = {
  192         8, 12, 6, 8, 10, 11, -1
  193 };
  194 
  195 const char *chv_southeast_pin_names[] = {
  196         "MF_PLT_CLK0_PAD",
  197         "PWM1_PAD",
  198         "MF_PLT_CLK1_PAD",
  199         "MF_PLT_CLK4_PAD",
  200         "MF_PLT_CLK3_PAD",
  201         "PWM0_PAD",
  202         "MF_PLT_CLK5_PAD",
  203         "MF_PLT_CLK2_PAD",
  204 
  205         "SDMMC2_D3_CD_B_PAD",
  206         "SDMMC1_CLK_PAD",
  207         "SDMMC1_D0_PAD",
  208         "SDMMC2_D1_PAD",
  209         "SDMMC2_CLK_PAD",
  210         "SDMMC1_D2_PAD",
  211         "SDMMC2_D2_PAD",
  212         "SDMMC2_CMD_PAD",
  213         "SDMMC1_CMD_PAD",
  214         "SDMMC1_D1_PAD",
  215         "SDMMC2_D0_PAD",
  216         "SDMMC1_D3_CD_B_PAD",
  217 
  218         "SDMMC3_D1_PAD",
  219         "SDMMC3_CLK_PAD",
  220         "SDMMC3_D3_PAD",
  221         "SDMMC3_D2_PAD",
  222         "SDMMC3_CMD_PAD",
  223         "SDMMC3_D0_PAD",
  224 
  225         "MF_LPC_AD2_PAD",
  226         "LPC_CLKRUNB_PAD",
  227         "MF_LPC_AD0_PAD",
  228         "LPC_FRAMEB_PAD",
  229         "MF_LPC_CLKOUT1_PAD",
  230         "MF_LPC_AD3_PAD",
  231         "MF_LPC_CLKOUT0_PAD",
  232         "MF_LPC_AD1_PAD",
  233 
  234         "SPI1_MISO_PAD",
  235         "SPI1_CS0_B_PAD",
  236         "SPI1_CLK_PAD",
  237         "MMC1_D6_PAD",
  238         "SPI1_MOSI_PAD",
  239         "MMC1_D5_PAD",
  240         "SPI1_CS1_B_PAD",
  241         "MMC1_D4_SD_WE_PAD",
  242         "MMC1_D7_PAD",
  243         "MMC1_RCLK_PAD",
  244 
  245         "USB_OC1_B_PAD",
  246         "PMU_RESETBUTTON_B_PAD",
  247         "GPIO_ALERT_PAD",
  248         "SDMMC3_PWR_EN_B_PAD",
  249         "ILB_SERIRQ_PAD",
  250         "USB_OC0_B_PAD",
  251         "SDMMC3_CD_B_PAD",
  252         "SPKR_PAD",
  253         "SUSPWRDNACK_PAD",
  254         "SPARE_PIN_PAD",
  255         "SDMMC3_1P8_EN_PAD",
  256 };
  257 
  258 #define SW_UID          1
  259 #define SW_BANK_PREFIX  "southwestbank"
  260 
  261 const int chv_southwest_pins[] = {
  262         8, 8, 8, 8, 8, 8, 8, -1
  263 };
  264 
  265 const char *chv_southwest_pin_names[] = {
  266         "FST_SPI_D2_PAD",
  267         "FST_SPI_D0_PAD",
  268         "FST_SPI_CLK_PAD",
  269         "FST_SPI_D3_PAD",
  270         "FST_SPI_CS1_B_PAD",
  271         "FST_SPI_D1_PAD",
  272         "FST_SPI_CS0_B_PAD",
  273         "FST_SPI_CS2_B_PAD",
  274 
  275         "UART1_RTS_B_PAD",
  276         "UART1_RXD_PAD",
  277         "UART2_RXD_PAD",
  278         "UART1_CTS_B_PAD",
  279         "UART2_RTS_B_PAD",
  280         "UART1_TXD_PAD",
  281         "UART2_TXD_PAD",
  282         "UART2_CTS_B_PAD",
  283 
  284         "MF_HDA_CLK"
  285         "MF_HDA_RSTB",
  286         "MF_HDA_SDIO",
  287         "MF_HDA_SDO",
  288         "MF_HDA_DOCKRSTB",
  289         "MF_HDA_SYNC",
  290         "MF_HDA_SDI1",
  291         "MF_HDA_DOCKENB",
  292 
  293         "I2C5_SDA_PAD",
  294         "I2C4_SDA_PAD",
  295         "I2C6_SDA_PAD",
  296         "I2C5_SCL_PAD",
  297         "I2C_NFC_SDA_PAD",
  298         "I2C4_SCL_PAD",
  299         "I2C6_SCL_PAD",
  300         "I2C_NFC_SCL_PAD",
  301 
  302         "I2C1_SDA_PAD",
  303         "I2C0_SDA_PAD",
  304         "I2C2_SDA_PAD",
  305         "I2C1_SCL_PAD",
  306         "I2C3_SDA_PAD",
  307         "I2C0_SCL_PAD",
  308         "I2C2_SCL_PAD",
  309         "I2C3_SCL_PAD",
  310 
  311         "SATA_GP0",
  312         "SATA_GP1",
  313         "SATA_LEDN",
  314         "SATA_GP2",
  315         "MF_SMB_ALERTB",
  316         "SATA_GP3",
  317         "MF_SMB_CLK",
  318         "MF_SMB_DATA",
  319 
  320         "PCIE_CLKREQ0B_PAD",
  321         "PCIE_CLKREQ1B_PAD",
  322         "GP_SSP_2_CLK_PAD",
  323         "PCIE_CLKREQ2B_PAD",
  324         "GP_SSP_2_RXD_PAD",
  325         "PCIE_CLKREQ3B_PAD",
  326         "GP_SSP_2_FS_PAD",
  327         "GP_SSP_2_TXD_PAD",
  328 };
  329 
  330 const char *virtualgpio[] = {
  331         "VIRTUAL0_PAD",
  332         "VIRTUAL1_PAD",
  333         "VIRTUAL2_PAD",
  334         "VIRTUAL3_PAD",
  335         "VIRTUAL4_PAD",
  336         "VIRTUAL5_PAD",
  337         "VIRTUAL6_PAD",
  338         "VIRTUAL7_PAD",
  339 };
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FreeBSD/Linux Kernel Cross Reference sys/dev/gpio/chvgpio_reg.h

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sys/dev/gpio/chvgpio_reg.h
