The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/dev/gpio/gpiosim.c

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    1 /*      $OpenBSD: gpiosim.c,v 1.2 2022/04/06 18:59:28 naddy Exp $       */
    2 
    3 /*
    4  * Copyright (c) 2007 Marc Balmer <mbalmer@openbsd.org>
    5  * All rights reserved.
    6  *
    7  * Permission to use, copy, modify, and distribute this software for any
    8  * purpose with or without fee is hereby granted, provided that the above
    9  * copyright notice and this permission notice appear in all copies.
   10  *
   11  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   12  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
   13  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
   14  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
   15  * WHATSOEVER RESULTING FROM LOSS OF MIND, USE, DATA OR PROFITS, WHETHER IN
   16  * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
   17  * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
   18  */
   19 
   20 /* 32 bit wide GPIO simulator  */
   21 #include <sys/param.h>
   22 #include <sys/systm.h>
   23 #include <sys/device.h>
   24 #include <sys/gpio.h>
   25 #include <sys/malloc.h>
   26 #include <sys/sysctl.h>
   27 #include <sys/ioccom.h>
   28 
   29 #include <dev/gpio/gpiovar.h>
   30 #include <dev/biovar.h>
   31 
   32 #define GPIOSIM_NPINS   32
   33 
   34 struct gpiosim_softc {
   35         struct device           sc_dev;
   36         u_int32_t               sc_state;
   37         struct gpio_chipset_tag sc_gpio_gc;
   38         gpio_pin_t              sc_gpio_pins[GPIOSIM_NPINS];
   39 };
   40 
   41 struct gpiosim_op {
   42         void *cookie;
   43         u_int32_t mask;
   44         u_int32_t state;
   45 };
   46 #define GPIOSIMREAD     _IOWR('G', 0, struct gpiosim_op)
   47 #define GPIOSIMWRITE    _IOW('G', 1, struct gpiosim_op)
   48 
   49 int     gpiosim_match(struct device *, void *, void *);
   50 void    gpiosim_attach(struct device *, struct device *, void *);
   51 int     gpiosim_ioctl(struct device *, u_long cmd, caddr_t data);
   52 
   53 int     gpiosim_pin_read(void *, int);
   54 void    gpiosim_pin_write(void *, int, int);
   55 void    gpiosim_pin_ctl(void *, int, int);
   56 
   57 const struct cfattach gpiosim_ca = {
   58         sizeof(struct gpiosim_softc), gpiosim_match, gpiosim_attach
   59 };
   60 
   61 struct cfdriver gpiosim_cd = {
   62         NULL, "gpiosim", DV_DULL
   63 };
   64 
   65 int
   66 gpiosim_match(struct device *parent, void *match, void *aux)
   67 {
   68         return 1;
   69 }
   70 
   71 void
   72 gpiosim_attach(struct device *parent, struct device *self, void *aux)
   73 {
   74         struct gpiosim_softc *sc = (void *)self;
   75         struct gpiobus_attach_args gba;
   76         int i;
   77 
   78         /* initialize pin array */
   79         for (i = 0; i < GPIOSIM_NPINS; i++) {
   80                 sc->sc_gpio_pins[i].pin_num = i;
   81                 sc->sc_gpio_pins[i].pin_caps = GPIO_PIN_INPUT |
   82                     GPIO_PIN_OUTPUT | GPIO_PIN_OPENDRAIN |
   83                     GPIO_PIN_PULLUP | GPIO_PIN_PULLDOWN |
   84                     GPIO_PIN_INVIN | GPIO_PIN_INVOUT;
   85 
   86                 /* read initial state */
   87                 sc->sc_gpio_pins[i].pin_flags = GPIO_PIN_INPUT;
   88                 sc->sc_state = 0;
   89 
   90                 /* create controller tag */
   91                 sc->sc_gpio_gc.gp_cookie = sc;
   92                 sc->sc_gpio_gc.gp_pin_read = gpiosim_pin_read;
   93                 sc->sc_gpio_gc.gp_pin_write = gpiosim_pin_write;
   94                 sc->sc_gpio_gc.gp_pin_ctl = gpiosim_pin_ctl;
   95 
   96                 gba.gba_name = "gpio";
   97                 gba.gba_gc = &sc->sc_gpio_gc;
   98                 gba.gba_pins = sc->sc_gpio_pins;
   99                 gba.gba_npins = GPIOSIM_NPINS;
  100         }
  101         printf("\n");
  102         config_found(&sc->sc_dev, &gba, gpiobus_print);
  103         bio_register(&sc->sc_dev, gpiosim_ioctl);
  104 }
  105 
  106 int
  107 gpiosim_ioctl(struct device *self, u_long cmd, caddr_t data)
  108 {
  109         struct gpiosim_softc *sc = (void *)self;
  110         struct gpiosim_op *op = (void *)data;
  111 
  112         switch (cmd) {
  113                 case GPIOSIMREAD:
  114                         op->state = sc->sc_state;
  115                         break;
  116                 case GPIOSIMWRITE:
  117                         sc->sc_state = (sc->sc_state & ~op->mask) |
  118                             (op->state & op->mask);
  119                         break;
  120         }
  121         return 0;
  122 }
  123 
  124 int
  125 gpiosim_pin_read(void *arg, int pin)
  126 {
  127         struct gpiosim_softc *sc = (struct gpiosim_softc *)arg;
  128 
  129         if (sc->sc_state & (1 << pin))
  130                 return GPIO_PIN_HIGH;
  131         else
  132                 return GPIO_PIN_LOW;
  133 }
  134 
  135 void
  136 gpiosim_pin_write(void *arg, int pin, int value)
  137 {
  138         struct gpiosim_softc *sc = (struct gpiosim_softc *)arg;
  139 
  140         if (value == 0)
  141                 sc->sc_state &= ~(1 << pin);
  142         else
  143                 sc->sc_state |= (1 << pin);
  144 }
  145 
  146 void
  147 gpiosim_pin_ctl(void *arg, int pin, int flags)
  148 {
  149         struct gpiosim_softc *sc = (struct gpiosim_softc *)arg;
  150 
  151         sc->sc_gpio_pins[pin].pin_flags = flags;
  152 }

Cache object: c607bb87155b194d9b3cd8206da2f973


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