Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/dev/gx/if_gxvar.h
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1 /*- 2 * Copyright (c) 1999,2000,2001 Jonathan Lemon 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. Neither the name of the author nor the names of any co-contributors 14 * may be used to endorse or promote products derived from this software 15 * without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD: releng/5.0/sys/dev/gx/if_gxvar.h 106937 2002-11-14 23:54:55Z sam $ 30 */ 31 32 #if __FreeBSD_version < 500000 33 #define GX_LOCK(gx) 34 #define GX_UNLOCK(gx) 35 #define mtx_init(a, b, c, d) 36 #define mtx_destroy(a) 37 struct mtx { int filler; }; 38 #else 39 #define GX_LOCK(gx) mtx_lock(&(gx)->gx_mtx) 40 #define GX_UNLOCK(gx) mtx_unlock(&(gx)->gx_mtx) 41 #endif 42 43 #ifdef __alpha__ 44 #undef vtophys 45 #define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va) 46 #endif 47 48 #ifndef PCIM_CMD_MWIEN 49 #define PCIM_CMD_MWIEN 0x0010 50 #endif 51 52 /* CSR_WRITE_8 assumes the register is in low/high order */ 53 #define CSR_WRITE_8(gx, reg, val) do { \ 54 bus_space_write_4((gx)->gx_btag, (gx)->gx_bhandle, \ 55 reg, (val) & 0xffffffff); \ 56 bus_space_write_4((gx)->gx_btag, (gx)->gx_bhandle, \ 57 (reg) + 4, (val) >> 32); \ 58 } while (0) 59 #define CSR_WRITE_4(gx, reg, val) \ 60 bus_space_write_4((gx)->gx_btag, (gx)->gx_bhandle, reg, val) 61 #define CSR_WRITE_2(gx, reg, val) \ 62 bus_space_write_2((gx)->gx_btag, (gx)->gx_bhandle, reg, val) 63 #define CSR_WRITE_1(gx, reg, val) \ 64 bus_space_write_1((gx)->gx_btag, (gx)->gx_bhandle, reg, val) 65 66 #define CSR_READ_4(gx, reg) \ 67 bus_space_read_4((gx)->gx_btag, (gx)->gx_bhandle, reg) 68 #define CSR_READ_2(gx, reg) \ 69 bus_space_read_2((gx)->gx_btag, (gx)->gx_bhandle, reg) 70 #define CSR_READ_1(gx, reg) \ 71 bus_space_read_1((gx)->gx_btag, (gx)->gx_bhandle, reg) 72 73 #define GX_SETBIT(gx, reg, x) \ 74 CSR_WRITE_4(gx, reg, (CSR_READ_4(gx, reg) | (x))) 75 #define GX_CLRBIT(gx, reg, x) \ 76 CSR_WRITE_4(gx, reg, (CSR_READ_4(gx, reg) & ~(x))) 77 78 /* 79 * In theory, these can go up to 64K each, but due to chip bugs, 80 * they are limited to 256 max. Descriptor counts should be a 81 * multiple of 8. 82 */ 83 #define GX_TX_RING_CNT 256 84 #define GX_RX_RING_CNT 256 85 86 #define GX_INC(x, y) (x) = (x + 1) % y 87 #define GX_PREV(x, y) (x == 0 ? y - 1 : x - 1) 88 89 #define GX_MAX_MTU (16 * 1024) 90 91 struct gx_ring_data { 92 struct gx_rx_desc gx_rx_ring[GX_RX_RING_CNT]; 93 struct gx_tx_desc gx_tx_ring[GX_TX_RING_CNT]; 94 }; 95 96 struct gx_chain_data { 97 struct mbuf *gx_rx_chain[GX_RX_RING_CNT]; 98 struct mbuf *gx_tx_chain[GX_TX_RING_CNT]; 99 }; 100 101 struct gx_regs { 102 int r_rx_base; 103 int r_rx_length; 104 int r_rx_head; 105 int r_rx_tail; 106 int r_rx_delay; 107 int r_rx_dma_ctrl; 108 109 int r_tx_base; 110 int r_tx_length; 111 int r_tx_head; 112 int r_tx_tail; 113 int r_tx_delay; 114 int r_tx_dma_ctrl; 115 }; 116 117 struct gx_softc { 118 struct arpcom arpcom; /* interface info */ 119 struct ifmedia gx_media; /* media info */ 120 bus_space_handle_t gx_bhandle; /* bus space handle */ 121 bus_space_tag_t gx_btag; /* bus space tag */ 122 void *gx_intrhand; /* irq handler handle */ 123 struct resource *gx_irq; /* IRQ resource handle */ 124 struct resource *gx_res; /* I/O or shared mem handle */ 125 device_t gx_dev; 126 device_t gx_miibus; 127 u_int8_t gx_unit; /* controller number */ 128 u_int8_t gx_tbimode; /* transceiver flag */ 129 int gx_vflags; /* version-specific flags */ 130 u_int32_t gx_ipg; /* version-specific IPG */ 131 struct gx_ring_data *gx_rdata; 132 struct gx_chain_data gx_cdata; 133 int gx_if_flags; 134 struct mbuf *gx_pkthdr; 135 struct mbuf **gx_pktnextp; 136 int gx_rx_tail_idx; /* receive ring tail index */ 137 int gx_tx_tail_idx; /* transmit ring tail index */ 138 int gx_tx_head_idx; /* transmit ring tail index */ 139 int gx_txcnt; 140 int gx_txcontext; /* current TX context */ 141 struct gx_regs gx_reg; 142 struct mtx gx_mtx; 143 144 /* tunables */ 145 int gx_tx_intr_delay; 146 int gx_rx_intr_delay; 147 148 /* statistics */ 149 int gx_tx_interrupts; 150 int gx_rx_interrupts; 151 int gx_interrupts; 152 }; 153 154 /* 155 * flags to compensate for differing chip variants 156 */ 157 #define GXF_FORCE_TBI 0x0001 /* force TBI mode on */ 158 #define GXF_DMA 0x0002 /* has DMA control registers */ 159 #define GXF_ENABLE_MWI 0x0004 /* supports MWI burst mode */ 160 #define GXF_OLD_REGS 0x0008 /* use old register mapping */ 161 #define GXF_CSUM 0x0010 /* hardware checksum offload */ 162 163 /* 164 * TX Context definitions. 165 */ 166 #define GX_TXCONTEXT_NONE 0 167 #define GX_TXCONTEXT_TCPIP 1 168 #define GX_TXCONTEXT_UDPIP 2
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