The Design and Implementation of the FreeBSD Operating System, Second Edition
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FreeBSD/Linux Kernel Cross Reference
sys/dev/hatm/if_hatmreg.h

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    1 /*-
    2  * Copyright (c) 2001-2003
    3  *      Fraunhofer Institute for Open Communication Systems (FhG Fokus).
    4  *      All rights reserved.
    5  *
    6  * Redistribution and use in source and binary forms, with or without
    7  * modification, are permitted provided that the following conditions
    8  * are met:
    9  * 1. Redistributions of source code must retain the above copyright
   10  *    notice, this list of conditions and the following disclaimer.
   11  * 2. Redistributions in binary form must reproduce the above copyright
   12  *    notice, this list of conditions and the following disclaimer in the
   13  *    documentation and/or other materials provided with the distribution.
   14  *
   15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   25  * SUCH DAMAGE.
   26  *
   27  * Author: Hartmut Brandt <harti@freebsd.org>
   28  *
   29  * $FreeBSD: releng/8.4/sys/dev/hatm/if_hatmreg.h 139749 2005-01-06 01:43:34Z imp $
   30  *
   31  * Fore HE driver for NATM
   32  */
   33 
   34 /* check configuration */
   35 #if HE_CONFIG_VPI_BITS + HE_CONFIG_VCI_BITS > 12
   36 #error "hatm: too many bits configured for VPI/VCI"
   37 #endif
   38 
   39 #define HE_MAX_VCCS     (1 << (HE_CONFIG_VPI_BITS + HE_CONFIG_VCI_BITS))
   40 
   41 #define HE_VPI_MASK     ((1 << (HE_CONFIG_VPI_BITS))-1)
   42 #define HE_VCI_MASK     ((1 << (HE_CONFIG_VCI_BITS))-1)
   43 
   44 #define HE_VPI(CID)     (((CID) >> HE_CONFIG_VCI_BITS) & HE_VPI_MASK)
   45 #define HE_VCI(CID)     ((CID) & HE_VCI_MASK)
   46 
   47 #define HE_CID(VPI,VCI) ((((VPI) & HE_VPI_MASK) << HE_CONFIG_VCI_BITS) | \
   48         ((VCI) & HE_VCI_MASK))
   49 
   50 
   51 /* GEN_CNTL_0 register */
   52 #define HE_PCIR_GEN_CNTL_0              0x40
   53 #define HE_PCIM_CTL0_64BIT              (1 << 0)
   54 #define HE_PCIM_CTL0_IGNORE_TIMEOUT     (1 << 1)
   55 #define HE_PCIM_CTL0_INIT_ENB           (1 << 2)
   56 #define HE_PCIM_CTL0_MRM                (1 << 4)
   57 #define HE_PCIM_CTL0_MRL                (1 << 5)
   58 #define HE_PCIM_CTL0_BIGENDIAN          (1 << 16)
   59 #define HE_PCIM_CTL0_INT_PROC_ENB       (1 << 25)
   60 
   61 /*
   62  * Memory registers
   63  */
   64 #define HE_REGO_FLASH                   0x00000
   65 #define HE_REGO_RESET_CNTL              0x80000
   66 #define HE_REGM_RESET_STATE             (1 << 6)
   67 #define HE_REGO_HOST_CNTL               0x80004
   68 #define HE_REGM_HOST_BUS64              (1 << 27)
   69 #define HE_REGM_HOST_DESC_RD64          (1 << 26)
   70 #define HE_REGM_HOST_DATA_RD64          (1 << 25)
   71 #define HE_REGM_HOST_DATA_WR64          (1 << 24)
   72 #define HE_REGM_HOST_PROM_SEL           (1 << 12)
   73 #define HE_REGM_HOST_PROM_WREN          (1 << 11)
   74 #define HE_REGM_HOST_PROM_DATA_OUT      (1 << 10)
   75 #define HE_REGS_HOST_PROM_DATA_OUT      10
   76 #define HE_REGM_HOST_PROM_DATA_IN       (1 << 9)
   77 #define HE_REGS_HOST_PROM_DATA_IN       9
   78 #define HE_REGM_HOST_PROM_CLOCK         (1 << 8)
   79 #define HE_REGM_HOST_PROM_BITS          (0x00001f00)
   80 #define HE_REGM_HOST_QUICK_RD           (1 << 7)
   81 #define HE_REGM_HOST_QUICK_WR           (1 << 6)
   82 #define HE_REGM_HOST_OUTFF_ENB          (1 << 5)
   83 #define HE_REGM_HOST_CMDFF_ENB          (1 << 4)
   84 #define HE_REGO_LB_SWAP                 0x80008
   85 #define HE_REGM_LBSWAP_RNUM             (0xf << 27)
   86 #define HE_REGS_LBSWAP_RNUM             27
   87 #define HE_REGM_LBSWAP_DATA_WR_SWAP     (1 << 20)
   88 #define HE_REGM_LBSWAP_DESC_RD_SWAP     (1 << 19)
   89 #define HE_REGM_LBSWAP_DATA_RD_SWAP     (1 << 18)
   90 #define HE_REGM_LBSWAP_INTR_SWAP        (1 << 17)
   91 #define HE_REGM_LBSWAP_DESC_WR_SWAP     (1 << 16)
   92 #define HE_REGM_LBSWAP_BIG_ENDIAN       (1 << 14)
   93 #define HE_REGM_LBSWAP_XFER_SIZE        (1 << 7)
   94 
   95 #define HE_REGO_LB_MEM_ADDR             0x8000C
   96 #define HE_REGO_LB_MEM_DATA             0x80010
   97 #define HE_REGO_LB_MEM_ACCESS           0x80014
   98 #define HE_REGM_LB_MEM_HNDSHK           (1 << 30)
   99 #define HE_REGM_LB_MEM_READ             0x3
  100 #define HE_REGM_LB_MEM_WRITE            0x7
  101 
  102 #define HE_REGO_SDRAM_CNTL              0x80018
  103 #define HE_REGM_SDRAM_64BIT             (1 << 3)
  104 #define HE_REGO_INT_FIFO                0x8001C
  105 #define HE_REGM_INT_FIFO_CLRA           (1 << 8)
  106 #define HE_REGM_INT_FIFO_CLRB           (1 << 9)
  107 #define HE_REGM_INT_FIFO_CLRC           (1 << 10)
  108 #define HE_REGM_INT_FIFO_CLRD           (1 << 11)
  109 #define HE_REGO_ABORT_ADDR              0x80020
  110 
  111 #define HE_REGO_IRQ0_BASE               0x80080
  112 #define HE_REGO_IRQ_BASE(Q)             (HE_REGO_IRQ0_BASE + (Q) * 0x10 + 0x00)
  113 #define HE_REGM_IRQ_BASE_TAIL           0x3ff
  114 #define HE_REGO_IRQ_HEAD(Q)             (HE_REGO_IRQ0_BASE + (Q) * 0x10 + 0x04)
  115 #define HE_REGS_IRQ_HEAD_SIZE           22
  116 #define HE_REGS_IRQ_HEAD_THRESH         12
  117 #define HE_REGS_IRQ_HEAD_HEAD           2
  118 #define HE_REGO_IRQ_CNTL(Q)             (HE_REGO_IRQ0_BASE + (Q) * 0x10 + 0x08)
  119 #define HE_REGM_IRQ_A                   (0 << 2)
  120 #define HE_REGM_IRQ_B                   (1 << 2)
  121 #define HE_REGM_IRQ_C                   (2 << 2)
  122 #define HE_REGM_IRQ_D                   (3 << 2)
  123 #define HE_REGO_IRQ_DATA(Q)             (HE_REGO_IRQ0_BASE + (Q) * 0x10 + 0x0C)
  124 
  125 #define HE_REGO_GRP_1_0_MAP             0x800C0
  126 #define HE_REGO_GRP_3_2_MAP             0x800C4
  127 #define HE_REGO_GRP_5_4_MAP             0x800C8
  128 #define HE_REGO_GRP_7_6_MAP             0x800CC
  129 
  130 /*
  131  * Receive buffer pools
  132  */
  133 #define HE_REGO_G0_RBPS_S       0x80400
  134 #define HE_REGO_G0_RBPS_T       0x80404
  135 #define HE_REGO_G0_RBPS_QI      0x80408
  136 #define HE_REGO_G0_RBPS_BL      0x8040C
  137 
  138 #define HE_REGO_RBP_S(K,G)      (HE_REGO_G0_RBPS_S + (K) * 0x10 + (G) * 0x20)
  139 #define HE_REGO_RBP_T(K,G)      (HE_REGO_G0_RBPS_T + (K) * 0x10 + (G) * 0x20)
  140 #define HE_REGO_RBP_QI(K,G)     (HE_REGO_G0_RBPS_QI + (K) * 0x10 + (G) * 0x20)
  141 #define HE_REGO_RBP_BL(K,G)     (HE_REGO_G0_RBPS_BL + (K) * 0x10 + (G) * 0x20)
  142 
  143 #define HE_REGS_RBP_HEAD        3
  144 #define HE_REGS_RBP_TAIL        3
  145 #define HE_REGS_RBP_SIZE        14
  146 #define HE_REGM_RBP_INTR_ENB    (1 << 13)
  147 #define HE_REGS_RBP_THRESH      0
  148 
  149 /*
  150  * Receive buffer return queues
  151  */
  152 #define HE_REGO_G0_RBRQ_ST      0x80500
  153 #define HE_REGO_G0_RBRQ_H       0x80504
  154 #define HE_REGO_G0_RBRQ_Q       0x80508
  155 #define HE_REGO_G0_RBRQ_I       0x8050C
  156 
  157 #define HE_REGO_RBRQ_ST(G)      (HE_REGO_G0_RBRQ_ST + (G) * 0x10)
  158 #define HE_REGO_RBRQ_H(G)       (HE_REGO_G0_RBRQ_H + (G) * 0x10)
  159 #define HE_REGO_RBRQ_Q(G)       (HE_REGO_G0_RBRQ_Q + (G) * 0x10)
  160 #define HE_REGO_RBRQ_I(G)       (HE_REGO_G0_RBRQ_I + (G) * 0x10)
  161 
  162 #define HE_REGS_RBRQ_HEAD       3
  163 #define HE_REGS_RBRQ_THRESH     13
  164 #define HE_REGS_RBRQ_SIZE       0
  165 #define HE_REGS_RBRQ_TIME       8
  166 #define HE_REGS_RBRQ_COUNT      0
  167 
  168 /*
  169  * Intermediate queues
  170  */
  171 #define HE_REGO_G0_INMQ_S       0x80580
  172 #define HE_REGO_G0_INMQ_L       0x80584
  173 #define HE_REGO_INMQ_S(G)       (HE_REGO_G0_INMQ_S + (G) * 8)
  174 #define HE_REGO_INMQ_L(G)       (HE_REGO_G0_INMQ_L + (G) * 8)
  175 
  176 #define HE_REGO_RHCONFIG                0x805C0
  177 #define HE_REGM_RHCONFIG_PHYENB         (1 << 10)
  178 #define HE_REGS_RHCONFIG_OAM_GID        7
  179 #define HE_REGS_RHCONFIG_PTMR_PRE       0
  180 
  181 /*
  182  * Transmit buffer return queues
  183  */
  184 #define HE_REGO_TBRQ0_B_T       0x80600
  185 #define HE_REGO_TBRQ0_H         0x80604
  186 #define HE_REGO_TBRQ0_S         0x80608
  187 #define HE_REGO_TBRQ0_THRESH    0x8060C
  188 
  189 #define HE_REGO_TBRQ_B_T(G)     (HE_REGO_TBRQ0_B_T + (G) * 0x10)
  190 #define HE_REGO_TBRQ_H(G)       (HE_REGO_TBRQ0_H + (G) * 0x10)
  191 #define HE_REGO_TBRQ_S(G)       (HE_REGO_TBRQ0_S + (G) * 0x10)
  192 #define HE_REGO_TBRQ_THRESH(G)  (HE_REGO_TBRQ0_THRESH + (G) * 0x10)
  193 
  194 #define HE_REGS_TBRQ_HEAD       2
  195 
  196 /*
  197  * Transmit packet descriptor ready queue
  198  */
  199 #define HE_REGO_TPDRQ_H         0x80680
  200 #define HE_REGS_TPDRQ_H_H       3
  201 /* #define HE_REGM_TPDRQ_H_H    ((HE_CONFIG_TPDRQ_SIZE - 1) << 3) */
  202 #define HE_REGO_TPDRQ_T         0x80684
  203 #define HE_REGS_TPDRQ_T_T       3
  204 /* #define HE_REGM_TPDRQ_T_T    ((HE_CONFIG_TPDRQ_SIZE - 1) << 3) */
  205 #define HE_REGO_TPDRQ_S         0x80688
  206 
  207 #define HE_REGO_UBUFF_BA        0x8068C
  208 
  209 #define HE_REGO_RLBF0_H         0x806C0
  210 #define HE_REGO_RLBF0_T         0x806C4
  211 #define HE_REGO_RLBF1_H         0x806C8
  212 #define HE_REGO_RLBF1_T         0x806CC
  213 #define HE_REGO_RLBF_H(N)       (HE_REGO_RLBF0_H + (N) * 8)
  214 #define HE_REGO_RLBF_T(N)       (HE_REGO_RLBF0_T + (N) * 8)
  215 
  216 #define HE_REGO_RLBC_H          0x806D0
  217 #define HE_REGO_RLBC_T          0x806D4
  218 #define HE_REGO_RLBC_H2         0x806D8
  219 #define HE_REGO_TLBF_H          0x806E0
  220 #define HE_REGO_TLBF_T          0x806E4
  221 
  222 #define HE_REGO_RLBF0_C         0x806E8
  223 #define HE_REGO_RLBF1_C         0x806EC
  224 #define HE_REGO_RLBF_C(N)       (HE_REGO_RLBF0_C + (N) * 4)
  225 
  226 #define HE_REGO_RXTHRSH         0x806F0
  227 #define HE_REGO_LITHRSH         0x806F4
  228 
  229 #define HE_REGO_LBARB           0x80700
  230 #define HE_REGS_LBARB_SLICE     28
  231 #define HE_REGS_LBARB_RNUM      23
  232 #define HE_REGS_LBARB_THPRI     21
  233 #define HE_REGS_LBARB_RHPRI     19
  234 #define HE_REGS_LBARB_TLPRI     17
  235 #define HE_REGS_LBARB_RLPRI     15
  236 #define HE_REGS_LBARB_BUS_MULT  8
  237 #define HE_REGS_LBARB_NET_PREF  0
  238 
  239 #define HE_REGO_SDRAMCON                0x80704
  240 #define HE_REGM_SDRAMCON_BANK           (1 << 14)
  241 #define HE_REGM_SDRAMCON_WIDE           (1 << 13)
  242 #define HE_REGM_SDRAMCON_TWRWAIT        (1 << 12)
  243 #define HE_REGM_SDRAMCON_TRPWAIT        (1 << 11)
  244 #define HE_REGM_SDRAMCON_TRASWAIT       (1 << 10)
  245 #define HE_REGS_SDRAMCON_REF            0
  246 
  247 #define HE_REGO_RCCSTAT                 0x8070C
  248 #define HE_REGM_RCCSTAT_PROG            (1 << 0)
  249 
  250 #define HE_REGO_TCMCONFIG               0x80740
  251 #define HE_REGS_TCMCONFIG_BANK_WAIT     6
  252 #define HE_REGS_TCMCONFIG_RW_WAIT       2
  253 #define HE_REGS_TCMCONFIG_TYPE          0
  254 
  255 #define HE_REGO_TSRB_BA         0x80744
  256 #define HE_REGO_TSRC_BA         0x80748
  257 #define HE_REGO_TMABR_BA        0x8074C
  258 #define HE_REGO_TPD_BA          0x80750
  259 #define HE_REGO_TSRD_BA         0x80758
  260 
  261 #define HE_REGO_TXCONFIG                0x80760
  262 #define HE_REGS_TXCONFIG_THRESH         22
  263 #define HE_REGM_TXCONFIG_UTMODE         (1 << 21)
  264 #define HE_REGS_TXCONFIG_VCI_MASK       17
  265 #define HE_REGS_TXCONFIG_LBFREE         0
  266 
  267 #define HE_REGO_TXAAL5_PROTO            0x80764
  268 
  269 #define HE_REGO_RCMCONFIG               0x80780
  270 #define HE_REGS_RCMCONFIG_BANK_WAIT     6
  271 #define HE_REGS_RCMCONFIG_RW_WAIT       2
  272 #define HE_REGS_RCMCONFIG_TYPE  0
  273 
  274 #define HE_REGO_RCMRSRB_BA              0x80784
  275 #define HE_REGO_RCMLBM_BA               0x80788
  276 #define HE_REGO_RCMABR_BA               0x8078C
  277 
  278 #define HE_REGO_RCCONFIG                0x807C0
  279 #define HE_REGS_RCCONFIG_UTDELAY        11
  280 #define HE_REGM_RCCONFIG_WRAP_MODE      (1 << 10)
  281 #define HE_REGM_RCCONFIG_UT_MODE        (1 << 9)
  282 #define HE_REGM_RCCONFIG_RXENB          (1 << 8)
  283 #define HE_REGS_RCCONFIG_VP             4
  284 #define HE_REGS_RCCONFIG_VC             0
  285 
  286 #define HE_REGO_MCC             0x807C4
  287 #define HE_REGO_OEC             0x807C8
  288 #define HE_REGO_DCC             0x807CC
  289 #define HE_REGO_CEC             0x807D0
  290 
  291 #define HE_REGO_HSP_BA          0x807F0
  292 
  293 #define HE_REGO_LBCONFIG        0x807F4
  294 
  295 #define HE_REGO_CON_DAT         0x807F8
  296 #define HE_REGO_CON_CTL         0x807FC
  297 #define HE_REGM_CON_MBOX        (2 << 30)
  298 #define HE_REGM_CON_TCM         (1 << 30)
  299 #define HE_REGM_CON_RCM         (0 << 30)
  300 #define HE_REGM_CON_WE          (1 << 29)
  301 #define HE_REGM_CON_STATUS      (1 << 28)
  302 #define HE_REGM_CON_DIS3        (1 << 22)
  303 #define HE_REGM_CON_DIS2        (1 << 21)
  304 #define HE_REGM_CON_DIS1        (1 << 20)
  305 #define HE_REGM_CON_DIS0        (1 << 19)
  306 #define HE_REGS_CON_DIS         19
  307 #define HE_REGS_CON_ADDR        0
  308 
  309 #define HE_REGO_SUNI            0x80800
  310 #define HE_REGO_SUNI_END        0x80C00
  311 
  312 #define HE_REGO_END             0x100000
  313 
  314 /*
  315  * MBOX registers
  316  */
  317 #define HE_REGO_CS_STPER0       0x000
  318 #define HE_REGO_CS_STPER(G)     (HE_REGO_CS_STPER0 + (G))
  319 #define HE_REGN_CS_STPER        32
  320 #define HE_REGO_CS_STTIM0       0x020
  321 #define HE_REGO_CS_STTIM(G)     (HE_REGO_CS_STTIM0 + (G))
  322 #define HE_REGO_CS_TGRLD0       0x040
  323 #define HE_REGO_CS_TGRLD(G)     (HE_REGO_CS_TGRLD0 + (G))
  324 #define HE_REGO_CS_ERTHR0       0x50
  325 #define HE_REGO_CS_ERTHR1       0x51
  326 #define HE_REGO_CS_ERTHR2       0x52
  327 #define HE_REGO_CS_ERTHR3       0x53
  328 #define HE_REGO_CS_ERTHR4       0x54
  329 #define HE_REGO_CS_ERCTL0       0x55
  330 #define HE_REGO_CS_ERCTL1       0x56
  331 #define HE_REGO_CS_ERCTL2       0x57
  332 #define HE_REGO_CS_ERSTAT0      0x58
  333 #define HE_REGO_CS_ERSTAT1      0x59
  334 #define HE_REGO_CS_RTCCT        0x60
  335 #define HE_REGO_CS_RTFWC        0x61
  336 #define HE_REGO_CS_RTFWR        0x62
  337 #define HE_REGO_CS_RTFTC        0x63
  338 #define HE_REGO_CS_RTATR        0x64
  339 #define HE_REGO_CS_TFBSET       0x70
  340 #define HE_REGO_CS_TFBADD       0x71
  341 #define HE_REGO_CS_TFBSUB       0x72
  342 #define HE_REGO_CS_WCRMAX       0x73
  343 #define HE_REGO_CS_WCRMIN       0x74
  344 #define HE_REGO_CS_WCRINC       0x75
  345 #define HE_REGO_CS_WCRDEC       0x76
  346 #define HE_REGO_CS_WCRCEIL      0x77
  347 #define HE_REGO_CS_BWDCNT       0x78
  348 #define HE_REGO_CS_OTPPER       0x80
  349 #define HE_REGO_CS_OTWPER       0x81
  350 #define HE_REGO_CS_OTTLIM       0x82
  351 #define HE_REGO_CS_OTTCNT       0x83
  352 #define HE_REGO_CS_HGRRT0       0x90
  353 #define HE_REGO_CS_HGRRT(G)     (HE_REGO_CS_HGRRT0 + (G))
  354 #define HE_REGO_CS_ORPTRS       0xA0
  355 #define HE_REGO_RCON_CLOSE      0x100
  356 #define HE_REGO_CS_END          0x101
  357 
  358 #define HE_REGT_CS_ERTHR {                                              \
  359         {                       /* 155 */                               \
  360           { 0x000800ea, 0x000400ea, 0x000200ea },       /* ERTHR0 */    \
  361           { 0x000C3388, 0x00063388, 0x00033388 },       /* ERTHR1 */    \
  362           { 0x00101018, 0x00081018, 0x00041018 },       /* ERTHR2 */    \
  363           { 0x00181dac, 0x000c1dac, 0x00061dac },       /* ERTHR3 */    \
  364           { 0x0028051a, 0x0014051a, 0x000a051a },       /* ERTHR4 */    \
  365         }, {                    /* 622 */                               \
  366           { 0x000800fa, 0x000400fa, 0x000200fa },       /* ERTHR0 */    \
  367           { 0x000c33cb, 0x000633cb, 0x000333cb },       /* ERTHR1 */    \
  368           { 0x0010101b, 0x0008101b, 0x0004101b },       /* ERTHR2 */    \
  369           { 0x00181dac, 0x000c1dac, 0x00061dac },       /* ERTHR3 */    \
  370           { 0x00280600, 0x00140600, 0x000a0600 },       /* ERTHR4 */    \
  371         }                                                               \
  372 }
  373 
  374 #define HE_REGT_CS_ERCTL {                                              \
  375         { 0x0235e4b1, 0x4701, 0x64b1 }, /* 155 */                       \
  376         { 0x023de8b3, 0x1801, 0x68b3 }  /* 622 */                       \
  377 }
  378 
  379 #define HE_REGT_CS_ERSTAT {                                             \
  380         { 0x1280, 0x64b1 },             /* 155 */                       \
  381         { 0x1280, 0x68b3 },             /* 622 */                       \
  382 }
  383 
  384 #define HE_REGT_CS_RTFWR {                                              \
  385         0xf424,                         /* 155 */                       \
  386         0x14585                         /* 622 */                       \
  387 }
  388 
  389 #define HE_REGT_CS_RTATR {                                              \
  390         0x4680,                         /* 155 */                       \
  391         0x4680                          /* 622 */                       \
  392 }
  393 
  394 #define HE_REGT_CS_BWALLOC {                                            \
  395         { 0x000563b7, 0x64b1, 0x5ab1, 0xe4b1, 0xdab1, 0x64b1 }, /* 155 */\
  396         { 0x00159ece, 0x68b3, 0x5eb3, 0xe8b3, 0xdeb3, 0x68b3 }, /* 622 */\
  397 }
  398 
  399 #define HE_REGT_CS_ORCF {                                               \
  400         { 0x6, 0x1e },                  /* 155 */                       \
  401         { 0x5, 0x14 }                   /* 622 */                       \
  402 }
  403 
  404 /* 
  405  * TSRs - NR is relative to the starting number of the block
  406  */
  407 #define HE_REGO_TSRA(BASE,CID,NR) ((BASE) + ((CID) << 3) + (NR))
  408 #define HE_REGO_TSRB(BASE,CID,NR) ((BASE) + ((CID) << 2) + (NR))
  409 #define HE_REGO_TSRC(BASE,CID,NR) ((BASE) + ((CID) << 1) + (NR))
  410 #define HE_REGO_TSRD(BASE,CID)    ((BASE) + (CID))
  411 
  412 #define HE_REGM_TSR0_CONN_STATE         (7 << 28)
  413 #define HE_REGS_TSR0_CONN_STATE         28
  414 #define HE_REGM_TSR0_USE_WMIN           (1 << 23)
  415 #define HE_REGM_TSR0_GROUP              (7 << 18)
  416 #define HE_REGS_TSR0_GROUP              18
  417 #define HE_REGM_TSR0_TRAFFIC            (3 << 16)
  418 #define HE_REGS_TSR0_TRAFFIC            16
  419 #define HE_REGM_TSR0_TRAFFIC_CBR        0
  420 #define HE_REGM_TSR0_TRAFFIC_UBR        1
  421 #define HE_REGM_TSR0_TRAFFIC_ABR        2
  422 #define HE_REGM_TSR0_PROT               (1 << 15)
  423 #define HE_REGM_TSR0_AAL                (3 << 12)
  424 #define HE_REGS_TSR0_AAL                12
  425 #define HE_REGM_TSR0_AAL_5              0
  426 #define HE_REGM_TSR0_AAL_0              1
  427 #define HE_REGM_TSR0_AAL_0T             2
  428 #define HE_REGM_TSR0_HALT_ER            (1 << 11)
  429 #define HE_REGM_TSR0_MARK_CI            (1 << 10)
  430 #define HE_REGM_TSR0_MARK_ER            (1 << 9)
  431 #define HE_REGM_TSR0_UPDATE_GER         (1 << 8)
  432 #define HE_REGM_TSR0_RC                 0xff
  433 
  434 #define HE_REGM_TSR1_PCR                (0x7fff << 16)
  435 #define HE_REGS_TSR1_PCR                16
  436 #define HE_REGM_TSR1_MCR                (0x7fff << 0)
  437 #define HE_REGS_TSR1_MCR                0
  438 
  439 #define HE_REGM_TSR2_ACR                (0x7fff << 16)
  440 #define HE_REGS_TSR2_ACR                16
  441 
  442 #define HE_REGM_TSR3_NRM                (0xff << 24)
  443 #define HE_REGS_TSR3_NRM                24
  444 #define HE_REGM_TSR3_CRM                (0xff << 0)
  445 #define HE_REGS_TSR3_CRM                0
  446 
  447 #define HE_REGM_TSR4_FLUSH              (1 << 31)
  448 #define HE_REGM_TSR4_SESS_END           (1 << 30)
  449 #define HE_REGM_TSR4_OAM_CRC10          (1 << 28)
  450 #define HE_REGM_TSR4_NULL_CRC10         (1 << 27)
  451 #define HE_REGM_TSR4_PROT               (1 << 26)
  452 #define HE_REGM_TSR4_AAL                (3 << 24)
  453 #define HE_REGS_TSR4_AAL                24
  454 #define HE_REGM_TSR4_AAL_5              0
  455 #define HE_REGM_TSR4_AAL_0              1
  456 #define HE_REGM_TSR4_AAL_0T             2
  457 
  458 #define HE_REGM_TSR9_INIT               0x00100000
  459 
  460 #define HE_REGM_TSR11_ICR               (0x7fff << 16)
  461 #define HE_REGS_TSR11_ICR               16
  462 #define HE_REGM_TSR11_TRM               (0x7 << 13)
  463 #define HE_REGS_TSR11_TRM               13
  464 #define HE_REGM_TSR11_NRM               (0x7 << 10)
  465 #define HE_REGS_TSR11_NRM               10
  466 #define HE_REGM_TSR11_ADTF              0x3ff
  467 #define HE_REGS_TSR11_ADTF              0
  468 
  469 #define HE_REGM_TSR13_RDF               (0xf << 23)
  470 #define HE_REGS_TSR13_RDF               23
  471 #define HE_REGM_TSR13_RIF               (0xf << 19)
  472 #define HE_REGS_TSR13_RIF               19
  473 #define HE_REGM_TSR13_CDF               (0x7 << 16)
  474 #define HE_REGS_TSR13_CDF               16
  475 #define HE_REGM_TSR13_CRM               0xffff
  476 #define HE_REGS_TSR13_CRM               0
  477 
  478 #define HE_REGM_TSR14_CBR_DELETE        (1 << 31)
  479 #define HE_REGM_TSR14_ABR_CLOSE         (1 << 16)
  480 
  481 /*
  482  * RSRs
  483  */
  484 #define HE_REGO_RSRA(BASE,CID,NR) ((BASE) + ((CID) << 3) + (NR))
  485 #define HE_REGO_RSRB(BASE,CID,NR) ((BASE) + ((CID) << 1) + (NR))
  486 
  487 #define HE_REGM_RSR0_PTI7               (1 << 15)
  488 #define HE_REGM_RSR0_RM                 (1 << 14)
  489 #define HE_REGM_RSR0_F5OAM              (1 << 13)
  490 #define HE_REGM_RSR0_STARTPDU           (1 << 10)
  491 #define HE_REGM_RSR0_OPEN               (1 << 6)
  492 #define HE_REGM_RSR0_PPD                (1 << 5)
  493 #define HE_REGM_RSR0_EPD                (1 << 4)
  494 #define HE_REGM_RSR0_TCPCS              (1 << 3)
  495 #define HE_REGM_RSR0_AAL                0x7
  496 #define HE_REGM_RSR0_AAL_5              0x0
  497 #define HE_REGM_RSR0_AAL_0              0x1
  498 #define HE_REGM_RSR0_AAL_0T             0x2
  499 #define HE_REGM_RSR0_AAL_RAW            0x3
  500 #define HE_REGM_RSR0_AAL_RAWCRC10       0x4
  501 
  502 #define HE_REGM_RSR1_AQI                (1 << 20)
  503 #define HE_REGM_RSR1_RBPL_ONLY          (1 << 19)
  504 #define HE_REGM_RSR1_GROUP              (7 << 16)
  505 #define HE_REGS_RSR1_GROUP              16
  506 
  507 #define HE_REGM_RSR4_AQI                (1 << 30)
  508 #define HE_REGM_RSR4_GROUP              (7 << 27)
  509 #define HE_REGS_RSR4_GROUP              27
  510 #define HE_REGM_RSR4_RBPL_ONLY          (1 << 26)
  511 
  512 /*
  513  * Relative to RCMABR_BA
  514  */
  515 #define HE_REGO_CM_GQTBL        0x000
  516 #define HE_REGL_CM_GQTBL        0x100
  517 #define HE_REGO_CM_RGTBL        0x100
  518 #define HE_REGL_CM_RGTBL        0x100
  519 #define HE_REGO_CM_TNRMTBL      0x200
  520 #define HE_REGL_CM_TNRMTBL      0x100
  521 #define HE_REGO_CM_ORCF         0x300
  522 #define HE_REGL_CM_ORCF         0x100
  523 #define HE_REGO_CM_RTGTBL       0x400
  524 #define HE_REGL_CM_RTGTBL       0x200
  525 #define HE_REGO_CM_IRCF         0x600
  526 #define HE_REGL_CM_IRCF         0x200
  527 
  528 /*
  529  * Interrupt Status
  530  */
  531 #define HE_REGM_ITYPE           0xf8
  532 #define HE_REGM_IGROUP          0x07
  533 #define HE_REGM_ITYPE_TBRQ      (0x0 << 3)
  534 #define HE_REGM_ITYPE_TPD       (0x1 << 3)
  535 #define HE_REGM_ITYPE_RBPS      (0x2 << 3)
  536 #define HE_REGM_ITYPE_RBPL      (0x3 << 3)
  537 #define HE_REGM_ITYPE_RBRQ      (0x4 << 3)
  538 #define HE_REGM_ITYPE_RBRQT     (0x5 << 3)
  539 #define HE_REGM_ITYPE_PHYS      (0x6 << 3)
  540 #define HE_REGM_ITYPE_UNKNOWN   0xf8
  541 #define HE_REGM_ITYPE_ERR       0x80
  542 #define HE_REGM_ITYPE_PERR      0x81
  543 #define HE_REGM_ITYPE_ABORT     0x82
  544 #define HE_REGM_ITYPE_INVALID   0xf8
  545 
  546 /*
  547  * Serial EEPROM
  548  */
  549 #define HE_EEPROM_PROD_ID       0x08
  550 #define HE_EEPROM_PROD_ID_LEN   30
  551 #define HE_EEPROM_REV           0x26
  552 #define HE_EEPROM_REV_LEN       4
  553 #define HE_EEPROM_M_SN          0x3A
  554 #define HE_EEPROM_MEDIA         0x3E
  555 #define HE_EEPROM_MAC           0x42
  556 
  557 #define HE_MEDIA_UTP155 0x06
  558 #define HE_MEDIA_MMF155 0x26
  559 #define HE_MEDIA_MMF622 0x27
  560 #define HE_MEDIA_SMF155 0x46
  561 #define HE_MEDIA_SMF622 0x47
  562 
  563 #define HE_622_CLOCK            66667000
  564 #define HE_155_CLOCK            50000000
  565 
  566 /*
  567  * Statistics
  568  */
  569 struct fatm_statshe {
  570 };
  571 
  572 /*
  573  * Queue entries
  574  */
  575 /* Receive Buffer Pool Queue entry */
  576 struct he_rbpen {
  577         uint32_t        phys;           /* physical address */
  578         uint32_t        handle;         /* handle or virtual address */
  579 };
  580 /* Receive Buffer Return Queue entry */
  581 struct he_rbrqen {
  582         uint32_t        addr;           /* handle and flags */
  583         uint32_t        len;            /* length and CID */
  584 };
  585 #define HE_REGM_RBRQ_ADDR               0xFFFFFFC0
  586 #define HE_REGS_RBRQ_ADDR               6
  587 #define HE_REGM_RBRQ_FLAGS              0x0000003F
  588 #define HE_REGM_RBRQ_HBUF_ERROR         (1 << 0)
  589 #define HE_REGM_RBRQ_CON_CLOSED         (1 << 1)
  590 #define HE_REGM_RBRQ_AAL5_PROT          (1 << 2)
  591 #define HE_REGM_RBRQ_END_PDU            (1 << 3)
  592 #define HE_REGM_RBRQ_LEN_ERROR          (1 << 4)
  593 #define HE_REGM_RBRQ_CRC_ERROR          (1 << 5)
  594 #define HE_REGM_RBRQ_CID                (0x1fff << 16)
  595 #define HE_REGS_RBRQ_CID                16
  596 #define HE_REGM_RBRQ_LEN                0xffff
  597 
  598 /* Transmit Packet Descriptor Ready Queue entry */
  599 struct he_tpdrqen {
  600         uint32_t        tpd;            /* physical address */
  601         uint32_t        cid;            /* connection id */
  602 };
  603 /* Transmit buffer return queue */
  604 struct he_tbrqen {
  605         uint32_t        addr;           /* handle and flags */
  606 };
  607 #define HE_REGM_TBRQ_ADDR       0xffffffc0
  608 #define HE_REGM_TBRQ_FLAGS      0x0000000a
  609 #define HE_REGM_TBRQ_EOS        0x00000008
  610 #define HE_REGM_TBRQ_MULT       0x00000002
  611 
  612 struct he_tpd {
  613         uint32_t        addr;           /* handle or virtual address and flags */
  614         uint32_t        res;            /* reserved */
  615         struct {
  616             uint32_t    addr;           /* buffer address */
  617             uint32_t    len;            /* buffer length and flags */
  618         }               bufs[3];
  619 };
  620 #define HE_REGM_TPD_ADDR        0xffffffC0
  621 #define HE_REGS_TPD_ADDR        6
  622 #define HE_REGM_TPD_INTR        0x0001
  623 #define HE_REGM_TPD_CLP         0x0002
  624 #define HE_REGM_TPD_EOS         0x0004
  625 #define HE_REGM_TPD_PTI         0x0038
  626 #define HE_REGS_TPD_PTI         3
  627 #define HE_REGM_TPD_LST         0x80000000
  628 
  629 /* 
  630  * The HOST STATUS PAGE
  631  */
  632 struct he_hsp {
  633         struct {
  634                 uint32_t        tbrq_tail;
  635                 uint32_t        res1[15];
  636                 uint32_t        rbrq_tail;
  637                 uint32_t        res2[15];
  638         } group[8];
  639 };
  640 
  641 #define HE_MAX_PDU      (65535)

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