Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/dev/hdmi/dwc_hdmireg.h
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1 /*- 2 * Copyright (c) 2015 Oleksandr Tymoshenko <gonzo@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29 #ifndef __DWC_HDMIREG_H__ 30 #define __DWC_HDMIREG_H__ 31 #define HDMI_DESIGN_ID 0x0000 32 #define HDMI_REVISION_ID 0x0001 33 #define HDMI_PRODUCT_ID0 0x0002 34 #define HDMI_PRODUCT_ID1 0x0003 35 36 /* Interrupt Registers */ 37 #define HDMI_IH_FC_STAT0 0x0100 38 #define HDMI_IH_FC_STAT1 0x0101 39 #define HDMI_IH_FC_STAT2 0x0102 40 #define HDMI_IH_AS_STAT0 0x0103 41 #define HDMI_IH_PHY_STAT0 0x0104 42 #define HDMI_IH_PHY_STAT0_HPD (1 << 0) 43 #define HDMI_IH_I2CM_STAT0 0x0105 44 #define HDMI_IH_CEC_STAT0 0x0106 45 #define HDMI_IH_VP_STAT0 0x0107 46 #define HDMI_IH_I2CMPHY_STAT0 0x0108 47 #define HDMI_IH_I2CMPHY_STAT0_DONE (1 << 1) 48 #define HDMI_IH_I2CMPHY_STAT0_ERROR (1 << 0) 49 #define HDMI_IH_AHBDMAAUD_STAT0 0x0109 50 51 #define HDMI_IH_MUTE_FC_STAT0 0x0180 52 #define HDMI_IH_MUTE_FC_STAT1 0x0181 53 #define HDMI_IH_MUTE_FC_STAT2 0x0182 54 #define HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK (0x3) 55 #define HDMI_IH_MUTE_AS_STAT0 0x0183 56 #define HDMI_IH_MUTE_PHY_STAT0 0x0184 57 #define HDMI_IH_MUTE_I2CM_STAT0 0x0185 58 #define HDMI_IH_MUTE_CEC_STAT0 0x0186 59 #define HDMI_IH_MUTE_VP_STAT0 0x0187 60 #define HDMI_IH_MUTE_I2CMPHY_STAT0 0x0188 61 #define HDMI_IH_MUTE_AHBDMAAUD_STAT0 0x0189 62 #define HDMI_IH_MUTE 0x01FF 63 #define HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT (1<<1) 64 #define HDMI_IH_MUTE_MUTE_ALL_INTERRUPT (1<<0) 65 66 /* Video Sample Registers */ 67 #define HDMI_TX_INVID0 0x0200 68 #define HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_MASK 0x80 69 #define HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_ENABLE 0x80 70 #define HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE 0x00 71 #define HDMI_TX_INVID0_VIDEO_MAPPING_MASK 0x1F 72 #define HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET 0 73 #define HDMI_TX_INSTUFFING 0x0201 74 #define HDMI_TX_INSTUFFING_BDBDATA_STUFFING_MASK 0x4 75 #define HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE 0x4 76 #define HDMI_TX_INSTUFFING_BDBDATA_STUFFING_DISABLE 0x0 77 #define HDMI_TX_INSTUFFING_RCRDATA_STUFFING_MASK 0x2 78 #define HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE 0x2 79 #define HDMI_TX_INSTUFFING_RCRDATA_STUFFING_DISABLE 0x0 80 #define HDMI_TX_INSTUFFING_GYDATA_STUFFING_MASK 0x1 81 #define HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE 0x1 82 #define HDMI_TX_INSTUFFING_GYDATA_STUFFING_DISABLE 0x0 83 #define HDMI_TX_GYDATA0 0x0202 84 #define HDMI_TX_GYDATA1 0x0203 85 #define HDMI_TX_RCRDATA0 0x0204 86 #define HDMI_TX_RCRDATA1 0x0205 87 #define HDMI_TX_BCBDATA0 0x0206 88 #define HDMI_TX_BCBDATA1 0x0207 89 90 /* Video Packetizer Registers */ 91 #define HDMI_VP_STATUS 0x0800 92 #define HDMI_VP_PR_CD 0x0801 93 #define HDMI_VP_PR_CD_COLOR_DEPTH_MASK 0xF0 94 #define HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET 4 95 #define HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK 0x0F 96 #define HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET 0 97 98 #define HDMI_VP_STUFF 0x0802 99 #define HDMI_VP_STUFF_IDEFAULT_PHASE_MASK 0x20 100 #define HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET 5 101 #define HDMI_VP_STUFF_IFIX_PP_TO_LAST_MASK 0x10 102 #define HDMI_VP_STUFF_IFIX_PP_TO_LAST_OFFSET 4 103 #define HDMI_VP_STUFF_ICX_GOTO_P0_ST_MASK 0x8 104 #define HDMI_VP_STUFF_ICX_GOTO_P0_ST_OFFSET 3 105 #define HDMI_VP_STUFF_YCC422_STUFFING_MASK 0x4 106 #define HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE 0x4 107 #define HDMI_VP_STUFF_YCC422_STUFFING_DIRECT_MODE 0x0 108 #define HDMI_VP_STUFF_PP_STUFFING_MASK 0x2 109 #define HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE 0x2 110 #define HDMI_VP_STUFF_PP_STUFFING_DIRECT_MODE 0x0 111 #define HDMI_VP_STUFF_PR_STUFFING_MASK 0x1 112 #define HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE 0x1 113 #define HDMI_VP_STUFF_PR_STUFFING_DIRECT_MODE 0x0 114 #define HDMI_VP_REMAP 0x0803 115 #define HDMI_VP_REMAP_MASK 0x3 116 #define HDMI_VP_REMAP_YCC422_24BIT 0x2 117 #define HDMI_VP_REMAP_YCC422_20BIT 0x1 118 #define HDMI_VP_REMAP_YCC422_16BIT 0x0 119 #define HDMI_VP_CONF 0x0804 120 #define HDMI_VP_CONF_BYPASS_EN_MASK 0x40 121 #define HDMI_VP_CONF_BYPASS_EN_ENABLE 0x40 122 #define HDMI_VP_CONF_BYPASS_EN_DISABLE 0x00 123 #define HDMI_VP_CONF_PP_EN_ENMASK 0x20 124 #define HDMI_VP_CONF_PP_EN_ENABLE 0x20 125 #define HDMI_VP_CONF_PP_EN_DISABLE 0x00 126 #define HDMI_VP_CONF_PR_EN_MASK 0x10 127 #define HDMI_VP_CONF_PR_EN_ENABLE 0x10 128 #define HDMI_VP_CONF_PR_EN_DISABLE 0x00 129 #define HDMI_VP_CONF_YCC422_EN_MASK 0x8 130 #define HDMI_VP_CONF_YCC422_EN_ENABLE 0x8 131 #define HDMI_VP_CONF_YCC422_EN_DISABLE 0x0 132 #define HDMI_VP_CONF_BYPASS_SELECT_MASK 0x4 133 #define HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER 0x4 134 #define HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER 0x0 135 #define HDMI_VP_CONF_OUTPUT_SELECTOR_MASK 0x3 136 #define HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS 0x3 137 #define HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422 0x1 138 #define HDMI_VP_CONF_OUTPUT_SELECTOR_PP 0x0 139 #define HDMI_VP_STAT 0x0805 140 #define HDMI_VP_INT 0x0806 141 #define HDMI_VP_MASK 0x0807 142 #define HDMI_VP_POL 0x0808 143 144 /* Frame Composer Registers */ 145 #define HDMI_FC_INVIDCONF 0x1000 146 #define HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH 0x40 147 #define HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW 0x00 148 #define HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH 0x20 149 #define HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW 0x00 150 #define HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH 0x10 151 #define HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW 0x00 152 #define HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE 0x8 153 #define HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE 0x0 154 #define HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH 0x2 155 #define HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW 0x0 156 #define HDMI_FC_INVIDCONF_IN_I_P_INTERLACED 0x1 157 #define HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE 0x0 158 #define HDMI_FC_INHACTV0 0x1001 159 #define HDMI_FC_INHACTV1 0x1002 160 #define HDMI_FC_INHBLANK0 0x1003 161 #define HDMI_FC_INHBLANK1 0x1004 162 #define HDMI_FC_INVACTV0 0x1005 163 #define HDMI_FC_INVACTV1 0x1006 164 #define HDMI_FC_INVBLANK 0x1007 165 #define HDMI_FC_HSYNCINDELAY0 0x1008 166 #define HDMI_FC_HSYNCINDELAY1 0x1009 167 #define HDMI_FC_HSYNCINWIDTH0 0x100A 168 #define HDMI_FC_HSYNCINWIDTH1 0x100B 169 #define HDMI_FC_VSYNCINDELAY 0x100C 170 #define HDMI_FC_VSYNCINWIDTH 0x100D 171 #define HDMI_FC_INFREQ0 0x100E 172 #define HDMI_FC_INFREQ1 0x100F 173 #define HDMI_FC_INFREQ2 0x1010 174 #define HDMI_FC_CTRLDUR 0x1011 175 #define HDMI_FC_EXCTRLDUR 0x1012 176 #define HDMI_FC_EXCTRLSPAC 0x1013 177 #define HDMI_FC_CH0PREAM 0x1014 178 #define HDMI_FC_CH1PREAM 0x1015 179 #define HDMI_FC_CH2PREAM 0x1016 180 #define HDMI_FC_AVICONF3 0x1017 181 #define HDMI_FC_GCP 0x1018 182 #define HDMI_FC_AVICONF0 0x1019 183 #define HDMI_FC_AVICONF1 0x101A 184 #define HDMI_FC_AVICONF2 0x101B 185 #define HDMI_FC_AVIVID 0x101C 186 #define HDMI_FC_AVIETB0 0x101D 187 #define HDMI_FC_AVIETB1 0x101E 188 #define HDMI_FC_AVISBB0 0x101F 189 #define HDMI_FC_AVISBB1 0x1020 190 #define HDMI_FC_AVIELB0 0x1021 191 #define HDMI_FC_AVIELB1 0x1022 192 #define HDMI_FC_AVISRB0 0x1023 193 #define HDMI_FC_AVISRB1 0x1024 194 #define HDMI_FC_AUDICONF0 0x1025 195 #define HDMI_FC_AUDICONF1 0x1026 196 #define HDMI_FC_AUDICONF2 0x1027 197 #define HDMI_FC_AUDICONF3 0x1028 198 #define HDMI_FC_VSDIEEEID0 0x1029 199 #define HDMI_FC_VSDSIZE 0x102A 200 #define HDMI_FC_VSDIEEEID1 0x1030 201 #define HDMI_FC_VSDIEEEID2 0x1031 202 #define HDMI_FC_VSDPAYLOAD0 0x1032 203 #define HDMI_FC_VSDPAYLOAD1 0x1033 204 #define HDMI_FC_VSDPAYLOAD2 0x1034 205 #define HDMI_FC_VSDPAYLOAD3 0x1035 206 #define HDMI_FC_VSDPAYLOAD4 0x1036 207 #define HDMI_FC_VSDPAYLOAD5 0x1037 208 #define HDMI_FC_VSDPAYLOAD6 0x1038 209 #define HDMI_FC_VSDPAYLOAD7 0x1039 210 #define HDMI_FC_VSDPAYLOAD8 0x103A 211 #define HDMI_FC_VSDPAYLOAD9 0x103B 212 #define HDMI_FC_VSDPAYLOAD10 0x103C 213 #define HDMI_FC_VSDPAYLOAD11 0x103D 214 #define HDMI_FC_VSDPAYLOAD12 0x103E 215 #define HDMI_FC_VSDPAYLOAD13 0x103F 216 #define HDMI_FC_VSDPAYLOAD14 0x1040 217 #define HDMI_FC_VSDPAYLOAD15 0x1041 218 #define HDMI_FC_VSDPAYLOAD16 0x1042 219 #define HDMI_FC_VSDPAYLOAD17 0x1043 220 #define HDMI_FC_VSDPAYLOAD18 0x1044 221 #define HDMI_FC_VSDPAYLOAD19 0x1045 222 #define HDMI_FC_VSDPAYLOAD20 0x1046 223 #define HDMI_FC_VSDPAYLOAD21 0x1047 224 #define HDMI_FC_VSDPAYLOAD22 0x1048 225 #define HDMI_FC_VSDPAYLOAD23 0x1049 226 #define HDMI_FC_SPDVENDORNAME0 0x104A 227 #define HDMI_FC_SPDVENDORNAME1 0x104B 228 #define HDMI_FC_SPDVENDORNAME2 0x104C 229 #define HDMI_FC_SPDVENDORNAME3 0x104D 230 #define HDMI_FC_SPDVENDORNAME4 0x104E 231 #define HDMI_FC_SPDVENDORNAME5 0x104F 232 #define HDMI_FC_SPDVENDORNAME6 0x1050 233 #define HDMI_FC_SPDVENDORNAME7 0x1051 234 #define HDMI_FC_SDPPRODUCTNAME0 0x1052 235 #define HDMI_FC_SDPPRODUCTNAME1 0x1053 236 #define HDMI_FC_SDPPRODUCTNAME2 0x1054 237 #define HDMI_FC_SDPPRODUCTNAME3 0x1055 238 #define HDMI_FC_SDPPRODUCTNAME4 0x1056 239 #define HDMI_FC_SDPPRODUCTNAME5 0x1057 240 #define HDMI_FC_SDPPRODUCTNAME6 0x1058 241 #define HDMI_FC_SDPPRODUCTNAME7 0x1059 242 #define HDMI_FC_SDPPRODUCTNAME8 0x105A 243 #define HDMI_FC_SDPPRODUCTNAME9 0x105B 244 #define HDMI_FC_SDPPRODUCTNAME10 0x105C 245 #define HDMI_FC_SDPPRODUCTNAME11 0x105D 246 #define HDMI_FC_SDPPRODUCTNAME12 0x105E 247 #define HDMI_FC_SDPPRODUCTNAME13 0x105F 248 #define HDMI_FC_SDPPRODUCTNAME14 0x1060 249 #define HDMI_FC_SPDPRODUCTNAME15 0x1061 250 #define HDMI_FC_SPDDEVICEINF 0x1062 251 #define HDMI_FC_AUDSCONF 0x1063 252 #define HDMI_FC_AUDSSTAT 0x1064 253 #define HDMI_FC_AUDSV 0x1065 254 #define HDMI_FC_DATACH0FILL 0x1070 255 #define HDMI_FC_DATACH1FILL 0x1071 256 #define HDMI_FC_DATACH2FILL 0x1072 257 #define HDMI_FC_CTRLQHIGH 0x1073 258 #define HDMI_FC_CTRLQLOW 0x1074 259 #define HDMI_FC_ACP0 0x1075 260 #define HDMI_FC_ACP28 0x1076 261 #define HDMI_FC_ACP27 0x1077 262 #define HDMI_FC_ACP26 0x1078 263 #define HDMI_FC_ACP25 0x1079 264 #define HDMI_FC_ACP24 0x107A 265 #define HDMI_FC_ACP23 0x107B 266 #define HDMI_FC_ACP22 0x107C 267 #define HDMI_FC_ACP21 0x107D 268 #define HDMI_FC_ACP20 0x107E 269 #define HDMI_FC_ACP19 0x107F 270 #define HDMI_FC_ACP18 0x1080 271 #define HDMI_FC_ACP17 0x1081 272 #define HDMI_FC_ACP16 0x1082 273 #define HDMI_FC_ACP15 0x1083 274 #define HDMI_FC_ACP14 0x1084 275 #define HDMI_FC_ACP13 0x1085 276 #define HDMI_FC_ACP12 0x1086 277 #define HDMI_FC_ACP11 0x1087 278 #define HDMI_FC_ACP10 0x1088 279 #define HDMI_FC_ACP9 0x1089 280 #define HDMI_FC_ACP8 0x108A 281 #define HDMI_FC_ACP7 0x108B 282 #define HDMI_FC_ACP6 0x108C 283 #define HDMI_FC_ACP5 0x108D 284 #define HDMI_FC_ACP4 0x108E 285 #define HDMI_FC_ACP3 0x108F 286 #define HDMI_FC_ACP2 0x1090 287 #define HDMI_FC_ACP1 0x1091 288 #define HDMI_FC_ISCR1_0 0x1092 289 #define HDMI_FC_ISCR1_16 0x1093 290 #define HDMI_FC_ISCR1_15 0x1094 291 #define HDMI_FC_ISCR1_14 0x1095 292 #define HDMI_FC_ISCR1_13 0x1096 293 #define HDMI_FC_ISCR1_12 0x1097 294 #define HDMI_FC_ISCR1_11 0x1098 295 #define HDMI_FC_ISCR1_10 0x1099 296 #define HDMI_FC_ISCR1_9 0x109A 297 #define HDMI_FC_ISCR1_8 0x109B 298 #define HDMI_FC_ISCR1_7 0x109C 299 #define HDMI_FC_ISCR1_6 0x109D 300 #define HDMI_FC_ISCR1_5 0x109E 301 #define HDMI_FC_ISCR1_4 0x109F 302 #define HDMI_FC_ISCR1_3 0x10A0 303 #define HDMI_FC_ISCR1_2 0x10A1 304 #define HDMI_FC_ISCR1_1 0x10A2 305 #define HDMI_FC_ISCR2_15 0x10A3 306 #define HDMI_FC_ISCR2_14 0x10A4 307 #define HDMI_FC_ISCR2_13 0x10A5 308 #define HDMI_FC_ISCR2_12 0x10A6 309 #define HDMI_FC_ISCR2_11 0x10A7 310 #define HDMI_FC_ISCR2_10 0x10A8 311 #define HDMI_FC_ISCR2_9 0x10A9 312 #define HDMI_FC_ISCR2_8 0x10AA 313 #define HDMI_FC_ISCR2_7 0x10AB 314 #define HDMI_FC_ISCR2_6 0x10AC 315 #define HDMI_FC_ISCR2_5 0x10AD 316 #define HDMI_FC_ISCR2_4 0x10AE 317 #define HDMI_FC_ISCR2_3 0x10AF 318 #define HDMI_FC_ISCR2_2 0x10B0 319 #define HDMI_FC_ISCR2_1 0x10B1 320 #define HDMI_FC_ISCR2_0 0x10B2 321 #define HDMI_FC_DATAUTO0 0x10B3 322 #define HDMI_FC_DATAUTO1 0x10B4 323 #define HDMI_FC_DATAUTO2 0x10B5 324 #define HDMI_FC_DATMAN 0x10B6 325 #define HDMI_FC_DATAUTO3 0x10B7 326 #define HDMI_FC_RDRB0 0x10B8 327 #define HDMI_FC_RDRB1 0x10B9 328 #define HDMI_FC_RDRB2 0x10BA 329 #define HDMI_FC_RDRB3 0x10BB 330 #define HDMI_FC_RDRB4 0x10BC 331 #define HDMI_FC_RDRB5 0x10BD 332 #define HDMI_FC_RDRB6 0x10BE 333 #define HDMI_FC_RDRB7 0x10BF 334 #define HDMI_FC_STAT0 0x10D0 335 #define HDMI_FC_INT0 0x10D1 336 #define HDMI_FC_MASK0 0x10D2 337 #define HDMI_FC_POL0 0x10D3 338 #define HDMI_FC_STAT1 0x10D4 339 #define HDMI_FC_INT1 0x10D5 340 #define HDMI_FC_MASK1 0x10D6 341 #define HDMI_FC_POL1 0x10D7 342 #define HDMI_FC_STAT2 0x10D8 343 #define HDMI_FC_INT2 0x10D9 344 #define HDMI_FC_MASK2 0x10DA 345 #define HDMI_FC_MASK2_LOW_PRI (1 << 1) 346 #define HDMI_FC_MASK2_HIGH_PRI (1 << 0) 347 #define HDMI_FC_POL2 0x10DB 348 #define HDMI_FC_PRCONF 0x10E0 349 350 #define HDMI_FC_GMD_STAT 0x1100 351 #define HDMI_FC_GMD_EN 0x1101 352 #define HDMI_FC_GMD_UP 0x1102 353 #define HDMI_FC_GMD_CONF 0x1103 354 #define HDMI_FC_GMD_HB 0x1104 355 #define HDMI_FC_GMD_PB0 0x1105 356 #define HDMI_FC_GMD_PB1 0x1106 357 #define HDMI_FC_GMD_PB2 0x1107 358 #define HDMI_FC_GMD_PB3 0x1108 359 #define HDMI_FC_GMD_PB4 0x1109 360 #define HDMI_FC_GMD_PB5 0x110A 361 #define HDMI_FC_GMD_PB6 0x110B 362 #define HDMI_FC_GMD_PB7 0x110C 363 #define HDMI_FC_GMD_PB8 0x110D 364 #define HDMI_FC_GMD_PB9 0x110E 365 #define HDMI_FC_GMD_PB10 0x110F 366 #define HDMI_FC_GMD_PB11 0x1110 367 #define HDMI_FC_GMD_PB12 0x1111 368 #define HDMI_FC_GMD_PB13 0x1112 369 #define HDMI_FC_GMD_PB14 0x1113 370 #define HDMI_FC_GMD_PB15 0x1114 371 #define HDMI_FC_GMD_PB16 0x1115 372 #define HDMI_FC_GMD_PB17 0x1116 373 #define HDMI_FC_GMD_PB18 0x1117 374 #define HDMI_FC_GMD_PB19 0x1118 375 #define HDMI_FC_GMD_PB20 0x1119 376 #define HDMI_FC_GMD_PB21 0x111A 377 #define HDMI_FC_GMD_PB22 0x111B 378 #define HDMI_FC_GMD_PB23 0x111C 379 #define HDMI_FC_GMD_PB24 0x111D 380 #define HDMI_FC_GMD_PB25 0x111E 381 #define HDMI_FC_GMD_PB26 0x111F 382 #define HDMI_FC_GMD_PB27 0x1120 383 384 #define HDMI_FC_DBGFORCE 0x1200 385 #define HDMI_FC_DBGAUD0CH0 0x1201 386 #define HDMI_FC_DBGAUD1CH0 0x1202 387 #define HDMI_FC_DBGAUD2CH0 0x1203 388 #define HDMI_FC_DBGAUD0CH1 0x1204 389 #define HDMI_FC_DBGAUD1CH1 0x1205 390 #define HDMI_FC_DBGAUD2CH1 0x1206 391 #define HDMI_FC_DBGAUD0CH2 0x1207 392 #define HDMI_FC_DBGAUD1CH2 0x1208 393 #define HDMI_FC_DBGAUD2CH2 0x1209 394 #define HDMI_FC_DBGAUD0CH3 0x120A 395 #define HDMI_FC_DBGAUD1CH3 0x120B 396 #define HDMI_FC_DBGAUD2CH3 0x120C 397 #define HDMI_FC_DBGAUD0CH4 0x120D 398 #define HDMI_FC_DBGAUD1CH4 0x120E 399 #define HDMI_FC_DBGAUD2CH4 0x120F 400 #define HDMI_FC_DBGAUD0CH5 0x1210 401 #define HDMI_FC_DBGAUD1CH5 0x1211 402 #define HDMI_FC_DBGAUD2CH5 0x1212 403 #define HDMI_FC_DBGAUD0CH6 0x1213 404 #define HDMI_FC_DBGAUD1CH6 0x1214 405 #define HDMI_FC_DBGAUD2CH6 0x1215 406 #define HDMI_FC_DBGAUD0CH7 0x1216 407 #define HDMI_FC_DBGAUD1CH7 0x1217 408 #define HDMI_FC_DBGAUD2CH7 0x1218 409 #define HDMI_FC_DBGTMDS0 0x1219 410 #define HDMI_FC_DBGTMDS1 0x121A 411 #define HDMI_FC_DBGTMDS2 0x121B 412 413 #define HDMI_PHY_CONF0 0x3000 414 #define HDMI_PHY_CONF0_PDZ_MASK 0x80 415 #define HDMI_PHY_CONF0_PDZ_OFFSET 7 416 #define HDMI_PHY_CONF0_ENTMDS_MASK 0x40 417 #define HDMI_PHY_CONF0_ENTMDS_OFFSET 6 418 #define HDMI_PHY_CONF0_SPARECTRL 0x20 419 #define HDMI_PHY_CONF0_GEN2_PDDQ_MASK 0x10 420 #define HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET 4 421 #define HDMI_PHY_CONF0_GEN2_TXPWRON_MASK 0x8 422 #define HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET 3 423 #define HDMI_PHY_CONF0_GEN2_ENHPDRXSENSE_MASK 0x4 424 #define HDMI_PHY_CONF0_GEN2_ENHPDRXSENSE_OFFSET 2 425 #define HDMI_PHY_CONF0_SELDATAENPOL_MASK 0x2 426 #define HDMI_PHY_CONF0_SELDATAENPOL_OFFSET 1 427 #define HDMI_PHY_CONF0_SELDIPIF_MASK 0x1 428 #define HDMI_PHY_CONF0_SELDIPIF_OFFSET 0 429 #define HDMI_PHY_TST0 0x3001 430 #define HDMI_PHY_TST0_TSTCLR_MASK 0x20 431 #define HDMI_PHY_TST0_TSTCLR_OFFSET 5 432 #define HDMI_PHY_TST0_TSTEN_MASK 0x10 433 #define HDMI_PHY_TST0_TSTEN_OFFSET 4 434 #define HDMI_PHY_TST0_TSTCLK_MASK 0x1 435 #define HDMI_PHY_TST0_TSTCLK_OFFSET 0 436 #define HDMI_PHY_TST1 0x3002 437 #define HDMI_PHY_TST2 0x3003 438 #define HDMI_PHY_STAT0 0x3004 439 #define HDMI_PHY_STAT0_RX_SENSE3 0x80 440 #define HDMI_PHY_STAT0_RX_SENSE2 0x40 441 #define HDMI_PHY_STAT0_RX_SENSE1 0x20 442 #define HDMI_PHY_STAT0_RX_SENSE0 0x10 443 #define HDMI_PHY_STAT0_RX_SENSE 0xf0 444 #define HDMI_PHY_STAT0_HPD 0x02 445 #define HDMI_PHY_TX_PHY_LOCK 0x01 446 #define HDMI_PHY_INT0 0x3005 447 #define HDMI_PHY_MASK0 0x3006 448 #define HDMI_PHY_POL0 0x3007 449 #define HDMI_PHY_POL0_HPD 0x02 450 451 /* HDMI Master PHY Registers */ 452 #define HDMI_PHY_I2CM_SLAVE_ADDR 0x3020 453 #define HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2 0x69 454 #define HDMI_PHY_I2CM_SLAVE_ADDR_HEAC_PHY 0x49 455 #define HDMI_PHY_I2CM_ADDRESS_ADDR 0x3021 456 #define HDMI_PHY_I2CM_DATAO_1_ADDR 0x3022 457 #define HDMI_PHY_I2CM_DATAO_0_ADDR 0x3023 458 #define HDMI_PHY_I2CM_DATAI_1_ADDR 0x3024 459 #define HDMI_PHY_I2CM_DATAI_0_ADDR 0x3025 460 #define HDMI_PHY_I2CM_OPERATION_ADDR 0x3026 461 #define HDMI_PHY_I2CM_INT_ADDR 0x3027 462 #define HDMI_PHY_I2CM_CTLINT_ADDR 0x3028 463 #define HDMI_PHY_I2CM_DIV_ADDR 0x3029 464 #define HDMI_PHY_I2CM_SOFTRSTZ_ADDR 0x302a 465 #define HDMI_PHY_I2CM_SS_SCL_HCNT_1_ADDR 0x302b 466 #define HDMI_PHY_I2CM_SS_SCL_HCNT_0_ADDR 0x302c 467 #define HDMI_PHY_I2CM_SS_SCL_LCNT_1_ADDR 0x302d 468 #define HDMI_PHY_I2CM_SS_SCL_LCNT_0_ADDR 0x302e 469 #define HDMI_PHY_I2CM_FS_SCL_HCNT_1_ADDR 0x302f 470 #define HDMI_PHY_I2CM_FS_SCL_HCNT_0_ADDR 0x3030 471 #define HDMI_PHY_I2CM_FS_SCL_LCNT_1_ADDR 0x3031 472 #define HDMI_PHY_I2CM_FS_SCL_LCNT_0_ADDR 0x3032 473 474 /* Audio Sampler Registers */ 475 #define HDMI_AUD_CONF0 0x3100 476 #define HDMI_AUD_CONF0_INTERFACE_MASK 0x20 477 #define HDMI_AUD_CONF0_INTERFACE_IIS 0x20 478 #define HDMI_AUD_CONF0_INTERFACE_SPDIF 0x00 479 #define HDMI_AUD_CONF0_I2SINEN_MASK 0x0f 480 #define HDMI_AUD_CONF0_I2SINEN_CH2 0x01 481 #define HDMI_AUD_CONF0_I2SINEN_CH4 0x03 482 #define HDMI_AUD_CONF0_I2SINEN_CH6 0x07 483 #define HDMI_AUD_CONF0_I2SINEN_CH8 0x0f 484 #define HDMI_AUD_CONF1 0x3101 485 #define HDMI_AUD_CONF1_DATAMODE_MASK 0xe0 486 #define HDMI_AUD_CONF1_DATAMODE_IIS 0x00 487 #define HDMI_AUD_CONF1_DATAMODE_RIGHT_J 0x20 488 #define HDMI_AUD_CONF1_DATAMODE_LEFT_J 0x40 489 #define HDMI_AUD_CONF1_DATAMODE_BURST_1 0x60 490 #define HDMI_AUD_CONF1_DATAMDOE_BURST_2 0x80 491 #define HDMI_AUD_CONF1_DATWIDTH_MASK 0x1f 492 #define HDMI_AUD_CONF1_DATWIDTH_16BIT 16 493 #define HDMI_AUD_CONF1_DATWIDTH_24BIT 24 494 #define HDMI_AUD_INT 0x3102 495 #define HDMI_AUD_CONF2 0x3103 496 #define HDMI_AUD_N1 0x3200 497 #define HDMI_AUD_N2 0x3201 498 #define HDMI_AUD_N3 0x3202 499 #define HDMI_AUD_CTS1 0x3203 500 #define HDMI_AUD_CTS2 0x3204 501 #define HDMI_AUD_CTS3 0x3205 502 #define HDMI_AUD_CTS3_N_SHIFT_MASK 0xe0 503 #define HDMI_AUD_CTS3_CTS_MANUAL 0x10 504 #define HDMI_AUD_INPUTCLKFS 0x3206 505 #define HDMI_AUD_INPUTCLKFS_128 0 506 #define HDMI_AUD_INPUTCLKFS_256 1 507 #define HDMI_AUD_INPUTCLKFS_512 2 508 #define HDMI_AUD_INPUTCLKFS_1024 3 509 #define HDMI_AUD_INPUTCLKFS_64 4 510 #define HDMI_AUD_SPDIFINT 0x3302 511 #define HDMI_AUD_CONF0_HBR 0x3400 512 #define HDMI_AUD_HBR_STATUS 0x3401 513 #define HDMI_AUD_HBR_INT 0x3402 514 #define HDMI_AUD_HBR_POL 0x3403 515 #define HDMI_AUD_HBR_MASK 0x3404 516 517 /* 518 * Generic Parallel Audio Interface Registers 519 * Not used as GPAUD interface is not enabled in hw 520 */ 521 #define HDMI_GP_CONF0 0x3500 522 #define HDMI_GP_CONF1 0x3501 523 #define HDMI_GP_CONF2 0x3502 524 #define HDMI_GP_STAT 0x3503 525 #define HDMI_GP_INT 0x3504 526 #define HDMI_GP_MASK 0x3505 527 #define HDMI_GP_POL 0x3506 528 529 /* Main Controller Registers */ 530 #define HDMI_MC_SFRDIV 0x4000 531 #define HDMI_MC_CLKDIS 0x4001 532 #define HDMI_MC_CLKDIS_HDCPCLK_DISABLE (1 << 6) 533 #define HDMI_MC_CLKDIS_CECCLK_DISABLE (1 << 5) 534 #define HDMI_MC_CLKDIS_CSCCLK_DISABLE (1 << 4) 535 #define HDMI_MC_CLKDIS_AUDCLK_DISABLE (1 << 3) 536 #define HDMI_MC_CLKDIS_PREPCLK_DISABLE (1 << 2) 537 #define HDMI_MC_CLKDIS_TMDSCLK_DISABLE (1 << 1) 538 #define HDMI_MC_CLKDIS_PIXELCLK_DISABLE (1 << 0) 539 540 #define HDMI_MC_SWRSTZ 0x4002 541 #define HDMI_MC_SWRSTZ_TMDSSWRST_REQ 0x02 542 #define HDMI_MC_OPCTRL 0x4003 543 #define HDMI_MC_FLOWCTRL 0x4004 544 #define HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_MASK 0x1 545 #define HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH 0x1 546 #define HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS 0x0 547 #define HDMI_MC_PHYRSTZ 0x4005 548 #define HDMI_MC_PHYRSTZ_ASSERT 0x0 549 #define HDMI_MC_PHYRSTZ_DEASSERT 0x1 550 #define HDMI_MC_LOCKONCLOCK 0x4006 551 #define HDMI_MC_HEACPHY_RST 0x4007 552 #define HDMI_MC_HEACPHY_RST_ASSERT 0x1 553 #define HDMI_MC_HEACPHY_RST_DEASSERT 0x0 554 555 /* HDCP Encryption Engine Registers */ 556 #define HDMI_A_HDCPCFG0 0x5000 557 #define HDMI_A_HDCPCFG0_RXDETECT_MASK 0x4 558 #define HDMI_A_HDCPCFG0_RXDETECT_ENABLE 0x4 559 #define HDMI_A_HDCPCFG0_RXDETECT_DISABLE 0x0 560 #define HDMI_A_HDCPCFG1 0x5001 561 #define HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK 0x2 562 #define HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_DISABLE 0x2 563 #define HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_ENABLE 0x0 564 #define HDMI_A_HDCPOBS0 0x5002 565 #define HDMI_A_HDCPOBS1 0x5003 566 #define HDMI_A_HDCPOBS2 0x5004 567 #define HDMI_A_HDCPOBS3 0x5005 568 #define HDMI_A_APIINTCLR 0x5006 569 #define HDMI_A_APIINTSTAT 0x5007 570 #define HDMI_A_APIINTMSK 0x5008 571 #define HDMI_A_VIDPOLCFG 0x5009 572 #define HDMI_A_VIDPOLCFG_DATAENPOL_MASK 0x10 573 #define HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH 0x10 574 #define HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_LOW 0x0 575 #define HDMI_A_OESSWCFG 0x500A 576 #define HDMI_A_TIMER1SETUP0 0x500B 577 #define HDMI_A_TIMER1SETUP1 0x500C 578 #define HDMI_A_TIMER2SETUP0 0x500D 579 #define HDMI_A_TIMER2SETUP1 0x500E 580 #define HDMI_A_100MSCFG 0x500F 581 #define HDMI_A_2SCFG0 0x5010 582 #define HDMI_A_2SCFG1 0x5011 583 #define HDMI_A_5SCFG0 0x5012 584 #define HDMI_A_5SCFG1 0x5013 585 #define HDMI_A_SRMVERLSB 0x5014 586 #define HDMI_A_SRMVERMSB 0x5015 587 #define HDMI_A_SRMCTRL 0x5016 588 #define HDMI_A_SFRSETUP 0x5017 589 #define HDMI_A_I2CHSETUP 0x5018 590 #define HDMI_A_INTSETUP 0x5019 591 #define HDMI_A_PRESETUP 0x501A 592 #define HDMI_A_SRM_BASE 0x5020 593 594 /* CEC Engine Registers */ 595 #define HDMI_CEC_CTRL 0x7D00 596 #define HDMI_CEC_STAT 0x7D01 597 #define HDMI_CEC_MASK 0x7D02 598 #define HDMI_CEC_POLARITY 0x7D03 599 #define HDMI_CEC_INT 0x7D04 600 #define HDMI_CEC_ADDR_L 0x7D05 601 #define HDMI_CEC_ADDR_H 0x7D06 602 #define HDMI_CEC_TX_CNT 0x7D07 603 #define HDMI_CEC_RX_CNT 0x7D08 604 #define HDMI_CEC_TX_DATA0 0x7D10 605 #define HDMI_CEC_TX_DATA1 0x7D11 606 #define HDMI_CEC_TX_DATA2 0x7D12 607 #define HDMI_CEC_TX_DATA3 0x7D13 608 #define HDMI_CEC_TX_DATA4 0x7D14 609 #define HDMI_CEC_TX_DATA5 0x7D15 610 #define HDMI_CEC_TX_DATA6 0x7D16 611 #define HDMI_CEC_TX_DATA7 0x7D17 612 #define HDMI_CEC_TX_DATA8 0x7D18 613 #define HDMI_CEC_TX_DATA9 0x7D19 614 #define HDMI_CEC_TX_DATA10 0x7D1a 615 #define HDMI_CEC_TX_DATA11 0x7D1b 616 #define HDMI_CEC_TX_DATA12 0x7D1c 617 #define HDMI_CEC_TX_DATA13 0x7D1d 618 #define HDMI_CEC_TX_DATA14 0x7D1e 619 #define HDMI_CEC_TX_DATA15 0x7D1f 620 #define HDMI_CEC_RX_DATA0 0x7D20 621 #define HDMI_CEC_RX_DATA1 0x7D21 622 #define HDMI_CEC_RX_DATA2 0x7D22 623 #define HDMI_CEC_RX_DATA3 0x7D23 624 #define HDMI_CEC_RX_DATA4 0x7D24 625 #define HDMI_CEC_RX_DATA5 0x7D25 626 #define HDMI_CEC_RX_DATA6 0x7D26 627 #define HDMI_CEC_RX_DATA7 0x7D27 628 #define HDMI_CEC_RX_DATA8 0x7D28 629 #define HDMI_CEC_RX_DATA9 0x7D29 630 #define HDMI_CEC_RX_DATA10 0x7D2a 631 #define HDMI_CEC_RX_DATA11 0x7D2b 632 #define HDMI_CEC_RX_DATA12 0x7D2c 633 #define HDMI_CEC_RX_DATA13 0x7D2d 634 #define HDMI_CEC_RX_DATA14 0x7D2e 635 #define HDMI_CEC_RX_DATA15 0x7D2f 636 #define HDMI_CEC_LOCK 0x7D30 637 #define HDMI_CEC_WKUPCTRL 0x7D31 638 639 /* I2C Master Registers (E-DDC) */ 640 #define HDMI_I2CM_SLAVE 0x7E00 641 #define HDMI_I2CMESS 0x7E01 642 #define HDMI_I2CM_DATAO 0x7E02 643 #define HDMI_I2CM_DATAI 0x7E03 644 #define HDMI_I2CM_OPERATION 0x7E04 645 #define HDMI_PHY_I2CM_OPERATION_ADDR_WRITE 0x10 646 #define HDMI_PHY_I2CM_OPERATION_ADDR_READ 0x1 647 #define HDMI_I2CM_INT 0x7E05 648 #define HDMI_I2CM_CTLINT 0x7E06 649 #define HDMI_I2CM_DIV 0x7E07 650 #define HDMI_I2CM_SEGADDR 0x7E08 651 #define HDMI_I2CM_SOFTRSTZ 0x7E09 652 #define HDMI_I2CM_SEGPTR 0x7E0A 653 #define HDMI_I2CM_SS_SCL_HCNT_1_ADDR 0x7E0B 654 #define HDMI_I2CM_SS_SCL_HCNT_0_ADDR 0x7E0C 655 #define HDMI_I2CM_SS_SCL_LCNT_1_ADDR 0x7E0D 656 #define HDMI_I2CM_SS_SCL_LCNT_0_ADDR 0x7E0E 657 #define HDMI_I2CM_FS_SCL_HCNT_1_ADDR 0x7E0F 658 #define HDMI_I2CM_FS_SCL_HCNT_0_ADDR 0x7E10 659 #define HDMI_I2CM_FS_SCL_LCNT_1_ADDR 0x7E11 660 #define HDMI_I2CM_FS_SCL_LCNT_0_ADDR 0x7E12 661 662 /* HDMI PHY register with access through I2C */ 663 #define HDMI_PHY_I2C_CKCALCTRL 0x5 664 #define CKCALCTRL_OVERRIDE (1 << 15) 665 #define HDMI_PHY_I2C_CPCE_CTRL 0x6 666 #define CPCE_CTRL_45_25 ((3 << 7) | (3 << 5)) 667 #define CPCE_CTRL_92_50 ((2 << 7) | (2 << 5)) 668 #define CPCE_CTRL_185 ((1 << 7) | (1 << 5)) 669 #define CPCE_CTRL_370 ((0 << 7) | (0 << 5)) 670 #define HDMI_PHY_I2C_CKSYMTXCTRL 0x9 671 #define CKSYMTXCTRL_OVERRIDE (1 << 15) 672 #define CKSYMTXCTRL_TX_SYMON (1 << 3) 673 #define CKSYMTXCTRL_TX_TRAON (1 << 2) 674 #define CKSYMTXCTRL_TX_TRBON (1 << 1) 675 #define CKSYMTXCTRL_TX_CK_SYMON (1 << 0) 676 #define HDMI_PHY_I2C_VLEVCTRL 0x0E 677 #define HDMI_PHY_I2C_CURRCTRL 0x10 678 #define HDMI_PHY_I2C_PLLPHBYCTRL 0x13 679 #define VLEVCTRL_TX_LVL(x) ((x) << 5) 680 #define VLEVCTRL_CK_LVL(x) (x) 681 #define HDMI_PHY_I2C_GMPCTRL 0x15 682 #define GMPCTRL_45_25 0x00 683 #define GMPCTRL_92_50 0x05 684 #define GMPCTRL_185 0x0a 685 #define GMPCTRL_370 0x0f 686 #define HDMI_PHY_I2C_MSM_CTRL 0x17 687 #define MSM_CTRL_FB_CLK (0x3 << 1) 688 #define HDMI_PHY_I2C_TXTERM 0x19 689 #define TXTERM_133 0x5 690 691 #endif /* __DWC_HDMIREG_H__ */
Cache object: 0637b7639aa51771c0b9218b220c5bbf
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