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sys/dev/hifn/hifn7751.c
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1 /* $OpenBSD: hifn7751.c,v 1.120 2002/05/17 00:33:34 deraadt Exp $ */ 2 3 /*- 4 * Invertex AEON / Hifn 7751 driver 5 * Copyright (c) 1999 Invertex Inc. All rights reserved. 6 * Copyright (c) 1999 Theo de Raadt 7 * Copyright (c) 2000-2001 Network Security Technologies, Inc. 8 * http://www.netsec.net 9 * Copyright (c) 2003 Hifn Inc. 10 * 11 * This driver is based on a previous driver by Invertex, for which they 12 * requested: Please send any comments, feedback, bug-fixes, or feature 13 * requests to software@invertex.com. 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions 17 * are met: 18 * 19 * 1. Redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer. 21 * 2. Redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution. 24 * 3. The name of the author may not be used to endorse or promote products 25 * derived from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 28 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 29 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 30 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 31 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 32 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 33 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 34 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 35 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 36 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37 * 38 * Effort sponsored in part by the Defense Advanced Research Projects 39 * Agency (DARPA) and Air Force Research Laboratory, Air Force 40 * Materiel Command, USAF, under agreement number F30602-01-2-0537. 41 */ 42 43 #include <sys/cdefs.h> 44 __FBSDID("$FreeBSD: releng/8.4/sys/dev/hifn/hifn7751.c 233025 2012-03-16 09:22:59Z scottl $"); 45 46 /* 47 * Driver for various Hifn encryption processors. 48 */ 49 #include "opt_hifn.h" 50 51 #include <sys/param.h> 52 #include <sys/systm.h> 53 #include <sys/proc.h> 54 #include <sys/errno.h> 55 #include <sys/malloc.h> 56 #include <sys/kernel.h> 57 #include <sys/module.h> 58 #include <sys/mbuf.h> 59 #include <sys/lock.h> 60 #include <sys/mutex.h> 61 #include <sys/sysctl.h> 62 63 #include <vm/vm.h> 64 #include <vm/pmap.h> 65 66 #include <machine/bus.h> 67 #include <machine/resource.h> 68 #include <sys/bus.h> 69 #include <sys/rman.h> 70 71 #include <opencrypto/cryptodev.h> 72 #include <sys/random.h> 73 #include <sys/kobj.h> 74 75 #include "cryptodev_if.h" 76 77 #include <dev/pci/pcivar.h> 78 #include <dev/pci/pcireg.h> 79 80 #ifdef HIFN_RNDTEST 81 #include <dev/rndtest/rndtest.h> 82 #endif 83 #include <dev/hifn/hifn7751reg.h> 84 #include <dev/hifn/hifn7751var.h> 85 86 #ifdef HIFN_VULCANDEV 87 #include <sys/conf.h> 88 #include <sys/uio.h> 89 90 static struct cdevsw vulcanpk_cdevsw; /* forward declaration */ 91 #endif 92 93 /* 94 * Prototypes and count for the pci_device structure 95 */ 96 static int hifn_probe(device_t); 97 static int hifn_attach(device_t); 98 static int hifn_detach(device_t); 99 static int hifn_suspend(device_t); 100 static int hifn_resume(device_t); 101 static int hifn_shutdown(device_t); 102 103 static int hifn_newsession(device_t, u_int32_t *, struct cryptoini *); 104 static int hifn_freesession(device_t, u_int64_t); 105 static int hifn_process(device_t, struct cryptop *, int); 106 107 static device_method_t hifn_methods[] = { 108 /* Device interface */ 109 DEVMETHOD(device_probe, hifn_probe), 110 DEVMETHOD(device_attach, hifn_attach), 111 DEVMETHOD(device_detach, hifn_detach), 112 DEVMETHOD(device_suspend, hifn_suspend), 113 DEVMETHOD(device_resume, hifn_resume), 114 DEVMETHOD(device_shutdown, hifn_shutdown), 115 116 /* crypto device methods */ 117 DEVMETHOD(cryptodev_newsession, hifn_newsession), 118 DEVMETHOD(cryptodev_freesession,hifn_freesession), 119 DEVMETHOD(cryptodev_process, hifn_process), 120 121 DEVMETHOD_END 122 }; 123 static driver_t hifn_driver = { 124 "hifn", 125 hifn_methods, 126 sizeof (struct hifn_softc) 127 }; 128 static devclass_t hifn_devclass; 129 130 DRIVER_MODULE(hifn, pci, hifn_driver, hifn_devclass, 0, 0); 131 MODULE_DEPEND(hifn, crypto, 1, 1, 1); 132 #ifdef HIFN_RNDTEST 133 MODULE_DEPEND(hifn, rndtest, 1, 1, 1); 134 #endif 135 136 static void hifn_reset_board(struct hifn_softc *, int); 137 static void hifn_reset_puc(struct hifn_softc *); 138 static void hifn_puc_wait(struct hifn_softc *); 139 static int hifn_enable_crypto(struct hifn_softc *); 140 static void hifn_set_retry(struct hifn_softc *sc); 141 static void hifn_init_dma(struct hifn_softc *); 142 static void hifn_init_pci_registers(struct hifn_softc *); 143 static int hifn_sramsize(struct hifn_softc *); 144 static int hifn_dramsize(struct hifn_softc *); 145 static int hifn_ramtype(struct hifn_softc *); 146 static void hifn_sessions(struct hifn_softc *); 147 static void hifn_intr(void *); 148 static u_int hifn_write_command(struct hifn_command *, u_int8_t *); 149 static u_int32_t hifn_next_signature(u_int32_t a, u_int cnt); 150 static void hifn_callback(struct hifn_softc *, struct hifn_command *, u_int8_t *); 151 static int hifn_crypto(struct hifn_softc *, struct hifn_command *, struct cryptop *, int); 152 static int hifn_readramaddr(struct hifn_softc *, int, u_int8_t *); 153 static int hifn_writeramaddr(struct hifn_softc *, int, u_int8_t *); 154 static int hifn_dmamap_load_src(struct hifn_softc *, struct hifn_command *); 155 static int hifn_dmamap_load_dst(struct hifn_softc *, struct hifn_command *); 156 static int hifn_init_pubrng(struct hifn_softc *); 157 static void hifn_rng(void *); 158 static void hifn_tick(void *); 159 static void hifn_abort(struct hifn_softc *); 160 static void hifn_alloc_slot(struct hifn_softc *, int *, int *, int *, int *); 161 162 static void hifn_write_reg_0(struct hifn_softc *, bus_size_t, u_int32_t); 163 static void hifn_write_reg_1(struct hifn_softc *, bus_size_t, u_int32_t); 164 165 static __inline u_int32_t 166 READ_REG_0(struct hifn_softc *sc, bus_size_t reg) 167 { 168 u_int32_t v = bus_space_read_4(sc->sc_st0, sc->sc_sh0, reg); 169 sc->sc_bar0_lastreg = (bus_size_t) -1; 170 return (v); 171 } 172 #define WRITE_REG_0(sc, reg, val) hifn_write_reg_0(sc, reg, val) 173 174 static __inline u_int32_t 175 READ_REG_1(struct hifn_softc *sc, bus_size_t reg) 176 { 177 u_int32_t v = bus_space_read_4(sc->sc_st1, sc->sc_sh1, reg); 178 sc->sc_bar1_lastreg = (bus_size_t) -1; 179 return (v); 180 } 181 #define WRITE_REG_1(sc, reg, val) hifn_write_reg_1(sc, reg, val) 182 183 SYSCTL_NODE(_hw, OID_AUTO, hifn, CTLFLAG_RD, 0, "Hifn driver parameters"); 184 185 #ifdef HIFN_DEBUG 186 static int hifn_debug = 0; 187 SYSCTL_INT(_hw_hifn, OID_AUTO, debug, CTLFLAG_RW, &hifn_debug, 188 0, "control debugging msgs"); 189 #endif 190 191 static struct hifn_stats hifnstats; 192 SYSCTL_STRUCT(_hw_hifn, OID_AUTO, stats, CTLFLAG_RD, &hifnstats, 193 hifn_stats, "driver statistics"); 194 static int hifn_maxbatch = 1; 195 SYSCTL_INT(_hw_hifn, OID_AUTO, maxbatch, CTLFLAG_RW, &hifn_maxbatch, 196 0, "max ops to batch w/o interrupt"); 197 198 /* 199 * Probe for a supported device. The PCI vendor and device 200 * IDs are used to detect devices we know how to handle. 201 */ 202 static int 203 hifn_probe(device_t dev) 204 { 205 if (pci_get_vendor(dev) == PCI_VENDOR_INVERTEX && 206 pci_get_device(dev) == PCI_PRODUCT_INVERTEX_AEON) 207 return (BUS_PROBE_DEFAULT); 208 if (pci_get_vendor(dev) == PCI_VENDOR_HIFN && 209 (pci_get_device(dev) == PCI_PRODUCT_HIFN_7751 || 210 pci_get_device(dev) == PCI_PRODUCT_HIFN_7951 || 211 pci_get_device(dev) == PCI_PRODUCT_HIFN_7955 || 212 pci_get_device(dev) == PCI_PRODUCT_HIFN_7956 || 213 pci_get_device(dev) == PCI_PRODUCT_HIFN_7811)) 214 return (BUS_PROBE_DEFAULT); 215 if (pci_get_vendor(dev) == PCI_VENDOR_NETSEC && 216 pci_get_device(dev) == PCI_PRODUCT_NETSEC_7751) 217 return (BUS_PROBE_DEFAULT); 218 return (ENXIO); 219 } 220 221 static void 222 hifn_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 223 { 224 bus_addr_t *paddr = (bus_addr_t*) arg; 225 *paddr = segs->ds_addr; 226 } 227 228 static const char* 229 hifn_partname(struct hifn_softc *sc) 230 { 231 /* XXX sprintf numbers when not decoded */ 232 switch (pci_get_vendor(sc->sc_dev)) { 233 case PCI_VENDOR_HIFN: 234 switch (pci_get_device(sc->sc_dev)) { 235 case PCI_PRODUCT_HIFN_6500: return "Hifn 6500"; 236 case PCI_PRODUCT_HIFN_7751: return "Hifn 7751"; 237 case PCI_PRODUCT_HIFN_7811: return "Hifn 7811"; 238 case PCI_PRODUCT_HIFN_7951: return "Hifn 7951"; 239 case PCI_PRODUCT_HIFN_7955: return "Hifn 7955"; 240 case PCI_PRODUCT_HIFN_7956: return "Hifn 7956"; 241 } 242 return "Hifn unknown-part"; 243 case PCI_VENDOR_INVERTEX: 244 switch (pci_get_device(sc->sc_dev)) { 245 case PCI_PRODUCT_INVERTEX_AEON: return "Invertex AEON"; 246 } 247 return "Invertex unknown-part"; 248 case PCI_VENDOR_NETSEC: 249 switch (pci_get_device(sc->sc_dev)) { 250 case PCI_PRODUCT_NETSEC_7751: return "NetSec 7751"; 251 } 252 return "NetSec unknown-part"; 253 } 254 return "Unknown-vendor unknown-part"; 255 } 256 257 static void 258 default_harvest(struct rndtest_state *rsp, void *buf, u_int count) 259 { 260 random_harvest(buf, count, count*NBBY, 0, RANDOM_PURE); 261 } 262 263 static u_int 264 checkmaxmin(device_t dev, const char *what, u_int v, u_int min, u_int max) 265 { 266 if (v > max) { 267 device_printf(dev, "Warning, %s %u out of range, " 268 "using max %u\n", what, v, max); 269 v = max; 270 } else if (v < min) { 271 device_printf(dev, "Warning, %s %u out of range, " 272 "using min %u\n", what, v, min); 273 v = min; 274 } 275 return v; 276 } 277 278 /* 279 * Select PLL configuration for 795x parts. This is complicated in 280 * that we cannot determine the optimal parameters without user input. 281 * The reference clock is derived from an external clock through a 282 * multiplier. The external clock is either the host bus (i.e. PCI) 283 * or an external clock generator. When using the PCI bus we assume 284 * the clock is either 33 or 66 MHz; for an external source we cannot 285 * tell the speed. 286 * 287 * PLL configuration is done with a string: "pci" for PCI bus, or "ext" 288 * for an external source, followed by the frequency. We calculate 289 * the appropriate multiplier and PLL register contents accordingly. 290 * When no configuration is given we default to "pci66" since that 291 * always will allow the card to work. If a card is using the PCI 292 * bus clock and in a 33MHz slot then it will be operating at half 293 * speed until the correct information is provided. 294 * 295 * We use a default setting of "ext66" because according to Mike Ham 296 * of HiFn, almost every board in existence has an external crystal 297 * populated at 66Mhz. Using PCI can be a problem on modern motherboards, 298 * because PCI33 can have clocks from 0 to 33Mhz, and some have 299 * non-PCI-compliant spread-spectrum clocks, which can confuse the pll. 300 */ 301 static void 302 hifn_getpllconfig(device_t dev, u_int *pll) 303 { 304 const char *pllspec; 305 u_int freq, mul, fl, fh; 306 u_int32_t pllconfig; 307 char *nxt; 308 309 if (resource_string_value("hifn", device_get_unit(dev), 310 "pllconfig", &pllspec)) 311 pllspec = "ext66"; 312 fl = 33, fh = 66; 313 pllconfig = 0; 314 if (strncmp(pllspec, "ext", 3) == 0) { 315 pllspec += 3; 316 pllconfig |= HIFN_PLL_REF_SEL; 317 switch (pci_get_device(dev)) { 318 case PCI_PRODUCT_HIFN_7955: 319 case PCI_PRODUCT_HIFN_7956: 320 fl = 20, fh = 100; 321 break; 322 #ifdef notyet 323 case PCI_PRODUCT_HIFN_7954: 324 fl = 20, fh = 66; 325 break; 326 #endif 327 } 328 } else if (strncmp(pllspec, "pci", 3) == 0) 329 pllspec += 3; 330 freq = strtoul(pllspec, &nxt, 10); 331 if (nxt == pllspec) 332 freq = 66; 333 else 334 freq = checkmaxmin(dev, "frequency", freq, fl, fh); 335 /* 336 * Calculate multiplier. We target a Fck of 266 MHz, 337 * allowing only even values, possibly rounded down. 338 * Multipliers > 8 must set the charge pump current. 339 */ 340 mul = checkmaxmin(dev, "PLL divisor", (266 / freq) &~ 1, 2, 12); 341 pllconfig |= (mul / 2 - 1) << HIFN_PLL_ND_SHIFT; 342 if (mul > 8) 343 pllconfig |= HIFN_PLL_IS; 344 *pll = pllconfig; 345 } 346 347 /* 348 * Attach an interface that successfully probed. 349 */ 350 static int 351 hifn_attach(device_t dev) 352 { 353 struct hifn_softc *sc = device_get_softc(dev); 354 u_int32_t cmd; 355 caddr_t kva; 356 int rseg, rid; 357 char rbase; 358 u_int16_t ena, rev; 359 360 KASSERT(sc != NULL, ("hifn_attach: null software carrier!")); 361 bzero(sc, sizeof (*sc)); 362 sc->sc_dev = dev; 363 364 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), "hifn driver", MTX_DEF); 365 366 /* XXX handle power management */ 367 368 /* 369 * The 7951 and 795x have a random number generator and 370 * public key support; note this. 371 */ 372 if (pci_get_vendor(dev) == PCI_VENDOR_HIFN && 373 (pci_get_device(dev) == PCI_PRODUCT_HIFN_7951 || 374 pci_get_device(dev) == PCI_PRODUCT_HIFN_7955 || 375 pci_get_device(dev) == PCI_PRODUCT_HIFN_7956)) 376 sc->sc_flags = HIFN_HAS_RNG | HIFN_HAS_PUBLIC; 377 /* 378 * The 7811 has a random number generator and 379 * we also note it's identity 'cuz of some quirks. 380 */ 381 if (pci_get_vendor(dev) == PCI_VENDOR_HIFN && 382 pci_get_device(dev) == PCI_PRODUCT_HIFN_7811) 383 sc->sc_flags |= HIFN_IS_7811 | HIFN_HAS_RNG; 384 385 /* 386 * The 795x parts support AES. 387 */ 388 if (pci_get_vendor(dev) == PCI_VENDOR_HIFN && 389 (pci_get_device(dev) == PCI_PRODUCT_HIFN_7955 || 390 pci_get_device(dev) == PCI_PRODUCT_HIFN_7956)) { 391 sc->sc_flags |= HIFN_IS_7956 | HIFN_HAS_AES; 392 /* 393 * Select PLL configuration. This depends on the 394 * bus and board design and must be manually configured 395 * if the default setting is unacceptable. 396 */ 397 hifn_getpllconfig(dev, &sc->sc_pllconfig); 398 } 399 400 /* 401 * Configure support for memory-mapped access to 402 * registers and for DMA operations. 403 */ 404 #define PCIM_ENA (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN) 405 cmd = pci_read_config(dev, PCIR_COMMAND, 4); 406 cmd |= PCIM_ENA; 407 pci_write_config(dev, PCIR_COMMAND, cmd, 4); 408 cmd = pci_read_config(dev, PCIR_COMMAND, 4); 409 if ((cmd & PCIM_ENA) != PCIM_ENA) { 410 device_printf(dev, "failed to enable %s\n", 411 (cmd & PCIM_ENA) == 0 ? 412 "memory mapping & bus mastering" : 413 (cmd & PCIM_CMD_MEMEN) == 0 ? 414 "memory mapping" : "bus mastering"); 415 goto fail_pci; 416 } 417 #undef PCIM_ENA 418 419 /* 420 * Setup PCI resources. Note that we record the bus 421 * tag and handle for each register mapping, this is 422 * used by the READ_REG_0, WRITE_REG_0, READ_REG_1, 423 * and WRITE_REG_1 macros throughout the driver. 424 */ 425 rid = HIFN_BAR0; 426 sc->sc_bar0res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 427 RF_ACTIVE); 428 if (sc->sc_bar0res == NULL) { 429 device_printf(dev, "cannot map bar%d register space\n", 0); 430 goto fail_pci; 431 } 432 sc->sc_st0 = rman_get_bustag(sc->sc_bar0res); 433 sc->sc_sh0 = rman_get_bushandle(sc->sc_bar0res); 434 sc->sc_bar0_lastreg = (bus_size_t) -1; 435 436 rid = HIFN_BAR1; 437 sc->sc_bar1res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 438 RF_ACTIVE); 439 if (sc->sc_bar1res == NULL) { 440 device_printf(dev, "cannot map bar%d register space\n", 1); 441 goto fail_io0; 442 } 443 sc->sc_st1 = rman_get_bustag(sc->sc_bar1res); 444 sc->sc_sh1 = rman_get_bushandle(sc->sc_bar1res); 445 sc->sc_bar1_lastreg = (bus_size_t) -1; 446 447 hifn_set_retry(sc); 448 449 /* 450 * Setup the area where the Hifn DMA's descriptors 451 * and associated data structures. 452 */ 453 if (bus_dma_tag_create(bus_get_dma_tag(dev), /* PCI parent */ 454 1, 0, /* alignment,boundary */ 455 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 456 BUS_SPACE_MAXADDR, /* highaddr */ 457 NULL, NULL, /* filter, filterarg */ 458 HIFN_MAX_DMALEN, /* maxsize */ 459 MAX_SCATTER, /* nsegments */ 460 HIFN_MAX_SEGLEN, /* maxsegsize */ 461 BUS_DMA_ALLOCNOW, /* flags */ 462 NULL, /* lockfunc */ 463 NULL, /* lockarg */ 464 &sc->sc_dmat)) { 465 device_printf(dev, "cannot allocate DMA tag\n"); 466 goto fail_io1; 467 } 468 if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, &sc->sc_dmamap)) { 469 device_printf(dev, "cannot create dma map\n"); 470 bus_dma_tag_destroy(sc->sc_dmat); 471 goto fail_io1; 472 } 473 if (bus_dmamem_alloc(sc->sc_dmat, (void**) &kva, BUS_DMA_NOWAIT, &sc->sc_dmamap)) { 474 device_printf(dev, "cannot alloc dma buffer\n"); 475 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 476 bus_dma_tag_destroy(sc->sc_dmat); 477 goto fail_io1; 478 } 479 if (bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, kva, 480 sizeof (*sc->sc_dma), 481 hifn_dmamap_cb, &sc->sc_dma_physaddr, 482 BUS_DMA_NOWAIT)) { 483 device_printf(dev, "cannot load dma map\n"); 484 bus_dmamem_free(sc->sc_dmat, kva, sc->sc_dmamap); 485 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 486 bus_dma_tag_destroy(sc->sc_dmat); 487 goto fail_io1; 488 } 489 sc->sc_dma = (struct hifn_dma *)kva; 490 bzero(sc->sc_dma, sizeof(*sc->sc_dma)); 491 492 KASSERT(sc->sc_st0 != 0, ("hifn_attach: null bar0 tag!")); 493 KASSERT(sc->sc_sh0 != 0, ("hifn_attach: null bar0 handle!")); 494 KASSERT(sc->sc_st1 != 0, ("hifn_attach: null bar1 tag!")); 495 KASSERT(sc->sc_sh1 != 0, ("hifn_attach: null bar1 handle!")); 496 497 /* 498 * Reset the board and do the ``secret handshake'' 499 * to enable the crypto support. Then complete the 500 * initialization procedure by setting up the interrupt 501 * and hooking in to the system crypto support so we'll 502 * get used for system services like the crypto device, 503 * IPsec, RNG device, etc. 504 */ 505 hifn_reset_board(sc, 0); 506 507 if (hifn_enable_crypto(sc) != 0) { 508 device_printf(dev, "crypto enabling failed\n"); 509 goto fail_mem; 510 } 511 hifn_reset_puc(sc); 512 513 hifn_init_dma(sc); 514 hifn_init_pci_registers(sc); 515 516 /* XXX can't dynamically determine ram type for 795x; force dram */ 517 if (sc->sc_flags & HIFN_IS_7956) 518 sc->sc_drammodel = 1; 519 else if (hifn_ramtype(sc)) 520 goto fail_mem; 521 522 if (sc->sc_drammodel == 0) 523 hifn_sramsize(sc); 524 else 525 hifn_dramsize(sc); 526 527 /* 528 * Workaround for NetSec 7751 rev A: half ram size because two 529 * of the address lines were left floating 530 */ 531 if (pci_get_vendor(dev) == PCI_VENDOR_NETSEC && 532 pci_get_device(dev) == PCI_PRODUCT_NETSEC_7751 && 533 pci_get_revid(dev) == 0x61) /*XXX???*/ 534 sc->sc_ramsize >>= 1; 535 536 /* 537 * Arrange the interrupt line. 538 */ 539 rid = 0; 540 sc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 541 RF_SHAREABLE|RF_ACTIVE); 542 if (sc->sc_irq == NULL) { 543 device_printf(dev, "could not map interrupt\n"); 544 goto fail_mem; 545 } 546 /* 547 * NB: Network code assumes we are blocked with splimp() 548 * so make sure the IRQ is marked appropriately. 549 */ 550 if (bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_NET | INTR_MPSAFE, 551 NULL, hifn_intr, sc, &sc->sc_intrhand)) { 552 device_printf(dev, "could not setup interrupt\n"); 553 goto fail_intr2; 554 } 555 556 hifn_sessions(sc); 557 558 /* 559 * NB: Keep only the low 16 bits; this masks the chip id 560 * from the 7951. 561 */ 562 rev = READ_REG_1(sc, HIFN_1_REVID) & 0xffff; 563 564 rseg = sc->sc_ramsize / 1024; 565 rbase = 'K'; 566 if (sc->sc_ramsize >= (1024 * 1024)) { 567 rbase = 'M'; 568 rseg /= 1024; 569 } 570 device_printf(sc->sc_dev, "%s, rev %u, %d%cB %cram", 571 hifn_partname(sc), rev, 572 rseg, rbase, sc->sc_drammodel ? 'd' : 's'); 573 if (sc->sc_flags & HIFN_IS_7956) 574 printf(", pll=0x%x<%s clk, %ux mult>", 575 sc->sc_pllconfig, 576 sc->sc_pllconfig & HIFN_PLL_REF_SEL ? "ext" : "pci", 577 2 + 2*((sc->sc_pllconfig & HIFN_PLL_ND) >> 11)); 578 printf("\n"); 579 580 sc->sc_cid = crypto_get_driverid(dev, CRYPTOCAP_F_HARDWARE); 581 if (sc->sc_cid < 0) { 582 device_printf(dev, "could not get crypto driver id\n"); 583 goto fail_intr; 584 } 585 586 WRITE_REG_0(sc, HIFN_0_PUCNFG, 587 READ_REG_0(sc, HIFN_0_PUCNFG) | HIFN_PUCNFG_CHIPID); 588 ena = READ_REG_0(sc, HIFN_0_PUSTAT) & HIFN_PUSTAT_CHIPENA; 589 590 switch (ena) { 591 case HIFN_PUSTAT_ENA_2: 592 crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0); 593 crypto_register(sc->sc_cid, CRYPTO_ARC4, 0, 0); 594 if (sc->sc_flags & HIFN_HAS_AES) 595 crypto_register(sc->sc_cid, CRYPTO_AES_CBC, 0, 0); 596 /*FALLTHROUGH*/ 597 case HIFN_PUSTAT_ENA_1: 598 crypto_register(sc->sc_cid, CRYPTO_MD5, 0, 0); 599 crypto_register(sc->sc_cid, CRYPTO_SHA1, 0, 0); 600 crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0); 601 crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0); 602 crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0); 603 break; 604 } 605 606 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 607 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 608 609 if (sc->sc_flags & (HIFN_HAS_PUBLIC | HIFN_HAS_RNG)) 610 hifn_init_pubrng(sc); 611 612 callout_init(&sc->sc_tickto, CALLOUT_MPSAFE); 613 callout_reset(&sc->sc_tickto, hz, hifn_tick, sc); 614 615 return (0); 616 617 fail_intr: 618 bus_teardown_intr(dev, sc->sc_irq, sc->sc_intrhand); 619 fail_intr2: 620 /* XXX don't store rid */ 621 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq); 622 fail_mem: 623 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 624 bus_dmamem_free(sc->sc_dmat, sc->sc_dma, sc->sc_dmamap); 625 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 626 bus_dma_tag_destroy(sc->sc_dmat); 627 628 /* Turn off DMA polling */ 629 WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | 630 HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); 631 fail_io1: 632 bus_release_resource(dev, SYS_RES_MEMORY, HIFN_BAR1, sc->sc_bar1res); 633 fail_io0: 634 bus_release_resource(dev, SYS_RES_MEMORY, HIFN_BAR0, sc->sc_bar0res); 635 fail_pci: 636 mtx_destroy(&sc->sc_mtx); 637 return (ENXIO); 638 } 639 640 /* 641 * Detach an interface that successfully probed. 642 */ 643 static int 644 hifn_detach(device_t dev) 645 { 646 struct hifn_softc *sc = device_get_softc(dev); 647 648 KASSERT(sc != NULL, ("hifn_detach: null software carrier!")); 649 650 /* disable interrupts */ 651 WRITE_REG_1(sc, HIFN_1_DMA_IER, 0); 652 653 /*XXX other resources */ 654 callout_stop(&sc->sc_tickto); 655 callout_stop(&sc->sc_rngto); 656 #ifdef HIFN_RNDTEST 657 if (sc->sc_rndtest) 658 rndtest_detach(sc->sc_rndtest); 659 #endif 660 661 /* Turn off DMA polling */ 662 WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | 663 HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); 664 665 crypto_unregister_all(sc->sc_cid); 666 667 bus_generic_detach(dev); /*XXX should be no children, right? */ 668 669 bus_teardown_intr(dev, sc->sc_irq, sc->sc_intrhand); 670 /* XXX don't store rid */ 671 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq); 672 673 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap); 674 bus_dmamem_free(sc->sc_dmat, sc->sc_dma, sc->sc_dmamap); 675 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap); 676 bus_dma_tag_destroy(sc->sc_dmat); 677 678 bus_release_resource(dev, SYS_RES_MEMORY, HIFN_BAR1, sc->sc_bar1res); 679 bus_release_resource(dev, SYS_RES_MEMORY, HIFN_BAR0, sc->sc_bar0res); 680 681 mtx_destroy(&sc->sc_mtx); 682 683 return (0); 684 } 685 686 /* 687 * Stop all chip I/O so that the kernel's probe routines don't 688 * get confused by errant DMAs when rebooting. 689 */ 690 static int 691 hifn_shutdown(device_t dev) 692 { 693 #ifdef notyet 694 hifn_stop(device_get_softc(dev)); 695 #endif 696 return (0); 697 } 698 699 /* 700 * Device suspend routine. Stop the interface and save some PCI 701 * settings in case the BIOS doesn't restore them properly on 702 * resume. 703 */ 704 static int 705 hifn_suspend(device_t dev) 706 { 707 struct hifn_softc *sc = device_get_softc(dev); 708 #ifdef notyet 709 hifn_stop(sc); 710 #endif 711 sc->sc_suspended = 1; 712 713 return (0); 714 } 715 716 /* 717 * Device resume routine. Restore some PCI settings in case the BIOS 718 * doesn't, re-enable busmastering, and restart the interface if 719 * appropriate. 720 */ 721 static int 722 hifn_resume(device_t dev) 723 { 724 struct hifn_softc *sc = device_get_softc(dev); 725 #ifdef notyet 726 /* reenable busmastering */ 727 pci_enable_busmaster(dev); 728 pci_enable_io(dev, HIFN_RES); 729 730 /* reinitialize interface if necessary */ 731 if (ifp->if_flags & IFF_UP) 732 rl_init(sc); 733 #endif 734 sc->sc_suspended = 0; 735 736 return (0); 737 } 738 739 static int 740 hifn_init_pubrng(struct hifn_softc *sc) 741 { 742 u_int32_t r; 743 int i; 744 745 #ifdef HIFN_RNDTEST 746 sc->sc_rndtest = rndtest_attach(sc->sc_dev); 747 if (sc->sc_rndtest) 748 sc->sc_harvest = rndtest_harvest; 749 else 750 sc->sc_harvest = default_harvest; 751 #else 752 sc->sc_harvest = default_harvest; 753 #endif 754 if ((sc->sc_flags & HIFN_IS_7811) == 0) { 755 /* Reset 7951 public key/rng engine */ 756 WRITE_REG_1(sc, HIFN_1_PUB_RESET, 757 READ_REG_1(sc, HIFN_1_PUB_RESET) | HIFN_PUBRST_RESET); 758 759 for (i = 0; i < 100; i++) { 760 DELAY(1000); 761 if ((READ_REG_1(sc, HIFN_1_PUB_RESET) & 762 HIFN_PUBRST_RESET) == 0) 763 break; 764 } 765 766 if (i == 100) { 767 device_printf(sc->sc_dev, "public key init failed\n"); 768 return (1); 769 } 770 } 771 772 /* Enable the rng, if available */ 773 if (sc->sc_flags & HIFN_HAS_RNG) { 774 if (sc->sc_flags & HIFN_IS_7811) { 775 r = READ_REG_1(sc, HIFN_1_7811_RNGENA); 776 if (r & HIFN_7811_RNGENA_ENA) { 777 r &= ~HIFN_7811_RNGENA_ENA; 778 WRITE_REG_1(sc, HIFN_1_7811_RNGENA, r); 779 } 780 WRITE_REG_1(sc, HIFN_1_7811_RNGCFG, 781 HIFN_7811_RNGCFG_DEFL); 782 r |= HIFN_7811_RNGENA_ENA; 783 WRITE_REG_1(sc, HIFN_1_7811_RNGENA, r); 784 } else 785 WRITE_REG_1(sc, HIFN_1_RNG_CONFIG, 786 READ_REG_1(sc, HIFN_1_RNG_CONFIG) | 787 HIFN_RNGCFG_ENA); 788 789 sc->sc_rngfirst = 1; 790 if (hz >= 100) 791 sc->sc_rnghz = hz / 100; 792 else 793 sc->sc_rnghz = 1; 794 callout_init(&sc->sc_rngto, CALLOUT_MPSAFE); 795 callout_reset(&sc->sc_rngto, sc->sc_rnghz, hifn_rng, sc); 796 } 797 798 /* Enable public key engine, if available */ 799 if (sc->sc_flags & HIFN_HAS_PUBLIC) { 800 WRITE_REG_1(sc, HIFN_1_PUB_IEN, HIFN_PUBIEN_DONE); 801 sc->sc_dmaier |= HIFN_DMAIER_PUBDONE; 802 WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier); 803 #ifdef HIFN_VULCANDEV 804 sc->sc_pkdev = make_dev(&vulcanpk_cdevsw, 0, 805 UID_ROOT, GID_WHEEL, 0666, 806 "vulcanpk"); 807 sc->sc_pkdev->si_drv1 = sc; 808 #endif 809 } 810 811 return (0); 812 } 813 814 static void 815 hifn_rng(void *vsc) 816 { 817 #define RANDOM_BITS(n) (n)*sizeof (u_int32_t), (n)*sizeof (u_int32_t)*NBBY, 0 818 struct hifn_softc *sc = vsc; 819 u_int32_t sts, num[2]; 820 int i; 821 822 if (sc->sc_flags & HIFN_IS_7811) { 823 /* ONLY VALID ON 7811!!!! */ 824 for (i = 0; i < 5; i++) { 825 sts = READ_REG_1(sc, HIFN_1_7811_RNGSTS); 826 if (sts & HIFN_7811_RNGSTS_UFL) { 827 device_printf(sc->sc_dev, 828 "RNG underflow: disabling\n"); 829 return; 830 } 831 if ((sts & HIFN_7811_RNGSTS_RDY) == 0) 832 break; 833 834 /* 835 * There are at least two words in the RNG FIFO 836 * at this point. 837 */ 838 num[0] = READ_REG_1(sc, HIFN_1_7811_RNGDAT); 839 num[1] = READ_REG_1(sc, HIFN_1_7811_RNGDAT); 840 /* NB: discard first data read */ 841 if (sc->sc_rngfirst) 842 sc->sc_rngfirst = 0; 843 else 844 (*sc->sc_harvest)(sc->sc_rndtest, 845 num, sizeof (num)); 846 } 847 } else { 848 num[0] = READ_REG_1(sc, HIFN_1_RNG_DATA); 849 850 /* NB: discard first data read */ 851 if (sc->sc_rngfirst) 852 sc->sc_rngfirst = 0; 853 else 854 (*sc->sc_harvest)(sc->sc_rndtest, 855 num, sizeof (num[0])); 856 } 857 858 callout_reset(&sc->sc_rngto, sc->sc_rnghz, hifn_rng, sc); 859 #undef RANDOM_BITS 860 } 861 862 static void 863 hifn_puc_wait(struct hifn_softc *sc) 864 { 865 int i; 866 int reg = HIFN_0_PUCTRL; 867 868 if (sc->sc_flags & HIFN_IS_7956) { 869 reg = HIFN_0_PUCTRL2; 870 } 871 872 for (i = 5000; i > 0; i--) { 873 DELAY(1); 874 if (!(READ_REG_0(sc, reg) & HIFN_PUCTRL_RESET)) 875 break; 876 } 877 if (!i) 878 device_printf(sc->sc_dev, "proc unit did not reset\n"); 879 } 880 881 /* 882 * Reset the processing unit. 883 */ 884 static void 885 hifn_reset_puc(struct hifn_softc *sc) 886 { 887 /* Reset processing unit */ 888 int reg = HIFN_0_PUCTRL; 889 890 if (sc->sc_flags & HIFN_IS_7956) { 891 reg = HIFN_0_PUCTRL2; 892 } 893 WRITE_REG_0(sc, reg, HIFN_PUCTRL_DMAENA); 894 895 hifn_puc_wait(sc); 896 } 897 898 /* 899 * Set the Retry and TRDY registers; note that we set them to 900 * zero because the 7811 locks up when forced to retry (section 901 * 3.6 of "Specification Update SU-0014-04". Not clear if we 902 * should do this for all Hifn parts, but it doesn't seem to hurt. 903 */ 904 static void 905 hifn_set_retry(struct hifn_softc *sc) 906 { 907 /* NB: RETRY only responds to 8-bit reads/writes */ 908 pci_write_config(sc->sc_dev, HIFN_RETRY_TIMEOUT, 0, 1); 909 pci_write_config(sc->sc_dev, HIFN_TRDY_TIMEOUT, 0, 4); 910 } 911 912 /* 913 * Resets the board. Values in the regesters are left as is 914 * from the reset (i.e. initial values are assigned elsewhere). 915 */ 916 static void 917 hifn_reset_board(struct hifn_softc *sc, int full) 918 { 919 u_int32_t reg; 920 921 /* 922 * Set polling in the DMA configuration register to zero. 0x7 avoids 923 * resetting the board and zeros out the other fields. 924 */ 925 WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | 926 HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); 927 928 /* 929 * Now that polling has been disabled, we have to wait 1 ms 930 * before resetting the board. 931 */ 932 DELAY(1000); 933 934 /* Reset the DMA unit */ 935 if (full) { 936 WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MODE); 937 DELAY(1000); 938 } else { 939 WRITE_REG_1(sc, HIFN_1_DMA_CNFG, 940 HIFN_DMACNFG_MODE | HIFN_DMACNFG_MSTRESET); 941 hifn_reset_puc(sc); 942 } 943 944 KASSERT(sc->sc_dma != NULL, ("hifn_reset_board: null DMA tag!")); 945 bzero(sc->sc_dma, sizeof(*sc->sc_dma)); 946 947 /* Bring dma unit out of reset */ 948 WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | 949 HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); 950 951 hifn_puc_wait(sc); 952 hifn_set_retry(sc); 953 954 if (sc->sc_flags & HIFN_IS_7811) { 955 for (reg = 0; reg < 1000; reg++) { 956 if (READ_REG_1(sc, HIFN_1_7811_MIPSRST) & 957 HIFN_MIPSRST_CRAMINIT) 958 break; 959 DELAY(1000); 960 } 961 if (reg == 1000) 962 printf(": cram init timeout\n"); 963 } else { 964 /* set up DMA configuration register #2 */ 965 /* turn off all PK and BAR0 swaps */ 966 WRITE_REG_1(sc, HIFN_1_DMA_CNFG2, 967 (3 << HIFN_DMACNFG2_INIT_WRITE_BURST_SHIFT)| 968 (3 << HIFN_DMACNFG2_INIT_READ_BURST_SHIFT)| 969 (2 << HIFN_DMACNFG2_TGT_WRITE_BURST_SHIFT)| 970 (2 << HIFN_DMACNFG2_TGT_READ_BURST_SHIFT)); 971 } 972 973 } 974 975 static u_int32_t 976 hifn_next_signature(u_int32_t a, u_int cnt) 977 { 978 int i; 979 u_int32_t v; 980 981 for (i = 0; i < cnt; i++) { 982 983 /* get the parity */ 984 v = a & 0x80080125; 985 v ^= v >> 16; 986 v ^= v >> 8; 987 v ^= v >> 4; 988 v ^= v >> 2; 989 v ^= v >> 1; 990 991 a = (v & 1) ^ (a << 1); 992 } 993 994 return a; 995 } 996 997 struct pci2id { 998 u_short pci_vendor; 999 u_short pci_prod; 1000 char card_id[13]; 1001 }; 1002 static struct pci2id pci2id[] = { 1003 { 1004 PCI_VENDOR_HIFN, 1005 PCI_PRODUCT_HIFN_7951, 1006 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 1007 0x00, 0x00, 0x00, 0x00, 0x00 } 1008 }, { 1009 PCI_VENDOR_HIFN, 1010 PCI_PRODUCT_HIFN_7955, 1011 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 1012 0x00, 0x00, 0x00, 0x00, 0x00 } 1013 }, { 1014 PCI_VENDOR_HIFN, 1015 PCI_PRODUCT_HIFN_7956, 1016 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 1017 0x00, 0x00, 0x00, 0x00, 0x00 } 1018 }, { 1019 PCI_VENDOR_NETSEC, 1020 PCI_PRODUCT_NETSEC_7751, 1021 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 1022 0x00, 0x00, 0x00, 0x00, 0x00 } 1023 }, { 1024 PCI_VENDOR_INVERTEX, 1025 PCI_PRODUCT_INVERTEX_AEON, 1026 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 1027 0x00, 0x00, 0x00, 0x00, 0x00 } 1028 }, { 1029 PCI_VENDOR_HIFN, 1030 PCI_PRODUCT_HIFN_7811, 1031 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 1032 0x00, 0x00, 0x00, 0x00, 0x00 } 1033 }, { 1034 /* 1035 * Other vendors share this PCI ID as well, such as 1036 * http://www.powercrypt.com, and obviously they also 1037 * use the same key. 1038 */ 1039 PCI_VENDOR_HIFN, 1040 PCI_PRODUCT_HIFN_7751, 1041 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 1042 0x00, 0x00, 0x00, 0x00, 0x00 } 1043 }, 1044 }; 1045 1046 /* 1047 * Checks to see if crypto is already enabled. If crypto isn't enable, 1048 * "hifn_enable_crypto" is called to enable it. The check is important, 1049 * as enabling crypto twice will lock the board. 1050 */ 1051 static int 1052 hifn_enable_crypto(struct hifn_softc *sc) 1053 { 1054 u_int32_t dmacfg, ramcfg, encl, addr, i; 1055 char *offtbl = NULL; 1056 1057 for (i = 0; i < sizeof(pci2id)/sizeof(pci2id[0]); i++) { 1058 if (pci2id[i].pci_vendor == pci_get_vendor(sc->sc_dev) && 1059 pci2id[i].pci_prod == pci_get_device(sc->sc_dev)) { 1060 offtbl = pci2id[i].card_id; 1061 break; 1062 } 1063 } 1064 if (offtbl == NULL) { 1065 device_printf(sc->sc_dev, "Unknown card!\n"); 1066 return (1); 1067 } 1068 1069 ramcfg = READ_REG_0(sc, HIFN_0_PUCNFG); 1070 dmacfg = READ_REG_1(sc, HIFN_1_DMA_CNFG); 1071 1072 /* 1073 * The RAM config register's encrypt level bit needs to be set before 1074 * every read performed on the encryption level register. 1075 */ 1076 WRITE_REG_0(sc, HIFN_0_PUCNFG, ramcfg | HIFN_PUCNFG_CHIPID); 1077 1078 encl = READ_REG_0(sc, HIFN_0_PUSTAT) & HIFN_PUSTAT_CHIPENA; 1079 1080 /* 1081 * Make sure we don't re-unlock. Two unlocks kills chip until the 1082 * next reboot. 1083 */ 1084 if (encl == HIFN_PUSTAT_ENA_1 || encl == HIFN_PUSTAT_ENA_2) { 1085 #ifdef HIFN_DEBUG 1086 if (hifn_debug) 1087 device_printf(sc->sc_dev, 1088 "Strong crypto already enabled!\n"); 1089 #endif 1090 goto report; 1091 } 1092 1093 if (encl != 0 && encl != HIFN_PUSTAT_ENA_0) { 1094 #ifdef HIFN_DEBUG 1095 if (hifn_debug) 1096 device_printf(sc->sc_dev, 1097 "Unknown encryption level 0x%x\n", encl); 1098 #endif 1099 return 1; 1100 } 1101 1102 WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_UNLOCK | 1103 HIFN_DMACNFG_MSTRESET | HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE); 1104 DELAY(1000); 1105 addr = READ_REG_1(sc, HIFN_UNLOCK_SECRET1); 1106 DELAY(1000); 1107 WRITE_REG_1(sc, HIFN_UNLOCK_SECRET2, 0); 1108 DELAY(1000); 1109 1110 for (i = 0; i <= 12; i++) { 1111 addr = hifn_next_signature(addr, offtbl[i] + 0x101); 1112 WRITE_REG_1(sc, HIFN_UNLOCK_SECRET2, addr); 1113 1114 DELAY(1000); 1115 } 1116 1117 WRITE_REG_0(sc, HIFN_0_PUCNFG, ramcfg | HIFN_PUCNFG_CHIPID); 1118 encl = READ_REG_0(sc, HIFN_0_PUSTAT) & HIFN_PUSTAT_CHIPENA; 1119 1120 #ifdef HIFN_DEBUG 1121 if (hifn_debug) { 1122 if (encl != HIFN_PUSTAT_ENA_1 && encl != HIFN_PUSTAT_ENA_2) 1123 device_printf(sc->sc_dev, "Engine is permanently " 1124 "locked until next system reset!\n"); 1125 else 1126 device_printf(sc->sc_dev, "Engine enabled " 1127 "successfully!\n"); 1128 } 1129 #endif 1130 1131 report: 1132 WRITE_REG_0(sc, HIFN_0_PUCNFG, ramcfg); 1133 WRITE_REG_1(sc, HIFN_1_DMA_CNFG, dmacfg); 1134 1135 switch (encl) { 1136 case HIFN_PUSTAT_ENA_1: 1137 case HIFN_PUSTAT_ENA_2: 1138 break; 1139 case HIFN_PUSTAT_ENA_0: 1140 default: 1141 device_printf(sc->sc_dev, "disabled"); 1142 break; 1143 } 1144 1145 return 0; 1146 } 1147 1148 /* 1149 * Give initial values to the registers listed in the "Register Space" 1150 * section of the HIFN Software Development reference manual. 1151 */ 1152 static void 1153 hifn_init_pci_registers(struct hifn_softc *sc) 1154 { 1155 /* write fixed values needed by the Initialization registers */ 1156 WRITE_REG_0(sc, HIFN_0_PUCTRL, HIFN_PUCTRL_DMAENA); 1157 WRITE_REG_0(sc, HIFN_0_FIFOCNFG, HIFN_FIFOCNFG_THRESHOLD); 1158 WRITE_REG_0(sc, HIFN_0_PUIER, HIFN_PUIER_DSTOVER); 1159 1160 /* write all 4 ring address registers */ 1161 WRITE_REG_1(sc, HIFN_1_DMA_CRAR, sc->sc_dma_physaddr + 1162 offsetof(struct hifn_dma, cmdr[0])); 1163 WRITE_REG_1(sc, HIFN_1_DMA_SRAR, sc->sc_dma_physaddr + 1164 offsetof(struct hifn_dma, srcr[0])); 1165 WRITE_REG_1(sc, HIFN_1_DMA_DRAR, sc->sc_dma_physaddr + 1166 offsetof(struct hifn_dma, dstr[0])); 1167 WRITE_REG_1(sc, HIFN_1_DMA_RRAR, sc->sc_dma_physaddr + 1168 offsetof(struct hifn_dma, resr[0])); 1169 1170 DELAY(2000); 1171 1172 /* write status register */ 1173 WRITE_REG_1(sc, HIFN_1_DMA_CSR, 1174 HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS | 1175 HIFN_DMACSR_S_CTRL_DIS | HIFN_DMACSR_C_CTRL_DIS | 1176 HIFN_DMACSR_D_ABORT | HIFN_DMACSR_D_DONE | HIFN_DMACSR_D_LAST | 1177 HIFN_DMACSR_D_WAIT | HIFN_DMACSR_D_OVER | 1178 HIFN_DMACSR_R_ABORT | HIFN_DMACSR_R_DONE | HIFN_DMACSR_R_LAST | 1179 HIFN_DMACSR_R_WAIT | HIFN_DMACSR_R_OVER | 1180 HIFN_DMACSR_S_ABORT | HIFN_DMACSR_S_DONE | HIFN_DMACSR_S_LAST | 1181 HIFN_DMACSR_S_WAIT | 1182 HIFN_DMACSR_C_ABORT | HIFN_DMACSR_C_DONE | HIFN_DMACSR_C_LAST | 1183 HIFN_DMACSR_C_WAIT | 1184 HIFN_DMACSR_ENGINE | 1185 ((sc->sc_flags & HIFN_HAS_PUBLIC) ? 1186 HIFN_DMACSR_PUBDONE : 0) | 1187 ((sc->sc_flags & HIFN_IS_7811) ? 1188 HIFN_DMACSR_ILLW | HIFN_DMACSR_ILLR : 0)); 1189 1190 sc->sc_d_busy = sc->sc_r_busy = sc->sc_s_busy = sc->sc_c_busy = 0; 1191 sc->sc_dmaier |= HIFN_DMAIER_R_DONE | HIFN_DMAIER_C_ABORT | 1192 HIFN_DMAIER_D_OVER | HIFN_DMAIER_R_OVER | 1193 HIFN_DMAIER_S_ABORT | HIFN_DMAIER_D_ABORT | HIFN_DMAIER_R_ABORT | 1194 ((sc->sc_flags & HIFN_IS_7811) ? 1195 HIFN_DMAIER_ILLW | HIFN_DMAIER_ILLR : 0); 1196 sc->sc_dmaier &= ~HIFN_DMAIER_C_WAIT; 1197 WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier); 1198 1199 1200 if (sc->sc_flags & HIFN_IS_7956) { 1201 u_int32_t pll; 1202 1203 WRITE_REG_0(sc, HIFN_0_PUCNFG, HIFN_PUCNFG_COMPSING | 1204 HIFN_PUCNFG_TCALLPHASES | 1205 HIFN_PUCNFG_TCDRVTOTEM | HIFN_PUCNFG_BUS32); 1206 1207 /* turn off the clocks and insure bypass is set */ 1208 pll = READ_REG_1(sc, HIFN_1_PLL); 1209 pll = (pll &~ (HIFN_PLL_PK_CLK_SEL | HIFN_PLL_PE_CLK_SEL)) 1210 | HIFN_PLL_BP | HIFN_PLL_MBSET; 1211 WRITE_REG_1(sc, HIFN_1_PLL, pll); 1212 DELAY(10*1000); /* 10ms */ 1213 1214 /* change configuration */ 1215 pll = (pll &~ HIFN_PLL_CONFIG) | sc->sc_pllconfig; 1216 WRITE_REG_1(sc, HIFN_1_PLL, pll); 1217 DELAY(10*1000); /* 10ms */ 1218 1219 /* disable bypass */ 1220 pll &= ~HIFN_PLL_BP; 1221 WRITE_REG_1(sc, HIFN_1_PLL, pll); 1222 /* enable clocks with new configuration */ 1223 pll |= HIFN_PLL_PK_CLK_SEL | HIFN_PLL_PE_CLK_SEL; 1224 WRITE_REG_1(sc, HIFN_1_PLL, pll); 1225 } else { 1226 WRITE_REG_0(sc, HIFN_0_PUCNFG, HIFN_PUCNFG_COMPSING | 1227 HIFN_PUCNFG_DRFR_128 | HIFN_PUCNFG_TCALLPHASES | 1228 HIFN_PUCNFG_TCDRVTOTEM | HIFN_PUCNFG_BUS32 | 1229 (sc->sc_drammodel ? HIFN_PUCNFG_DRAM : HIFN_PUCNFG_SRAM)); 1230 } 1231 1232 WRITE_REG_0(sc, HIFN_0_PUISR, HIFN_PUISR_DSTOVER); 1233 WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET | 1234 HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE | HIFN_DMACNFG_LAST | 1235 ((HIFN_POLL_FREQUENCY << 16 ) & HIFN_DMACNFG_POLLFREQ) | 1236 ((HIFN_POLL_SCALAR << 8) & HIFN_DMACNFG_POLLINVAL)); 1237 } 1238 1239 /* 1240 * The maximum number of sessions supported by the card 1241 * is dependent on the amount of context ram, which 1242 * encryption algorithms are enabled, and how compression 1243 * is configured. This should be configured before this 1244 * routine is called. 1245 */ 1246 static void 1247 hifn_sessions(struct hifn_softc *sc) 1248 { 1249 u_int32_t pucnfg; 1250 int ctxsize; 1251 1252 pucnfg = READ_REG_0(sc, HIFN_0_PUCNFG); 1253 1254 if (pucnfg & HIFN_PUCNFG_COMPSING) { 1255 if (pucnfg & HIFN_PUCNFG_ENCCNFG) 1256 ctxsize = 128; 1257 else 1258 ctxsize = 512; 1259 /* 1260 * 7955/7956 has internal context memory of 32K 1261 */ 1262 if (sc->sc_flags & HIFN_IS_7956) 1263 sc->sc_maxses = 32768 / ctxsize; 1264 else 1265 sc->sc_maxses = 1 + 1266 ((sc->sc_ramsize - 32768) / ctxsize); 1267 } else 1268 sc->sc_maxses = sc->sc_ramsize / 16384; 1269 1270 if (sc->sc_maxses > 2048) 1271 sc->sc_maxses = 2048; 1272 } 1273 1274 /* 1275 * Determine ram type (sram or dram). Board should be just out of a reset 1276 * state when this is called. 1277 */ 1278 static int 1279 hifn_ramtype(struct hifn_softc *sc) 1280 { 1281 u_int8_t data[8], dataexpect[8]; 1282 int i; 1283 1284 for (i = 0; i < sizeof(data); i++) 1285 data[i] = dataexpect[i] = 0x55; 1286 if (hifn_writeramaddr(sc, 0, data)) 1287 return (-1); 1288 if (hifn_readramaddr(sc, 0, data)) 1289 return (-1); 1290 if (bcmp(data, dataexpect, sizeof(data)) != 0) { 1291 sc->sc_drammodel = 1; 1292 return (0); 1293 } 1294 1295 for (i = 0; i < sizeof(data); i++) 1296 data[i] = dataexpect[i] = 0xaa; 1297 if (hifn_writeramaddr(sc, 0, data)) 1298 return (-1); 1299 if (hifn_readramaddr(sc, 0, data)) 1300 return (-1); 1301 if (bcmp(data, dataexpect, sizeof(data)) != 0) { 1302 sc->sc_drammodel = 1; 1303 return (0); 1304 } 1305 1306 return (0); 1307 } 1308 1309 #define HIFN_SRAM_MAX (32 << 20) 1310 #define HIFN_SRAM_STEP_SIZE 16384 1311 #define HIFN_SRAM_GRANULARITY (HIFN_SRAM_MAX / HIFN_SRAM_STEP_SIZE) 1312 1313 static int 1314 hifn_sramsize(struct hifn_softc *sc) 1315 { 1316 u_int32_t a; 1317 u_int8_t data[8]; 1318 u_int8_t dataexpect[sizeof(data)]; 1319 int32_t i; 1320 1321 for (i = 0; i < sizeof(data); i++) 1322 data[i] = dataexpect[i] = i ^ 0x5a; 1323 1324 for (i = HIFN_SRAM_GRANULARITY - 1; i >= 0; i--) { 1325 a = i * HIFN_SRAM_STEP_SIZE; 1326 bcopy(&i, data, sizeof(i)); 1327 hifn_writeramaddr(sc, a, data); 1328 } 1329 1330 for (i = 0; i < HIFN_SRAM_GRANULARITY; i++) { 1331 a = i * HIFN_SRAM_STEP_SIZE; 1332 bcopy(&i, dataexpect, sizeof(i)); 1333 if (hifn_readramaddr(sc, a, data) < 0) 1334 return (0); 1335 if (bcmp(data, dataexpect, sizeof(data)) != 0) 1336 return (0); 1337 sc->sc_ramsize = a + HIFN_SRAM_STEP_SIZE; 1338 } 1339 1340 return (0); 1341 } 1342 1343 /* 1344 * XXX For dram boards, one should really try all of the 1345 * HIFN_PUCNFG_DSZ_*'s. This just assumes that PUCNFG 1346 * is already set up correctly. 1347 */ 1348 static int 1349 hifn_dramsize(struct hifn_softc *sc) 1350 { 1351 u_int32_t cnfg; 1352 1353 if (sc->sc_flags & HIFN_IS_7956) { 1354 /* 1355 * 7955/7956 have a fixed internal ram of only 32K. 1356 */ 1357 sc->sc_ramsize = 32768; 1358 } else { 1359 cnfg = READ_REG_0(sc, HIFN_0_PUCNFG) & 1360 HIFN_PUCNFG_DRAMMASK; 1361 sc->sc_ramsize = 1 << ((cnfg >> 13) + 18); 1362 } 1363 return (0); 1364 } 1365 1366 static void 1367 hifn_alloc_slot(struct hifn_softc *sc, int *cmdp, int *srcp, int *dstp, int *resp) 1368 { 1369 struct hifn_dma *dma = sc->sc_dma; 1370 1371 if (dma->cmdi == HIFN_D_CMD_RSIZE) { 1372 dma->cmdi = 0; 1373 dma->cmdr[HIFN_D_CMD_RSIZE].l = htole32(HIFN_D_VALID | 1374 HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 1375 HIFN_CMDR_SYNC(sc, HIFN_D_CMD_RSIZE, 1376 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1377 } 1378 *cmdp = dma->cmdi++; 1379 dma->cmdk = dma->cmdi; 1380 1381 if (dma->srci == HIFN_D_SRC_RSIZE) { 1382 dma->srci = 0; 1383 dma->srcr[HIFN_D_SRC_RSIZE].l = htole32(HIFN_D_VALID | 1384 HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 1385 HIFN_SRCR_SYNC(sc, HIFN_D_SRC_RSIZE, 1386 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1387 } 1388 *srcp = dma->srci++; 1389 dma->srck = dma->srci; 1390 1391 if (dma->dsti == HIFN_D_DST_RSIZE) { 1392 dma->dsti = 0; 1393 dma->dstr[HIFN_D_DST_RSIZE].l = htole32(HIFN_D_VALID | 1394 HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 1395 HIFN_DSTR_SYNC(sc, HIFN_D_DST_RSIZE, 1396 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1397 } 1398 *dstp = dma->dsti++; 1399 dma->dstk = dma->dsti; 1400 1401 if (dma->resi == HIFN_D_RES_RSIZE) { 1402 dma->resi = 0; 1403 dma->resr[HIFN_D_RES_RSIZE].l = htole32(HIFN_D_VALID | 1404 HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 1405 HIFN_RESR_SYNC(sc, HIFN_D_RES_RSIZE, 1406 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1407 } 1408 *resp = dma->resi++; 1409 dma->resk = dma->resi; 1410 } 1411 1412 static int 1413 hifn_writeramaddr(struct hifn_softc *sc, int addr, u_int8_t *data) 1414 { 1415 struct hifn_dma *dma = sc->sc_dma; 1416 hifn_base_command_t wc; 1417 const u_int32_t masks = HIFN_D_VALID | HIFN_D_LAST | HIFN_D_MASKDONEIRQ; 1418 int r, cmdi, resi, srci, dsti; 1419 1420 wc.masks = htole16(3 << 13); 1421 wc.session_num = htole16(addr >> 14); 1422 wc.total_source_count = htole16(8); 1423 wc.total_dest_count = htole16(addr & 0x3fff); 1424 1425 hifn_alloc_slot(sc, &cmdi, &srci, &dsti, &resi); 1426 1427 WRITE_REG_1(sc, HIFN_1_DMA_CSR, 1428 HIFN_DMACSR_C_CTRL_ENA | HIFN_DMACSR_S_CTRL_ENA | 1429 HIFN_DMACSR_D_CTRL_ENA | HIFN_DMACSR_R_CTRL_ENA); 1430 1431 /* build write command */ 1432 bzero(dma->command_bufs[cmdi], HIFN_MAX_COMMAND); 1433 *(hifn_base_command_t *)dma->command_bufs[cmdi] = wc; 1434 bcopy(data, &dma->test_src, sizeof(dma->test_src)); 1435 1436 dma->srcr[srci].p = htole32(sc->sc_dma_physaddr 1437 + offsetof(struct hifn_dma, test_src)); 1438 dma->dstr[dsti].p = htole32(sc->sc_dma_physaddr 1439 + offsetof(struct hifn_dma, test_dst)); 1440 1441 dma->cmdr[cmdi].l = htole32(16 | masks); 1442 dma->srcr[srci].l = htole32(8 | masks); 1443 dma->dstr[dsti].l = htole32(4 | masks); 1444 dma->resr[resi].l = htole32(4 | masks); 1445 1446 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1447 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1448 1449 for (r = 10000; r >= 0; r--) { 1450 DELAY(10); 1451 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1452 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1453 if ((dma->resr[resi].l & htole32(HIFN_D_VALID)) == 0) 1454 break; 1455 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1456 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1457 } 1458 if (r == 0) { 1459 device_printf(sc->sc_dev, "writeramaddr -- " 1460 "result[%d](addr %d) still valid\n", resi, addr); 1461 r = -1; 1462 return (-1); 1463 } else 1464 r = 0; 1465 1466 WRITE_REG_1(sc, HIFN_1_DMA_CSR, 1467 HIFN_DMACSR_C_CTRL_DIS | HIFN_DMACSR_S_CTRL_DIS | 1468 HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS); 1469 1470 return (r); 1471 } 1472 1473 static int 1474 hifn_readramaddr(struct hifn_softc *sc, int addr, u_int8_t *data) 1475 { 1476 struct hifn_dma *dma = sc->sc_dma; 1477 hifn_base_command_t rc; 1478 const u_int32_t masks = HIFN_D_VALID | HIFN_D_LAST | HIFN_D_MASKDONEIRQ; 1479 int r, cmdi, srci, dsti, resi; 1480 1481 rc.masks = htole16(2 << 13); 1482 rc.session_num = htole16(addr >> 14); 1483 rc.total_source_count = htole16(addr & 0x3fff); 1484 rc.total_dest_count = htole16(8); 1485 1486 hifn_alloc_slot(sc, &cmdi, &srci, &dsti, &resi); 1487 1488 WRITE_REG_1(sc, HIFN_1_DMA_CSR, 1489 HIFN_DMACSR_C_CTRL_ENA | HIFN_DMACSR_S_CTRL_ENA | 1490 HIFN_DMACSR_D_CTRL_ENA | HIFN_DMACSR_R_CTRL_ENA); 1491 1492 bzero(dma->command_bufs[cmdi], HIFN_MAX_COMMAND); 1493 *(hifn_base_command_t *)dma->command_bufs[cmdi] = rc; 1494 1495 dma->srcr[srci].p = htole32(sc->sc_dma_physaddr + 1496 offsetof(struct hifn_dma, test_src)); 1497 dma->test_src = 0; 1498 dma->dstr[dsti].p = htole32(sc->sc_dma_physaddr + 1499 offsetof(struct hifn_dma, test_dst)); 1500 dma->test_dst = 0; 1501 dma->cmdr[cmdi].l = htole32(8 | masks); 1502 dma->srcr[srci].l = htole32(8 | masks); 1503 dma->dstr[dsti].l = htole32(8 | masks); 1504 dma->resr[resi].l = htole32(HIFN_MAX_RESULT | masks); 1505 1506 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1507 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1508 1509 for (r = 10000; r >= 0; r--) { 1510 DELAY(10); 1511 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1512 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1513 if ((dma->resr[resi].l & htole32(HIFN_D_VALID)) == 0) 1514 break; 1515 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1516 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1517 } 1518 if (r == 0) { 1519 device_printf(sc->sc_dev, "readramaddr -- " 1520 "result[%d](addr %d) still valid\n", resi, addr); 1521 r = -1; 1522 } else { 1523 r = 0; 1524 bcopy(&dma->test_dst, data, sizeof(dma->test_dst)); 1525 } 1526 1527 WRITE_REG_1(sc, HIFN_1_DMA_CSR, 1528 HIFN_DMACSR_C_CTRL_DIS | HIFN_DMACSR_S_CTRL_DIS | 1529 HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS); 1530 1531 return (r); 1532 } 1533 1534 /* 1535 * Initialize the descriptor rings. 1536 */ 1537 static void 1538 hifn_init_dma(struct hifn_softc *sc) 1539 { 1540 struct hifn_dma *dma = sc->sc_dma; 1541 int i; 1542 1543 hifn_set_retry(sc); 1544 1545 /* initialize static pointer values */ 1546 for (i = 0; i < HIFN_D_CMD_RSIZE; i++) 1547 dma->cmdr[i].p = htole32(sc->sc_dma_physaddr + 1548 offsetof(struct hifn_dma, command_bufs[i][0])); 1549 for (i = 0; i < HIFN_D_RES_RSIZE; i++) 1550 dma->resr[i].p = htole32(sc->sc_dma_physaddr + 1551 offsetof(struct hifn_dma, result_bufs[i][0])); 1552 1553 dma->cmdr[HIFN_D_CMD_RSIZE].p = 1554 htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, cmdr[0])); 1555 dma->srcr[HIFN_D_SRC_RSIZE].p = 1556 htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, srcr[0])); 1557 dma->dstr[HIFN_D_DST_RSIZE].p = 1558 htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, dstr[0])); 1559 dma->resr[HIFN_D_RES_RSIZE].p = 1560 htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, resr[0])); 1561 1562 dma->cmdu = dma->srcu = dma->dstu = dma->resu = 0; 1563 dma->cmdi = dma->srci = dma->dsti = dma->resi = 0; 1564 dma->cmdk = dma->srck = dma->dstk = dma->resk = 0; 1565 } 1566 1567 /* 1568 * Writes out the raw command buffer space. Returns the 1569 * command buffer size. 1570 */ 1571 static u_int 1572 hifn_write_command(struct hifn_command *cmd, u_int8_t *buf) 1573 { 1574 u_int8_t *buf_pos; 1575 hifn_base_command_t *base_cmd; 1576 hifn_mac_command_t *mac_cmd; 1577 hifn_crypt_command_t *cry_cmd; 1578 int using_mac, using_crypt, len, ivlen; 1579 u_int32_t dlen, slen; 1580 1581 buf_pos = buf; 1582 using_mac = cmd->base_masks & HIFN_BASE_CMD_MAC; 1583 using_crypt = cmd->base_masks & HIFN_BASE_CMD_CRYPT; 1584 1585 base_cmd = (hifn_base_command_t *)buf_pos; 1586 base_cmd->masks = htole16(cmd->base_masks); 1587 slen = cmd->src_mapsize; 1588 if (cmd->sloplen) 1589 dlen = cmd->dst_mapsize - cmd->sloplen + sizeof(u_int32_t); 1590 else 1591 dlen = cmd->dst_mapsize; 1592 base_cmd->total_source_count = htole16(slen & HIFN_BASE_CMD_LENMASK_LO); 1593 base_cmd->total_dest_count = htole16(dlen & HIFN_BASE_CMD_LENMASK_LO); 1594 dlen >>= 16; 1595 slen >>= 16; 1596 base_cmd->session_num = htole16( 1597 ((slen << HIFN_BASE_CMD_SRCLEN_S) & HIFN_BASE_CMD_SRCLEN_M) | 1598 ((dlen << HIFN_BASE_CMD_DSTLEN_S) & HIFN_BASE_CMD_DSTLEN_M)); 1599 buf_pos += sizeof(hifn_base_command_t); 1600 1601 if (using_mac) { 1602 mac_cmd = (hifn_mac_command_t *)buf_pos; 1603 dlen = cmd->maccrd->crd_len; 1604 mac_cmd->source_count = htole16(dlen & 0xffff); 1605 dlen >>= 16; 1606 mac_cmd->masks = htole16(cmd->mac_masks | 1607 ((dlen << HIFN_MAC_CMD_SRCLEN_S) & HIFN_MAC_CMD_SRCLEN_M)); 1608 mac_cmd->header_skip = htole16(cmd->maccrd->crd_skip); 1609 mac_cmd->reserved = 0; 1610 buf_pos += sizeof(hifn_mac_command_t); 1611 } 1612 1613 if (using_crypt) { 1614 cry_cmd = (hifn_crypt_command_t *)buf_pos; 1615 dlen = cmd->enccrd->crd_len; 1616 cry_cmd->source_count = htole16(dlen & 0xffff); 1617 dlen >>= 16; 1618 cry_cmd->masks = htole16(cmd->cry_masks | 1619 ((dlen << HIFN_CRYPT_CMD_SRCLEN_S) & HIFN_CRYPT_CMD_SRCLEN_M)); 1620 cry_cmd->header_skip = htole16(cmd->enccrd->crd_skip); 1621 cry_cmd->reserved = 0; 1622 buf_pos += sizeof(hifn_crypt_command_t); 1623 } 1624 1625 if (using_mac && cmd->mac_masks & HIFN_MAC_CMD_NEW_KEY) { 1626 bcopy(cmd->mac, buf_pos, HIFN_MAC_KEY_LENGTH); 1627 buf_pos += HIFN_MAC_KEY_LENGTH; 1628 } 1629 1630 if (using_crypt && cmd->cry_masks & HIFN_CRYPT_CMD_NEW_KEY) { 1631 switch (cmd->cry_masks & HIFN_CRYPT_CMD_ALG_MASK) { 1632 case HIFN_CRYPT_CMD_ALG_3DES: 1633 bcopy(cmd->ck, buf_pos, HIFN_3DES_KEY_LENGTH); 1634 buf_pos += HIFN_3DES_KEY_LENGTH; 1635 break; 1636 case HIFN_CRYPT_CMD_ALG_DES: 1637 bcopy(cmd->ck, buf_pos, HIFN_DES_KEY_LENGTH); 1638 buf_pos += HIFN_DES_KEY_LENGTH; 1639 break; 1640 case HIFN_CRYPT_CMD_ALG_RC4: 1641 len = 256; 1642 do { 1643 int clen; 1644 1645 clen = MIN(cmd->cklen, len); 1646 bcopy(cmd->ck, buf_pos, clen); 1647 len -= clen; 1648 buf_pos += clen; 1649 } while (len > 0); 1650 bzero(buf_pos, 4); 1651 buf_pos += 4; 1652 break; 1653 case HIFN_CRYPT_CMD_ALG_AES: 1654 /* 1655 * AES keys are variable 128, 192 and 1656 * 256 bits (16, 24 and 32 bytes). 1657 */ 1658 bcopy(cmd->ck, buf_pos, cmd->cklen); 1659 buf_pos += cmd->cklen; 1660 break; 1661 } 1662 } 1663 1664 if (using_crypt && cmd->cry_masks & HIFN_CRYPT_CMD_NEW_IV) { 1665 switch (cmd->cry_masks & HIFN_CRYPT_CMD_ALG_MASK) { 1666 case HIFN_CRYPT_CMD_ALG_AES: 1667 ivlen = HIFN_AES_IV_LENGTH; 1668 break; 1669 default: 1670 ivlen = HIFN_IV_LENGTH; 1671 break; 1672 } 1673 bcopy(cmd->iv, buf_pos, ivlen); 1674 buf_pos += ivlen; 1675 } 1676 1677 if ((cmd->base_masks & (HIFN_BASE_CMD_MAC|HIFN_BASE_CMD_CRYPT)) == 0) { 1678 bzero(buf_pos, 8); 1679 buf_pos += 8; 1680 } 1681 1682 return (buf_pos - buf); 1683 } 1684 1685 static int 1686 hifn_dmamap_aligned(struct hifn_operand *op) 1687 { 1688 int i; 1689 1690 for (i = 0; i < op->nsegs; i++) { 1691 if (op->segs[i].ds_addr & 3) 1692 return (0); 1693 if ((i != (op->nsegs - 1)) && (op->segs[i].ds_len & 3)) 1694 return (0); 1695 } 1696 return (1); 1697 } 1698 1699 static __inline int 1700 hifn_dmamap_dstwrap(struct hifn_softc *sc, int idx) 1701 { 1702 struct hifn_dma *dma = sc->sc_dma; 1703 1704 if (++idx == HIFN_D_DST_RSIZE) { 1705 dma->dstr[idx].l = htole32(HIFN_D_VALID | HIFN_D_JUMP | 1706 HIFN_D_MASKDONEIRQ); 1707 HIFN_DSTR_SYNC(sc, idx, 1708 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1709 idx = 0; 1710 } 1711 return (idx); 1712 } 1713 1714 static int 1715 hifn_dmamap_load_dst(struct hifn_softc *sc, struct hifn_command *cmd) 1716 { 1717 struct hifn_dma *dma = sc->sc_dma; 1718 struct hifn_operand *dst = &cmd->dst; 1719 u_int32_t p, l; 1720 int idx, used = 0, i; 1721 1722 idx = dma->dsti; 1723 for (i = 0; i < dst->nsegs - 1; i++) { 1724 dma->dstr[idx].p = htole32(dst->segs[i].ds_addr); 1725 dma->dstr[idx].l = htole32(HIFN_D_VALID | 1726 HIFN_D_MASKDONEIRQ | dst->segs[i].ds_len); 1727 HIFN_DSTR_SYNC(sc, idx, 1728 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1729 used++; 1730 1731 idx = hifn_dmamap_dstwrap(sc, idx); 1732 } 1733 1734 if (cmd->sloplen == 0) { 1735 p = dst->segs[i].ds_addr; 1736 l = HIFN_D_VALID | HIFN_D_MASKDONEIRQ | HIFN_D_LAST | 1737 dst->segs[i].ds_len; 1738 } else { 1739 p = sc->sc_dma_physaddr + 1740 offsetof(struct hifn_dma, slop[cmd->slopidx]); 1741 l = HIFN_D_VALID | HIFN_D_MASKDONEIRQ | HIFN_D_LAST | 1742 sizeof(u_int32_t); 1743 1744 if ((dst->segs[i].ds_len - cmd->sloplen) != 0) { 1745 dma->dstr[idx].p = htole32(dst->segs[i].ds_addr); 1746 dma->dstr[idx].l = htole32(HIFN_D_VALID | 1747 HIFN_D_MASKDONEIRQ | 1748 (dst->segs[i].ds_len - cmd->sloplen)); 1749 HIFN_DSTR_SYNC(sc, idx, 1750 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1751 used++; 1752 1753 idx = hifn_dmamap_dstwrap(sc, idx); 1754 } 1755 } 1756 dma->dstr[idx].p = htole32(p); 1757 dma->dstr[idx].l = htole32(l); 1758 HIFN_DSTR_SYNC(sc, idx, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1759 used++; 1760 1761 idx = hifn_dmamap_dstwrap(sc, idx); 1762 1763 dma->dsti = idx; 1764 dma->dstu += used; 1765 return (idx); 1766 } 1767 1768 static __inline int 1769 hifn_dmamap_srcwrap(struct hifn_softc *sc, int idx) 1770 { 1771 struct hifn_dma *dma = sc->sc_dma; 1772 1773 if (++idx == HIFN_D_SRC_RSIZE) { 1774 dma->srcr[idx].l = htole32(HIFN_D_VALID | 1775 HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 1776 HIFN_SRCR_SYNC(sc, HIFN_D_SRC_RSIZE, 1777 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1778 idx = 0; 1779 } 1780 return (idx); 1781 } 1782 1783 static int 1784 hifn_dmamap_load_src(struct hifn_softc *sc, struct hifn_command *cmd) 1785 { 1786 struct hifn_dma *dma = sc->sc_dma; 1787 struct hifn_operand *src = &cmd->src; 1788 int idx, i; 1789 u_int32_t last = 0; 1790 1791 idx = dma->srci; 1792 for (i = 0; i < src->nsegs; i++) { 1793 if (i == src->nsegs - 1) 1794 last = HIFN_D_LAST; 1795 1796 dma->srcr[idx].p = htole32(src->segs[i].ds_addr); 1797 dma->srcr[idx].l = htole32(src->segs[i].ds_len | 1798 HIFN_D_VALID | HIFN_D_MASKDONEIRQ | last); 1799 HIFN_SRCR_SYNC(sc, idx, 1800 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1801 1802 idx = hifn_dmamap_srcwrap(sc, idx); 1803 } 1804 dma->srci = idx; 1805 dma->srcu += src->nsegs; 1806 return (idx); 1807 } 1808 1809 static void 1810 hifn_op_cb(void* arg, bus_dma_segment_t *seg, int nsegs, bus_size_t mapsize, int error) 1811 { 1812 struct hifn_operand *op = arg; 1813 1814 KASSERT(nsegs <= MAX_SCATTER, 1815 ("hifn_op_cb: too many DMA segments (%u > %u) " 1816 "returned when mapping operand", nsegs, MAX_SCATTER)); 1817 op->mapsize = mapsize; 1818 op->nsegs = nsegs; 1819 bcopy(seg, op->segs, nsegs * sizeof (seg[0])); 1820 } 1821 1822 static int 1823 hifn_crypto( 1824 struct hifn_softc *sc, 1825 struct hifn_command *cmd, 1826 struct cryptop *crp, 1827 int hint) 1828 { 1829 struct hifn_dma *dma = sc->sc_dma; 1830 u_int32_t cmdlen, csr; 1831 int cmdi, resi, err = 0; 1832 1833 /* 1834 * need 1 cmd, and 1 res 1835 * 1836 * NB: check this first since it's easy. 1837 */ 1838 HIFN_LOCK(sc); 1839 if ((dma->cmdu + 1) > HIFN_D_CMD_RSIZE || 1840 (dma->resu + 1) > HIFN_D_RES_RSIZE) { 1841 #ifdef HIFN_DEBUG 1842 if (hifn_debug) { 1843 device_printf(sc->sc_dev, 1844 "cmd/result exhaustion, cmdu %u resu %u\n", 1845 dma->cmdu, dma->resu); 1846 } 1847 #endif 1848 hifnstats.hst_nomem_cr++; 1849 HIFN_UNLOCK(sc); 1850 return (ERESTART); 1851 } 1852 1853 if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, &cmd->src_map)) { 1854 hifnstats.hst_nomem_map++; 1855 HIFN_UNLOCK(sc); 1856 return (ENOMEM); 1857 } 1858 1859 if (crp->crp_flags & CRYPTO_F_IMBUF) { 1860 if (bus_dmamap_load_mbuf(sc->sc_dmat, cmd->src_map, 1861 cmd->src_m, hifn_op_cb, &cmd->src, BUS_DMA_NOWAIT)) { 1862 hifnstats.hst_nomem_load++; 1863 err = ENOMEM; 1864 goto err_srcmap1; 1865 } 1866 } else if (crp->crp_flags & CRYPTO_F_IOV) { 1867 if (bus_dmamap_load_uio(sc->sc_dmat, cmd->src_map, 1868 cmd->src_io, hifn_op_cb, &cmd->src, BUS_DMA_NOWAIT)) { 1869 hifnstats.hst_nomem_load++; 1870 err = ENOMEM; 1871 goto err_srcmap1; 1872 } 1873 } else { 1874 err = EINVAL; 1875 goto err_srcmap1; 1876 } 1877 1878 if (hifn_dmamap_aligned(&cmd->src)) { 1879 cmd->sloplen = cmd->src_mapsize & 3; 1880 cmd->dst = cmd->src; 1881 } else { 1882 if (crp->crp_flags & CRYPTO_F_IOV) { 1883 err = EINVAL; 1884 goto err_srcmap; 1885 } else if (crp->crp_flags & CRYPTO_F_IMBUF) { 1886 int totlen, len; 1887 struct mbuf *m, *m0, *mlast; 1888 1889 KASSERT(cmd->dst_m == cmd->src_m, 1890 ("hifn_crypto: dst_m initialized improperly")); 1891 hifnstats.hst_unaligned++; 1892 /* 1893 * Source is not aligned on a longword boundary. 1894 * Copy the data to insure alignment. If we fail 1895 * to allocate mbufs or clusters while doing this 1896 * we return ERESTART so the operation is requeued 1897 * at the crypto later, but only if there are 1898 * ops already posted to the hardware; otherwise we 1899 * have no guarantee that we'll be re-entered. 1900 */ 1901 totlen = cmd->src_mapsize; 1902 if (cmd->src_m->m_flags & M_PKTHDR) { 1903 len = MHLEN; 1904 MGETHDR(m0, M_DONTWAIT, MT_DATA); 1905 if (m0 && !m_dup_pkthdr(m0, cmd->src_m, M_DONTWAIT)) { 1906 m_free(m0); 1907 m0 = NULL; 1908 } 1909 } else { 1910 len = MLEN; 1911 MGET(m0, M_DONTWAIT, MT_DATA); 1912 } 1913 if (m0 == NULL) { 1914 hifnstats.hst_nomem_mbuf++; 1915 err = dma->cmdu ? ERESTART : ENOMEM; 1916 goto err_srcmap; 1917 } 1918 if (totlen >= MINCLSIZE) { 1919 MCLGET(m0, M_DONTWAIT); 1920 if ((m0->m_flags & M_EXT) == 0) { 1921 hifnstats.hst_nomem_mcl++; 1922 err = dma->cmdu ? ERESTART : ENOMEM; 1923 m_freem(m0); 1924 goto err_srcmap; 1925 } 1926 len = MCLBYTES; 1927 } 1928 totlen -= len; 1929 m0->m_pkthdr.len = m0->m_len = len; 1930 mlast = m0; 1931 1932 while (totlen > 0) { 1933 MGET(m, M_DONTWAIT, MT_DATA); 1934 if (m == NULL) { 1935 hifnstats.hst_nomem_mbuf++; 1936 err = dma->cmdu ? ERESTART : ENOMEM; 1937 m_freem(m0); 1938 goto err_srcmap; 1939 } 1940 len = MLEN; 1941 if (totlen >= MINCLSIZE) { 1942 MCLGET(m, M_DONTWAIT); 1943 if ((m->m_flags & M_EXT) == 0) { 1944 hifnstats.hst_nomem_mcl++; 1945 err = dma->cmdu ? ERESTART : ENOMEM; 1946 mlast->m_next = m; 1947 m_freem(m0); 1948 goto err_srcmap; 1949 } 1950 len = MCLBYTES; 1951 } 1952 1953 m->m_len = len; 1954 m0->m_pkthdr.len += len; 1955 totlen -= len; 1956 1957 mlast->m_next = m; 1958 mlast = m; 1959 } 1960 cmd->dst_m = m0; 1961 } 1962 } 1963 1964 if (cmd->dst_map == NULL) { 1965 if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, &cmd->dst_map)) { 1966 hifnstats.hst_nomem_map++; 1967 err = ENOMEM; 1968 goto err_srcmap; 1969 } 1970 if (crp->crp_flags & CRYPTO_F_IMBUF) { 1971 if (bus_dmamap_load_mbuf(sc->sc_dmat, cmd->dst_map, 1972 cmd->dst_m, hifn_op_cb, &cmd->dst, BUS_DMA_NOWAIT)) { 1973 hifnstats.hst_nomem_map++; 1974 err = ENOMEM; 1975 goto err_dstmap1; 1976 } 1977 } else if (crp->crp_flags & CRYPTO_F_IOV) { 1978 if (bus_dmamap_load_uio(sc->sc_dmat, cmd->dst_map, 1979 cmd->dst_io, hifn_op_cb, &cmd->dst, BUS_DMA_NOWAIT)) { 1980 hifnstats.hst_nomem_load++; 1981 err = ENOMEM; 1982 goto err_dstmap1; 1983 } 1984 } 1985 } 1986 1987 #ifdef HIFN_DEBUG 1988 if (hifn_debug) { 1989 device_printf(sc->sc_dev, 1990 "Entering cmd: stat %8x ien %8x u %d/%d/%d/%d n %d/%d\n", 1991 READ_REG_1(sc, HIFN_1_DMA_CSR), 1992 READ_REG_1(sc, HIFN_1_DMA_IER), 1993 dma->cmdu, dma->srcu, dma->dstu, dma->resu, 1994 cmd->src_nsegs, cmd->dst_nsegs); 1995 } 1996 #endif 1997 1998 if (cmd->src_map == cmd->dst_map) { 1999 bus_dmamap_sync(sc->sc_dmat, cmd->src_map, 2000 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 2001 } else { 2002 bus_dmamap_sync(sc->sc_dmat, cmd->src_map, 2003 BUS_DMASYNC_PREWRITE); 2004 bus_dmamap_sync(sc->sc_dmat, cmd->dst_map, 2005 BUS_DMASYNC_PREREAD); 2006 } 2007 2008 /* 2009 * need N src, and N dst 2010 */ 2011 if ((dma->srcu + cmd->src_nsegs) > HIFN_D_SRC_RSIZE || 2012 (dma->dstu + cmd->dst_nsegs + 1) > HIFN_D_DST_RSIZE) { 2013 #ifdef HIFN_DEBUG 2014 if (hifn_debug) { 2015 device_printf(sc->sc_dev, 2016 "src/dst exhaustion, srcu %u+%u dstu %u+%u\n", 2017 dma->srcu, cmd->src_nsegs, 2018 dma->dstu, cmd->dst_nsegs); 2019 } 2020 #endif 2021 hifnstats.hst_nomem_sd++; 2022 err = ERESTART; 2023 goto err_dstmap; 2024 } 2025 2026 if (dma->cmdi == HIFN_D_CMD_RSIZE) { 2027 dma->cmdi = 0; 2028 dma->cmdr[HIFN_D_CMD_RSIZE].l = htole32(HIFN_D_VALID | 2029 HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 2030 HIFN_CMDR_SYNC(sc, HIFN_D_CMD_RSIZE, 2031 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2032 } 2033 cmdi = dma->cmdi++; 2034 cmdlen = hifn_write_command(cmd, dma->command_bufs[cmdi]); 2035 HIFN_CMD_SYNC(sc, cmdi, BUS_DMASYNC_PREWRITE); 2036 2037 /* .p for command/result already set */ 2038 dma->cmdr[cmdi].l = htole32(cmdlen | HIFN_D_VALID | HIFN_D_LAST | 2039 HIFN_D_MASKDONEIRQ); 2040 HIFN_CMDR_SYNC(sc, cmdi, 2041 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2042 dma->cmdu++; 2043 2044 /* 2045 * We don't worry about missing an interrupt (which a "command wait" 2046 * interrupt salvages us from), unless there is more than one command 2047 * in the queue. 2048 */ 2049 if (dma->cmdu > 1) { 2050 sc->sc_dmaier |= HIFN_DMAIER_C_WAIT; 2051 WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier); 2052 } 2053 2054 hifnstats.hst_ipackets++; 2055 hifnstats.hst_ibytes += cmd->src_mapsize; 2056 2057 hifn_dmamap_load_src(sc, cmd); 2058 2059 /* 2060 * Unlike other descriptors, we don't mask done interrupt from 2061 * result descriptor. 2062 */ 2063 #ifdef HIFN_DEBUG 2064 if (hifn_debug) 2065 printf("load res\n"); 2066 #endif 2067 if (dma->resi == HIFN_D_RES_RSIZE) { 2068 dma->resi = 0; 2069 dma->resr[HIFN_D_RES_RSIZE].l = htole32(HIFN_D_VALID | 2070 HIFN_D_JUMP | HIFN_D_MASKDONEIRQ); 2071 HIFN_RESR_SYNC(sc, HIFN_D_RES_RSIZE, 2072 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2073 } 2074 resi = dma->resi++; 2075 KASSERT(dma->hifn_commands[resi] == NULL, 2076 ("hifn_crypto: command slot %u busy", resi)); 2077 dma->hifn_commands[resi] = cmd; 2078 HIFN_RES_SYNC(sc, resi, BUS_DMASYNC_PREREAD); 2079 if ((hint & CRYPTO_HINT_MORE) && sc->sc_curbatch < hifn_maxbatch) { 2080 dma->resr[resi].l = htole32(HIFN_MAX_RESULT | 2081 HIFN_D_VALID | HIFN_D_LAST | HIFN_D_MASKDONEIRQ); 2082 sc->sc_curbatch++; 2083 if (sc->sc_curbatch > hifnstats.hst_maxbatch) 2084 hifnstats.hst_maxbatch = sc->sc_curbatch; 2085 hifnstats.hst_totbatch++; 2086 } else { 2087 dma->resr[resi].l = htole32(HIFN_MAX_RESULT | 2088 HIFN_D_VALID | HIFN_D_LAST); 2089 sc->sc_curbatch = 0; 2090 } 2091 HIFN_RESR_SYNC(sc, resi, 2092 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2093 dma->resu++; 2094 2095 if (cmd->sloplen) 2096 cmd->slopidx = resi; 2097 2098 hifn_dmamap_load_dst(sc, cmd); 2099 2100 csr = 0; 2101 if (sc->sc_c_busy == 0) { 2102 csr |= HIFN_DMACSR_C_CTRL_ENA; 2103 sc->sc_c_busy = 1; 2104 } 2105 if (sc->sc_s_busy == 0) { 2106 csr |= HIFN_DMACSR_S_CTRL_ENA; 2107 sc->sc_s_busy = 1; 2108 } 2109 if (sc->sc_r_busy == 0) { 2110 csr |= HIFN_DMACSR_R_CTRL_ENA; 2111 sc->sc_r_busy = 1; 2112 } 2113 if (sc->sc_d_busy == 0) { 2114 csr |= HIFN_DMACSR_D_CTRL_ENA; 2115 sc->sc_d_busy = 1; 2116 } 2117 if (csr) 2118 WRITE_REG_1(sc, HIFN_1_DMA_CSR, csr); 2119 2120 #ifdef HIFN_DEBUG 2121 if (hifn_debug) { 2122 device_printf(sc->sc_dev, "command: stat %8x ier %8x\n", 2123 READ_REG_1(sc, HIFN_1_DMA_CSR), 2124 READ_REG_1(sc, HIFN_1_DMA_IER)); 2125 } 2126 #endif 2127 2128 sc->sc_active = 5; 2129 HIFN_UNLOCK(sc); 2130 KASSERT(err == 0, ("hifn_crypto: success with error %u", err)); 2131 return (err); /* success */ 2132 2133 err_dstmap: 2134 if (cmd->src_map != cmd->dst_map) 2135 bus_dmamap_unload(sc->sc_dmat, cmd->dst_map); 2136 err_dstmap1: 2137 if (cmd->src_map != cmd->dst_map) 2138 bus_dmamap_destroy(sc->sc_dmat, cmd->dst_map); 2139 err_srcmap: 2140 if (crp->crp_flags & CRYPTO_F_IMBUF) { 2141 if (cmd->src_m != cmd->dst_m) 2142 m_freem(cmd->dst_m); 2143 } 2144 bus_dmamap_unload(sc->sc_dmat, cmd->src_map); 2145 err_srcmap1: 2146 bus_dmamap_destroy(sc->sc_dmat, cmd->src_map); 2147 HIFN_UNLOCK(sc); 2148 return (err); 2149 } 2150 2151 static void 2152 hifn_tick(void* vsc) 2153 { 2154 struct hifn_softc *sc = vsc; 2155 2156 HIFN_LOCK(sc); 2157 if (sc->sc_active == 0) { 2158 struct hifn_dma *dma = sc->sc_dma; 2159 u_int32_t r = 0; 2160 2161 if (dma->cmdu == 0 && sc->sc_c_busy) { 2162 sc->sc_c_busy = 0; 2163 r |= HIFN_DMACSR_C_CTRL_DIS; 2164 } 2165 if (dma->srcu == 0 && sc->sc_s_busy) { 2166 sc->sc_s_busy = 0; 2167 r |= HIFN_DMACSR_S_CTRL_DIS; 2168 } 2169 if (dma->dstu == 0 && sc->sc_d_busy) { 2170 sc->sc_d_busy = 0; 2171 r |= HIFN_DMACSR_D_CTRL_DIS; 2172 } 2173 if (dma->resu == 0 && sc->sc_r_busy) { 2174 sc->sc_r_busy = 0; 2175 r |= HIFN_DMACSR_R_CTRL_DIS; 2176 } 2177 if (r) 2178 WRITE_REG_1(sc, HIFN_1_DMA_CSR, r); 2179 } else 2180 sc->sc_active--; 2181 HIFN_UNLOCK(sc); 2182 callout_reset(&sc->sc_tickto, hz, hifn_tick, sc); 2183 } 2184 2185 static void 2186 hifn_intr(void *arg) 2187 { 2188 struct hifn_softc *sc = arg; 2189 struct hifn_dma *dma; 2190 u_int32_t dmacsr, restart; 2191 int i, u; 2192 2193 dmacsr = READ_REG_1(sc, HIFN_1_DMA_CSR); 2194 2195 /* Nothing in the DMA unit interrupted */ 2196 if ((dmacsr & sc->sc_dmaier) == 0) 2197 return; 2198 2199 HIFN_LOCK(sc); 2200 2201 dma = sc->sc_dma; 2202 2203 #ifdef HIFN_DEBUG 2204 if (hifn_debug) { 2205 device_printf(sc->sc_dev, 2206 "irq: stat %08x ien %08x damier %08x i %d/%d/%d/%d k %d/%d/%d/%d u %d/%d/%d/%d\n", 2207 dmacsr, READ_REG_1(sc, HIFN_1_DMA_IER), sc->sc_dmaier, 2208 dma->cmdi, dma->srci, dma->dsti, dma->resi, 2209 dma->cmdk, dma->srck, dma->dstk, dma->resk, 2210 dma->cmdu, dma->srcu, dma->dstu, dma->resu); 2211 } 2212 #endif 2213 2214 WRITE_REG_1(sc, HIFN_1_DMA_CSR, dmacsr & sc->sc_dmaier); 2215 2216 if ((sc->sc_flags & HIFN_HAS_PUBLIC) && 2217 (dmacsr & HIFN_DMACSR_PUBDONE)) 2218 WRITE_REG_1(sc, HIFN_1_PUB_STATUS, 2219 READ_REG_1(sc, HIFN_1_PUB_STATUS) | HIFN_PUBSTS_DONE); 2220 2221 restart = dmacsr & (HIFN_DMACSR_D_OVER | HIFN_DMACSR_R_OVER); 2222 if (restart) 2223 device_printf(sc->sc_dev, "overrun %x\n", dmacsr); 2224 2225 if (sc->sc_flags & HIFN_IS_7811) { 2226 if (dmacsr & HIFN_DMACSR_ILLR) 2227 device_printf(sc->sc_dev, "illegal read\n"); 2228 if (dmacsr & HIFN_DMACSR_ILLW) 2229 device_printf(sc->sc_dev, "illegal write\n"); 2230 } 2231 2232 restart = dmacsr & (HIFN_DMACSR_C_ABORT | HIFN_DMACSR_S_ABORT | 2233 HIFN_DMACSR_D_ABORT | HIFN_DMACSR_R_ABORT); 2234 if (restart) { 2235 device_printf(sc->sc_dev, "abort, resetting.\n"); 2236 hifnstats.hst_abort++; 2237 hifn_abort(sc); 2238 HIFN_UNLOCK(sc); 2239 return; 2240 } 2241 2242 if ((dmacsr & HIFN_DMACSR_C_WAIT) && (dma->cmdu == 0)) { 2243 /* 2244 * If no slots to process and we receive a "waiting on 2245 * command" interrupt, we disable the "waiting on command" 2246 * (by clearing it). 2247 */ 2248 sc->sc_dmaier &= ~HIFN_DMAIER_C_WAIT; 2249 WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier); 2250 } 2251 2252 /* clear the rings */ 2253 i = dma->resk; u = dma->resu; 2254 while (u != 0) { 2255 HIFN_RESR_SYNC(sc, i, 2256 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2257 if (dma->resr[i].l & htole32(HIFN_D_VALID)) { 2258 HIFN_RESR_SYNC(sc, i, 2259 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2260 break; 2261 } 2262 2263 if (i != HIFN_D_RES_RSIZE) { 2264 struct hifn_command *cmd; 2265 u_int8_t *macbuf = NULL; 2266 2267 HIFN_RES_SYNC(sc, i, BUS_DMASYNC_POSTREAD); 2268 cmd = dma->hifn_commands[i]; 2269 KASSERT(cmd != NULL, 2270 ("hifn_intr: null command slot %u", i)); 2271 dma->hifn_commands[i] = NULL; 2272 2273 if (cmd->base_masks & HIFN_BASE_CMD_MAC) { 2274 macbuf = dma->result_bufs[i]; 2275 macbuf += 12; 2276 } 2277 2278 hifn_callback(sc, cmd, macbuf); 2279 hifnstats.hst_opackets++; 2280 u--; 2281 } 2282 2283 if (++i == (HIFN_D_RES_RSIZE + 1)) 2284 i = 0; 2285 } 2286 dma->resk = i; dma->resu = u; 2287 2288 i = dma->srck; u = dma->srcu; 2289 while (u != 0) { 2290 if (i == HIFN_D_SRC_RSIZE) 2291 i = 0; 2292 HIFN_SRCR_SYNC(sc, i, 2293 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2294 if (dma->srcr[i].l & htole32(HIFN_D_VALID)) { 2295 HIFN_SRCR_SYNC(sc, i, 2296 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2297 break; 2298 } 2299 i++, u--; 2300 } 2301 dma->srck = i; dma->srcu = u; 2302 2303 i = dma->cmdk; u = dma->cmdu; 2304 while (u != 0) { 2305 HIFN_CMDR_SYNC(sc, i, 2306 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2307 if (dma->cmdr[i].l & htole32(HIFN_D_VALID)) { 2308 HIFN_CMDR_SYNC(sc, i, 2309 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2310 break; 2311 } 2312 if (i != HIFN_D_CMD_RSIZE) { 2313 u--; 2314 HIFN_CMD_SYNC(sc, i, BUS_DMASYNC_POSTWRITE); 2315 } 2316 if (++i == (HIFN_D_CMD_RSIZE + 1)) 2317 i = 0; 2318 } 2319 dma->cmdk = i; dma->cmdu = u; 2320 2321 HIFN_UNLOCK(sc); 2322 2323 if (sc->sc_needwakeup) { /* XXX check high watermark */ 2324 int wakeup = sc->sc_needwakeup & (CRYPTO_SYMQ|CRYPTO_ASYMQ); 2325 #ifdef HIFN_DEBUG 2326 if (hifn_debug) 2327 device_printf(sc->sc_dev, 2328 "wakeup crypto (%x) u %d/%d/%d/%d\n", 2329 sc->sc_needwakeup, 2330 dma->cmdu, dma->srcu, dma->dstu, dma->resu); 2331 #endif 2332 sc->sc_needwakeup &= ~wakeup; 2333 crypto_unblock(sc->sc_cid, wakeup); 2334 } 2335 } 2336 2337 /* 2338 * Allocate a new 'session' and return an encoded session id. 'sidp' 2339 * contains our registration id, and should contain an encoded session 2340 * id on successful allocation. 2341 */ 2342 static int 2343 hifn_newsession(device_t dev, u_int32_t *sidp, struct cryptoini *cri) 2344 { 2345 struct hifn_softc *sc = device_get_softc(dev); 2346 struct cryptoini *c; 2347 int mac = 0, cry = 0, sesn; 2348 struct hifn_session *ses = NULL; 2349 2350 KASSERT(sc != NULL, ("hifn_newsession: null softc")); 2351 if (sidp == NULL || cri == NULL || sc == NULL) 2352 return (EINVAL); 2353 2354 HIFN_LOCK(sc); 2355 if (sc->sc_sessions == NULL) { 2356 ses = sc->sc_sessions = (struct hifn_session *)malloc( 2357 sizeof(*ses), M_DEVBUF, M_NOWAIT); 2358 if (ses == NULL) { 2359 HIFN_UNLOCK(sc); 2360 return (ENOMEM); 2361 } 2362 sesn = 0; 2363 sc->sc_nsessions = 1; 2364 } else { 2365 for (sesn = 0; sesn < sc->sc_nsessions; sesn++) { 2366 if (!sc->sc_sessions[sesn].hs_used) { 2367 ses = &sc->sc_sessions[sesn]; 2368 break; 2369 } 2370 } 2371 2372 if (ses == NULL) { 2373 sesn = sc->sc_nsessions; 2374 ses = (struct hifn_session *)malloc((sesn + 1) * 2375 sizeof(*ses), M_DEVBUF, M_NOWAIT); 2376 if (ses == NULL) { 2377 HIFN_UNLOCK(sc); 2378 return (ENOMEM); 2379 } 2380 bcopy(sc->sc_sessions, ses, sesn * sizeof(*ses)); 2381 bzero(sc->sc_sessions, sesn * sizeof(*ses)); 2382 free(sc->sc_sessions, M_DEVBUF); 2383 sc->sc_sessions = ses; 2384 ses = &sc->sc_sessions[sesn]; 2385 sc->sc_nsessions++; 2386 } 2387 } 2388 HIFN_UNLOCK(sc); 2389 2390 bzero(ses, sizeof(*ses)); 2391 ses->hs_used = 1; 2392 2393 for (c = cri; c != NULL; c = c->cri_next) { 2394 switch (c->cri_alg) { 2395 case CRYPTO_MD5: 2396 case CRYPTO_SHA1: 2397 case CRYPTO_MD5_HMAC: 2398 case CRYPTO_SHA1_HMAC: 2399 if (mac) 2400 return (EINVAL); 2401 mac = 1; 2402 ses->hs_mlen = c->cri_mlen; 2403 if (ses->hs_mlen == 0) { 2404 switch (c->cri_alg) { 2405 case CRYPTO_MD5: 2406 case CRYPTO_MD5_HMAC: 2407 ses->hs_mlen = 16; 2408 break; 2409 case CRYPTO_SHA1: 2410 case CRYPTO_SHA1_HMAC: 2411 ses->hs_mlen = 20; 2412 break; 2413 } 2414 } 2415 break; 2416 case CRYPTO_DES_CBC: 2417 case CRYPTO_3DES_CBC: 2418 case CRYPTO_AES_CBC: 2419 /* XXX this may read fewer, does it matter? */ 2420 read_random(ses->hs_iv, 2421 c->cri_alg == CRYPTO_AES_CBC ? 2422 HIFN_AES_IV_LENGTH : HIFN_IV_LENGTH); 2423 /*FALLTHROUGH*/ 2424 case CRYPTO_ARC4: 2425 if (cry) 2426 return (EINVAL); 2427 cry = 1; 2428 break; 2429 default: 2430 return (EINVAL); 2431 } 2432 } 2433 if (mac == 0 && cry == 0) 2434 return (EINVAL); 2435 2436 *sidp = HIFN_SID(device_get_unit(sc->sc_dev), sesn); 2437 2438 return (0); 2439 } 2440 2441 /* 2442 * Deallocate a session. 2443 * XXX this routine should run a zero'd mac/encrypt key into context ram. 2444 * XXX to blow away any keys already stored there. 2445 */ 2446 static int 2447 hifn_freesession(device_t dev, u_int64_t tid) 2448 { 2449 struct hifn_softc *sc = device_get_softc(dev); 2450 int session, error; 2451 u_int32_t sid = CRYPTO_SESID2LID(tid); 2452 2453 KASSERT(sc != NULL, ("hifn_freesession: null softc")); 2454 if (sc == NULL) 2455 return (EINVAL); 2456 2457 HIFN_LOCK(sc); 2458 session = HIFN_SESSION(sid); 2459 if (session < sc->sc_nsessions) { 2460 bzero(&sc->sc_sessions[session], sizeof(struct hifn_session)); 2461 error = 0; 2462 } else 2463 error = EINVAL; 2464 HIFN_UNLOCK(sc); 2465 2466 return (error); 2467 } 2468 2469 static int 2470 hifn_process(device_t dev, struct cryptop *crp, int hint) 2471 { 2472 struct hifn_softc *sc = device_get_softc(dev); 2473 struct hifn_command *cmd = NULL; 2474 int session, err, ivlen; 2475 struct cryptodesc *crd1, *crd2, *maccrd, *enccrd; 2476 2477 if (crp == NULL || crp->crp_callback == NULL) { 2478 hifnstats.hst_invalid++; 2479 return (EINVAL); 2480 } 2481 session = HIFN_SESSION(crp->crp_sid); 2482 2483 if (sc == NULL || session >= sc->sc_nsessions) { 2484 err = EINVAL; 2485 goto errout; 2486 } 2487 2488 cmd = malloc(sizeof(struct hifn_command), M_DEVBUF, M_NOWAIT | M_ZERO); 2489 if (cmd == NULL) { 2490 hifnstats.hst_nomem++; 2491 err = ENOMEM; 2492 goto errout; 2493 } 2494 2495 if (crp->crp_flags & CRYPTO_F_IMBUF) { 2496 cmd->src_m = (struct mbuf *)crp->crp_buf; 2497 cmd->dst_m = (struct mbuf *)crp->crp_buf; 2498 } else if (crp->crp_flags & CRYPTO_F_IOV) { 2499 cmd->src_io = (struct uio *)crp->crp_buf; 2500 cmd->dst_io = (struct uio *)crp->crp_buf; 2501 } else { 2502 err = EINVAL; 2503 goto errout; /* XXX we don't handle contiguous buffers! */ 2504 } 2505 2506 crd1 = crp->crp_desc; 2507 if (crd1 == NULL) { 2508 err = EINVAL; 2509 goto errout; 2510 } 2511 crd2 = crd1->crd_next; 2512 2513 if (crd2 == NULL) { 2514 if (crd1->crd_alg == CRYPTO_MD5_HMAC || 2515 crd1->crd_alg == CRYPTO_SHA1_HMAC || 2516 crd1->crd_alg == CRYPTO_SHA1 || 2517 crd1->crd_alg == CRYPTO_MD5) { 2518 maccrd = crd1; 2519 enccrd = NULL; 2520 } else if (crd1->crd_alg == CRYPTO_DES_CBC || 2521 crd1->crd_alg == CRYPTO_3DES_CBC || 2522 crd1->crd_alg == CRYPTO_AES_CBC || 2523 crd1->crd_alg == CRYPTO_ARC4) { 2524 if ((crd1->crd_flags & CRD_F_ENCRYPT) == 0) 2525 cmd->base_masks |= HIFN_BASE_CMD_DECODE; 2526 maccrd = NULL; 2527 enccrd = crd1; 2528 } else { 2529 err = EINVAL; 2530 goto errout; 2531 } 2532 } else { 2533 if ((crd1->crd_alg == CRYPTO_MD5_HMAC || 2534 crd1->crd_alg == CRYPTO_SHA1_HMAC || 2535 crd1->crd_alg == CRYPTO_MD5 || 2536 crd1->crd_alg == CRYPTO_SHA1) && 2537 (crd2->crd_alg == CRYPTO_DES_CBC || 2538 crd2->crd_alg == CRYPTO_3DES_CBC || 2539 crd2->crd_alg == CRYPTO_AES_CBC || 2540 crd2->crd_alg == CRYPTO_ARC4) && 2541 ((crd2->crd_flags & CRD_F_ENCRYPT) == 0)) { 2542 cmd->base_masks = HIFN_BASE_CMD_DECODE; 2543 maccrd = crd1; 2544 enccrd = crd2; 2545 } else if ((crd1->crd_alg == CRYPTO_DES_CBC || 2546 crd1->crd_alg == CRYPTO_ARC4 || 2547 crd1->crd_alg == CRYPTO_3DES_CBC || 2548 crd1->crd_alg == CRYPTO_AES_CBC) && 2549 (crd2->crd_alg == CRYPTO_MD5_HMAC || 2550 crd2->crd_alg == CRYPTO_SHA1_HMAC || 2551 crd2->crd_alg == CRYPTO_MD5 || 2552 crd2->crd_alg == CRYPTO_SHA1) && 2553 (crd1->crd_flags & CRD_F_ENCRYPT)) { 2554 enccrd = crd1; 2555 maccrd = crd2; 2556 } else { 2557 /* 2558 * We cannot order the 7751 as requested 2559 */ 2560 err = EINVAL; 2561 goto errout; 2562 } 2563 } 2564 2565 if (enccrd) { 2566 cmd->enccrd = enccrd; 2567 cmd->base_masks |= HIFN_BASE_CMD_CRYPT; 2568 switch (enccrd->crd_alg) { 2569 case CRYPTO_ARC4: 2570 cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_RC4; 2571 break; 2572 case CRYPTO_DES_CBC: 2573 cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_DES | 2574 HIFN_CRYPT_CMD_MODE_CBC | 2575 HIFN_CRYPT_CMD_NEW_IV; 2576 break; 2577 case CRYPTO_3DES_CBC: 2578 cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_3DES | 2579 HIFN_CRYPT_CMD_MODE_CBC | 2580 HIFN_CRYPT_CMD_NEW_IV; 2581 break; 2582 case CRYPTO_AES_CBC: 2583 cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_AES | 2584 HIFN_CRYPT_CMD_MODE_CBC | 2585 HIFN_CRYPT_CMD_NEW_IV; 2586 break; 2587 default: 2588 err = EINVAL; 2589 goto errout; 2590 } 2591 if (enccrd->crd_alg != CRYPTO_ARC4) { 2592 ivlen = ((enccrd->crd_alg == CRYPTO_AES_CBC) ? 2593 HIFN_AES_IV_LENGTH : HIFN_IV_LENGTH); 2594 if (enccrd->crd_flags & CRD_F_ENCRYPT) { 2595 if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) 2596 bcopy(enccrd->crd_iv, cmd->iv, ivlen); 2597 else 2598 bcopy(sc->sc_sessions[session].hs_iv, 2599 cmd->iv, ivlen); 2600 2601 if ((enccrd->crd_flags & CRD_F_IV_PRESENT) 2602 == 0) { 2603 crypto_copyback(crp->crp_flags, 2604 crp->crp_buf, enccrd->crd_inject, 2605 ivlen, cmd->iv); 2606 } 2607 } else { 2608 if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) 2609 bcopy(enccrd->crd_iv, cmd->iv, ivlen); 2610 else { 2611 crypto_copydata(crp->crp_flags, 2612 crp->crp_buf, enccrd->crd_inject, 2613 ivlen, cmd->iv); 2614 } 2615 } 2616 } 2617 2618 if (enccrd->crd_flags & CRD_F_KEY_EXPLICIT) 2619 cmd->cry_masks |= HIFN_CRYPT_CMD_NEW_KEY; 2620 cmd->ck = enccrd->crd_key; 2621 cmd->cklen = enccrd->crd_klen >> 3; 2622 cmd->cry_masks |= HIFN_CRYPT_CMD_NEW_KEY; 2623 2624 /* 2625 * Need to specify the size for the AES key in the masks. 2626 */ 2627 if ((cmd->cry_masks & HIFN_CRYPT_CMD_ALG_MASK) == 2628 HIFN_CRYPT_CMD_ALG_AES) { 2629 switch (cmd->cklen) { 2630 case 16: 2631 cmd->cry_masks |= HIFN_CRYPT_CMD_KSZ_128; 2632 break; 2633 case 24: 2634 cmd->cry_masks |= HIFN_CRYPT_CMD_KSZ_192; 2635 break; 2636 case 32: 2637 cmd->cry_masks |= HIFN_CRYPT_CMD_KSZ_256; 2638 break; 2639 default: 2640 err = EINVAL; 2641 goto errout; 2642 } 2643 } 2644 } 2645 2646 if (maccrd) { 2647 cmd->maccrd = maccrd; 2648 cmd->base_masks |= HIFN_BASE_CMD_MAC; 2649 2650 switch (maccrd->crd_alg) { 2651 case CRYPTO_MD5: 2652 cmd->mac_masks |= HIFN_MAC_CMD_ALG_MD5 | 2653 HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HASH | 2654 HIFN_MAC_CMD_POS_IPSEC; 2655 break; 2656 case CRYPTO_MD5_HMAC: 2657 cmd->mac_masks |= HIFN_MAC_CMD_ALG_MD5 | 2658 HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HMAC | 2659 HIFN_MAC_CMD_POS_IPSEC | HIFN_MAC_CMD_TRUNC; 2660 break; 2661 case CRYPTO_SHA1: 2662 cmd->mac_masks |= HIFN_MAC_CMD_ALG_SHA1 | 2663 HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HASH | 2664 HIFN_MAC_CMD_POS_IPSEC; 2665 break; 2666 case CRYPTO_SHA1_HMAC: 2667 cmd->mac_masks |= HIFN_MAC_CMD_ALG_SHA1 | 2668 HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HMAC | 2669 HIFN_MAC_CMD_POS_IPSEC | HIFN_MAC_CMD_TRUNC; 2670 break; 2671 } 2672 2673 if (maccrd->crd_alg == CRYPTO_SHA1_HMAC || 2674 maccrd->crd_alg == CRYPTO_MD5_HMAC) { 2675 cmd->mac_masks |= HIFN_MAC_CMD_NEW_KEY; 2676 bcopy(maccrd->crd_key, cmd->mac, maccrd->crd_klen >> 3); 2677 bzero(cmd->mac + (maccrd->crd_klen >> 3), 2678 HIFN_MAC_KEY_LENGTH - (maccrd->crd_klen >> 3)); 2679 } 2680 } 2681 2682 cmd->crp = crp; 2683 cmd->session_num = session; 2684 cmd->softc = sc; 2685 2686 err = hifn_crypto(sc, cmd, crp, hint); 2687 if (!err) { 2688 return 0; 2689 } else if (err == ERESTART) { 2690 /* 2691 * There weren't enough resources to dispatch the request 2692 * to the part. Notify the caller so they'll requeue this 2693 * request and resubmit it again soon. 2694 */ 2695 #ifdef HIFN_DEBUG 2696 if (hifn_debug) 2697 device_printf(sc->sc_dev, "requeue request\n"); 2698 #endif 2699 free(cmd, M_DEVBUF); 2700 sc->sc_needwakeup |= CRYPTO_SYMQ; 2701 return (err); 2702 } 2703 2704 errout: 2705 if (cmd != NULL) 2706 free(cmd, M_DEVBUF); 2707 if (err == EINVAL) 2708 hifnstats.hst_invalid++; 2709 else 2710 hifnstats.hst_nomem++; 2711 crp->crp_etype = err; 2712 crypto_done(crp); 2713 return (err); 2714 } 2715 2716 static void 2717 hifn_abort(struct hifn_softc *sc) 2718 { 2719 struct hifn_dma *dma = sc->sc_dma; 2720 struct hifn_command *cmd; 2721 struct cryptop *crp; 2722 int i, u; 2723 2724 i = dma->resk; u = dma->resu; 2725 while (u != 0) { 2726 cmd = dma->hifn_commands[i]; 2727 KASSERT(cmd != NULL, ("hifn_abort: null command slot %u", i)); 2728 dma->hifn_commands[i] = NULL; 2729 crp = cmd->crp; 2730 2731 if ((dma->resr[i].l & htole32(HIFN_D_VALID)) == 0) { 2732 /* Salvage what we can. */ 2733 u_int8_t *macbuf; 2734 2735 if (cmd->base_masks & HIFN_BASE_CMD_MAC) { 2736 macbuf = dma->result_bufs[i]; 2737 macbuf += 12; 2738 } else 2739 macbuf = NULL; 2740 hifnstats.hst_opackets++; 2741 hifn_callback(sc, cmd, macbuf); 2742 } else { 2743 if (cmd->src_map == cmd->dst_map) { 2744 bus_dmamap_sync(sc->sc_dmat, cmd->src_map, 2745 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2746 } else { 2747 bus_dmamap_sync(sc->sc_dmat, cmd->src_map, 2748 BUS_DMASYNC_POSTWRITE); 2749 bus_dmamap_sync(sc->sc_dmat, cmd->dst_map, 2750 BUS_DMASYNC_POSTREAD); 2751 } 2752 2753 if (cmd->src_m != cmd->dst_m) { 2754 m_freem(cmd->src_m); 2755 crp->crp_buf = (caddr_t)cmd->dst_m; 2756 } 2757 2758 /* non-shared buffers cannot be restarted */ 2759 if (cmd->src_map != cmd->dst_map) { 2760 /* 2761 * XXX should be EAGAIN, delayed until 2762 * after the reset. 2763 */ 2764 crp->crp_etype = ENOMEM; 2765 bus_dmamap_unload(sc->sc_dmat, cmd->dst_map); 2766 bus_dmamap_destroy(sc->sc_dmat, cmd->dst_map); 2767 } else 2768 crp->crp_etype = ENOMEM; 2769 2770 bus_dmamap_unload(sc->sc_dmat, cmd->src_map); 2771 bus_dmamap_destroy(sc->sc_dmat, cmd->src_map); 2772 2773 free(cmd, M_DEVBUF); 2774 if (crp->crp_etype != EAGAIN) 2775 crypto_done(crp); 2776 } 2777 2778 if (++i == HIFN_D_RES_RSIZE) 2779 i = 0; 2780 u--; 2781 } 2782 dma->resk = i; dma->resu = u; 2783 2784 hifn_reset_board(sc, 1); 2785 hifn_init_dma(sc); 2786 hifn_init_pci_registers(sc); 2787 } 2788 2789 static void 2790 hifn_callback(struct hifn_softc *sc, struct hifn_command *cmd, u_int8_t *macbuf) 2791 { 2792 struct hifn_dma *dma = sc->sc_dma; 2793 struct cryptop *crp = cmd->crp; 2794 struct cryptodesc *crd; 2795 struct mbuf *m; 2796 int totlen, i, u, ivlen; 2797 2798 if (cmd->src_map == cmd->dst_map) { 2799 bus_dmamap_sync(sc->sc_dmat, cmd->src_map, 2800 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2801 } else { 2802 bus_dmamap_sync(sc->sc_dmat, cmd->src_map, 2803 BUS_DMASYNC_POSTWRITE); 2804 bus_dmamap_sync(sc->sc_dmat, cmd->dst_map, 2805 BUS_DMASYNC_POSTREAD); 2806 } 2807 2808 if (crp->crp_flags & CRYPTO_F_IMBUF) { 2809 if (cmd->src_m != cmd->dst_m) { 2810 crp->crp_buf = (caddr_t)cmd->dst_m; 2811 totlen = cmd->src_mapsize; 2812 for (m = cmd->dst_m; m != NULL; m = m->m_next) { 2813 if (totlen < m->m_len) { 2814 m->m_len = totlen; 2815 totlen = 0; 2816 } else 2817 totlen -= m->m_len; 2818 } 2819 cmd->dst_m->m_pkthdr.len = cmd->src_m->m_pkthdr.len; 2820 m_freem(cmd->src_m); 2821 } 2822 } 2823 2824 if (cmd->sloplen != 0) { 2825 crypto_copyback(crp->crp_flags, crp->crp_buf, 2826 cmd->src_mapsize - cmd->sloplen, cmd->sloplen, 2827 (caddr_t)&dma->slop[cmd->slopidx]); 2828 } 2829 2830 i = dma->dstk; u = dma->dstu; 2831 while (u != 0) { 2832 if (i == HIFN_D_DST_RSIZE) 2833 i = 0; 2834 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 2835 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2836 if (dma->dstr[i].l & htole32(HIFN_D_VALID)) { 2837 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 2838 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2839 break; 2840 } 2841 i++, u--; 2842 } 2843 dma->dstk = i; dma->dstu = u; 2844 2845 hifnstats.hst_obytes += cmd->dst_mapsize; 2846 2847 if ((cmd->base_masks & (HIFN_BASE_CMD_CRYPT | HIFN_BASE_CMD_DECODE)) == 2848 HIFN_BASE_CMD_CRYPT) { 2849 for (crd = crp->crp_desc; crd; crd = crd->crd_next) { 2850 if (crd->crd_alg != CRYPTO_DES_CBC && 2851 crd->crd_alg != CRYPTO_3DES_CBC && 2852 crd->crd_alg != CRYPTO_AES_CBC) 2853 continue; 2854 ivlen = ((crd->crd_alg == CRYPTO_AES_CBC) ? 2855 HIFN_AES_IV_LENGTH : HIFN_IV_LENGTH); 2856 crypto_copydata(crp->crp_flags, crp->crp_buf, 2857 crd->crd_skip + crd->crd_len - ivlen, ivlen, 2858 cmd->softc->sc_sessions[cmd->session_num].hs_iv); 2859 break; 2860 } 2861 } 2862 2863 if (macbuf != NULL) { 2864 for (crd = crp->crp_desc; crd; crd = crd->crd_next) { 2865 int len; 2866 2867 if (crd->crd_alg != CRYPTO_MD5 && 2868 crd->crd_alg != CRYPTO_SHA1 && 2869 crd->crd_alg != CRYPTO_MD5_HMAC && 2870 crd->crd_alg != CRYPTO_SHA1_HMAC) { 2871 continue; 2872 } 2873 len = cmd->softc->sc_sessions[cmd->session_num].hs_mlen; 2874 crypto_copyback(crp->crp_flags, crp->crp_buf, 2875 crd->crd_inject, len, macbuf); 2876 break; 2877 } 2878 } 2879 2880 if (cmd->src_map != cmd->dst_map) { 2881 bus_dmamap_unload(sc->sc_dmat, cmd->dst_map); 2882 bus_dmamap_destroy(sc->sc_dmat, cmd->dst_map); 2883 } 2884 bus_dmamap_unload(sc->sc_dmat, cmd->src_map); 2885 bus_dmamap_destroy(sc->sc_dmat, cmd->src_map); 2886 free(cmd, M_DEVBUF); 2887 crypto_done(crp); 2888 } 2889 2890 /* 2891 * 7811 PB3 rev/2 parts lock-up on burst writes to Group 0 2892 * and Group 1 registers; avoid conditions that could create 2893 * burst writes by doing a read in between the writes. 2894 * 2895 * NB: The read we interpose is always to the same register; 2896 * we do this because reading from an arbitrary (e.g. last) 2897 * register may not always work. 2898 */ 2899 static void 2900 hifn_write_reg_0(struct hifn_softc *sc, bus_size_t reg, u_int32_t val) 2901 { 2902 if (sc->sc_flags & HIFN_IS_7811) { 2903 if (sc->sc_bar0_lastreg == reg - 4) 2904 bus_space_read_4(sc->sc_st0, sc->sc_sh0, HIFN_0_PUCNFG); 2905 sc->sc_bar0_lastreg = reg; 2906 } 2907 bus_space_write_4(sc->sc_st0, sc->sc_sh0, reg, val); 2908 } 2909 2910 static void 2911 hifn_write_reg_1(struct hifn_softc *sc, bus_size_t reg, u_int32_t val) 2912 { 2913 if (sc->sc_flags & HIFN_IS_7811) { 2914 if (sc->sc_bar1_lastreg == reg - 4) 2915 bus_space_read_4(sc->sc_st1, sc->sc_sh1, HIFN_1_REVID); 2916 sc->sc_bar1_lastreg = reg; 2917 } 2918 bus_space_write_4(sc->sc_st1, sc->sc_sh1, reg, val); 2919 } 2920 2921 #ifdef HIFN_VULCANDEV 2922 /* 2923 * this code provides support for mapping the PK engine's register 2924 * into a userspace program. 2925 * 2926 */ 2927 static int 2928 vulcanpk_mmap(struct cdev *dev, vm_offset_t offset, 2929 vm_paddr_t *paddr, int nprot) 2930 { 2931 struct hifn_softc *sc; 2932 vm_paddr_t pd; 2933 void *b; 2934 2935 sc = dev->si_drv1; 2936 2937 pd = rman_get_start(sc->sc_bar1res); 2938 b = rman_get_virtual(sc->sc_bar1res); 2939 2940 #if 0 2941 printf("vpk mmap: %p(%08x) offset=%d\n", b, pd, offset); 2942 hexdump(b, HIFN_1_PUB_MEMEND, "vpk", 0); 2943 #endif 2944 2945 if (offset == 0) { 2946 *paddr = pd; 2947 return (0); 2948 } 2949 return (-1); 2950 } 2951 2952 static struct cdevsw vulcanpk_cdevsw = { 2953 .d_version = D_VERSION, 2954 .d_mmap = vulcanpk_mmap, 2955 .d_name = "vulcanpk", 2956 }; 2957 #endif /* HIFN_VULCANDEV */
Cache object: 17321ee17f00195f9f62dbbeca251771
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