FreeBSD/Linux Kernel Cross Reference
sys/dev/hpt27xx/him.h
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2011 HighPoint Technologies, Inc.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 *
28 * $FreeBSD$
29 */
30
31 #include <dev/hpt27xx/hpt27xx_config.h>
32
33 #ifndef _HPT_HIM_H_
34 #define _HPT_HIM_H_
35
36 #define VERMAGIC_HIM 55
37
38 #if defined(__cplusplus)
39 extern "C" {
40 #endif
41
42 #include <dev/hpt27xx/list.h>
43
44 #define SECTOR_TO_BYTE_SHIFT 9
45 #define SECTOR_TO_BYTE(x) ((HPT_U32)(x) << SECTOR_TO_BYTE_SHIFT)
46 #define BYTE_TO_SECTOR(x) ((x)>>SECTOR_TO_BYTE_SHIFT)
47
48 typedef struct _PCI_ID
49 {
50 HPT_U16 vid;
51 HPT_U16 did;
52 HPT_U32 subsys;
53 HPT_U8 rev;
54 HPT_U8 nbase;
55 HPT_U16 reserve;
56 }
57 PCI_ID;
58
59 typedef struct _PCI_ADDRESS
60 {
61 HPT_U8 tree;
62 HPT_U8 bus;
63 HPT_U8 device;
64 HPT_U8 function;
65 }
66 PCI_ADDRESS;
67
68 typedef struct _HIM_ADAPTER_CONFIG
69 {
70 PCI_ADDRESS pci_addr;
71 PCI_ID pci_id;
72
73 HPT_U8 max_devices;
74
75 HPT_U8 bProbeInInitializing:1;
76
77 HPT_U8 bSpinupOneDevEachTime:1;
78
79 HPT_U8 bGlobalNcq:1;
80 HPT_U8 bSGPIOPartSupport:1;
81
82 HPT_U8 bNeedSASIdleTimer:1;
83 HPT_U8 reserved:3;
84
85 HPT_U8 bDevsPerBus;
86 HPT_U8 first_on_slot;
87
88 HPT_U8 bChipType;
89 HPT_U8 bChipIntrNum;
90 HPT_U8 bChipFlags;
91 HPT_U8 bNumBuses;
92
93 HPT_U8 szVendorID[36];
94 HPT_U8 szProductID[36];
95 HPT_U32 nvramSize;
96 HPT_U64 nvramAddress;
97 HPT_U8 slot_index;
98 HPT_U8 maxWidth;
99 HPT_U8 currentWidth;
100 HPT_U8 maxSpeed;
101 HPT_U8 currentSpeed;
102 HPT_U8 reserved2[7];
103 }
104 HIM_ADAPTER_CONFIG, *PHIM_ADAPTER_CONFIG;
105
106 typedef struct _HIM_CHANNEL_CONFIG
107 {
108 HPT_U32 io_port;
109 HPT_U32 ctl_port;
110 } HIM_CHANNEL_CONFIG, *PHIM_CHANNEL_CONFIG;
111
112 typedef struct _HIM_DEVICE_FLAGS
113 {
114 HPT_UINT df_atapi :1;
115 HPT_UINT df_removable_drive :1;
116 HPT_UINT df_on_line :1;
117 HPT_UINT df_reduce_mode :1;
118 HPT_UINT df_sata :1;
119 HPT_UINT df_on_pm_port :1;
120 HPT_UINT df_support_read_ahead :1;
121 HPT_UINT df_read_ahead_enabled :1;
122 HPT_UINT df_support_write_cache :1;
123 HPT_UINT df_write_cache_enabled :1;
124 HPT_UINT df_cdrom_device :1;
125 HPT_UINT df_tape_device :1;
126 HPT_UINT df_changer_device :1;
127 HPT_UINT df_support_tcq :1;
128 HPT_UINT df_tcq_enabled :1;
129 HPT_UINT df_support_ncq :1;
130 HPT_UINT df_ncq_enabled :1;
131 HPT_UINT df_sas :1;
132 HPT_UINT df_in_enclosure :1;
133 HPT_UINT df_ssd :1;
134 } DEVICE_FLAGS, *PDEVICE_FLAGS;
135
136 #pragma pack(1)
137 typedef struct _IDENTIFY_DATA {
138 HPT_U16 GeneralConfiguration;
139 HPT_U16 NumberOfCylinders;
140 HPT_U16 Reserved1;
141 HPT_U16 NumberOfHeads;
142 HPT_U16 UnformattedBytesPerTrack;
143 HPT_U16 UnformattedBytesPerSector;
144 HPT_U8 SasAddress[8];
145 HPT_U16 SerialNumber[10];
146 HPT_U16 BufferType;
147 HPT_U16 BufferSectorSize;
148 HPT_U16 NumberOfEccBytes;
149 HPT_U16 FirmwareRevision[4];
150 HPT_U16 ModelNumber[20];
151 HPT_U8 MaximumBlockTransfer;
152 HPT_U8 VendorUnique2;
153 HPT_U16 DoubleWordIo;
154 HPT_U16 Capabilities;
155 HPT_U16 Reserved2;
156 HPT_U8 VendorUnique3;
157 HPT_U8 PioCycleTimingMode;
158 HPT_U8 VendorUnique4;
159 HPT_U8 DmaCycleTimingMode;
160 HPT_U16 TranslationFieldsValid;
161 HPT_U16 NumberOfCurrentCylinders;
162 HPT_U16 NumberOfCurrentHeads;
163 HPT_U16 CurrentSectorsPerTrack;
164 HPT_U32 CurrentSectorCapacity;
165 HPT_U16 CurrentMultiSectorSetting;
166 HPT_U32 UserAddressableSectors;
167 HPT_U8 SingleWordDMASupport;
168 HPT_U8 SingleWordDMAActive;
169 HPT_U8 MultiWordDMASupport;
170 HPT_U8 MultiWordDMAActive;
171 HPT_U8 AdvancedPIOModes;
172 HPT_U8 Reserved4;
173 HPT_U16 MinimumMWXferCycleTime;
174 HPT_U16 RecommendedMWXferCycleTime;
175 HPT_U16 MinimumPIOCycleTime;
176 HPT_U16 MinimumPIOCycleTimeIORDY;
177 HPT_U16 Reserved5[2];
178 HPT_U16 ReleaseTimeOverlapped;
179 HPT_U16 ReleaseTimeServiceCommand;
180 HPT_U16 MajorRevision;
181 HPT_U16 MinorRevision;
182 HPT_U16 MaxQueueDepth;
183 HPT_U16 SataCapability;
184 HPT_U16 Reserved6[9];
185 HPT_U16 CommandSupport;
186 HPT_U16 CommandEnable;
187 HPT_U16 UtralDmaMode;
188 HPT_U16 Reserved7[11];
189 HPT_U32 Lba48BitLow;
190 HPT_U32 Lba48BitHigh;
191 HPT_U16 Reserved8[23];
192 HPT_U16 SpecialFunctionsEnabled;
193 HPT_U16 Reserved9[128];
194 }
195 #ifdef __GNUC__
196 __attribute__((packed))
197 #endif
198 IDENTIFY_DATA, *PIDENTIFY_DATA;
199 #pragma pack()
200
201 typedef struct _HIM_DEVICE_CONFIG
202 {
203 HPT_U64 capacity;
204 HPT_U32 logical_sector_size;
205
206 DEVICE_FLAGS flags;
207
208 HPT_U8 path_id;
209 HPT_U8 target_id;
210 HPT_U8 max_queue_depth;
211 HPT_U8 spin_up_mode;
212
213 HPT_U8 reserved;
214 HPT_U8 transfer_mode;
215 HPT_U8 bMaxShowMode;
216 HPT_U8 bDeUsable_Mode;
217
218 HPT_U16 max_sectors_per_cmd;
219
220 PIDENTIFY_DATA pIdentifyData;
221
222
223 HPT_U8 fixed_path_id; /*equals to phy id */
224 }
225 HIM_DEVICE_CONFIG, *PHIM_DEVICE_CONFIG;
226
227
228 #define _DIT_MODE 0
229 #define _DIT_601 1
230 #define _DIT_READ_AHEAD 2
231 #define _DIT_WRITE_CACHE 3
232 #define _DIT_TCQ 4
233 #define _DIT_NCQ 5
234 #define _DIT_BEEP_OFF 6
235 #define _DIT_SPIN_UP_MODE 7
236 #define _DIT_IDLE_STANDBY 8
237 #define _DIT_IDENTIFY 9
238
239 #define SPIN_UP_MODE_NOSUPPORT 0
240 #define SPIN_UP_MODE_FULL 1
241 #define SPIN_UP_MODE_STANDBY 2
242
243 struct tcq_control {
244 HPT_U8 enable;
245 HPT_U8 depth;
246 };
247
248 struct ncq_control {
249 HPT_U8 enable;
250 HPT_U8 depth;
251 };
252
253 typedef struct _HIM_ALTERABLE_DEV_INFO{
254 HPT_U8 type;
255 union {
256 HPT_U8 mode;
257 HPT_U8 enable_read_ahead;
258 HPT_U8 enable_read_cache;
259 HPT_U8 enable_write_cache;
260 struct tcq_control tcq;
261 struct ncq_control ncq;
262 void * adapter;
263 HPT_U8 spin_up_mode;
264 HPT_U8 idle_standby_timeout;
265 HPT_U8 identify_indicator;
266 }u;
267 } HIM_ALTERABLE_DEV_INFO, *PHIM_ALTERABLE_DEV_INFO;
268
269 struct _COMMAND;
270 struct _IOCTL_ARG;
271
272 typedef void (*PROBE_CALLBACK)(void *arg, void *dev, int index);
273
274 typedef struct _HIM {
275 char *name;
276 struct _HIM *next;
277 HPT_UINT max_sg_descriptors;
278 #define _HIM_INTERFACE(_type, _fn, _args) _type (* _fn) _args;
279 #include <dev/hpt27xx/himfuncs.h>
280 }
281 HIM, *PHIM;
282
283
284 #pragma pack(1)
285 #ifdef SG_FLAG_EOT
286 #error "don't use SG_FLAG_EOT with _SG.eot. clean the code!"
287 #endif
288
289 typedef struct _SG {
290 HPT_U32 size;
291 HPT_UINT eot;
292 union {
293 HPT_U8 FAR * _logical;
294 BUS_ADDRESS bus;
295 }
296 addr;
297 }
298 SG, *PSG;
299 #pragma pack()
300
301 typedef struct _AtaCommand
302 {
303 HPT_U64 Lba;
304 HPT_U16 nSectors;
305 HPT_U16 pad;
306 } AtaComm, *PAtaComm;
307
308 #define ATA_CMD_NOP 0x0
309
310 #define ATA_CMD_SET_FEATURES 0xef
311 #define ATA_CMD_FLUSH 0xE7
312 #define ATA_CMD_VERIFY 0x40
313 #define ATA_CMD_STANDBY 0xe2
314 #define ATA_CMD_READ_MULTI 0xC4
315 #define ATA_CMD_READ_MULTI_EXT 0x29
316 #define ATA_CMD_WRITE_MULTI 0xC5
317 #define ATA_CMD_WRITE_MULTI_EXT 0x39
318 #define ATA_CMD_WRITE_MULTI_FUA_EXT 0xCE
319
320 #define ATA_CMD_READ_DMA 0xc8 /* IDE DMA read command */
321 #define ATA_CMD_WRITE_DMA 0xca /* IDE DMA write command */
322 #define ATA_CMD_READ_DMA_EXT 0x25
323 #define ATA_CMD_READ_QUEUE_EXT 0x26
324 #define ATA_CMD_READ_MAX_ADDR 0x27
325 #define ATA_CMD_READ_EXT 0x24
326 #define ATA_CMD_VERIFY_EXT 0x42
327 #define ATA_CMD_WRITE_DMA_EXT 0x35
328 #define ATA_CMD_WRITE_QUEUE_EXT 0x36
329 #define ATA_CMD_WRITE_EXT 0x34
330
331 #define ATA_SET_FEATURES_XFER 0x3
332 #define ATA_SECTOR_SIZE 512
333
334 typedef struct _PassthroughCmd {
335 HPT_U16 bFeaturesReg;
336 HPT_U16 bSectorCountReg;
337 HPT_U16 bLbaLowReg;
338 HPT_U16 bLbaMidReg;
339 HPT_U16 bLbaHighReg;
340 HPT_U8 bDriveHeadReg;
341 HPT_U8 bCommandReg;
342 HPT_U16 nSectors;
343 HPT_U8 *pDataBuffer;
344 }
345 PassthroughCmd;
346
347 typedef struct _ScsiComm {
348 HPT_U8 cdbLength;
349 HPT_U8 senseLength;
350 HPT_U8 scsiStatus;
351 HPT_U8 reserve1;
352 HPT_U32 dataLength;
353 HPT_U8 cdb[16];
354 HPT_U8 *senseBuffer;
355 }
356 ScsiComm;
357
358 typedef struct _ScsiExtComm {
359 HPT_U8 cdbLength;
360 HPT_U8 senseLength;
361 HPT_U8 scsiStatus;
362 HPT_U8 reserve1;
363 HPT_U32 dataLength;
364 HPT_U8 cdb[16];
365 HPT_U8 *senseBuffer;
366 HPT_U8 lun[8];
367 }
368 ScsiExtComm;
369
370
371 #define CTRL_CMD_REBUILD 1
372 #define CTRL_CMD_VERIFY 2
373 #define CTRL_CMD_INIT 3
374
375
376 typedef struct _R5ControlCmd {
377 HPT_U64 StripeLine;
378 HPT_U16 Offset;
379 HPT_U8 Command;
380 HPT_U8 CmdTarget;
381 }
382 R5ControlCmd, *PR5ControlCmd;
383
384 typedef struct _HPT_ADDRESS
385 {
386 HPT_U8 * logical;
387 BUS_ADDRESS bus;
388 }
389 HPT_ADDRESS;
390
391
392 typedef struct ctl_pages {
393 HPT_ADDRESS *pages;
394 HPT_UINT page_size;
395 HPT_UINT npages;
396 HPT_UINT min_sg_descriptors;
397 } CONTROL_PAGES, *PCONTROL_PAGES;
398
399 typedef struct _R1ControlCmd {
400 HPT_U64 Lba;
401 HPT_U16 nSectors;
402 HPT_U8 Command;
403 HPT_U8 CmdTarget;
404 PCONTROL_PAGES ctl_pages;
405 }
406 R1ControlCmd, *PR1ControlCmd;
407
408 typedef void (*TQ_PROC)(void *arg);
409
410 struct tq_item {
411 TQ_PROC proc;
412 void *arg;
413 struct tq_item *next;
414 };
415
416 #define INIT_TQ_ITEM(t, p, a) \
417 do { (t)->proc = p; (t)->arg = a; (t)->next = 0; } while (0)
418
419 typedef struct _COMMAND
420 {
421
422 struct _VBUS * vbus;
423
424 struct freelist *grplist;
425 HPT_UINT grpcnt;
426
427
428 struct list_head q_link;
429 struct tq_item done_dpc;
430
431 HPT_UINT extsize;
432 void *ext;
433
434
435
436 void *target;
437 void *priv;
438 HPT_UPTR priv2;
439
440 int priority;
441 struct lock_request *owned_lock;
442 struct lock_request *lock_req;
443 void (*dtor)(struct _COMMAND *, void *);
444 void *dtor_arg;
445
446 union{
447 AtaComm Ide;
448 PassthroughCmd Passthrough;
449 ScsiComm Scsi;
450 ScsiExtComm ScsiExt;
451 R5ControlCmd R5Control;
452 R1ControlCmd R1Control;
453 } uCmd;
454
455 HPT_U8 type; /* CMD_TYPE_* */
456
457 struct {
458 HPT_U8 physical_sg: 1;
459 HPT_U8 data_in: 1;
460 HPT_U8 data_out: 1;
461 HPT_U8 transform : 1;
462 HPT_U8 hard_flush: 2;
463 HPT_U8 from_cc: 1;
464 HPT_U8 force_cc: 1;
465 } flags;
466
467 /* return status */
468 HPT_U8 Result;
469 /* retry count */
470 HPT_U8 RetryCount;
471
472
473 PSG psg;
474
475
476 int (*buildsgl)(struct _COMMAND *cmd, PSG psg, int logical);
477 void (*done)(struct _COMMAND *cmd);
478 }
479 COMMAND, *PCOMMAND;
480
481 /* command types */
482 #define CMD_TYPE_IO 0
483 #define CMD_TYPE_CONTROL 1
484 #define CMD_TYPE_ATAPI 2
485 #define CMD_TYPE_SCSI CMD_TYPE_ATAPI
486 #define CMD_TYPE_PASSTHROUGH 3
487 #define CMD_TYPE_FLUSH 4
488 #define CMD_TYPE_SCSI_EXT 5
489 #define CMD_TYPE_IO_INDIRECT 0x80
490
491 /* flush command flags */
492 #define CF_HARD_FLUSH_CACHE 1
493 #define CF_HARD_FLUSH_STANDBY 2
494
495 /* command return values */
496 #define RETURN_PENDING 0
497 #define RETURN_SUCCESS 1
498 #define RETURN_BAD_DEVICE 2
499 #define RETURN_BAD_PARAMETER 3
500 #define RETURN_WRITE_NO_DRQ 4
501 #define RETURN_DEVICE_BUSY 5
502 #define RETURN_INVALID_REQUEST 6
503 #define RETURN_SELECTION_TIMEOUT 7
504 #define RETURN_IDE_ERROR 8
505 #define RETURN_NEED_LOGICAL_SG 9
506 #define RETURN_NEED_PHYSICAL_SG 10
507 #define RETURN_RETRY 11
508 #define RETURN_DATA_ERROR 12
509 #define RETURN_BUS_RESET 13
510 #define RETURN_BAD_TRANSFER_LENGTH 14
511 #define RETURN_INSUFFICIENT_MEMORY 15
512 #define RETURN_SECTOR_ERROR 16
513 #define RETURN_NEED_SPINUP 17
514
515 #if defined(__cplusplus)
516 }
517 #endif
518 #endif
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