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sys/dev/hptmv/entry.c
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1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2004-2005 HighPoint Technologies, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/kernel.h> 35 #include <sys/bus.h> 36 #include <sys/malloc.h> 37 #include <sys/resource.h> 38 #include <sys/time.h> 39 #include <sys/callout.h> 40 #include <sys/signalvar.h> 41 #include <sys/eventhandler.h> 42 #include <sys/proc.h> 43 #include <sys/kthread.h> 44 45 #include <sys/mutex.h> 46 #include <sys/module.h> 47 #include <sys/sx.h> 48 49 #include <dev/pci/pcireg.h> 50 #include <dev/pci/pcivar.h> 51 52 #ifndef __KERNEL__ 53 #define __KERNEL__ 54 #endif 55 56 #include <dev/hptmv/global.h> 57 #include <dev/hptmv/hptintf.h> 58 #include <dev/hptmv/osbsd.h> 59 #include <dev/hptmv/access601.h> 60 61 62 #ifdef DEBUG 63 #ifdef DEBUG_LEVEL 64 int hpt_dbg_level = DEBUG_LEVEL; 65 #else 66 int hpt_dbg_level = 0; 67 #endif 68 #endif 69 70 #define MV_ERROR printf 71 72 /* 73 * CAM SIM entry points 74 */ 75 static int hpt_probe (device_t dev); 76 static void launch_worker_thread(void); 77 static int hpt_attach(device_t dev); 78 static int hpt_detach(device_t dev); 79 static int hpt_shutdown(device_t dev); 80 static void hpt_poll(struct cam_sim *sim); 81 static void hpt_intr(void *arg); 82 static void hpt_async(void *callback_arg, u_int32_t code, struct cam_path *path, void *arg); 83 static void hpt_action(struct cam_sim *sim, union ccb *ccb); 84 85 static device_method_t driver_methods[] = { 86 /* Device interface */ 87 DEVMETHOD(device_probe, hpt_probe), 88 DEVMETHOD(device_attach, hpt_attach), 89 DEVMETHOD(device_detach, hpt_detach), 90 91 DEVMETHOD(device_shutdown, hpt_shutdown), 92 DEVMETHOD_END 93 }; 94 95 static driver_t hpt_pci_driver = { 96 __str(PROC_DIR_NAME), 97 driver_methods, 98 sizeof(IAL_ADAPTER_T) 99 }; 100 101 #define __DRIVER_MODULE(p1, p2, p3, p4, p5) DRIVER_MODULE(p1, p2, p3, p4, p5) 102 __DRIVER_MODULE(PROC_DIR_NAME, pci, hpt_pci_driver, 0, 0); 103 MODULE_DEPEND(PROC_DIR_NAME, cam, 1, 1, 1); 104 105 #define ccb_ccb_ptr spriv_ptr0 106 #define ccb_adapter ccb_h.spriv_ptr1 107 108 static void SetInquiryData(PINQUIRYDATA inquiryData, PVDevice pVDev); 109 static void HPTLIBAPI OsSendCommand (_VBUS_ARG union ccb * ccb); 110 static void HPTLIBAPI fOsCommandDone(_VBUS_ARG PCommand pCmd); 111 static void ccb_done(union ccb *ccb); 112 static void hpt_queue_ccb(union ccb **ccb_Q, union ccb *ccb); 113 static void hpt_free_ccb(union ccb **ccb_Q, union ccb *ccb); 114 static void hpt_intr_locked(IAL_ADAPTER_T *pAdapter); 115 static void hptmv_free_edma_queues(IAL_ADAPTER_T *pAdapter); 116 static void hptmv_free_channel(IAL_ADAPTER_T *pAdapter, MV_U8 channelNum); 117 static void handleEdmaError(_VBUS_ARG PCommand pCmd); 118 static int hptmv_init_channel(IAL_ADAPTER_T *pAdapter, MV_U8 channelNum); 119 static int fResetActiveCommands(PVBus _vbus_p); 120 static void fRegisterVdevice(IAL_ADAPTER_T *pAdapter); 121 static int hptmv_allocate_edma_queues(IAL_ADAPTER_T *pAdapter); 122 static void hptmv_handle_event_disconnect(void *data); 123 static void hptmv_handle_event_connect(void *data); 124 static int start_channel(IAL_ADAPTER_T *pAdapter, MV_U8 channelNum); 125 static void init_vdev_params(IAL_ADAPTER_T *pAdapter, MV_U8 channel); 126 static int hptmv_parse_identify_results(MV_SATA_CHANNEL *pMvSataChannel); 127 static int HPTLIBAPI fOsBuildSgl(_VBUS_ARG PCommand pCmd, FPSCAT_GATH pSg, 128 int logical); 129 static MV_BOOLEAN CommandCompletionCB(MV_SATA_ADAPTER *pMvSataAdapter, 130 MV_U8 channelNum, MV_COMPLETION_TYPE comp_type, MV_VOID_PTR commandId, 131 MV_U16 responseFlags, MV_U32 timeStamp, 132 MV_STORAGE_DEVICE_REGISTERS *registerStruct); 133 static MV_BOOLEAN hptmv_event_notify(MV_SATA_ADAPTER *pMvSataAdapter, 134 MV_EVENT_TYPE eventType, MV_U32 param1, MV_U32 param2); 135 136 #define ccb_ccb_ptr spriv_ptr0 137 #define ccb_adapter ccb_h.spriv_ptr1 138 139 static struct sx hptmv_list_lock; 140 SX_SYSINIT(hptmv_list_lock, &hptmv_list_lock, "hptmv list"); 141 IAL_ADAPTER_T *gIal_Adapter = NULL; 142 IAL_ADAPTER_T *pCurAdapter = NULL; 143 static MV_SATA_CHANNEL gMvSataChannels[MAX_VBUS][MV_SATA_CHANNELS_NUM]; 144 145 typedef struct st_HPT_DPC { 146 IAL_ADAPTER_T *pAdapter; 147 void (*dpc)(IAL_ADAPTER_T *, void *, UCHAR); 148 void *arg; 149 UCHAR flags; 150 } ST_HPT_DPC; 151 152 #define MAX_DPC 16 153 UCHAR DPC_Request_Nums = 0; 154 static ST_HPT_DPC DpcQueue[MAX_DPC]; 155 static int DpcQueue_First=0; 156 static int DpcQueue_Last = 0; 157 static struct mtx DpcQueue_Lock; 158 MTX_SYSINIT(hpmtv_dpc_lock, &DpcQueue_Lock, "hptmv dpc", MTX_DEF); 159 160 char DRIVER_VERSION[] = "v1.16"; 161 162 /******************************************************************************* 163 * Name: hptmv_free_channel 164 * 165 * Description: free allocated queues for the given channel 166 * 167 * Parameters: pMvSataAdapter - pointer to the RR18xx controller this 168 * channel connected to. 169 * channelNum - channel number. 170 * 171 ******************************************************************************/ 172 static void 173 hptmv_free_channel(IAL_ADAPTER_T *pAdapter, MV_U8 channelNum) 174 { 175 HPT_ASSERT(channelNum < MV_SATA_CHANNELS_NUM); 176 pAdapter->mvSataAdapter.sataChannel[channelNum] = NULL; 177 } 178 179 static void failDevice(PVDevice pVDev) 180 { 181 PVBus _vbus_p = pVDev->pVBus; 182 IAL_ADAPTER_T *pAdapter = (IAL_ADAPTER_T *)_vbus_p->OsExt; 183 184 pVDev->u.disk.df_on_line = 0; 185 pVDev->vf_online = 0; 186 if (pVDev->pfnDeviceFailed) 187 CallWhenIdle(_VBUS_P (DPC_PROC)pVDev->pfnDeviceFailed, pVDev); 188 189 fNotifyGUI(ET_DEVICE_REMOVED, pVDev); 190 191 #ifndef FOR_DEMO 192 if (pAdapter->ver_601==2 && !pAdapter->beeping) { 193 pAdapter->beeping = 1; 194 BeepOn(pAdapter->mvSataAdapter.adapterIoBaseAddress); 195 set_fail_led(&pAdapter->mvSataAdapter, pVDev->u.disk.mv->channelNumber, 1); 196 } 197 #endif 198 } 199 200 int MvSataResetChannel(MV_SATA_ADAPTER *pMvSataAdapter, MV_U8 channel); 201 202 static void 203 handleEdmaError(_VBUS_ARG PCommand pCmd) 204 { 205 PDevice pDevice = &pCmd->pVDevice->u.disk; 206 MV_SATA_ADAPTER * pSataAdapter = pDevice->mv->mvSataAdapter; 207 208 if (!pDevice->df_on_line) { 209 KdPrint(("Device is offline")); 210 pCmd->Result = RETURN_BAD_DEVICE; 211 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd); 212 return; 213 } 214 215 if (pCmd->RetryCount++>5) { 216 hpt_printk(("too many retries on channel(%d)\n", pDevice->mv->channelNumber)); 217 failed: 218 failDevice(pCmd->pVDevice); 219 pCmd->Result = RETURN_IDE_ERROR; 220 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd); 221 return; 222 } 223 224 /* reset the channel and retry the command */ 225 if (MvSataResetChannel(pSataAdapter, pDevice->mv->channelNumber)) 226 goto failed; 227 228 fNotifyGUI(ET_DEVICE_ERROR, Map2pVDevice(pDevice)); 229 230 hpt_printk(("Retry on channel(%d)\n", pDevice->mv->channelNumber)); 231 fDeviceSendCommand(_VBUS_P pCmd); 232 } 233 234 /**************************************************************** 235 * Name: hptmv_init_channel 236 * 237 * Description: allocate request and response queues for the EDMA of the 238 * given channel and sets other fields. 239 * 240 * Parameters: 241 * pAdapter - pointer to the emulated adapter data structure 242 * channelNum - channel number. 243 * Return: 0 on success, otherwise on failure 244 ****************************************************************/ 245 static int 246 hptmv_init_channel(IAL_ADAPTER_T *pAdapter, MV_U8 channelNum) 247 { 248 MV_SATA_CHANNEL *pMvSataChannel; 249 dma_addr_t req_dma_addr; 250 dma_addr_t rsp_dma_addr; 251 252 if (channelNum >= MV_SATA_CHANNELS_NUM) 253 { 254 MV_ERROR("RR18xx[%d]: Bad channelNum=%d", 255 pAdapter->mvSataAdapter.adapterId, channelNum); 256 return -1; 257 } 258 259 pMvSataChannel = &gMvSataChannels[pAdapter->mvSataAdapter.adapterId][channelNum]; 260 pAdapter->mvSataAdapter.sataChannel[channelNum] = pMvSataChannel; 261 pMvSataChannel->channelNumber = channelNum; 262 pMvSataChannel->lba48Address = MV_FALSE; 263 pMvSataChannel->maxReadTransfer = MV_FALSE; 264 265 pMvSataChannel->requestQueue = (struct mvDmaRequestQueueEntry *) 266 (pAdapter->requestsArrayBaseAlignedAddr + (channelNum * MV_EDMA_REQUEST_QUEUE_SIZE)); 267 req_dma_addr = pAdapter->requestsArrayBaseDmaAlignedAddr + (channelNum * MV_EDMA_REQUEST_QUEUE_SIZE); 268 269 270 KdPrint(("requestQueue addr is 0x%llX", (HPT_U64)(ULONG_PTR)req_dma_addr)); 271 272 /* check the 1K alignment of the request queue*/ 273 if (req_dma_addr & 0x3ff) 274 { 275 MV_ERROR("RR18xx[%d]: request queue allocated isn't 1 K aligned," 276 " dma_addr=%llx channel=%d\n", pAdapter->mvSataAdapter.adapterId, 277 (HPT_U64)(ULONG_PTR)req_dma_addr, channelNum); 278 return -1; 279 } 280 pMvSataChannel->requestQueuePciLowAddress = req_dma_addr; 281 pMvSataChannel->requestQueuePciHiAddress = 0; 282 KdPrint(("RR18xx[%d,%d]: request queue allocated: 0x%p", 283 pAdapter->mvSataAdapter.adapterId, channelNum, 284 pMvSataChannel->requestQueue)); 285 pMvSataChannel->responseQueue = (struct mvDmaResponseQueueEntry *) 286 (pAdapter->responsesArrayBaseAlignedAddr + (channelNum * MV_EDMA_RESPONSE_QUEUE_SIZE)); 287 rsp_dma_addr = pAdapter->responsesArrayBaseDmaAlignedAddr + (channelNum * MV_EDMA_RESPONSE_QUEUE_SIZE); 288 289 /* check the 256 alignment of the response queue*/ 290 if (rsp_dma_addr & 0xff) 291 { 292 MV_ERROR("RR18xx[%d,%d]: response queue allocated isn't 256 byte " 293 "aligned, dma_addr=%llx\n", 294 pAdapter->mvSataAdapter.adapterId, channelNum, (HPT_U64)(ULONG_PTR)rsp_dma_addr); 295 return -1; 296 } 297 pMvSataChannel->responseQueuePciLowAddress = rsp_dma_addr; 298 pMvSataChannel->responseQueuePciHiAddress = 0; 299 KdPrint(("RR18xx[%d,%d]: response queue allocated: 0x%p", 300 pAdapter->mvSataAdapter.adapterId, channelNum, 301 pMvSataChannel->responseQueue)); 302 303 pAdapter->mvChannel[channelNum].online = MV_TRUE; 304 return 0; 305 } 306 307 /****************************************************************************** 308 * Name: hptmv_parse_identify_results 309 * 310 * Description: this functions parses the identify command results, checks 311 * that the connected deives can be accesed by RR18xx EDMA, 312 * and updates the channel structure accordingly. 313 * 314 * Parameters: pMvSataChannel, pointer to the channel data structure. 315 * 316 * Returns: =0 ->success, < 0 ->failure. 317 * 318 ******************************************************************************/ 319 static int 320 hptmv_parse_identify_results(MV_SATA_CHANNEL *pMvSataChannel) 321 { 322 MV_U16 *iden = pMvSataChannel->identifyDevice; 323 324 /*LBA addressing*/ 325 if (! (iden[IDEN_CAPACITY_1_OFFSET] & 0x200)) 326 { 327 KdPrint(("IAL Error in IDENTIFY info: LBA not supported\n")); 328 return -1; 329 } 330 else 331 { 332 KdPrint(("%25s - %s\n", "Capabilities", "LBA supported")); 333 } 334 /*DMA support*/ 335 if (! (iden[IDEN_CAPACITY_1_OFFSET] & 0x100)) 336 { 337 KdPrint(("IAL Error in IDENTIFY info: DMA not supported\n")); 338 return -1; 339 } 340 else 341 { 342 KdPrint(("%25s - %s\n", "Capabilities", "DMA supported")); 343 } 344 /* PIO */ 345 if ((iden[IDEN_VALID] & 2) == 0) 346 { 347 KdPrint(("IAL Error in IDENTIFY info: not able to find PIO mode\n")); 348 return -1; 349 } 350 KdPrint(("%25s - 0x%02x\n", "PIO modes supported", 351 iden[IDEN_PIO_MODE_SPPORTED] & 0xff)); 352 353 /*UDMA*/ 354 if ((iden[IDEN_VALID] & 4) == 0) 355 { 356 KdPrint(("IAL Error in IDENTIFY info: not able to find UDMA mode\n")); 357 return -1; 358 } 359 360 /* 48 bit address */ 361 if ((iden[IDEN_SUPPORTED_COMMANDS2] & 0x400)) 362 { 363 KdPrint(("%25s - %s\n", "LBA48 addressing", "supported")); 364 pMvSataChannel->lba48Address = MV_TRUE; 365 } 366 else 367 { 368 KdPrint(("%25s - %s\n", "LBA48 addressing", "Not supported")); 369 pMvSataChannel->lba48Address = MV_FALSE; 370 } 371 return 0; 372 } 373 374 static void 375 init_vdev_params(IAL_ADAPTER_T *pAdapter, MV_U8 channel) 376 { 377 PVDevice pVDev = &pAdapter->VDevices[channel]; 378 MV_SATA_CHANNEL *pMvSataChannel = pAdapter->mvSataAdapter.sataChannel[channel]; 379 MV_U16_PTR IdentifyData = pMvSataChannel->identifyDevice; 380 381 pMvSataChannel->outstandingCommands = 0; 382 383 pVDev->u.disk.mv = pMvSataChannel; 384 pVDev->u.disk.df_on_line = 1; 385 pVDev->u.disk.pVBus = &pAdapter->VBus; 386 pVDev->pVBus = &pAdapter->VBus; 387 388 #ifdef SUPPORT_48BIT_LBA 389 if (pMvSataChannel->lba48Address == MV_TRUE) 390 pVDev->u.disk.dDeRealCapacity = ((IdentifyData[101]<<16) | IdentifyData[100]) - 1; 391 else 392 #endif 393 if(IdentifyData[53] & 1) { 394 pVDev->u.disk.dDeRealCapacity = 395 (((IdentifyData[58]<<16 | IdentifyData[57]) < (IdentifyData[61]<<16 | IdentifyData[60])) ? 396 (IdentifyData[61]<<16 | IdentifyData[60]) : 397 (IdentifyData[58]<<16 | IdentifyData[57])) - 1; 398 } else 399 pVDev->u.disk.dDeRealCapacity = 400 (IdentifyData[61]<<16 | IdentifyData[60]) - 1; 401 402 pVDev->u.disk.bDeUsable_Mode = pVDev->u.disk.bDeModeSetting = 403 pAdapter->mvChannel[channel].maxPioModeSupported - MV_ATA_TRANSFER_PIO_0; 404 405 if (pAdapter->mvChannel[channel].maxUltraDmaModeSupported!=0xFF) { 406 pVDev->u.disk.bDeUsable_Mode = pVDev->u.disk.bDeModeSetting = 407 pAdapter->mvChannel[channel].maxUltraDmaModeSupported - MV_ATA_TRANSFER_UDMA_0 + 8; 408 } 409 } 410 411 static void device_change(IAL_ADAPTER_T *pAdapter , MV_U8 channelIndex, int plugged) 412 { 413 PVDevice pVDev; 414 MV_SATA_ADAPTER *pMvSataAdapter = &pAdapter->mvSataAdapter; 415 MV_SATA_CHANNEL *pMvSataChannel = pMvSataAdapter->sataChannel[channelIndex]; 416 417 if (!pMvSataChannel) return; 418 419 if (plugged) 420 { 421 pVDev = &(pAdapter->VDevices[channelIndex]); 422 init_vdev_params(pAdapter, channelIndex); 423 424 pVDev->VDeviceType = pVDev->u.disk.df_atapi? VD_ATAPI : 425 pVDev->u.disk.df_removable_drive? VD_REMOVABLE : VD_SINGLE_DISK; 426 427 pVDev->VDeviceCapacity = pVDev->u.disk.dDeRealCapacity-SAVE_FOR_RAID_INFO; 428 pVDev->pfnSendCommand = pfnSendCommand[pVDev->VDeviceType]; 429 pVDev->pfnDeviceFailed = pfnDeviceFailed[pVDev->VDeviceType]; 430 pVDev->vf_online = 1; 431 432 #ifdef SUPPORT_ARRAY 433 if(pVDev->pParent) 434 { 435 int iMember; 436 for(iMember = 0; iMember < pVDev->pParent->u.array.bArnMember; iMember++) 437 if((PVDevice)pVDev->pParent->u.array.pMember[iMember] == pVDev) 438 pVDev->pParent->u.array.pMember[iMember] = NULL; 439 pVDev->pParent = NULL; 440 } 441 #endif 442 fNotifyGUI(ET_DEVICE_PLUGGED,pVDev); 443 fCheckBootable(pVDev); 444 RegisterVDevice(pVDev); 445 446 #ifndef FOR_DEMO 447 if (pAdapter->beeping) { 448 pAdapter->beeping = 0; 449 BeepOff(pAdapter->mvSataAdapter.adapterIoBaseAddress); 450 } 451 #endif 452 453 } 454 else 455 { 456 pVDev = &(pAdapter->VDevices[channelIndex]); 457 failDevice(pVDev); 458 } 459 } 460 461 static int 462 start_channel(IAL_ADAPTER_T *pAdapter, MV_U8 channelNum) 463 { 464 MV_SATA_ADAPTER *pMvSataAdapter = &pAdapter->mvSataAdapter; 465 MV_SATA_CHANNEL *pMvSataChannel = pMvSataAdapter->sataChannel[channelNum]; 466 MV_CHANNEL *pChannelInfo = &(pAdapter->mvChannel[channelNum]); 467 MV_U32 udmaMode,pioMode; 468 469 KdPrint(("RR18xx [%d]: start channel (%d)", pMvSataAdapter->adapterId, 470 channelNum)); 471 472 473 /* Software reset channel */ 474 if (mvStorageDevATASoftResetDevice(pMvSataAdapter, channelNum) == MV_FALSE) 475 { 476 MV_ERROR("RR18xx [%d,%d]: failed to perform Software reset\n", 477 pMvSataAdapter->adapterId, channelNum); 478 return -1; 479 } 480 481 /* Hardware reset channel */ 482 if (mvSataChannelHardReset(pMvSataAdapter, channelNum) == MV_FALSE) 483 { 484 /* If failed, try again - this is when trying to hardreset a channel */ 485 /* when drive is just spinning up */ 486 StallExec(5000000); /* wait 5 sec before trying again */ 487 if (mvSataChannelHardReset(pMvSataAdapter, channelNum) == MV_FALSE) 488 { 489 MV_ERROR("RR18xx [%d,%d]: failed to perform Hard reset\n", 490 pMvSataAdapter->adapterId, channelNum); 491 return -1; 492 } 493 } 494 495 /* identify device*/ 496 if (mvStorageDevATAIdentifyDevice(pMvSataAdapter, channelNum) == MV_FALSE) 497 { 498 MV_ERROR("RR18xx [%d,%d]: failed to perform ATA Identify command\n" 499 , pMvSataAdapter->adapterId, channelNum); 500 return -1; 501 } 502 if (hptmv_parse_identify_results(pMvSataChannel)) 503 { 504 MV_ERROR("RR18xx [%d,%d]: Error in parsing ATA Identify message\n" 505 , pMvSataAdapter->adapterId, channelNum); 506 return -1; 507 } 508 509 /* mvStorageDevATASetFeatures */ 510 /* Disable 8 bit PIO in case CFA enabled */ 511 if (pMvSataChannel->identifyDevice[86] & 4) 512 { 513 KdPrint(("RR18xx [%d]: Disable 8 bit PIO (CFA enabled) \n", 514 pMvSataAdapter->adapterId)); 515 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum, 516 MV_ATA_SET_FEATURES_DISABLE_8_BIT_PIO, 0, 517 0, 0, 0) == MV_FALSE) 518 { 519 MV_ERROR("RR18xx [%d]: channel %d: mvStorageDevATASetFeatures" 520 " failed\n", pMvSataAdapter->adapterId, channelNum); 521 return -1; 522 } 523 } 524 /* Write cache */ 525 #ifdef ENABLE_WRITE_CACHE 526 if (pMvSataChannel->identifyDevice[82] & 0x20) 527 { 528 if (!(pMvSataChannel->identifyDevice[85] & 0x20)) /* if not enabled by default */ 529 { 530 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum, 531 MV_ATA_SET_FEATURES_ENABLE_WCACHE, 0, 532 0, 0, 0) == MV_FALSE) 533 { 534 MV_ERROR("RR18xx [%d]: channel %d: mvStorageDevATASetFeatures failed\n", 535 pMvSataAdapter->adapterId, channelNum); 536 return -1; 537 } 538 } 539 KdPrint(("RR18xx [%d]: channel %d, write cache enabled\n", 540 pMvSataAdapter->adapterId, channelNum)); 541 } 542 else 543 { 544 KdPrint(("RR18xx [%d]: channel %d, write cache not supported\n", 545 pMvSataAdapter->adapterId, channelNum)); 546 } 547 #else /* disable write cache */ 548 { 549 if (pMvSataChannel->identifyDevice[85] & 0x20) 550 { 551 KdPrint(("RR18xx [%d]: channel =%d, disable write cache\n", 552 pMvSataAdapter->adapterId, channelNum)); 553 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum, 554 MV_ATA_SET_FEATURES_DISABLE_WCACHE, 0, 555 0, 0, 0) == MV_FALSE) 556 { 557 MV_ERROR("RR18xx [%d]: channel %d: mvStorageDevATASetFeatures failed\n", 558 pMvSataAdapter->adapterId, channelNum); 559 return -1; 560 } 561 } 562 KdPrint(("RR18xx [%d]: channel=%d, write cache disabled\n", 563 pMvSataAdapter->adapterId, channelNum)); 564 } 565 #endif 566 567 /* Set transfer mode */ 568 KdPrint(("RR18xx [%d] Set transfer mode XFER_PIO_SLOW\n", 569 pMvSataAdapter->adapterId)); 570 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum, 571 MV_ATA_SET_FEATURES_TRANSFER, 572 MV_ATA_TRANSFER_PIO_SLOW, 0, 0, 0) == 573 MV_FALSE) 574 { 575 MV_ERROR("RR18xx [%d] channel %d: Set Features failed\n", 576 pMvSataAdapter->adapterId, channelNum); 577 return -1; 578 } 579 580 if (pMvSataChannel->identifyDevice[IDEN_PIO_MODE_SPPORTED] & 1) 581 { 582 pioMode = MV_ATA_TRANSFER_PIO_4; 583 } 584 else if (pMvSataChannel->identifyDevice[IDEN_PIO_MODE_SPPORTED] & 2) 585 { 586 pioMode = MV_ATA_TRANSFER_PIO_3; 587 } 588 else 589 { 590 MV_ERROR("IAL Error in IDENTIFY info: PIO modes 3 and 4 not supported\n"); 591 pioMode = MV_ATA_TRANSFER_PIO_SLOW; 592 } 593 594 KdPrint(("RR18xx [%d] Set transfer mode XFER_PIO_4\n", 595 pMvSataAdapter->adapterId)); 596 pAdapter->mvChannel[channelNum].maxPioModeSupported = pioMode; 597 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum, 598 MV_ATA_SET_FEATURES_TRANSFER, 599 pioMode, 0, 0, 0) == MV_FALSE) 600 { 601 MV_ERROR("RR18xx [%d] channel %d: Set Features failed\n", 602 pMvSataAdapter->adapterId, channelNum); 603 return -1; 604 } 605 606 udmaMode = MV_ATA_TRANSFER_UDMA_0; 607 if (pMvSataChannel->identifyDevice[IDEN_UDMA_MODE] & 0x40) 608 { 609 udmaMode = MV_ATA_TRANSFER_UDMA_6; 610 } 611 else if (pMvSataChannel->identifyDevice[IDEN_UDMA_MODE] & 0x20) 612 { 613 udmaMode = MV_ATA_TRANSFER_UDMA_5; 614 } 615 else if (pMvSataChannel->identifyDevice[IDEN_UDMA_MODE] & 0x10) 616 { 617 udmaMode = MV_ATA_TRANSFER_UDMA_4; 618 } 619 else if (pMvSataChannel->identifyDevice[IDEN_UDMA_MODE] & 8) 620 { 621 udmaMode = MV_ATA_TRANSFER_UDMA_3; 622 } 623 else if (pMvSataChannel->identifyDevice[IDEN_UDMA_MODE] & 4) 624 { 625 udmaMode = MV_ATA_TRANSFER_UDMA_2; 626 } 627 628 KdPrint(("RR18xx [%d] Set transfer mode XFER_UDMA_%d\n", 629 pMvSataAdapter->adapterId, udmaMode & 0xf)); 630 pChannelInfo->maxUltraDmaModeSupported = udmaMode; 631 632 /*if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum, 633 MV_ATA_SET_FEATURES_TRANSFER, udmaMode, 634 0, 0, 0) == MV_FALSE) 635 { 636 MV_ERROR("RR18xx [%d] channel %d: Set Features failed\n", 637 pMvSataAdapter->adapterId, channelNum); 638 return -1; 639 }*/ 640 if (pChannelInfo->maxUltraDmaModeSupported == 0xFF) 641 return TRUE; 642 else 643 do 644 { 645 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum, 646 MV_ATA_SET_FEATURES_TRANSFER, 647 pChannelInfo->maxUltraDmaModeSupported, 648 0, 0, 0) == MV_FALSE) 649 { 650 if (pChannelInfo->maxUltraDmaModeSupported > MV_ATA_TRANSFER_UDMA_0) 651 { 652 if (mvStorageDevATASoftResetDevice(pMvSataAdapter, channelNum) == MV_FALSE) 653 { 654 MV_REG_WRITE_BYTE(pMvSataAdapter->adapterIoBaseAddress, 655 pMvSataChannel->eDmaRegsOffset + 656 0x11c, /* command reg */ 657 MV_ATA_COMMAND_IDLE_IMMEDIATE); 658 mvMicroSecondsDelay(10000); 659 mvSataChannelHardReset(pMvSataAdapter, channelNum); 660 if (mvStorageDevATASoftResetDevice(pMvSataAdapter, channelNum) == MV_FALSE) 661 return FALSE; 662 } 663 if (mvSataChannelHardReset(pMvSataAdapter, channelNum) == MV_FALSE) 664 return FALSE; 665 pChannelInfo->maxUltraDmaModeSupported--; 666 continue; 667 } 668 else return FALSE; 669 } 670 break; 671 }while (1); 672 673 /* Read look ahead */ 674 #ifdef ENABLE_READ_AHEAD 675 if (pMvSataChannel->identifyDevice[82] & 0x40) 676 { 677 if (!(pMvSataChannel->identifyDevice[85] & 0x40)) /* if not enabled by default */ 678 { 679 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum, 680 MV_ATA_SET_FEATURES_ENABLE_RLA, 0, 0, 681 0, 0) == MV_FALSE) 682 { 683 MV_ERROR("RR18xx [%d] channel %d: Set Features failed\n", 684 pMvSataAdapter->adapterId, channelNum); 685 return -1; 686 } 687 } 688 KdPrint(("RR18xx [%d]: channel=%d, read look ahead enabled\n", 689 pMvSataAdapter->adapterId, channelNum)); 690 } 691 else 692 { 693 KdPrint(("RR18xx [%d]: channel %d, Read Look Ahead not supported\n", 694 pMvSataAdapter->adapterId, channelNum)); 695 } 696 #else 697 { 698 if (pMvSataChannel->identifyDevice[86] & 0x20) 699 { 700 KdPrint(("RR18xx [%d]:channel %d, disable read look ahead\n", 701 pMvSataAdapter->adapterId, channelNum)); 702 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum, 703 MV_ATA_SET_FEATURES_DISABLE_RLA, 0, 0, 704 0, 0) == MV_FALSE) 705 { 706 MV_ERROR("RR18xx [%d]:channel %d: ATA Set Features failed\n", 707 pMvSataAdapter->adapterId, channelNum); 708 return -1; 709 } 710 } 711 KdPrint(("RR18xx [%d]:channel %d, read look ahead disabled\n", 712 pMvSataAdapter->adapterId, channelNum)); 713 } 714 #endif 715 716 717 { 718 KdPrint(("RR18xx [%d]: channel %d config EDMA, Non Queued Mode\n", 719 pMvSataAdapter->adapterId, 720 channelNum)); 721 if (mvSataConfigEdmaMode(pMvSataAdapter, channelNum, 722 MV_EDMA_MODE_NOT_QUEUED, 0) == MV_FALSE) 723 { 724 MV_ERROR("RR18xx [%d] channel %d Error: mvSataConfigEdmaMode failed\n", 725 pMvSataAdapter->adapterId, channelNum); 726 return -1; 727 } 728 } 729 /* Enable EDMA */ 730 if (mvSataEnableChannelDma(pMvSataAdapter, channelNum) == MV_FALSE) 731 { 732 MV_ERROR("RR18xx [%d] Failed to enable DMA, channel=%d\n", 733 pMvSataAdapter->adapterId, channelNum); 734 return -1; 735 } 736 MV_ERROR("RR18xx [%d,%d]: channel started successfully\n", 737 pMvSataAdapter->adapterId, channelNum); 738 739 #ifndef FOR_DEMO 740 set_fail_led(pMvSataAdapter, channelNum, 0); 741 #endif 742 return 0; 743 } 744 745 static void 746 hptmv_handle_event(void * data, int flag) 747 { 748 IAL_ADAPTER_T *pAdapter = (IAL_ADAPTER_T *)data; 749 MV_SATA_ADAPTER *pMvSataAdapter = &pAdapter->mvSataAdapter; 750 MV_U8 channelIndex; 751 752 mtx_assert(&pAdapter->lock, MA_OWNED); 753 /* mvOsSemTake(&pMvSataAdapter->semaphore); */ 754 for (channelIndex = 0; channelIndex < MV_SATA_CHANNELS_NUM; channelIndex++) 755 { 756 switch(pAdapter->sataEvents[channelIndex]) 757 { 758 case SATA_EVENT_CHANNEL_CONNECTED: 759 /* Handle only connects */ 760 if (flag == 1) 761 break; 762 KdPrint(("RR18xx [%d,%d]: new device connected\n", 763 pMvSataAdapter->adapterId, channelIndex)); 764 hptmv_init_channel(pAdapter, channelIndex); 765 if (mvSataConfigureChannel( pMvSataAdapter, channelIndex) == MV_FALSE) 766 { 767 MV_ERROR("RR18xx [%d,%d] Failed to configure\n", 768 pMvSataAdapter->adapterId, channelIndex); 769 hptmv_free_channel(pAdapter, channelIndex); 770 } 771 else 772 { 773 /*mvSataChannelHardReset(pMvSataAdapter, channel);*/ 774 if (start_channel( pAdapter, channelIndex)) 775 { 776 MV_ERROR("RR18xx [%d,%d]Failed to start channel\n", 777 pMvSataAdapter->adapterId, channelIndex); 778 hptmv_free_channel(pAdapter, channelIndex); 779 } 780 else 781 { 782 device_change(pAdapter, channelIndex, TRUE); 783 } 784 } 785 pAdapter->sataEvents[channelIndex] = SATA_EVENT_NO_CHANGE; 786 break; 787 788 case SATA_EVENT_CHANNEL_DISCONNECTED: 789 /* Handle only disconnects */ 790 if (flag == 0) 791 break; 792 KdPrint(("RR18xx [%d,%d]: device disconnected\n", 793 pMvSataAdapter->adapterId, channelIndex)); 794 /* Flush pending commands */ 795 if(pMvSataAdapter->sataChannel[channelIndex]) 796 { 797 _VBUS_INST(&pAdapter->VBus) 798 mvSataFlushDmaQueue (pMvSataAdapter, channelIndex, 799 MV_FLUSH_TYPE_CALLBACK); 800 CheckPendingCall(_VBUS_P0); 801 mvSataRemoveChannel(pMvSataAdapter,channelIndex); 802 hptmv_free_channel(pAdapter, channelIndex); 803 pMvSataAdapter->sataChannel[channelIndex] = NULL; 804 KdPrint(("RR18xx [%d,%d]: channel removed\n", 805 pMvSataAdapter->adapterId, channelIndex)); 806 if (pAdapter->outstandingCommands==0 && DPC_Request_Nums==0) 807 Check_Idle_Call(pAdapter); 808 } 809 else 810 { 811 KdPrint(("RR18xx [%d,%d]: channel already removed!!\n", 812 pMvSataAdapter->adapterId, channelIndex)); 813 } 814 pAdapter->sataEvents[channelIndex] = SATA_EVENT_NO_CHANGE; 815 break; 816 817 case SATA_EVENT_NO_CHANGE: 818 break; 819 820 default: 821 break; 822 } 823 } 824 /* mvOsSemRelease(&pMvSataAdapter->semaphore); */ 825 } 826 827 #define EVENT_CONNECT 1 828 #define EVENT_DISCONNECT 0 829 830 static void 831 hptmv_handle_event_connect(void *data) 832 { 833 hptmv_handle_event (data, 0); 834 } 835 836 static void 837 hptmv_handle_event_disconnect(void *data) 838 { 839 hptmv_handle_event (data, 1); 840 } 841 842 static MV_BOOLEAN 843 hptmv_event_notify(MV_SATA_ADAPTER *pMvSataAdapter, MV_EVENT_TYPE eventType, 844 MV_U32 param1, MV_U32 param2) 845 { 846 IAL_ADAPTER_T *pAdapter = pMvSataAdapter->IALData; 847 848 switch (eventType) 849 { 850 case MV_EVENT_TYPE_SATA_CABLE: 851 { 852 MV_U8 channel = param2; 853 854 if (param1 == EVENT_CONNECT) 855 { 856 pAdapter->sataEvents[channel] = SATA_EVENT_CHANNEL_CONNECTED; 857 KdPrint(("RR18xx [%d,%d]: device connected event received\n", 858 pMvSataAdapter->adapterId, channel)); 859 /* Delete previous timers (if multiple drives connected in the same time */ 860 callout_reset(&pAdapter->event_timer_connect, 10 * hz, hptmv_handle_event_connect, pAdapter); 861 } 862 else if (param1 == EVENT_DISCONNECT) 863 { 864 pAdapter->sataEvents[channel] = SATA_EVENT_CHANNEL_DISCONNECTED; 865 KdPrint(("RR18xx [%d,%d]: device disconnected event received \n", 866 pMvSataAdapter->adapterId, channel)); 867 device_change(pAdapter, channel, FALSE); 868 /* Delete previous timers (if multiple drives disconnected in the same time */ 869 /*callout_reset(&pAdapter->event_timer_disconnect, 10 * hz, hptmv_handle_event_disconnect, pAdapter); */ 870 /*It is not necessary to wait, handle it directly*/ 871 hptmv_handle_event_disconnect(pAdapter); 872 } 873 else 874 { 875 876 MV_ERROR("RR18xx: illegal value for param1(%d) at " 877 "connect/disconnect event, host=%d\n", param1, 878 pMvSataAdapter->adapterId ); 879 880 } 881 } 882 break; 883 case MV_EVENT_TYPE_ADAPTER_ERROR: 884 KdPrint(("RR18xx: DEVICE error event received, pci cause " 885 "reg=%x, don't how to handle this\n", param1)); 886 return MV_TRUE; 887 default: 888 MV_ERROR("RR18xx[%d]: unknown event type (%d)\n", 889 pMvSataAdapter->adapterId, eventType); 890 return MV_FALSE; 891 } 892 return MV_TRUE; 893 } 894 895 static int 896 hptmv_allocate_edma_queues(IAL_ADAPTER_T *pAdapter) 897 { 898 pAdapter->requestsArrayBaseAddr = (MV_U8 *)contigmalloc(REQUESTS_ARRAY_SIZE, 899 M_DEVBUF, M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0ul); 900 if (pAdapter->requestsArrayBaseAddr == NULL) 901 { 902 MV_ERROR("RR18xx[%d]: Failed to allocate memory for EDMA request" 903 " queues\n", pAdapter->mvSataAdapter.adapterId); 904 return -1; 905 } 906 pAdapter->requestsArrayBaseDmaAddr = fOsPhysicalAddress(pAdapter->requestsArrayBaseAddr); 907 pAdapter->requestsArrayBaseAlignedAddr = pAdapter->requestsArrayBaseAddr; 908 pAdapter->requestsArrayBaseAlignedAddr += MV_EDMA_REQUEST_QUEUE_SIZE; 909 pAdapter->requestsArrayBaseAlignedAddr = (MV_U8 *) 910 (((ULONG_PTR)pAdapter->requestsArrayBaseAlignedAddr) & ~(ULONG_PTR)(MV_EDMA_REQUEST_QUEUE_SIZE - 1)); 911 pAdapter->requestsArrayBaseDmaAlignedAddr = pAdapter->requestsArrayBaseDmaAddr; 912 pAdapter->requestsArrayBaseDmaAlignedAddr += MV_EDMA_REQUEST_QUEUE_SIZE; 913 pAdapter->requestsArrayBaseDmaAlignedAddr &= ~(ULONG_PTR)(MV_EDMA_REQUEST_QUEUE_SIZE - 1); 914 915 if ((pAdapter->requestsArrayBaseDmaAlignedAddr - pAdapter->requestsArrayBaseDmaAddr) != 916 (pAdapter->requestsArrayBaseAlignedAddr - pAdapter->requestsArrayBaseAddr)) 917 { 918 MV_ERROR("RR18xx[%d]: Error in Request Quueues Alignment\n", 919 pAdapter->mvSataAdapter.adapterId); 920 contigfree(pAdapter->requestsArrayBaseAddr, REQUESTS_ARRAY_SIZE, M_DEVBUF); 921 return -1; 922 } 923 /* response queues */ 924 pAdapter->responsesArrayBaseAddr = (MV_U8 *)contigmalloc(RESPONSES_ARRAY_SIZE, 925 M_DEVBUF, M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0ul); 926 if (pAdapter->responsesArrayBaseAddr == NULL) 927 { 928 MV_ERROR("RR18xx[%d]: Failed to allocate memory for EDMA response" 929 " queues\n", pAdapter->mvSataAdapter.adapterId); 930 contigfree(pAdapter->requestsArrayBaseAddr, RESPONSES_ARRAY_SIZE, M_DEVBUF); 931 return -1; 932 } 933 pAdapter->responsesArrayBaseDmaAddr = fOsPhysicalAddress(pAdapter->responsesArrayBaseAddr); 934 pAdapter->responsesArrayBaseAlignedAddr = pAdapter->responsesArrayBaseAddr; 935 pAdapter->responsesArrayBaseAlignedAddr += MV_EDMA_RESPONSE_QUEUE_SIZE; 936 pAdapter->responsesArrayBaseAlignedAddr = (MV_U8 *) 937 (((ULONG_PTR)pAdapter->responsesArrayBaseAlignedAddr) & ~(ULONG_PTR)(MV_EDMA_RESPONSE_QUEUE_SIZE - 1)); 938 pAdapter->responsesArrayBaseDmaAlignedAddr = pAdapter->responsesArrayBaseDmaAddr; 939 pAdapter->responsesArrayBaseDmaAlignedAddr += MV_EDMA_RESPONSE_QUEUE_SIZE; 940 pAdapter->responsesArrayBaseDmaAlignedAddr &= ~(ULONG_PTR)(MV_EDMA_RESPONSE_QUEUE_SIZE - 1); 941 942 if ((pAdapter->responsesArrayBaseDmaAlignedAddr - pAdapter->responsesArrayBaseDmaAddr) != 943 (pAdapter->responsesArrayBaseAlignedAddr - pAdapter->responsesArrayBaseAddr)) 944 { 945 MV_ERROR("RR18xx[%d]: Error in Response Queues Alignment\n", 946 pAdapter->mvSataAdapter.adapterId); 947 contigfree(pAdapter->requestsArrayBaseAddr, REQUESTS_ARRAY_SIZE, M_DEVBUF); 948 contigfree(pAdapter->responsesArrayBaseAddr, RESPONSES_ARRAY_SIZE, M_DEVBUF); 949 return -1; 950 } 951 return 0; 952 } 953 954 static void 955 hptmv_free_edma_queues(IAL_ADAPTER_T *pAdapter) 956 { 957 contigfree(pAdapter->requestsArrayBaseAddr, REQUESTS_ARRAY_SIZE, M_DEVBUF); 958 contigfree(pAdapter->responsesArrayBaseAddr, RESPONSES_ARRAY_SIZE, M_DEVBUF); 959 } 960 961 static PVOID 962 AllocatePRDTable(IAL_ADAPTER_T *pAdapter) 963 { 964 PVOID ret; 965 if (pAdapter->pFreePRDLink) { 966 KdPrint(("pAdapter->pFreePRDLink:%p\n",pAdapter->pFreePRDLink)); 967 ret = pAdapter->pFreePRDLink; 968 pAdapter->pFreePRDLink = *(void**)ret; 969 return ret; 970 } 971 return NULL; 972 } 973 974 static void 975 FreePRDTable(IAL_ADAPTER_T *pAdapter, PVOID PRDTable) 976 { 977 *(void**)PRDTable = pAdapter->pFreePRDLink; 978 pAdapter->pFreePRDLink = PRDTable; 979 } 980 981 extern PVDevice fGetFirstChild(PVDevice pLogical); 982 extern void fResetBootMark(PVDevice pLogical); 983 static void 984 fRegisterVdevice(IAL_ADAPTER_T *pAdapter) 985 { 986 PVDevice pPhysical, pLogical; 987 PVBus pVBus; 988 int i,j; 989 990 for(i=0;i<MV_SATA_CHANNELS_NUM;i++) { 991 pPhysical = &(pAdapter->VDevices[i]); 992 pLogical = pPhysical; 993 while (pLogical->pParent) pLogical = pLogical->pParent; 994 if (pLogical->vf_online==0) { 995 pPhysical->vf_bootmark = pLogical->vf_bootmark = 0; 996 continue; 997 } 998 if (pLogical->VDeviceType==VD_SPARE || pPhysical!=fGetFirstChild(pLogical)) 999 continue; 1000 1001 pVBus = &pAdapter->VBus; 1002 if(pVBus) 1003 { 1004 j=0; 1005 while(j<MAX_VDEVICE_PER_VBUS && pVBus->pVDevice[j]) j++; 1006 if(j<MAX_VDEVICE_PER_VBUS){ 1007 pVBus->pVDevice[j] = pLogical; 1008 pLogical->pVBus = pVBus; 1009 1010 if (j>0 && pLogical->vf_bootmark) { 1011 if (pVBus->pVDevice[0]->vf_bootmark) { 1012 fResetBootMark(pLogical); 1013 } 1014 else { 1015 do { pVBus->pVDevice[j] = pVBus->pVDevice[j-1]; } while (--j); 1016 pVBus->pVDevice[0] = pLogical; 1017 } 1018 } 1019 } 1020 } 1021 } 1022 } 1023 1024 PVDevice 1025 GetSpareDisk(_VBUS_ARG PVDevice pArray) 1026 { 1027 IAL_ADAPTER_T *pAdapter = (IAL_ADAPTER_T *)pArray->pVBus->OsExt; 1028 LBA_T capacity = LongDiv(pArray->VDeviceCapacity, pArray->u.array.bArnMember-1); 1029 LBA_T thiscap, maxcap = MAX_LBA_T; 1030 PVDevice pVDevice, pFind = NULL; 1031 int i; 1032 1033 for(i=0;i<MV_SATA_CHANNELS_NUM;i++) 1034 { 1035 pVDevice = &pAdapter->VDevices[i]; 1036 if(!pVDevice) 1037 continue; 1038 thiscap = pArray->vf_format_v2? pVDevice->u.disk.dDeRealCapacity : pVDevice->VDeviceCapacity; 1039 /* find the smallest usable spare disk */ 1040 if (pVDevice->VDeviceType==VD_SPARE && 1041 pVDevice->u.disk.df_on_line && 1042 thiscap < maxcap && 1043 thiscap >= capacity) 1044 { 1045 maxcap = pVDevice->VDeviceCapacity; 1046 pFind = pVDevice; 1047 } 1048 } 1049 return pFind; 1050 } 1051 1052 /****************************************************************** 1053 * IO ATA Command 1054 *******************************************************************/ 1055 int HPTLIBAPI 1056 fDeReadWrite(PDevice pDev, ULONG Lba, UCHAR Cmd, void *tmpBuffer) 1057 { 1058 return mvReadWrite(pDev->mv, Lba, Cmd, tmpBuffer); 1059 } 1060 1061 void HPTLIBAPI fDeSelectMode(PDevice pDev, UCHAR NewMode) 1062 { 1063 MV_SATA_CHANNEL *pSataChannel = pDev->mv; 1064 MV_SATA_ADAPTER *pSataAdapter = pSataChannel->mvSataAdapter; 1065 MV_U8 channelIndex = pSataChannel->channelNumber; 1066 UCHAR mvMode; 1067 /* 508x don't use MW-DMA? */ 1068 if (NewMode>4 && NewMode<8) NewMode = 4; 1069 pDev->bDeModeSetting = NewMode; 1070 if (NewMode<=4) 1071 mvMode = MV_ATA_TRANSFER_PIO_0 + NewMode; 1072 else 1073 mvMode = MV_ATA_TRANSFER_UDMA_0 + (NewMode-8); 1074 1075 /*To fix 88i8030 bug*/ 1076 if (mvMode > MV_ATA_TRANSFER_UDMA_0 && mvMode < MV_ATA_TRANSFER_UDMA_4) 1077 mvMode = MV_ATA_TRANSFER_UDMA_0; 1078 1079 mvSataDisableChannelDma(pSataAdapter, channelIndex); 1080 /* Flush pending commands */ 1081 mvSataFlushDmaQueue (pSataAdapter, channelIndex, MV_FLUSH_TYPE_NONE); 1082 1083 if (mvStorageDevATASetFeatures(pSataAdapter, channelIndex, 1084 MV_ATA_SET_FEATURES_TRANSFER, 1085 mvMode, 0, 0, 0) == MV_FALSE) 1086 { 1087 KdPrint(("channel %d: Set Features failed\n", channelIndex)); 1088 } 1089 /* Enable EDMA */ 1090 if (mvSataEnableChannelDma(pSataAdapter, channelIndex) == MV_FALSE) 1091 KdPrint(("Failed to enable DMA, channel=%d", channelIndex)); 1092 } 1093 1094 int HPTLIBAPI fDeSetTCQ(PDevice pDev, int enable, int depth) 1095 { 1096 MV_SATA_CHANNEL *pSataChannel = pDev->mv; 1097 MV_SATA_ADAPTER *pSataAdapter = pSataChannel->mvSataAdapter; 1098 MV_U8 channelIndex = pSataChannel->channelNumber; 1099 IAL_ADAPTER_T *pAdapter = pSataAdapter->IALData; 1100 MV_CHANNEL *channelInfo = &(pAdapter->mvChannel[channelIndex]); 1101 int dmaActive = pSataChannel->queueCommandsEnabled; 1102 int ret = 0; 1103 1104 if (dmaActive) { 1105 mvSataDisableChannelDma(pSataAdapter, channelIndex); 1106 mvSataFlushDmaQueue(pSataAdapter,channelIndex,MV_FLUSH_TYPE_CALLBACK); 1107 } 1108 1109 if (enable) { 1110 if (pSataChannel->queuedDMA == MV_EDMA_MODE_NOT_QUEUED && 1111 (pSataChannel->identifyDevice[IDEN_SUPPORTED_COMMANDS2] & (0x2))) { 1112 UCHAR depth = ((pSataChannel->identifyDevice[IDEN_QUEUE_DEPTH]) & 0x1f) + 1; 1113 channelInfo->queueDepth = (depth==32)? 31 : depth; 1114 mvSataConfigEdmaMode(pSataAdapter, channelIndex, MV_EDMA_MODE_QUEUED, depth); 1115 ret = 1; 1116 } 1117 } 1118 else 1119 { 1120 if (pSataChannel->queuedDMA != MV_EDMA_MODE_NOT_QUEUED) { 1121 channelInfo->queueDepth = 2; 1122 mvSataConfigEdmaMode(pSataAdapter, channelIndex, MV_EDMA_MODE_NOT_QUEUED, 0); 1123 ret = 1; 1124 } 1125 } 1126 1127 if (dmaActive) 1128 mvSataEnableChannelDma(pSataAdapter,channelIndex); 1129 return ret; 1130 } 1131 1132 int HPTLIBAPI fDeSetNCQ(PDevice pDev, int enable, int depth) 1133 { 1134 return 0; 1135 } 1136 1137 int HPTLIBAPI fDeSetWriteCache(PDevice pDev, int enable) 1138 { 1139 MV_SATA_CHANNEL *pSataChannel = pDev->mv; 1140 MV_SATA_ADAPTER *pSataAdapter = pSataChannel->mvSataAdapter; 1141 MV_U8 channelIndex = pSataChannel->channelNumber; 1142 IAL_ADAPTER_T *pAdapter = pSataAdapter->IALData; 1143 MV_CHANNEL *channelInfo = &(pAdapter->mvChannel[channelIndex]); 1144 int dmaActive = pSataChannel->queueCommandsEnabled; 1145 int ret = 0; 1146 1147 if (dmaActive) { 1148 mvSataDisableChannelDma(pSataAdapter, channelIndex); 1149 mvSataFlushDmaQueue(pSataAdapter,channelIndex,MV_FLUSH_TYPE_CALLBACK); 1150 } 1151 1152 if ((pSataChannel->identifyDevice[82] & (0x20))) { 1153 if (enable) { 1154 if (mvStorageDevATASetFeatures(pSataAdapter, channelIndex, 1155 MV_ATA_SET_FEATURES_ENABLE_WCACHE, 0, 0, 0, 0)) 1156 { 1157 channelInfo->writeCacheEnabled = MV_TRUE; 1158 ret = 1; 1159 } 1160 } 1161 else { 1162 if (mvStorageDevATASetFeatures(pSataAdapter, channelIndex, 1163 MV_ATA_SET_FEATURES_DISABLE_WCACHE, 0, 0, 0, 0)) 1164 { 1165 channelInfo->writeCacheEnabled = MV_FALSE; 1166 ret = 1; 1167 } 1168 } 1169 } 1170 1171 if (dmaActive) 1172 mvSataEnableChannelDma(pSataAdapter,channelIndex); 1173 return ret; 1174 } 1175 1176 int HPTLIBAPI fDeSetReadAhead(PDevice pDev, int enable) 1177 { 1178 MV_SATA_CHANNEL *pSataChannel = pDev->mv; 1179 MV_SATA_ADAPTER *pSataAdapter = pSataChannel->mvSataAdapter; 1180 MV_U8 channelIndex = pSataChannel->channelNumber; 1181 IAL_ADAPTER_T *pAdapter = pSataAdapter->IALData; 1182 MV_CHANNEL *channelInfo = &(pAdapter->mvChannel[channelIndex]); 1183 int dmaActive = pSataChannel->queueCommandsEnabled; 1184 int ret = 0; 1185 1186 if (dmaActive) { 1187 mvSataDisableChannelDma(pSataAdapter, channelIndex); 1188 mvSataFlushDmaQueue(pSataAdapter,channelIndex,MV_FLUSH_TYPE_CALLBACK); 1189 } 1190 1191 if ((pSataChannel->identifyDevice[82] & (0x40))) { 1192 if (enable) { 1193 if (mvStorageDevATASetFeatures(pSataAdapter, channelIndex, 1194 MV_ATA_SET_FEATURES_ENABLE_RLA, 0, 0, 0, 0)) 1195 { 1196 channelInfo->readAheadEnabled = MV_TRUE; 1197 ret = 1; 1198 } 1199 } 1200 else { 1201 if (mvStorageDevATASetFeatures(pSataAdapter, channelIndex, 1202 MV_ATA_SET_FEATURES_DISABLE_RLA, 0, 0, 0, 0)) 1203 { 1204 channelInfo->readAheadEnabled = MV_FALSE; 1205 ret = 1; 1206 } 1207 } 1208 } 1209 1210 if (dmaActive) 1211 mvSataEnableChannelDma(pSataAdapter,channelIndex); 1212 return ret; 1213 } 1214 1215 #ifdef SUPPORT_ARRAY 1216 #define IdeRegisterVDevice fCheckArray 1217 #else 1218 void 1219 IdeRegisterVDevice(PDevice pDev) 1220 { 1221 PVDevice pVDev = Map2pVDevice(pDev); 1222 1223 pVDev->VDeviceType = pDev->df_atapi? VD_ATAPI : 1224 pDev->df_removable_drive? VD_REMOVABLE : VD_SINGLE_DISK; 1225 pVDev->vf_online = 1; 1226 pVDev->VDeviceCapacity = pDev->dDeRealCapacity; 1227 pVDev->pfnSendCommand = pfnSendCommand[pVDev->VDeviceType]; 1228 pVDev->pfnDeviceFailed = pfnDeviceFailed[pVDev->VDeviceType]; 1229 } 1230 #endif 1231 1232 static __inline PBUS_DMAMAP 1233 dmamap_get(struct IALAdapter * pAdapter) 1234 { 1235 PBUS_DMAMAP p = pAdapter->pbus_dmamap_list; 1236 if (p) 1237 pAdapter->pbus_dmamap_list = p-> next; 1238 return p; 1239 } 1240 1241 static __inline void 1242 dmamap_put(PBUS_DMAMAP p) 1243 { 1244 p->next = p->pAdapter->pbus_dmamap_list; 1245 p->pAdapter->pbus_dmamap_list = p; 1246 } 1247 1248 static int num_adapters = 0; 1249 static int 1250 init_adapter(IAL_ADAPTER_T *pAdapter) 1251 { 1252 PVBus _vbus_p = &pAdapter->VBus; 1253 MV_SATA_ADAPTER *pMvSataAdapter; 1254 int i, channel, rid; 1255 1256 PVDevice pVDev; 1257 1258 mtx_init(&pAdapter->lock, "hptsleeplock", NULL, MTX_DEF); 1259 callout_init_mtx(&pAdapter->event_timer_connect, &pAdapter->lock, 0); 1260 callout_init_mtx(&pAdapter->event_timer_disconnect, &pAdapter->lock, 0); 1261 1262 sx_xlock(&hptmv_list_lock); 1263 pAdapter->next = 0; 1264 1265 if(gIal_Adapter == NULL){ 1266 gIal_Adapter = pAdapter; 1267 pCurAdapter = gIal_Adapter; 1268 } 1269 else { 1270 pCurAdapter->next = pAdapter; 1271 pCurAdapter = pAdapter; 1272 } 1273 sx_xunlock(&hptmv_list_lock); 1274 1275 pAdapter->outstandingCommands = 0; 1276 1277 pMvSataAdapter = &(pAdapter->mvSataAdapter); 1278 _vbus_p->OsExt = (void *)pAdapter; 1279 pMvSataAdapter->IALData = pAdapter; 1280 1281 if (bus_dma_tag_create(bus_get_dma_tag(pAdapter->hpt_dev),/* parent */ 1282 4, /* alignment */ 1283 BUS_SPACE_MAXADDR_32BIT+1, /* boundary */ 1284 BUS_SPACE_MAXADDR, /* lowaddr */ 1285 BUS_SPACE_MAXADDR, /* highaddr */ 1286 NULL, NULL, /* filter, filterarg */ 1287 PAGE_SIZE * (MAX_SG_DESCRIPTORS-1), /* maxsize */ 1288 MAX_SG_DESCRIPTORS, /* nsegments */ 1289 0x10000, /* maxsegsize */ 1290 BUS_DMA_WAITOK, /* flags */ 1291 busdma_lock_mutex, /* lockfunc */ 1292 &pAdapter->lock, /* lockfuncarg */ 1293 &pAdapter->io_dma_parent /* tag */)) 1294 { 1295 return ENXIO; 1296 } 1297 1298 1299 if (hptmv_allocate_edma_queues(pAdapter)) 1300 { 1301 MV_ERROR("RR18xx: Failed to allocate memory for EDMA queues\n"); 1302 return ENOMEM; 1303 } 1304 1305 /* also map EPROM address */ 1306 rid = 0x10; 1307 if (!(pAdapter->mem_res = bus_alloc_resource_any(pAdapter->hpt_dev, 1308 SYS_RES_MEMORY, &rid, RF_ACTIVE)) 1309 || 1310 !(pMvSataAdapter->adapterIoBaseAddress = rman_get_virtual(pAdapter->mem_res))) 1311 { 1312 MV_ERROR("RR18xx: Failed to remap memory space\n"); 1313 hptmv_free_edma_queues(pAdapter); 1314 return ENXIO; 1315 } 1316 else 1317 { 1318 KdPrint(("RR18xx: io base address 0x%p\n", pMvSataAdapter->adapterIoBaseAddress)); 1319 } 1320 1321 pMvSataAdapter->adapterId = num_adapters++; 1322 /* get the revision ID */ 1323 pMvSataAdapter->pciConfigRevisionId = pci_read_config(pAdapter->hpt_dev, PCIR_REVID, 1); 1324 pMvSataAdapter->pciConfigDeviceId = pci_get_device(pAdapter->hpt_dev); 1325 1326 /* init RR18xx */ 1327 pMvSataAdapter->intCoalThre[0]= 1; 1328 pMvSataAdapter->intCoalThre[1]= 1; 1329 pMvSataAdapter->intTimeThre[0] = 1; 1330 pMvSataAdapter->intTimeThre[1] = 1; 1331 pMvSataAdapter->pciCommand = 0x0107E371; 1332 pMvSataAdapter->pciSerrMask = 0xd77fe6ul; 1333 pMvSataAdapter->pciInterruptMask = 0xd77fe6ul; 1334 pMvSataAdapter->mvSataEventNotify = hptmv_event_notify; 1335 1336 if (mvSataInitAdapter(pMvSataAdapter) == MV_FALSE) 1337 { 1338 MV_ERROR("RR18xx[%d]: core failed to initialize the adapter\n", 1339 pMvSataAdapter->adapterId); 1340 unregister: 1341 bus_release_resource(pAdapter->hpt_dev, SYS_RES_MEMORY, rid, pAdapter->mem_res); 1342 hptmv_free_edma_queues(pAdapter); 1343 return ENXIO; 1344 } 1345 pAdapter->ver_601 = pMvSataAdapter->pcbVersion; 1346 1347 #ifndef FOR_DEMO 1348 set_fail_leds(pMvSataAdapter, 0); 1349 #endif 1350 1351 /* setup command blocks */ 1352 KdPrint(("Allocate command blocks\n")); 1353 _vbus_(pFreeCommands) = 0; 1354 pAdapter->pCommandBlocks = 1355 malloc(sizeof(struct _Command) * MAX_COMMAND_BLOCKS_FOR_EACH_VBUS, M_DEVBUF, M_NOWAIT); 1356 KdPrint(("pCommandBlocks:%p\n",pAdapter->pCommandBlocks)); 1357 if (!pAdapter->pCommandBlocks) { 1358 MV_ERROR("insufficient memory\n"); 1359 goto unregister; 1360 } 1361 1362 for (i=0; i<MAX_COMMAND_BLOCKS_FOR_EACH_VBUS; i++) { 1363 FreeCommand(_VBUS_P &(pAdapter->pCommandBlocks[i])); 1364 } 1365 1366 /*Set up the bus_dmamap*/ 1367 pAdapter->pbus_dmamap = (PBUS_DMAMAP)malloc (sizeof(struct _BUS_DMAMAP) * MAX_QUEUE_COMM, M_DEVBUF, M_NOWAIT); 1368 if(!pAdapter->pbus_dmamap) { 1369 MV_ERROR("insufficient memory\n"); 1370 free(pAdapter->pCommandBlocks, M_DEVBUF); 1371 goto unregister; 1372 } 1373 1374 memset((void *)pAdapter->pbus_dmamap, 0, sizeof(struct _BUS_DMAMAP) * MAX_QUEUE_COMM); 1375 pAdapter->pbus_dmamap_list = 0; 1376 for (i=0; i < MAX_QUEUE_COMM; i++) { 1377 PBUS_DMAMAP pmap = &(pAdapter->pbus_dmamap[i]); 1378 pmap->pAdapter = pAdapter; 1379 dmamap_put(pmap); 1380 1381 if(bus_dmamap_create(pAdapter->io_dma_parent, 0, &pmap->dma_map)) { 1382 MV_ERROR("Can not allocate dma map\n"); 1383 free(pAdapter->pCommandBlocks, M_DEVBUF); 1384 free(pAdapter->pbus_dmamap, M_DEVBUF); 1385 goto unregister; 1386 } 1387 callout_init_mtx(&pmap->timeout, &pAdapter->lock, 0); 1388 } 1389 /* setup PRD Tables */ 1390 KdPrint(("Allocate PRD Tables\n")); 1391 pAdapter->pFreePRDLink = 0; 1392 1393 pAdapter->prdTableAddr = (PUCHAR)contigmalloc( 1394 (PRD_ENTRIES_SIZE*PRD_TABLES_FOR_VBUS + 32), M_DEVBUF, M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0ul); 1395 1396 KdPrint(("prdTableAddr:%p\n",pAdapter->prdTableAddr)); 1397 if (!pAdapter->prdTableAddr) { 1398 MV_ERROR("insufficient PRD Tables\n"); 1399 goto unregister; 1400 } 1401 pAdapter->prdTableAlignedAddr = (PUCHAR)(((ULONG_PTR)pAdapter->prdTableAddr + 0x1f) & ~(ULONG_PTR)0x1fL); 1402 { 1403 PUCHAR PRDTable = pAdapter->prdTableAlignedAddr; 1404 for (i=0; i<PRD_TABLES_FOR_VBUS; i++) 1405 { 1406 /* KdPrint(("i=%d,pAdapter->pFreePRDLink=%p\n",i,pAdapter->pFreePRDLink)); */ 1407 FreePRDTable(pAdapter, PRDTable); 1408 PRDTable += PRD_ENTRIES_SIZE; 1409 } 1410 } 1411 1412 /* enable the adapter interrupts */ 1413 1414 /* configure and start the connected channels*/ 1415 for (channel = 0; channel < MV_SATA_CHANNELS_NUM; channel++) 1416 { 1417 pAdapter->mvChannel[channel].online = MV_FALSE; 1418 if (mvSataIsStorageDeviceConnected(pMvSataAdapter, channel) 1419 == MV_TRUE) 1420 { 1421 KdPrint(("RR18xx[%d]: channel %d is connected\n", 1422 pMvSataAdapter->adapterId, channel)); 1423 1424 if (hptmv_init_channel(pAdapter, channel) == 0) 1425 { 1426 if (mvSataConfigureChannel(pMvSataAdapter, channel) == MV_FALSE) 1427 { 1428 MV_ERROR("RR18xx[%d]: Failed to configure channel" 1429 " %d\n",pMvSataAdapter->adapterId, channel); 1430 hptmv_free_channel(pAdapter, channel); 1431 } 1432 else 1433 { 1434 if (start_channel(pAdapter, channel)) 1435 { 1436 MV_ERROR("RR18xx[%d]: Failed to start channel," 1437 " channel=%d\n",pMvSataAdapter->adapterId, 1438 channel); 1439 hptmv_free_channel(pAdapter, channel); 1440 } 1441 pAdapter->mvChannel[channel].online = MV_TRUE; 1442 /* mvSataChannelSetEdmaLoopBackMode(pMvSataAdapter, 1443 channel, 1444 MV_TRUE);*/ 1445 } 1446 } 1447 } 1448 KdPrint(("pAdapter->mvChannel[channel].online:%x, channel:%d\n", 1449 pAdapter->mvChannel[channel].online, channel)); 1450 } 1451 1452 #ifdef SUPPORT_ARRAY 1453 for(i = MAX_ARRAY_DEVICE - 1; i >= 0; i--) { 1454 pVDev = ArrayTables(i); 1455 mArFreeArrayTable(pVDev); 1456 } 1457 #endif 1458 1459 KdPrint(("Initialize Devices\n")); 1460 for (channel = 0; channel < MV_SATA_CHANNELS_NUM; channel++) { 1461 MV_SATA_CHANNEL *pMvSataChannel = pMvSataAdapter->sataChannel[channel]; 1462 if (pMvSataChannel) { 1463 init_vdev_params(pAdapter, channel); 1464 IdeRegisterVDevice(&pAdapter->VDevices[channel].u.disk); 1465 } 1466 } 1467 #ifdef SUPPORT_ARRAY 1468 CheckArrayCritical(_VBUS_P0); 1469 #endif 1470 _vbus_p->nInstances = 1; 1471 fRegisterVdevice(pAdapter); 1472 1473 for (channel=0;channel<MV_SATA_CHANNELS_NUM;channel++) { 1474 pVDev = _vbus_p->pVDevice[channel]; 1475 if (pVDev && pVDev->vf_online) 1476 fCheckBootable(pVDev); 1477 } 1478 1479 #if defined(SUPPORT_ARRAY) && defined(_RAID5N_) 1480 init_raid5_memory(_VBUS_P0); 1481 _vbus_(r5).enable_write_back = 1; 1482 printf("RR18xx: RAID5 write-back %s\n", _vbus_(r5).enable_write_back? "enabled" : "disabled"); 1483 #endif 1484 1485 mvSataUnmaskAdapterInterrupt(pMvSataAdapter); 1486 return 0; 1487 } 1488 1489 int 1490 MvSataResetChannel(MV_SATA_ADAPTER *pMvSataAdapter, MV_U8 channel) 1491 { 1492 IAL_ADAPTER_T *pAdapter = (IAL_ADAPTER_T *)pMvSataAdapter->IALData; 1493 1494 mvSataDisableChannelDma(pMvSataAdapter, channel); 1495 /* Flush pending commands */ 1496 mvSataFlushDmaQueue (pMvSataAdapter, channel, MV_FLUSH_TYPE_CALLBACK); 1497 1498 /* Software reset channel */ 1499 if (mvStorageDevATASoftResetDevice(pMvSataAdapter, channel) == MV_FALSE) 1500 { 1501 MV_ERROR("RR18xx [%d,%d]: failed to perform Software reset\n", 1502 pMvSataAdapter->adapterId, channel); 1503 hptmv_free_channel(pAdapter, channel); 1504 return -1; 1505 } 1506 1507 /* Hardware reset channel */ 1508 if (mvSataChannelHardReset(pMvSataAdapter, channel)== MV_FALSE) 1509 { 1510 MV_ERROR("RR18xx [%d,%d] Failed to Hard reser the SATA channel\n", 1511 pMvSataAdapter->adapterId, channel); 1512 hptmv_free_channel(pAdapter, channel); 1513 return -1; 1514 } 1515 1516 if (mvSataIsStorageDeviceConnected(pMvSataAdapter, channel) == MV_FALSE) 1517 { 1518 MV_ERROR("RR18xx [%d,%d] Failed to Connect Device\n", 1519 pMvSataAdapter->adapterId, channel); 1520 hptmv_free_channel(pAdapter, channel); 1521 return -1; 1522 }else 1523 { 1524 MV_ERROR("channel %d: perform recalibrate command", channel); 1525 if (!mvStorageDevATAExecuteNonUDMACommand(pMvSataAdapter, channel, 1526 MV_NON_UDMA_PROTOCOL_NON_DATA, 1527 MV_FALSE, 1528 NULL, /* pBuffer*/ 1529 0, /* count */ 1530 0, /*features*/ 1531 /* sectorCount */ 1532 0, 1533 0, /* lbaLow */ 1534 0, /* lbaMid */ 1535 /* lbaHigh */ 1536 0, 1537 0, /* device */ 1538 /* command */ 1539 0x10)) 1540 MV_ERROR("channel %d: recalibrate failed", channel); 1541 1542 /* Set transfer mode */ 1543 if((mvStorageDevATASetFeatures(pMvSataAdapter, channel, 1544 MV_ATA_SET_FEATURES_TRANSFER, 1545 MV_ATA_TRANSFER_PIO_SLOW, 0, 0, 0) == MV_FALSE) || 1546 (mvStorageDevATASetFeatures(pMvSataAdapter, channel, 1547 MV_ATA_SET_FEATURES_TRANSFER, 1548 pAdapter->mvChannel[channel].maxPioModeSupported, 0, 0, 0) == MV_FALSE) || 1549 (mvStorageDevATASetFeatures(pMvSataAdapter, channel, 1550 MV_ATA_SET_FEATURES_TRANSFER, 1551 pAdapter->mvChannel[channel].maxUltraDmaModeSupported, 0, 0, 0) == MV_FALSE) ) 1552 { 1553 MV_ERROR("channel %d: Set Features failed", channel); 1554 hptmv_free_channel(pAdapter, channel); 1555 return -1; 1556 } 1557 /* Enable EDMA */ 1558 if (mvSataEnableChannelDma(pMvSataAdapter, channel) == MV_FALSE) 1559 { 1560 MV_ERROR("Failed to enable DMA, channel=%d", channel); 1561 hptmv_free_channel(pAdapter, channel); 1562 return -1; 1563 } 1564 } 1565 return 0; 1566 } 1567 1568 static int 1569 fResetActiveCommands(PVBus _vbus_p) 1570 { 1571 MV_SATA_ADAPTER *pMvSataAdapter = &((IAL_ADAPTER_T *)_vbus_p->OsExt)->mvSataAdapter; 1572 MV_U8 channel; 1573 for (channel=0;channel< MV_SATA_CHANNELS_NUM;channel++) { 1574 if (pMvSataAdapter->sataChannel[channel] && pMvSataAdapter->sataChannel[channel]->outstandingCommands) 1575 MvSataResetChannel(pMvSataAdapter,channel); 1576 } 1577 return 0; 1578 } 1579 1580 void fCompleteAllCommandsSynchronously(PVBus _vbus_p) 1581 { 1582 UINT cont; 1583 ULONG ticks = 0; 1584 MV_U8 channel; 1585 MV_SATA_ADAPTER *pMvSataAdapter = &((IAL_ADAPTER_T *)_vbus_p->OsExt)->mvSataAdapter; 1586 MV_SATA_CHANNEL *pMvSataChannel; 1587 1588 do { 1589 check_cmds: 1590 cont = 0; 1591 CheckPendingCall(_VBUS_P0); 1592 #ifdef _RAID5N_ 1593 dataxfer_poll(); 1594 xor_poll(); 1595 #endif 1596 for (channel=0;channel< MV_SATA_CHANNELS_NUM;channel++) { 1597 pMvSataChannel = pMvSataAdapter->sataChannel[channel]; 1598 if (pMvSataChannel && pMvSataChannel->outstandingCommands) 1599 { 1600 while (pMvSataChannel->outstandingCommands) { 1601 if (!mvSataInterruptServiceRoutine(pMvSataAdapter)) { 1602 StallExec(1000); 1603 if (ticks++ > 3000) { 1604 MvSataResetChannel(pMvSataAdapter,channel); 1605 goto check_cmds; 1606 } 1607 } 1608 else 1609 ticks = 0; 1610 } 1611 cont = 1; 1612 } 1613 } 1614 } while (cont); 1615 } 1616 1617 void 1618 fResetVBus(_VBUS_ARG0) 1619 { 1620 KdPrint(("fMvResetBus(%p)", _vbus_p)); 1621 1622 /* some commands may already finished. */ 1623 CheckPendingCall(_VBUS_P0); 1624 1625 fResetActiveCommands(_vbus_p); 1626 /* 1627 * the other pending commands may still be finished successfully. 1628 */ 1629 fCompleteAllCommandsSynchronously(_vbus_p); 1630 1631 /* Now there should be no pending commands. No more action needed. */ 1632 CheckIdleCall(_VBUS_P0); 1633 1634 KdPrint(("fMvResetBus() done")); 1635 } 1636 1637 /*No rescan function*/ 1638 void 1639 fRescanAllDevice(_VBUS_ARG0) 1640 { 1641 } 1642 1643 static MV_BOOLEAN 1644 CommandCompletionCB(MV_SATA_ADAPTER *pMvSataAdapter, 1645 MV_U8 channelNum, 1646 MV_COMPLETION_TYPE comp_type, 1647 MV_VOID_PTR commandId, 1648 MV_U16 responseFlags, 1649 MV_U32 timeStamp, 1650 MV_STORAGE_DEVICE_REGISTERS *registerStruct) 1651 { 1652 PCommand pCmd = (PCommand) commandId; 1653 _VBUS_INST(pCmd->pVDevice->pVBus) 1654 1655 if (pCmd->uScratch.sata_param.prdAddr) 1656 FreePRDTable(pMvSataAdapter->IALData,pCmd->uScratch.sata_param.prdAddr); 1657 1658 switch (comp_type) 1659 { 1660 case MV_COMPLETION_TYPE_NORMAL: 1661 pCmd->Result = RETURN_SUCCESS; 1662 break; 1663 case MV_COMPLETION_TYPE_ABORT: 1664 pCmd->Result = RETURN_BUS_RESET; 1665 break; 1666 case MV_COMPLETION_TYPE_ERROR: 1667 MV_ERROR("IAL: COMPLETION ERROR, adapter %d, channel %d, flags=%x\n", 1668 pMvSataAdapter->adapterId, channelNum, responseFlags); 1669 1670 if (responseFlags & 4) { 1671 MV_ERROR("ATA regs: error %x, sector count %x, LBA low %x, LBA mid %x," 1672 " LBA high %x, device %x, status %x\n", 1673 registerStruct->errorRegister, 1674 registerStruct->sectorCountRegister, 1675 registerStruct->lbaLowRegister, 1676 registerStruct->lbaMidRegister, 1677 registerStruct->lbaHighRegister, 1678 registerStruct->deviceRegister, 1679 registerStruct->statusRegister); 1680 } 1681 /*We can't do handleEdmaError directly here, because CommandCompletionCB is called by 1682 * mv's ISR, if we retry the command, than the internel data structure may be destroyed*/ 1683 pCmd->uScratch.sata_param.responseFlags = responseFlags; 1684 pCmd->uScratch.sata_param.bIdeStatus = registerStruct->statusRegister; 1685 pCmd->uScratch.sata_param.errorRegister = registerStruct->errorRegister; 1686 pCmd->pVDevice->u.disk.QueueLength--; 1687 CallAfterReturn(_VBUS_P (DPC_PROC)handleEdmaError,pCmd); 1688 return TRUE; 1689 1690 default: 1691 MV_ERROR(" Unknown completion type (%d)\n", comp_type); 1692 return MV_FALSE; 1693 } 1694 1695 if (pCmd->uCmd.Ide.Command == IDE_COMMAND_VERIFY && pCmd->uScratch.sata_param.cmd_priv > 1) { 1696 pCmd->uScratch.sata_param.cmd_priv --; 1697 return TRUE; 1698 } 1699 pCmd->pVDevice->u.disk.QueueLength--; 1700 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd); 1701 return TRUE; 1702 } 1703 1704 void 1705 fDeviceSendCommand(_VBUS_ARG PCommand pCmd) 1706 { 1707 MV_SATA_EDMA_PRD_ENTRY *pPRDTable = 0; 1708 MV_SATA_ADAPTER *pMvSataAdapter; 1709 MV_SATA_CHANNEL *pMvSataChannel; 1710 PVDevice pVDevice = pCmd->pVDevice; 1711 PDevice pDevice = &pVDevice->u.disk; 1712 LBA_T Lba = pCmd->uCmd.Ide.Lba; 1713 USHORT nSector = pCmd->uCmd.Ide.nSectors; 1714 1715 MV_QUEUE_COMMAND_RESULT result; 1716 MV_QUEUE_COMMAND_INFO commandInfo; 1717 MV_UDMA_COMMAND_PARAMS *pUdmaParams = &commandInfo.commandParams.udmaCommand; 1718 MV_NONE_UDMA_COMMAND_PARAMS *pNoUdmaParams = &commandInfo.commandParams.NoneUdmaCommand; 1719 1720 MV_BOOLEAN is48bit; 1721 MV_U8 channel; 1722 int i=0; 1723 1724 DECLARE_BUFFER(FPSCAT_GATH, tmpSg); 1725 1726 if (!pDevice->df_on_line) { 1727 MV_ERROR("Device is offline"); 1728 pCmd->Result = RETURN_BAD_DEVICE; 1729 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd); 1730 return; 1731 } 1732 1733 pDevice->HeadPosition = pCmd->uCmd.Ide.Lba + pCmd->uCmd.Ide.nSectors; 1734 pMvSataChannel = pDevice->mv; 1735 pMvSataAdapter = pMvSataChannel->mvSataAdapter; 1736 channel = pMvSataChannel->channelNumber; 1737 1738 /* old RAID0 has hidden lba. Remember to clear dDeHiddenLba when delete array! */ 1739 Lba += pDevice->dDeHiddenLba; 1740 /* check LBA */ 1741 if (Lba+nSector-1 > pDevice->dDeRealCapacity) { 1742 pCmd->Result = RETURN_INVALID_REQUEST; 1743 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd); 1744 return; 1745 } 1746 1747 /* 1748 * always use 48bit LBA if drive supports it. 1749 * Some Seagate drives report error if you use a 28-bit command 1750 * to access sector 0xfffffff. 1751 */ 1752 is48bit = pMvSataChannel->lba48Address; 1753 1754 switch (pCmd->uCmd.Ide.Command) 1755 { 1756 case IDE_COMMAND_READ: 1757 case IDE_COMMAND_WRITE: 1758 if (pDevice->bDeModeSetting<8) goto pio; 1759 1760 commandInfo.type = MV_QUEUED_COMMAND_TYPE_UDMA; 1761 pUdmaParams->isEXT = is48bit; 1762 pUdmaParams->numOfSectors = nSector; 1763 pUdmaParams->lowLBAAddress = Lba; 1764 pUdmaParams->highLBAAddress = 0; 1765 pUdmaParams->prdHighAddr = 0; 1766 pUdmaParams->callBack = CommandCompletionCB; 1767 pUdmaParams->commandId = (MV_VOID_PTR )pCmd; 1768 if(pCmd->uCmd.Ide.Command == IDE_COMMAND_READ) 1769 pUdmaParams->readWrite = MV_UDMA_TYPE_READ; 1770 else 1771 pUdmaParams->readWrite = MV_UDMA_TYPE_WRITE; 1772 1773 if (pCmd->pSgTable && pCmd->cf_physical_sg) { 1774 FPSCAT_GATH sg1=tmpSg, sg2=pCmd->pSgTable; 1775 do { *sg1++=*sg2; } while ((sg2++->wSgFlag & SG_FLAG_EOT)==0); 1776 } 1777 else { 1778 if (!pCmd->pfnBuildSgl || !pCmd->pfnBuildSgl(_VBUS_P pCmd, tmpSg, 0)) { 1779 pio: 1780 mvSataDisableChannelDma(pMvSataAdapter, channel); 1781 mvSataFlushDmaQueue(pMvSataAdapter, channel, MV_FLUSH_TYPE_CALLBACK); 1782 1783 if (pCmd->pSgTable && pCmd->cf_physical_sg==0) { 1784 FPSCAT_GATH sg1=tmpSg, sg2=pCmd->pSgTable; 1785 do { *sg1++=*sg2; } while ((sg2++->wSgFlag & SG_FLAG_EOT)==0); 1786 } 1787 else { 1788 if (!pCmd->pfnBuildSgl || !pCmd->pfnBuildSgl(_VBUS_P pCmd, tmpSg, 1)) { 1789 pCmd->Result = RETURN_NEED_LOGICAL_SG; 1790 goto finish_cmd; 1791 } 1792 } 1793 1794 do { 1795 ULONG size = tmpSg->wSgSize? tmpSg->wSgSize : 0x10000; 1796 ULONG_PTR addr = tmpSg->dSgAddress; 1797 if (size & 0x1ff) { 1798 pCmd->Result = RETURN_INVALID_REQUEST; 1799 goto finish_cmd; 1800 } 1801 if (mvStorageDevATAExecuteNonUDMACommand(pMvSataAdapter, channel, 1802 (pCmd->cf_data_out)?MV_NON_UDMA_PROTOCOL_PIO_DATA_OUT:MV_NON_UDMA_PROTOCOL_PIO_DATA_IN, 1803 is48bit, 1804 (MV_U16_PTR)addr, 1805 size >> 1, /* count */ 1806 0, /* features N/A */ 1807 (MV_U16)(size>>9), /*sector count*/ 1808 (MV_U16)( (is48bit? (MV_U16)((Lba >> 16) & 0xFF00) : 0 ) | (UCHAR)(Lba & 0xFF) ), /*lbalow*/ 1809 (MV_U16)((Lba >> 8) & 0xFF), /* lbaMid */ 1810 (MV_U16)((Lba >> 16) & 0xFF),/* lbaHigh */ 1811 (MV_U8)(0x40 | (is48bit ? 0 : (UCHAR)(Lba >> 24) & 0xFF )),/* device */ 1812 (MV_U8)(is48bit ? (pCmd->cf_data_in?IDE_COMMAND_READ_EXT:IDE_COMMAND_WRITE_EXT):pCmd->uCmd.Ide.Command) 1813 )==MV_FALSE) 1814 { 1815 pCmd->Result = RETURN_IDE_ERROR; 1816 goto finish_cmd; 1817 } 1818 Lba += size>>9; 1819 if(Lba & 0xF0000000) is48bit = MV_TRUE; 1820 } 1821 while ((tmpSg++->wSgFlag & SG_FLAG_EOT)==0); 1822 pCmd->Result = RETURN_SUCCESS; 1823 finish_cmd: 1824 mvSataEnableChannelDma(pMvSataAdapter,channel); 1825 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd); 1826 return; 1827 } 1828 } 1829 1830 pPRDTable = (MV_SATA_EDMA_PRD_ENTRY *) AllocatePRDTable(pMvSataAdapter->IALData); 1831 KdPrint(("pPRDTable:%p\n",pPRDTable)); 1832 if (!pPRDTable) { 1833 pCmd->Result = RETURN_DEVICE_BUSY; 1834 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd); 1835 HPT_ASSERT(0); 1836 return; 1837 } 1838 1839 do{ 1840 pPRDTable[i].highBaseAddr = (sizeof(tmpSg->dSgAddress)>4 ? (MV_U32)(tmpSg->dSgAddress>>32) : 0); 1841 pPRDTable[i].flags = (MV_U16)tmpSg->wSgFlag; 1842 pPRDTable[i].byteCount = (MV_U16)tmpSg->wSgSize; 1843 pPRDTable[i].lowBaseAddr = (MV_U32)tmpSg->dSgAddress; 1844 pPRDTable[i].reserved = 0; 1845 i++; 1846 }while((tmpSg++->wSgFlag & SG_FLAG_EOT)==0); 1847 1848 pUdmaParams->prdLowAddr = (ULONG)fOsPhysicalAddress(pPRDTable); 1849 if ((pUdmaParams->numOfSectors == 256) && (pMvSataChannel->lba48Address == MV_FALSE)) { 1850 pUdmaParams->numOfSectors = 0; 1851 } 1852 1853 pCmd->uScratch.sata_param.prdAddr = (PVOID)pPRDTable; 1854 1855 result = mvSataQueueCommand(pMvSataAdapter, channel, &commandInfo); 1856 1857 if (result != MV_QUEUE_COMMAND_RESULT_OK) 1858 { 1859 queue_failed: 1860 switch (result) 1861 { 1862 case MV_QUEUE_COMMAND_RESULT_BAD_LBA_ADDRESS: 1863 MV_ERROR("IAL Error: Edma Queue command failed. Bad LBA " 1864 "LBA[31:0](0x%08x)\n", pUdmaParams->lowLBAAddress); 1865 pCmd->Result = RETURN_IDE_ERROR; 1866 break; 1867 case MV_QUEUE_COMMAND_RESULT_QUEUED_MODE_DISABLED: 1868 MV_ERROR("IAL Error: Edma Queue command failed. EDMA" 1869 " disabled adapter %d channel %d\n", 1870 pMvSataAdapter->adapterId, channel); 1871 mvSataEnableChannelDma(pMvSataAdapter,channel); 1872 pCmd->Result = RETURN_IDE_ERROR; 1873 break; 1874 case MV_QUEUE_COMMAND_RESULT_FULL: 1875 MV_ERROR("IAL Error: Edma Queue command failed. Queue is" 1876 " Full adapter %d channel %d\n", 1877 pMvSataAdapter->adapterId, channel); 1878 pCmd->Result = RETURN_DEVICE_BUSY; 1879 break; 1880 case MV_QUEUE_COMMAND_RESULT_BAD_PARAMS: 1881 MV_ERROR("IAL Error: Edma Queue command failed. (Bad " 1882 "Params), pMvSataAdapter: %p, pSataChannel: %p.\n", 1883 pMvSataAdapter, pMvSataAdapter->sataChannel[channel]); 1884 pCmd->Result = RETURN_IDE_ERROR; 1885 break; 1886 default: 1887 MV_ERROR("IAL Error: Bad result value (%d) from queue" 1888 " command\n", result); 1889 pCmd->Result = RETURN_IDE_ERROR; 1890 } 1891 if(pPRDTable) 1892 FreePRDTable(pMvSataAdapter->IALData,pPRDTable); 1893 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd); 1894 } 1895 pDevice->QueueLength++; 1896 return; 1897 1898 case IDE_COMMAND_VERIFY: 1899 commandInfo.type = MV_QUEUED_COMMAND_TYPE_NONE_UDMA; 1900 pNoUdmaParams->bufPtr = NULL; 1901 pNoUdmaParams->callBack = CommandCompletionCB; 1902 pNoUdmaParams->commandId = (MV_VOID_PTR)pCmd; 1903 pNoUdmaParams->count = 0; 1904 pNoUdmaParams->features = 0; 1905 pNoUdmaParams->protocolType = MV_NON_UDMA_PROTOCOL_NON_DATA; 1906 1907 pCmd->uScratch.sata_param.cmd_priv = 1; 1908 if (pMvSataChannel->lba48Address == MV_TRUE){ 1909 pNoUdmaParams->command = MV_ATA_COMMAND_READ_VERIFY_SECTORS_EXT; 1910 pNoUdmaParams->isEXT = MV_TRUE; 1911 pNoUdmaParams->lbaHigh = (MV_U16)((Lba & 0xff0000) >> 16); 1912 pNoUdmaParams->lbaMid = (MV_U16)((Lba & 0xff00) >> 8); 1913 pNoUdmaParams->lbaLow = 1914 (MV_U16)(((Lba & 0xff000000) >> 16)| (Lba & 0xff)); 1915 pNoUdmaParams->sectorCount = nSector; 1916 pNoUdmaParams->device = 0x40; 1917 result = mvSataQueueCommand(pMvSataAdapter, channel, &commandInfo); 1918 if (result != MV_QUEUE_COMMAND_RESULT_OK){ 1919 goto queue_failed; 1920 } 1921 return; 1922 } 1923 else{ 1924 pNoUdmaParams->command = MV_ATA_COMMAND_READ_VERIFY_SECTORS; 1925 pNoUdmaParams->isEXT = MV_FALSE; 1926 pNoUdmaParams->lbaHigh = (MV_U16)((Lba & 0xff0000) >> 16); 1927 pNoUdmaParams->lbaMid = (MV_U16)((Lba & 0xff00) >> 8); 1928 pNoUdmaParams->lbaLow = (MV_U16)(Lba & 0xff); 1929 pNoUdmaParams->sectorCount = 0xff & nSector; 1930 pNoUdmaParams->device = (MV_U8)(0x40 | 1931 ((Lba & 0xf000000) >> 24)); 1932 pNoUdmaParams->callBack = CommandCompletionCB; 1933 result = mvSataQueueCommand(pMvSataAdapter, channel, &commandInfo); 1934 /*FIXME: how about the commands already queued? but marvel also forgets to consider this*/ 1935 if (result != MV_QUEUE_COMMAND_RESULT_OK){ 1936 goto queue_failed; 1937 } 1938 } 1939 break; 1940 default: 1941 pCmd->Result = RETURN_INVALID_REQUEST; 1942 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd); 1943 break; 1944 } 1945 } 1946 1947 /********************************************************** 1948 * 1949 * Probe the hostadapter. 1950 * 1951 **********************************************************/ 1952 static int 1953 hpt_probe(device_t dev) 1954 { 1955 if ((pci_get_vendor(dev) == MV_SATA_VENDOR_ID) && 1956 (pci_get_device(dev) == MV_SATA_DEVICE_ID_5081 1957 #ifdef FOR_DEMO 1958 || pci_get_device(dev) == MV_SATA_DEVICE_ID_5080 1959 #endif 1960 )) 1961 { 1962 KdPrintI((CONTROLLER_NAME " found\n")); 1963 device_set_desc(dev, CONTROLLER_NAME); 1964 return (BUS_PROBE_DEFAULT); 1965 } 1966 else 1967 return(ENXIO); 1968 } 1969 1970 /*********************************************************** 1971 * 1972 * Auto configuration: attach and init a host adapter. 1973 * 1974 ***********************************************************/ 1975 static int 1976 hpt_attach(device_t dev) 1977 { 1978 IAL_ADAPTER_T * pAdapter = device_get_softc(dev); 1979 int rid; 1980 union ccb *ccb; 1981 struct cam_devq *devq; 1982 struct cam_sim *hpt_vsim; 1983 1984 device_printf(dev, "%s Version %s \n", DRIVER_NAME, DRIVER_VERSION); 1985 1986 pAdapter->hpt_dev = dev; 1987 1988 rid = init_adapter(pAdapter); 1989 if (rid) 1990 return rid; 1991 1992 rid = 0; 1993 if ((pAdapter->hpt_irq = bus_alloc_resource_any(pAdapter->hpt_dev, SYS_RES_IRQ, &rid, RF_SHAREABLE | RF_ACTIVE)) == NULL) 1994 { 1995 hpt_printk(("can't allocate interrupt\n")); 1996 return(ENXIO); 1997 } 1998 1999 if (bus_setup_intr(pAdapter->hpt_dev, pAdapter->hpt_irq, 2000 INTR_TYPE_CAM | INTR_MPSAFE, 2001 NULL, hpt_intr, pAdapter, &pAdapter->hpt_intr)) 2002 { 2003 hpt_printk(("can't set up interrupt\n")); 2004 free(pAdapter, M_DEVBUF); 2005 return(ENXIO); 2006 } 2007 2008 2009 ccb = xpt_alloc_ccb(); 2010 ccb->ccb_h.pinfo.priority = 1; 2011 ccb->ccb_h.pinfo.index = CAM_UNQUEUED_INDEX; 2012 2013 /* 2014 * Create the device queue for our SIM(s). 2015 */ 2016 if((devq = cam_simq_alloc(8/*MAX_QUEUE_COMM*/)) == NULL) 2017 { 2018 KdPrint(("ENXIO\n")); 2019 return ENOMEM; 2020 } 2021 2022 /* 2023 * Construct our SIM entry 2024 */ 2025 hpt_vsim = cam_sim_alloc(hpt_action, hpt_poll, __str(PROC_DIR_NAME), 2026 pAdapter, device_get_unit(pAdapter->hpt_dev), 2027 &pAdapter->lock, 1, 8, devq); 2028 if (hpt_vsim == NULL) { 2029 cam_simq_free(devq); 2030 return ENOMEM; 2031 } 2032 2033 mtx_lock(&pAdapter->lock); 2034 if (xpt_bus_register(hpt_vsim, dev, 0) != CAM_SUCCESS) 2035 { 2036 cam_sim_free(hpt_vsim, /*free devq*/ TRUE); 2037 mtx_unlock(&pAdapter->lock); 2038 hpt_vsim = NULL; 2039 return ENXIO; 2040 } 2041 2042 if(xpt_create_path(&pAdapter->path, /*periph */ NULL, 2043 cam_sim_path(hpt_vsim), CAM_TARGET_WILDCARD, 2044 CAM_LUN_WILDCARD) != CAM_REQ_CMP) 2045 { 2046 xpt_bus_deregister(cam_sim_path(hpt_vsim)); 2047 cam_sim_free(hpt_vsim, /*free_devq*/TRUE); 2048 mtx_unlock(&pAdapter->lock); 2049 hpt_vsim = NULL; 2050 return ENXIO; 2051 } 2052 mtx_unlock(&pAdapter->lock); 2053 2054 xpt_setup_ccb(&(ccb->ccb_h), pAdapter->path, /*priority*/5); 2055 ccb->ccb_h.func_code = XPT_SASYNC_CB; 2056 ccb->csa.event_enable = AC_LOST_DEVICE; 2057 ccb->csa.callback = hpt_async; 2058 ccb->csa.callback_arg = hpt_vsim; 2059 xpt_action((union ccb *)ccb); 2060 xpt_free_ccb(ccb); 2061 2062 if (device_get_unit(dev) == 0) { 2063 /* Start the work thread. XXX */ 2064 launch_worker_thread(); 2065 } 2066 2067 return 0; 2068 } 2069 2070 static int 2071 hpt_detach(device_t dev) 2072 { 2073 return (EBUSY); 2074 } 2075 2076 2077 /*************************************************************** 2078 * The poll function is used to simulate the interrupt when 2079 * the interrupt subsystem is not functioning. 2080 * 2081 ***************************************************************/ 2082 static void 2083 hpt_poll(struct cam_sim *sim) 2084 { 2085 2086 hpt_intr_locked((void *)cam_sim_softc(sim)); 2087 } 2088 2089 /**************************************************************** 2090 * Name: hpt_intr 2091 * Description: Interrupt handler. 2092 ****************************************************************/ 2093 static void 2094 hpt_intr(void *arg) 2095 { 2096 IAL_ADAPTER_T *pAdapter; 2097 2098 pAdapter = arg; 2099 mtx_lock(&pAdapter->lock); 2100 hpt_intr_locked(pAdapter); 2101 mtx_unlock(&pAdapter->lock); 2102 } 2103 2104 static void 2105 hpt_intr_locked(IAL_ADAPTER_T *pAdapter) 2106 { 2107 2108 mtx_assert(&pAdapter->lock, MA_OWNED); 2109 /* KdPrintI(("----- Entering Isr() -----\n")); */ 2110 if (mvSataInterruptServiceRoutine(&pAdapter->mvSataAdapter) == MV_TRUE) 2111 { 2112 _VBUS_INST(&pAdapter->VBus) 2113 CheckPendingCall(_VBUS_P0); 2114 } 2115 2116 /* KdPrintI(("----- Leaving Isr() -----\n")); */ 2117 } 2118 2119 /********************************************************** 2120 * Asynchronous Events 2121 *********************************************************/ 2122 #if (!defined(UNREFERENCED_PARAMETER)) 2123 #define UNREFERENCED_PARAMETER(x) (void)(x) 2124 #endif 2125 2126 static void 2127 hpt_async(void * callback_arg, u_int32_t code, struct cam_path * path, 2128 void * arg) 2129 { 2130 /* debug XXXX */ 2131 panic("Here"); 2132 UNREFERENCED_PARAMETER(callback_arg); 2133 UNREFERENCED_PARAMETER(code); 2134 UNREFERENCED_PARAMETER(path); 2135 UNREFERENCED_PARAMETER(arg); 2136 2137 } 2138 2139 static void 2140 FlushAdapter(IAL_ADAPTER_T *pAdapter) 2141 { 2142 int i; 2143 2144 hpt_printk(("flush all devices\n")); 2145 2146 /* flush all devices */ 2147 for (i=0; i<MAX_VDEVICE_PER_VBUS; i++) { 2148 PVDevice pVDev = pAdapter->VBus.pVDevice[i]; 2149 if(pVDev) fFlushVDev(pVDev); 2150 } 2151 } 2152 2153 static int 2154 hpt_shutdown(device_t dev) 2155 { 2156 IAL_ADAPTER_T *pAdapter; 2157 2158 pAdapter = device_get_softc(dev); 2159 2160 EVENTHANDLER_DEREGISTER(shutdown_final, pAdapter->eh); 2161 mtx_lock(&pAdapter->lock); 2162 FlushAdapter(pAdapter); 2163 mtx_unlock(&pAdapter->lock); 2164 /* give the flush some time to happen, 2165 *otherwise "shutdown -p now" will make file system corrupted */ 2166 DELAY(1000 * 1000 * 5); 2167 return 0; 2168 } 2169 2170 void 2171 Check_Idle_Call(IAL_ADAPTER_T *pAdapter) 2172 { 2173 _VBUS_INST(&pAdapter->VBus) 2174 2175 if (mWaitingForIdle(_VBUS_P0)) { 2176 CheckIdleCall(_VBUS_P0); 2177 #ifdef SUPPORT_ARRAY 2178 { 2179 int i; 2180 PVDevice pArray; 2181 for(i = 0; i < MAX_ARRAY_PER_VBUS; i++){ 2182 if ((pArray=ArrayTables(i))->u.array.dArStamp==0) 2183 continue; 2184 else if (pArray->u.array.rf_auto_rebuild) { 2185 KdPrint(("auto rebuild.\n")); 2186 pArray->u.array.rf_auto_rebuild = 0; 2187 hpt_queue_dpc((HPT_DPC)hpt_rebuild_data_block, pAdapter, pArray, DUPLICATE); 2188 } 2189 } 2190 } 2191 #endif 2192 } 2193 /* launch the awaiting commands blocked by mWaitingForIdle */ 2194 while(pAdapter->pending_Q!= NULL) 2195 { 2196 _VBUS_INST(&pAdapter->VBus) 2197 union ccb *ccb = (union ccb *)pAdapter->pending_Q->ccb_h.ccb_ccb_ptr; 2198 hpt_free_ccb(&pAdapter->pending_Q, ccb); 2199 CallAfterReturn(_VBUS_P (DPC_PROC)OsSendCommand, ccb); 2200 } 2201 } 2202 2203 static void 2204 ccb_done(union ccb *ccb) 2205 { 2206 PBUS_DMAMAP pmap = (PBUS_DMAMAP)ccb->ccb_adapter; 2207 IAL_ADAPTER_T * pAdapter = pmap->pAdapter; 2208 KdPrintI(("ccb_done: ccb %p status %x\n", ccb, ccb->ccb_h.status)); 2209 2210 dmamap_put(pmap); 2211 xpt_done(ccb); 2212 2213 pAdapter->outstandingCommands--; 2214 2215 if (pAdapter->outstandingCommands == 0) 2216 { 2217 if(DPC_Request_Nums == 0) 2218 Check_Idle_Call(pAdapter); 2219 wakeup(pAdapter); 2220 } 2221 } 2222 2223 /**************************************************************** 2224 * Name: hpt_action 2225 * Description: Process a queued command from the CAM layer. 2226 * Parameters: sim - Pointer to SIM object 2227 * ccb - Pointer to SCSI command structure. 2228 ****************************************************************/ 2229 2230 void 2231 hpt_action(struct cam_sim *sim, union ccb *ccb) 2232 { 2233 IAL_ADAPTER_T * pAdapter = (IAL_ADAPTER_T *) cam_sim_softc(sim); 2234 PBUS_DMAMAP pmap; 2235 _VBUS_INST(&pAdapter->VBus) 2236 2237 mtx_assert(&pAdapter->lock, MA_OWNED); 2238 CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, ("hpt_action\n")); 2239 KdPrint(("hpt_action(%lx,%lx{%x})\n", (u_long)sim, (u_long)ccb, ccb->ccb_h.func_code)); 2240 2241 switch (ccb->ccb_h.func_code) 2242 { 2243 case XPT_SCSI_IO: /* Execute the requested I/O operation */ 2244 { 2245 /* ccb->ccb_h.path_id is not our bus id - don't check it */ 2246 2247 if (ccb->ccb_h.target_lun) { 2248 ccb->ccb_h.status = CAM_LUN_INVALID; 2249 xpt_done(ccb); 2250 return; 2251 } 2252 if (ccb->ccb_h.target_id >= MAX_VDEVICE_PER_VBUS || 2253 pAdapter->VBus.pVDevice[ccb->ccb_h.target_id]==0) { 2254 ccb->ccb_h.status = CAM_TID_INVALID; 2255 xpt_done(ccb); 2256 return; 2257 } 2258 2259 if (pAdapter->outstandingCommands==0 && DPC_Request_Nums==0) 2260 Check_Idle_Call(pAdapter); 2261 2262 pmap = dmamap_get(pAdapter); 2263 HPT_ASSERT(pmap); 2264 ccb->ccb_adapter = pmap; 2265 memset((void *)pmap->psg, 0, sizeof(pmap->psg)); 2266 2267 if (mWaitingForIdle(_VBUS_P0)) 2268 hpt_queue_ccb(&pAdapter->pending_Q, ccb); 2269 else 2270 OsSendCommand(_VBUS_P ccb); 2271 2272 /* KdPrint(("leave scsiio\n")); */ 2273 break; 2274 } 2275 2276 case XPT_RESET_BUS: 2277 KdPrint(("reset bus\n")); 2278 fResetVBus(_VBUS_P0); 2279 xpt_done(ccb); 2280 break; 2281 2282 case XPT_RESET_DEV: /* Bus Device Reset the specified SCSI device */ 2283 case XPT_ABORT: /* Abort the specified CCB */ 2284 case XPT_TERM_IO: /* Terminate the I/O process */ 2285 /* XXX Implement */ 2286 ccb->ccb_h.status = CAM_REQ_INVALID; 2287 xpt_done(ccb); 2288 break; 2289 2290 case XPT_GET_TRAN_SETTINGS: 2291 case XPT_SET_TRAN_SETTINGS: 2292 /* XXX Implement */ 2293 ccb->ccb_h.status = CAM_FUNC_NOTAVAIL; 2294 xpt_done(ccb); 2295 break; 2296 2297 case XPT_CALC_GEOMETRY: 2298 cam_calc_geometry(&ccb->ccg, 1); 2299 xpt_done(ccb); 2300 break; 2301 2302 case XPT_PATH_INQ: /* Path routing inquiry */ 2303 { 2304 struct ccb_pathinq *cpi = &ccb->cpi; 2305 2306 cpi->version_num = 1; /* XXX??? */ 2307 cpi->hba_inquiry = PI_SDTR_ABLE; 2308 cpi->target_sprt = 0; 2309 /* Not necessary to reset bus */ 2310 cpi->hba_misc = PIM_NOBUSRESET; 2311 cpi->hba_eng_cnt = 0; 2312 2313 cpi->max_target = MAX_VDEVICE_PER_VBUS; 2314 cpi->max_lun = 0; 2315 cpi->initiator_id = MAX_VDEVICE_PER_VBUS; 2316 2317 cpi->bus_id = cam_sim_bus(sim); 2318 cpi->base_transfer_speed = 3300; 2319 strlcpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); 2320 strlcpy(cpi->hba_vid, "HPT ", HBA_IDLEN); 2321 strlcpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN); 2322 cpi->unit_number = cam_sim_unit(sim); 2323 cpi->transport = XPORT_SPI; 2324 cpi->transport_version = 2; 2325 cpi->protocol = PROTO_SCSI; 2326 cpi->protocol_version = SCSI_REV_2; 2327 cpi->ccb_h.status = CAM_REQ_CMP; 2328 xpt_done(ccb); 2329 break; 2330 } 2331 2332 default: 2333 KdPrint(("invalid cmd\n")); 2334 ccb->ccb_h.status = CAM_REQ_INVALID; 2335 xpt_done(ccb); 2336 break; 2337 } 2338 /* KdPrint(("leave hpt_action..............\n")); */ 2339 } 2340 2341 /* shall be called at lock_driver() */ 2342 static void 2343 hpt_queue_ccb(union ccb **ccb_Q, union ccb *ccb) 2344 { 2345 if(*ccb_Q == NULL) 2346 ccb->ccb_h.ccb_ccb_ptr = ccb; 2347 else { 2348 ccb->ccb_h.ccb_ccb_ptr = (*ccb_Q)->ccb_h.ccb_ccb_ptr; 2349 (*ccb_Q)->ccb_h.ccb_ccb_ptr = (char *)ccb; 2350 } 2351 2352 *ccb_Q = ccb; 2353 } 2354 2355 /* shall be called at lock_driver() */ 2356 static void 2357 hpt_free_ccb(union ccb **ccb_Q, union ccb *ccb) 2358 { 2359 union ccb *TempCCB; 2360 2361 TempCCB = *ccb_Q; 2362 2363 if(ccb->ccb_h.ccb_ccb_ptr == ccb) /*it means SCpnt is the last one in CURRCMDs*/ 2364 *ccb_Q = NULL; 2365 else { 2366 while(TempCCB->ccb_h.ccb_ccb_ptr != (char *)ccb) 2367 TempCCB = (union ccb *)TempCCB->ccb_h.ccb_ccb_ptr; 2368 2369 TempCCB->ccb_h.ccb_ccb_ptr = ccb->ccb_h.ccb_ccb_ptr; 2370 2371 if(*ccb_Q == ccb) 2372 *ccb_Q = TempCCB; 2373 } 2374 } 2375 2376 #ifdef SUPPORT_ARRAY 2377 /*************************************************************************** 2378 * Function: hpt_worker_thread 2379 * Description: Do background rebuilding. Execute in kernel thread context. 2380 * Returns: None 2381 ***************************************************************************/ 2382 static void hpt_worker_thread(void) 2383 { 2384 2385 for(;;) { 2386 mtx_lock(&DpcQueue_Lock); 2387 while (DpcQueue_First!=DpcQueue_Last) { 2388 ST_HPT_DPC p; 2389 p = DpcQueue[DpcQueue_First]; 2390 DpcQueue_First++; 2391 DpcQueue_First %= MAX_DPC; 2392 DPC_Request_Nums++; 2393 mtx_unlock(&DpcQueue_Lock); 2394 p.dpc(p.pAdapter, p.arg, p.flags); 2395 2396 mtx_lock(&p.pAdapter->lock); 2397 mtx_lock(&DpcQueue_Lock); 2398 DPC_Request_Nums--; 2399 /* since we may have prevented Check_Idle_Call, do it here */ 2400 if (DPC_Request_Nums==0) { 2401 if (p.pAdapter->outstandingCommands == 0) { 2402 _VBUS_INST(&p.pAdapter->VBus); 2403 Check_Idle_Call(p.pAdapter); 2404 CheckPendingCall(_VBUS_P0); 2405 } 2406 } 2407 mtx_unlock(&p.pAdapter->lock); 2408 mtx_unlock(&DpcQueue_Lock); 2409 2410 /*Schedule out*/ 2411 if (SIGISMEMBER(curproc->p_siglist, SIGSTOP)) { 2412 /* abort rebuilding process. */ 2413 IAL_ADAPTER_T *pAdapter; 2414 PVDevice pArray; 2415 PVBus _vbus_p; 2416 int i; 2417 2418 sx_slock(&hptmv_list_lock); 2419 pAdapter = gIal_Adapter; 2420 2421 while(pAdapter != NULL){ 2422 mtx_lock(&pAdapter->lock); 2423 _vbus_p = &pAdapter->VBus; 2424 2425 for (i=0;i<MAX_ARRAY_PER_VBUS;i++) 2426 { 2427 if ((pArray=ArrayTables(i))->u.array.dArStamp==0) 2428 continue; 2429 else if (pArray->u.array.rf_rebuilding || 2430 pArray->u.array.rf_verifying || 2431 pArray->u.array.rf_initializing) 2432 { 2433 pArray->u.array.rf_abort_rebuild = 1; 2434 } 2435 } 2436 mtx_unlock(&pAdapter->lock); 2437 pAdapter = pAdapter->next; 2438 } 2439 sx_sunlock(&hptmv_list_lock); 2440 } 2441 mtx_lock(&DpcQueue_Lock); 2442 } 2443 mtx_unlock(&DpcQueue_Lock); 2444 2445 /*Remove this debug option*/ 2446 /* 2447 #ifdef DEBUG 2448 if (SIGISMEMBER(curproc->p_siglist, SIGSTOP)) 2449 pause("hptrdy", 2*hz); 2450 #endif 2451 */ 2452 kproc_suspend_check(curproc); 2453 pause("-", 2*hz); /* wait for something to do */ 2454 } 2455 } 2456 2457 static struct proc *hptdaemonproc; 2458 static struct kproc_desc hpt_kp = { 2459 "hpt_wt", 2460 hpt_worker_thread, 2461 &hptdaemonproc 2462 }; 2463 2464 /*Start this thread in the hpt_attach, to prevent kernel from loading it without our controller.*/ 2465 static void 2466 launch_worker_thread(void) 2467 { 2468 IAL_ADAPTER_T *pAdapTemp; 2469 2470 kproc_start(&hpt_kp); 2471 2472 sx_slock(&hptmv_list_lock); 2473 for (pAdapTemp = gIal_Adapter; pAdapTemp; pAdapTemp = pAdapTemp->next) { 2474 2475 _VBUS_INST(&pAdapTemp->VBus) 2476 int i; 2477 PVDevice pVDev; 2478 2479 for(i = 0; i < MAX_ARRAY_PER_VBUS; i++) 2480 if ((pVDev=ArrayTables(i))->u.array.dArStamp==0) 2481 continue; 2482 else{ 2483 if (pVDev->u.array.rf_need_rebuild && !pVDev->u.array.rf_rebuilding) 2484 hpt_queue_dpc((HPT_DPC)hpt_rebuild_data_block, pAdapTemp, pVDev, 2485 (UCHAR)((pVDev->u.array.CriticalMembers || pVDev->VDeviceType == VD_RAID_1)? DUPLICATE : REBUILD_PARITY)); 2486 } 2487 } 2488 sx_sunlock(&hptmv_list_lock); 2489 2490 /* 2491 * hpt_worker_thread needs to be suspended after shutdown sync, when fs sync finished. 2492 */ 2493 EVENTHANDLER_REGISTER(shutdown_post_sync, kproc_shutdown, hptdaemonproc, 2494 SHUTDOWN_PRI_LAST); 2495 } 2496 /* 2497 *SYSINIT(hptwt, SI_SUB_KTHREAD_IDLE, SI_ORDER_FIRST, launch_worker_thread, NULL); 2498 */ 2499 2500 #endif 2501 2502 /********************************************************************************/ 2503 2504 int HPTLIBAPI fOsBuildSgl(_VBUS_ARG PCommand pCmd, FPSCAT_GATH pSg, int logical) 2505 { 2506 union ccb *ccb = (union ccb *)pCmd->pOrgCommand; 2507 2508 if (logical) { 2509 pSg->dSgAddress = (ULONG_PTR)(UCHAR *)ccb->csio.data_ptr; 2510 pSg->wSgSize = ccb->csio.dxfer_len; 2511 pSg->wSgFlag = SG_FLAG_EOT; 2512 return TRUE; 2513 } 2514 /* since we have provided physical sg, nobody will ask us to build physical sg */ 2515 HPT_ASSERT(0); 2516 return FALSE; 2517 } 2518 2519 /*******************************************************************************/ 2520 ULONG HPTLIBAPI 2521 GetStamp(void) 2522 { 2523 /* 2524 * the system variable, ticks, can't be used since it hasn't yet been active 2525 * when our driver starts (ticks==0, it's a invalid stamp value) 2526 */ 2527 ULONG stamp; 2528 do { stamp = random(); } while (stamp==0); 2529 return stamp; 2530 } 2531 2532 2533 static void 2534 SetInquiryData(PINQUIRYDATA inquiryData, PVDevice pVDev) 2535 { 2536 int i; 2537 IDENTIFY_DATA2 *pIdentify = (IDENTIFY_DATA2*)pVDev->u.disk.mv->identifyDevice; 2538 2539 inquiryData->DeviceType = T_DIRECT; /*DIRECT_ACCESS_DEVICE*/ 2540 inquiryData->AdditionalLength = (UCHAR)(sizeof(INQUIRYDATA) - 5); 2541 #ifndef SERIAL_CMDS 2542 inquiryData->CommandQueue = 1; 2543 #endif 2544 2545 switch(pVDev->VDeviceType) { 2546 case VD_SINGLE_DISK: 2547 case VD_ATAPI: 2548 case VD_REMOVABLE: 2549 /* Set the removable bit, if applicable. */ 2550 if ((pVDev->u.disk.df_removable_drive) || (pIdentify->GeneralConfiguration & 0x80)) 2551 inquiryData->RemovableMedia = 1; 2552 2553 /* Fill in vendor identification fields. */ 2554 for (i = 0; i < 20; i += 2) { 2555 inquiryData->VendorId[i] = ((PUCHAR)pIdentify->ModelNumber)[i + 1]; 2556 inquiryData->VendorId[i+1] = ((PUCHAR)pIdentify->ModelNumber)[i]; 2557 2558 } 2559 2560 /* Initialize unused portion of product id. */ 2561 for (i = 0; i < 4; i++) inquiryData->ProductId[12+i] = ' '; 2562 2563 /* firmware revision */ 2564 for (i = 0; i < 4; i += 2) 2565 { 2566 inquiryData->ProductRevisionLevel[i] = ((PUCHAR)pIdentify->FirmwareRevision)[i+1]; 2567 inquiryData->ProductRevisionLevel[i+1] = ((PUCHAR)pIdentify->FirmwareRevision)[i]; 2568 } 2569 break; 2570 default: 2571 memcpy(&inquiryData->VendorId, "RR18xx ", 8); 2572 #ifdef SUPPORT_ARRAY 2573 switch(pVDev->VDeviceType){ 2574 case VD_RAID_0: 2575 if ((pVDev->u.array.pMember[0] && mIsArray(pVDev->u.array.pMember[0])) || 2576 (pVDev->u.array.pMember[1] && mIsArray(pVDev->u.array.pMember[1]))) 2577 memcpy(&inquiryData->ProductId, "RAID 1/0 Array ", 16); 2578 else 2579 memcpy(&inquiryData->ProductId, "RAID 0 Array ", 16); 2580 break; 2581 case VD_RAID_1: 2582 if ((pVDev->u.array.pMember[0] && mIsArray(pVDev->u.array.pMember[0])) || 2583 (pVDev->u.array.pMember[1] && mIsArray(pVDev->u.array.pMember[1]))) 2584 memcpy(&inquiryData->ProductId, "RAID 0/1 Array ", 16); 2585 else 2586 memcpy(&inquiryData->ProductId, "RAID 1 Array ", 16); 2587 break; 2588 case VD_RAID_5: 2589 memcpy(&inquiryData->ProductId, "RAID 5 Array ", 16); 2590 break; 2591 case VD_JBOD: 2592 memcpy(&inquiryData->ProductId, "JBOD Array ", 16); 2593 break; 2594 } 2595 #endif 2596 memcpy(&inquiryData->ProductRevisionLevel, "3.00", 4); 2597 break; 2598 } 2599 } 2600 2601 static void 2602 hpt_timeout(void *arg) 2603 { 2604 PBUS_DMAMAP pmap = (PBUS_DMAMAP)((union ccb *)arg)->ccb_adapter; 2605 IAL_ADAPTER_T *pAdapter = pmap->pAdapter; 2606 _VBUS_INST(&pAdapter->VBus) 2607 2608 mtx_assert(&pAdapter->lock, MA_OWNED); 2609 fResetVBus(_VBUS_P0); 2610 } 2611 2612 static void 2613 hpt_io_dmamap_callback(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 2614 { 2615 PCommand pCmd = (PCommand)arg; 2616 union ccb *ccb = pCmd->pOrgCommand; 2617 struct ccb_hdr *ccb_h = &ccb->ccb_h; 2618 PBUS_DMAMAP pmap = (PBUS_DMAMAP) ccb->ccb_adapter; 2619 IAL_ADAPTER_T *pAdapter = pmap->pAdapter; 2620 PVDevice pVDev = pAdapter->VBus.pVDevice[ccb_h->target_id]; 2621 FPSCAT_GATH psg = pCmd->pSgTable; 2622 int idx; 2623 _VBUS_INST(pVDev->pVBus) 2624 2625 HPT_ASSERT(pCmd->cf_physical_sg); 2626 2627 if (error) 2628 panic("busdma error"); 2629 2630 HPT_ASSERT(nsegs<= MAX_SG_DESCRIPTORS); 2631 2632 if (nsegs != 0) { 2633 for (idx = 0; idx < nsegs; idx++, psg++) { 2634 psg->dSgAddress = (ULONG_PTR)(UCHAR *)segs[idx].ds_addr; 2635 psg->wSgSize = segs[idx].ds_len; 2636 psg->wSgFlag = (idx == nsegs-1)? SG_FLAG_EOT: 0; 2637 /* KdPrint(("psg[%d]:add=%p,size=%x,flag=%x\n", idx, psg->dSgAddress,psg->wSgSize,psg->wSgFlag)); */ 2638 } 2639 /* psg[-1].wSgFlag = SG_FLAG_EOT; */ 2640 2641 if (pCmd->cf_data_in) { 2642 bus_dmamap_sync(pAdapter->io_dma_parent, pmap->dma_map, 2643 BUS_DMASYNC_PREREAD); 2644 } 2645 else if (pCmd->cf_data_out) { 2646 bus_dmamap_sync(pAdapter->io_dma_parent, pmap->dma_map, 2647 BUS_DMASYNC_PREWRITE); 2648 } 2649 } 2650 2651 callout_reset(&pmap->timeout, 20 * hz, hpt_timeout, ccb); 2652 pVDev->pfnSendCommand(_VBUS_P pCmd); 2653 CheckPendingCall(_VBUS_P0); 2654 } 2655 2656 2657 2658 static void HPTLIBAPI 2659 OsSendCommand(_VBUS_ARG union ccb *ccb) 2660 { 2661 PBUS_DMAMAP pmap = (PBUS_DMAMAP)ccb->ccb_adapter; 2662 IAL_ADAPTER_T *pAdapter = pmap->pAdapter; 2663 struct ccb_hdr *ccb_h = &ccb->ccb_h; 2664 struct ccb_scsiio *csio = &ccb->csio; 2665 PVDevice pVDev = pAdapter->VBus.pVDevice[ccb_h->target_id]; 2666 2667 KdPrintI(("OsSendCommand: ccb %p cdb %x-%x-%x\n", 2668 ccb, 2669 *(ULONG *)&ccb->csio.cdb_io.cdb_bytes[0], 2670 *(ULONG *)&ccb->csio.cdb_io.cdb_bytes[4], 2671 *(ULONG *)&ccb->csio.cdb_io.cdb_bytes[8] 2672 )); 2673 2674 pAdapter->outstandingCommands++; 2675 2676 if (pVDev == NULL || pVDev->vf_online == 0) { 2677 ccb->ccb_h.status = CAM_REQ_INVALID; 2678 ccb_done(ccb); 2679 goto Command_Complished; 2680 } 2681 2682 switch(ccb->csio.cdb_io.cdb_bytes[0]) 2683 { 2684 case TEST_UNIT_READY: 2685 case START_STOP_UNIT: 2686 case SYNCHRONIZE_CACHE: 2687 /* FALLTHROUGH */ 2688 ccb->ccb_h.status = CAM_REQ_CMP; 2689 break; 2690 2691 case INQUIRY: 2692 ZeroMemory(ccb->csio.data_ptr, ccb->csio.dxfer_len); 2693 SetInquiryData((PINQUIRYDATA)ccb->csio.data_ptr, pVDev); 2694 ccb_h->status = CAM_REQ_CMP; 2695 break; 2696 2697 case READ_CAPACITY: 2698 { 2699 UCHAR *rbuf=csio->data_ptr; 2700 unsigned int cap; 2701 2702 if (pVDev->VDeviceCapacity > 0xfffffffful) { 2703 cap = 0xfffffffful; 2704 } else { 2705 cap = pVDev->VDeviceCapacity - 1; 2706 } 2707 2708 rbuf[0] = (UCHAR)(cap>>24); 2709 rbuf[1] = (UCHAR)(cap>>16); 2710 rbuf[2] = (UCHAR)(cap>>8); 2711 rbuf[3] = (UCHAR)cap; 2712 /* Claim 512 byte blocks (big-endian). */ 2713 rbuf[4] = 0; 2714 rbuf[5] = 0; 2715 rbuf[6] = 2; 2716 rbuf[7] = 0; 2717 2718 ccb_h->status = CAM_REQ_CMP; 2719 break; 2720 } 2721 2722 case 0x9e: /*SERVICE_ACTION_IN*/ 2723 { 2724 UCHAR *rbuf = csio->data_ptr; 2725 LBA_T cap = pVDev->VDeviceCapacity - 1; 2726 2727 rbuf[0] = (UCHAR)(cap>>56); 2728 rbuf[1] = (UCHAR)(cap>>48); 2729 rbuf[2] = (UCHAR)(cap>>40); 2730 rbuf[3] = (UCHAR)(cap>>32); 2731 rbuf[4] = (UCHAR)(cap>>24); 2732 rbuf[5] = (UCHAR)(cap>>16); 2733 rbuf[6] = (UCHAR)(cap>>8); 2734 rbuf[7] = (UCHAR)cap; 2735 rbuf[8] = 0; 2736 rbuf[9] = 0; 2737 rbuf[10] = 2; 2738 rbuf[11] = 0; 2739 2740 ccb_h->status = CAM_REQ_CMP; 2741 break; 2742 } 2743 2744 case READ_6: 2745 case WRITE_6: 2746 case READ_10: 2747 case WRITE_10: 2748 case 0x88: /* READ_16 */ 2749 case 0x8a: /* WRITE_16 */ 2750 case 0x13: 2751 case 0x2f: 2752 { 2753 UCHAR Cdb[16]; 2754 UCHAR CdbLength; 2755 _VBUS_INST(pVDev->pVBus) 2756 PCommand pCmd = AllocateCommand(_VBUS_P0); 2757 int error; 2758 HPT_ASSERT(pCmd); 2759 2760 CdbLength = csio->cdb_len; 2761 if ((ccb->ccb_h.flags & CAM_CDB_POINTER) != 0) 2762 { 2763 if ((ccb->ccb_h.flags & CAM_CDB_PHYS) == 0) 2764 { 2765 bcopy(csio->cdb_io.cdb_ptr, Cdb, CdbLength); 2766 } 2767 else 2768 { 2769 KdPrintE(("ERROR!!!\n")); 2770 ccb->ccb_h.status = CAM_REQ_INVALID; 2771 break; 2772 } 2773 } 2774 else 2775 { 2776 bcopy(csio->cdb_io.cdb_bytes, Cdb, CdbLength); 2777 } 2778 2779 pCmd->pOrgCommand = ccb; 2780 pCmd->pVDevice = pVDev; 2781 pCmd->pfnCompletion = fOsCommandDone; 2782 pCmd->pfnBuildSgl = fOsBuildSgl; 2783 pCmd->pSgTable = pmap->psg; 2784 2785 switch (Cdb[0]) 2786 { 2787 case READ_6: 2788 case WRITE_6: 2789 case 0x13: 2790 pCmd->uCmd.Ide.Lba = ((ULONG)Cdb[1] << 16) | ((ULONG)Cdb[2] << 8) | (ULONG)Cdb[3]; 2791 pCmd->uCmd.Ide.nSectors = (USHORT) Cdb[4]; 2792 break; 2793 2794 case 0x88: /* READ_16 */ 2795 case 0x8a: /* WRITE_16 */ 2796 pCmd->uCmd.Ide.Lba = 2797 (HPT_U64)Cdb[2] << 56 | 2798 (HPT_U64)Cdb[3] << 48 | 2799 (HPT_U64)Cdb[4] << 40 | 2800 (HPT_U64)Cdb[5] << 32 | 2801 (HPT_U64)Cdb[6] << 24 | 2802 (HPT_U64)Cdb[7] << 16 | 2803 (HPT_U64)Cdb[8] << 8 | 2804 (HPT_U64)Cdb[9]; 2805 pCmd->uCmd.Ide.nSectors = (USHORT)Cdb[12] << 8 | (USHORT)Cdb[13]; 2806 break; 2807 2808 default: 2809 pCmd->uCmd.Ide.Lba = (ULONG)Cdb[5] | ((ULONG)Cdb[4] << 8) | ((ULONG)Cdb[3] << 16) | ((ULONG)Cdb[2] << 24); 2810 pCmd->uCmd.Ide.nSectors = (USHORT) Cdb[8] | ((USHORT)Cdb[7]<<8); 2811 break; 2812 } 2813 2814 switch (Cdb[0]) 2815 { 2816 case READ_6: 2817 case READ_10: 2818 case 0x88: /* READ_16 */ 2819 pCmd->uCmd.Ide.Command = IDE_COMMAND_READ; 2820 pCmd->cf_data_in = 1; 2821 break; 2822 2823 case WRITE_6: 2824 case WRITE_10: 2825 case 0x8a: /* WRITE_16 */ 2826 pCmd->uCmd.Ide.Command = IDE_COMMAND_WRITE; 2827 pCmd->cf_data_out = 1; 2828 break; 2829 case 0x13: 2830 case 0x2f: 2831 pCmd->uCmd.Ide.Command = IDE_COMMAND_VERIFY; 2832 break; 2833 } 2834 /*///////////////////////// */ 2835 pCmd->cf_physical_sg = 1; 2836 error = bus_dmamap_load_ccb(pAdapter->io_dma_parent, 2837 pmap->dma_map, 2838 ccb, 2839 hpt_io_dmamap_callback, 2840 pCmd, BUS_DMA_WAITOK 2841 ); 2842 KdPrint(("bus_dmamap_load return %d\n", error)); 2843 if (error && error!=EINPROGRESS) { 2844 hpt_printk(("bus_dmamap_load error %d\n", error)); 2845 FreeCommand(_VBUS_P pCmd); 2846 ccb->ccb_h.status = CAM_REQ_CMP_ERR; 2847 dmamap_put(pmap); 2848 pAdapter->outstandingCommands--; 2849 if (pAdapter->outstandingCommands == 0) 2850 wakeup(pAdapter); 2851 xpt_done(ccb); 2852 } 2853 goto Command_Complished; 2854 } 2855 2856 default: 2857 ccb->ccb_h.status = CAM_REQ_INVALID; 2858 break; 2859 } 2860 ccb_done(ccb); 2861 Command_Complished: 2862 CheckPendingCall(_VBUS_P0); 2863 return; 2864 } 2865 2866 static void HPTLIBAPI 2867 fOsCommandDone(_VBUS_ARG PCommand pCmd) 2868 { 2869 union ccb *ccb = pCmd->pOrgCommand; 2870 PBUS_DMAMAP pmap = (PBUS_DMAMAP)ccb->ccb_adapter; 2871 IAL_ADAPTER_T *pAdapter = pmap->pAdapter; 2872 2873 KdPrint(("fOsCommandDone(pcmd=%p, result=%d)\n", pCmd, pCmd->Result)); 2874 2875 callout_stop(&pmap->timeout); 2876 2877 switch(pCmd->Result) { 2878 case RETURN_SUCCESS: 2879 ccb->ccb_h.status = CAM_REQ_CMP; 2880 break; 2881 case RETURN_BAD_DEVICE: 2882 ccb->ccb_h.status = CAM_DEV_NOT_THERE; 2883 break; 2884 case RETURN_DEVICE_BUSY: 2885 ccb->ccb_h.status = CAM_BUSY; 2886 break; 2887 case RETURN_INVALID_REQUEST: 2888 ccb->ccb_h.status = CAM_REQ_INVALID; 2889 break; 2890 case RETURN_SELECTION_TIMEOUT: 2891 ccb->ccb_h.status = CAM_SEL_TIMEOUT; 2892 break; 2893 case RETURN_RETRY: 2894 ccb->ccb_h.status = CAM_BUSY; 2895 break; 2896 default: 2897 ccb->ccb_h.status = CAM_SCSI_STATUS_ERROR; 2898 break; 2899 } 2900 2901 if (pCmd->cf_data_in) { 2902 bus_dmamap_sync(pAdapter->io_dma_parent, pmap->dma_map, BUS_DMASYNC_POSTREAD); 2903 } 2904 else if (pCmd->cf_data_out) { 2905 bus_dmamap_sync(pAdapter->io_dma_parent, pmap->dma_map, BUS_DMASYNC_POSTWRITE); 2906 } 2907 2908 bus_dmamap_unload(pAdapter->io_dma_parent, pmap->dma_map); 2909 2910 FreeCommand(_VBUS_P pCmd); 2911 ccb_done(ccb); 2912 } 2913 2914 int 2915 hpt_queue_dpc(HPT_DPC dpc, IAL_ADAPTER_T * pAdapter, void *arg, UCHAR flags) 2916 { 2917 int p; 2918 2919 mtx_lock(&DpcQueue_Lock); 2920 p = (DpcQueue_Last + 1) % MAX_DPC; 2921 if (p==DpcQueue_First) { 2922 KdPrint(("DPC Queue full!\n")); 2923 mtx_unlock(&DpcQueue_Lock); 2924 return -1; 2925 } 2926 2927 DpcQueue[DpcQueue_Last].dpc = dpc; 2928 DpcQueue[DpcQueue_Last].pAdapter = pAdapter; 2929 DpcQueue[DpcQueue_Last].arg = arg; 2930 DpcQueue[DpcQueue_Last].flags = flags; 2931 DpcQueue_Last = p; 2932 mtx_unlock(&DpcQueue_Lock); 2933 2934 return 0; 2935 } 2936 2937 #ifdef _RAID5N_ 2938 /* 2939 * Allocate memory above 16M, otherwise we may eat all low memory for ISA devices. 2940 * How about the memory for 5081 request/response array and PRD table? 2941 */ 2942 void 2943 *os_alloc_page(_VBUS_ARG0) 2944 { 2945 return (void *)contigmalloc(0x1000, M_DEVBUF, M_NOWAIT, 0x1000000, 0xffffffff, PAGE_SIZE, 0ul); 2946 } 2947 2948 void 2949 *os_alloc_dma_page(_VBUS_ARG0) 2950 { 2951 return (void *)contigmalloc(0x1000, M_DEVBUF, M_NOWAIT, 0x1000000, 0xffffffff, PAGE_SIZE, 0ul); 2952 } 2953 2954 void 2955 os_free_page(_VBUS_ARG void *p) 2956 { 2957 contigfree(p, 0x1000, M_DEVBUF); 2958 } 2959 2960 void 2961 os_free_dma_page(_VBUS_ARG void *p) 2962 { 2963 contigfree(p, 0x1000, M_DEVBUF); 2964 } 2965 2966 void 2967 DoXor1(ULONG *p0, ULONG *p1, ULONG *p2, UINT nBytes) 2968 { 2969 UINT i; 2970 for (i = 0; i < nBytes / 4; i++) *p0++ = *p1++ ^ *p2++; 2971 } 2972 2973 void 2974 DoXor2(ULONG *p0, ULONG *p2, UINT nBytes) 2975 { 2976 UINT i; 2977 for (i = 0; i < nBytes / 4; i++) *p0++ ^= *p2++; 2978 } 2979 #endif
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