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sys/dev/hptmv/entry.c
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1 /* 2 * Copyright (c) 2004-2005 HighPoint Technologies, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29 #include <sys/param.h> 30 #include <sys/systm.h> 31 #include <sys/kernel.h> 32 #include <sys/bus.h> 33 #include <sys/malloc.h> 34 #include <sys/resource.h> 35 #include <sys/time.h> 36 #include <sys/callout.h> 37 #include <sys/signalvar.h> 38 #include <sys/eventhandler.h> 39 #include <sys/proc.h> 40 #include <sys/kthread.h> 41 42 #if (__FreeBSD_version >= 500000) 43 #include <sys/mutex.h> 44 #include <sys/module.h> 45 #endif 46 47 #if (__FreeBSD_version >= 500000) 48 #include <dev/pci/pcireg.h> 49 #include <dev/pci/pcivar.h> 50 #else 51 #include <pci/pcireg.h> 52 #include <pci/pcivar.h> 53 #include <sys/wait.h> 54 #include <sys/sysproto.h> 55 #endif 56 57 #ifndef __KERNEL__ 58 #define __KERNEL__ 59 #endif 60 61 #include <dev/hptmv/global.h> 62 #include <dev/hptmv/hptintf.h> 63 #include <dev/hptmv/osbsd.h> 64 #include <dev/hptmv/access601.h> 65 66 67 #ifdef DEBUG 68 #ifdef DEBUG_LEVEL 69 int hpt_dbg_level = DEBUG_LEVEL; 70 #else 71 int hpt_dbg_level = 0; 72 #endif 73 #endif 74 75 #define MV_ERROR printf 76 77 /* 78 * CAM SIM entry points 79 */ 80 static int hpt_probe (device_t dev); 81 static void launch_worker_thread(void); 82 static int hpt_attach(device_t dev); 83 static int hpt_detach(device_t dev); 84 static int hpt_shutdown(device_t dev); 85 static void hpt_poll(struct cam_sim *sim); 86 static void hpt_intr(void *arg); 87 static void hpt_async(void *callback_arg, u_int32_t code, struct cam_path *path, void *arg); 88 static void hpt_action(struct cam_sim *sim, union ccb *ccb); 89 90 static device_method_t driver_methods[] = { 91 /* Device interface */ 92 DEVMETHOD(device_probe, hpt_probe), 93 DEVMETHOD(device_attach, hpt_attach), 94 DEVMETHOD(device_detach, hpt_detach), 95 96 /* DEVMETHOD(device_shutdown, hpt_shutdown), */ 97 { 0, 0 } 98 }; 99 100 static driver_t hpt_pci_driver = { 101 __str(PROC_DIR_NAME), 102 driver_methods, 103 sizeof(IAL_ADAPTER_T) 104 }; 105 106 static devclass_t hpt_devclass; 107 108 #define __DRIVER_MODULE(p1, p2, p3, p4, p5, p6) DRIVER_MODULE(p1, p2, p3, p4, p5, p6) 109 __DRIVER_MODULE(PROC_DIR_NAME, pci, hpt_pci_driver, hpt_devclass, 0, 0); 110 111 #define ccb_ccb_ptr spriv_ptr0 112 #define ccb_adapter ccb_h.spriv_ptr1 113 114 static void SetInquiryData(PINQUIRYDATA inquiryData, PVDevice pVDev); 115 static void HPTLIBAPI OsSendCommand (_VBUS_ARG union ccb * ccb); 116 static void HPTLIBAPI fOsCommandDone(_VBUS_ARG PCommand pCmd); 117 static void ccb_done(union ccb *ccb); 118 static void hpt_queue_ccb(union ccb **ccb_Q, union ccb *ccb); 119 static void hpt_free_ccb(union ccb **ccb_Q, union ccb *ccb); 120 static void hptmv_free_edma_queues(IAL_ADAPTER_T *pAdapter); 121 static void hptmv_free_channel(IAL_ADAPTER_T *pAdapter, MV_U8 channelNum); 122 static void handleEdmaError(_VBUS_ARG PCommand pCmd); 123 static int hptmv_init_channel(IAL_ADAPTER_T *pAdapter, MV_U8 channelNum); 124 static int fResetActiveCommands(PVBus _vbus_p); 125 static void fRegisterVdevice(IAL_ADAPTER_T *pAdapter); 126 static int hptmv_allocate_edma_queues(IAL_ADAPTER_T *pAdapter); 127 static void hptmv_handle_event_disconnect(void *data); 128 static void hptmv_handle_event_connect(void *data); 129 static int start_channel(IAL_ADAPTER_T *pAdapter, MV_U8 channelNum); 130 static void init_vdev_params(IAL_ADAPTER_T *pAdapter, MV_U8 channel); 131 static int hptmv_parse_identify_results(MV_SATA_CHANNEL *pMvSataChannel); 132 static int HPTLIBAPI fOsBuildSgl(_VBUS_ARG PCommand pCmd, FPSCAT_GATH pSg, 133 int logical); 134 static MV_BOOLEAN CommandCompletionCB(MV_SATA_ADAPTER *pMvSataAdapter, 135 MV_U8 channelNum, MV_COMPLETION_TYPE comp_type, MV_VOID_PTR commandId, 136 MV_U16 responseFlags, MV_U32 timeStamp, 137 MV_STORAGE_DEVICE_REGISTERS *registerStruct); 138 static MV_BOOLEAN hptmv_event_notify(MV_SATA_ADAPTER *pMvSataAdapter, 139 MV_EVENT_TYPE eventType, MV_U32 param1, MV_U32 param2); 140 141 #define ccb_ccb_ptr spriv_ptr0 142 #define ccb_adapter ccb_h.spriv_ptr1 143 144 IAL_ADAPTER_T *gIal_Adapter = 0; 145 IAL_ADAPTER_T *pCurAdapter = 0; 146 static MV_SATA_CHANNEL gMvSataChannels[MAX_VBUS][MV_SATA_CHANNELS_NUM]; 147 148 typedef struct st_HPT_DPC { 149 IAL_ADAPTER_T *pAdapter; 150 void (*dpc)(IAL_ADAPTER_T *, void *, UCHAR); 151 void *arg; 152 UCHAR flags; 153 } ST_HPT_DPC; 154 155 #define MAX_DPC 16 156 UCHAR DPC_Request_Nums = 0; 157 static ST_HPT_DPC DpcQueue[MAX_DPC]; 158 static int DpcQueue_First=0; 159 static int DpcQueue_Last = 0; 160 161 char DRIVER_VERSION[] = "v1.16"; 162 163 #if (__FreeBSD_version >= 500000) 164 static struct mtx driver_lock; 165 intrmask_t lock_driver() 166 { 167 168 intrmask_t spl = 0; 169 mtx_lock(&driver_lock); 170 return spl; 171 } 172 void unlock_driver(intrmask_t spl) 173 { 174 mtx_unlock(&driver_lock); 175 } 176 #else 177 static int driver_locked = 0; 178 intrmask_t lock_driver() 179 { 180 intrmask_t spl = splcam(); 181 loop: 182 while (driver_locked) 183 tsleep(&driver_locked, PRIBIO, "hptlck", hz); 184 atomic_add_int(&driver_locked, 1); 185 if (driver_locked>1) { 186 atomic_subtract_int(&driver_locked, 1); 187 goto loop; 188 } 189 return spl; 190 } 191 192 void unlock_driver(intrmask_t spl) 193 { 194 atomic_subtract_int(&driver_locked, 1); 195 if (driver_locked==0) { 196 wakeup(&driver_locked); 197 } 198 splx(spl); 199 } 200 #endif 201 202 /******************************************************************************* 203 * Name: hptmv_free_channel 204 * 205 * Description: free allocated queues for the given channel 206 * 207 * Parameters: pMvSataAdapter - pointer to the RR18xx controler this 208 * channel connected to. 209 * channelNum - channel number. 210 * 211 ******************************************************************************/ 212 static void 213 hptmv_free_channel(IAL_ADAPTER_T *pAdapter, MV_U8 channelNum) 214 { 215 HPT_ASSERT(channelNum < MV_SATA_CHANNELS_NUM); 216 pAdapter->mvSataAdapter.sataChannel[channelNum] = NULL; 217 } 218 219 static void failDevice(PVDevice pVDev) 220 { 221 PVBus _vbus_p = pVDev->pVBus; 222 IAL_ADAPTER_T *pAdapter = (IAL_ADAPTER_T *)_vbus_p->OsExt; 223 224 pVDev->u.disk.df_on_line = 0; 225 pVDev->vf_online = 0; 226 if (pVDev->pfnDeviceFailed) 227 CallWhenIdle(_VBUS_P (DPC_PROC)pVDev->pfnDeviceFailed, pVDev); 228 229 fNotifyGUI(ET_DEVICE_REMOVED, pVDev); 230 231 #ifndef FOR_DEMO 232 if (pAdapter->ver_601==2 && !pAdapter->beeping) { 233 pAdapter->beeping = 1; 234 BeepOn(pAdapter->mvSataAdapter.adapterIoBaseAddress); 235 set_fail_led(&pAdapter->mvSataAdapter, pVDev->u.disk.mv->channelNumber, 1); 236 } 237 #endif 238 } 239 240 int MvSataResetChannel(MV_SATA_ADAPTER *pMvSataAdapter, MV_U8 channel); 241 242 static void 243 handleEdmaError(_VBUS_ARG PCommand pCmd) 244 { 245 PDevice pDevice = &pCmd->pVDevice->u.disk; 246 MV_SATA_ADAPTER * pSataAdapter = pDevice->mv->mvSataAdapter; 247 248 if (!pDevice->df_on_line) { 249 KdPrint(("Device is offline")); 250 pCmd->Result = RETURN_BAD_DEVICE; 251 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd); 252 return; 253 } 254 255 if (pCmd->RetryCount++>5) { 256 hpt_printk(("too many retries on channel(%d)\n", pDevice->mv->channelNumber)); 257 failed: 258 failDevice(pCmd->pVDevice); 259 pCmd->Result = RETURN_IDE_ERROR; 260 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd); 261 return; 262 } 263 264 /* reset the channel and retry the command */ 265 if (MvSataResetChannel(pSataAdapter, pDevice->mv->channelNumber)) 266 goto failed; 267 268 fNotifyGUI(ET_DEVICE_ERROR, Map2pVDevice(pDevice)); 269 270 hpt_printk(("Retry on channel(%d)\n", pDevice->mv->channelNumber)); 271 fDeviceSendCommand(_VBUS_P pCmd); 272 } 273 274 /**************************************************************** 275 * Name: hptmv_init_channel 276 * 277 * Description: allocate request and response queues for the EDMA of the 278 * given channel and sets other fields. 279 * 280 * Parameters: 281 * pAdapter - pointer to the emulated adapter data structure 282 * channelNum - channel number. 283 * Return: 0 on success, otherwise on failure 284 ****************************************************************/ 285 static int 286 hptmv_init_channel(IAL_ADAPTER_T *pAdapter, MV_U8 channelNum) 287 { 288 MV_SATA_CHANNEL *pMvSataChannel; 289 dma_addr_t req_dma_addr; 290 dma_addr_t rsp_dma_addr; 291 292 if (channelNum >= MV_SATA_CHANNELS_NUM) 293 { 294 MV_ERROR("RR18xx[%d]: Bad channelNum=%d", 295 pAdapter->mvSataAdapter.adapterId, channelNum); 296 return -1; 297 } 298 299 pMvSataChannel = &gMvSataChannels[pAdapter->mvSataAdapter.adapterId][channelNum]; 300 pAdapter->mvSataAdapter.sataChannel[channelNum] = pMvSataChannel; 301 pMvSataChannel->channelNumber = channelNum; 302 pMvSataChannel->lba48Address = MV_FALSE; 303 pMvSataChannel->maxReadTransfer = MV_FALSE; 304 305 pMvSataChannel->requestQueue = (struct mvDmaRequestQueueEntry *) 306 (pAdapter->requestsArrayBaseAlignedAddr + (channelNum * MV_EDMA_REQUEST_QUEUE_SIZE)); 307 req_dma_addr = pAdapter->requestsArrayBaseDmaAlignedAddr + (channelNum * MV_EDMA_REQUEST_QUEUE_SIZE); 308 309 310 KdPrint(("requestQueue addr is 0x%llX", (HPT_U64)(ULONG_PTR)req_dma_addr)); 311 312 /* check the 1K alignment of the request queue*/ 313 if (req_dma_addr & 0x3ff) 314 { 315 MV_ERROR("RR18xx[%d]: request queue allocated isn't 1 K aligned," 316 " dma_addr=%llx channel=%d\n", pAdapter->mvSataAdapter.adapterId, 317 (HPT_U64)(ULONG_PTR)req_dma_addr, channelNum); 318 return -1; 319 } 320 pMvSataChannel->requestQueuePciLowAddress = req_dma_addr; 321 pMvSataChannel->requestQueuePciHiAddress = 0; 322 KdPrint(("RR18xx[%d,%d]: request queue allocated: 0x%p", 323 pAdapter->mvSataAdapter.adapterId, channelNum, 324 pMvSataChannel->requestQueue)); 325 pMvSataChannel->responseQueue = (struct mvDmaResponseQueueEntry *) 326 (pAdapter->responsesArrayBaseAlignedAddr + (channelNum * MV_EDMA_RESPONSE_QUEUE_SIZE)); 327 rsp_dma_addr = pAdapter->responsesArrayBaseDmaAlignedAddr + (channelNum * MV_EDMA_RESPONSE_QUEUE_SIZE); 328 329 /* check the 256 alignment of the response queue*/ 330 if (rsp_dma_addr & 0xff) 331 { 332 MV_ERROR("RR18xx[%d,%d]: response queue allocated isn't 256 byte " 333 "aligned, dma_addr=%llx\n", 334 pAdapter->mvSataAdapter.adapterId, channelNum, (HPT_U64)(ULONG_PTR)rsp_dma_addr); 335 return -1; 336 } 337 pMvSataChannel->responseQueuePciLowAddress = rsp_dma_addr; 338 pMvSataChannel->responseQueuePciHiAddress = 0; 339 KdPrint(("RR18xx[%d,%d]: response queue allocated: 0x%p", 340 pAdapter->mvSataAdapter.adapterId, channelNum, 341 pMvSataChannel->responseQueue)); 342 343 pAdapter->mvChannel[channelNum].online = MV_TRUE; 344 return 0; 345 } 346 347 /****************************************************************************** 348 * Name: hptmv_parse_identify_results 349 * 350 * Description: this functions parses the identify command results, checks 351 * that the connected deives can be accesed by RR18xx EDMA, 352 * and updates the channel stucture accordingly. 353 * 354 * Parameters: pMvSataChannel, pointer to the channel data structure. 355 * 356 * Returns: =0 ->success, < 0 ->failure. 357 * 358 ******************************************************************************/ 359 static int 360 hptmv_parse_identify_results(MV_SATA_CHANNEL *pMvSataChannel) 361 { 362 MV_U16 *iden = pMvSataChannel->identifyDevice; 363 364 /*LBA addressing*/ 365 if (! (iden[IDEN_CAPACITY_1_OFFSET] & 0x200)) 366 { 367 KdPrint(("IAL Error in IDENTIFY info: LBA not supported\n")); 368 return -1; 369 } 370 else 371 { 372 KdPrint(("%25s - %s\n", "Capabilities", "LBA supported")); 373 } 374 /*DMA support*/ 375 if (! (iden[IDEN_CAPACITY_1_OFFSET] & 0x100)) 376 { 377 KdPrint(("IAL Error in IDENTIFY info: DMA not supported\n")); 378 return -1; 379 } 380 else 381 { 382 KdPrint(("%25s - %s\n", "Capabilities", "DMA supported")); 383 } 384 /* PIO */ 385 if ((iden[IDEN_VALID] & 2) == 0) 386 { 387 KdPrint(("IAL Error in IDENTIFY info: not able to find PIO mode\n")); 388 return -1; 389 } 390 KdPrint(("%25s - 0x%02x\n", "PIO modes supported", 391 iden[IDEN_PIO_MODE_SPPORTED] & 0xff)); 392 393 /*UDMA*/ 394 if ((iden[IDEN_VALID] & 4) == 0) 395 { 396 KdPrint(("IAL Error in IDENTIFY info: not able to find UDMA mode\n")); 397 return -1; 398 } 399 400 /* 48 bit address */ 401 if ((iden[IDEN_SUPPORTED_COMMANDS2] & 0x400)) 402 { 403 KdPrint(("%25s - %s\n", "LBA48 addressing", "supported")); 404 pMvSataChannel->lba48Address = MV_TRUE; 405 } 406 else 407 { 408 KdPrint(("%25s - %s\n", "LBA48 addressing", "Not supported")); 409 pMvSataChannel->lba48Address = MV_FALSE; 410 } 411 return 0; 412 } 413 414 static void 415 init_vdev_params(IAL_ADAPTER_T *pAdapter, MV_U8 channel) 416 { 417 PVDevice pVDev = &pAdapter->VDevices[channel]; 418 MV_SATA_CHANNEL *pMvSataChannel = pAdapter->mvSataAdapter.sataChannel[channel]; 419 MV_U16_PTR IdentifyData = pMvSataChannel->identifyDevice; 420 421 pMvSataChannel->outstandingCommands = 0; 422 423 pVDev->u.disk.mv = pMvSataChannel; 424 pVDev->u.disk.df_on_line = 1; 425 pVDev->u.disk.pVBus = &pAdapter->VBus; 426 pVDev->pVBus = &pAdapter->VBus; 427 428 #ifdef SUPPORT_48BIT_LBA 429 if (pMvSataChannel->lba48Address == MV_TRUE) 430 pVDev->u.disk.dDeRealCapacity = ((IdentifyData[101]<<16) | IdentifyData[100]) - 1; 431 else 432 #endif 433 if(IdentifyData[53] & 1) { 434 pVDev->u.disk.dDeRealCapacity = 435 (((IdentifyData[58]<<16 | IdentifyData[57]) < (IdentifyData[61]<<16 | IdentifyData[60])) ? 436 (IdentifyData[61]<<16 | IdentifyData[60]) : 437 (IdentifyData[58]<<16 | IdentifyData[57])) - 1; 438 } else 439 pVDev->u.disk.dDeRealCapacity = 440 (IdentifyData[61]<<16 | IdentifyData[60]) - 1; 441 442 pVDev->u.disk.bDeUsable_Mode = pVDev->u.disk.bDeModeSetting = 443 pAdapter->mvChannel[channel].maxPioModeSupported - MV_ATA_TRANSFER_PIO_0; 444 445 if (pAdapter->mvChannel[channel].maxUltraDmaModeSupported!=0xFF) { 446 pVDev->u.disk.bDeUsable_Mode = pVDev->u.disk.bDeModeSetting = 447 pAdapter->mvChannel[channel].maxUltraDmaModeSupported - MV_ATA_TRANSFER_UDMA_0 + 8; 448 } 449 } 450 451 static void device_change(IAL_ADAPTER_T *pAdapter , MV_U8 channelIndex, int plugged) 452 { 453 PVDevice pVDev; 454 MV_SATA_ADAPTER *pMvSataAdapter = &pAdapter->mvSataAdapter; 455 MV_SATA_CHANNEL *pMvSataChannel = pMvSataAdapter->sataChannel[channelIndex]; 456 457 if (!pMvSataChannel) return; 458 459 if (plugged) 460 { 461 pVDev = &(pAdapter->VDevices[channelIndex]); 462 init_vdev_params(pAdapter, channelIndex); 463 464 pVDev->VDeviceType = pVDev->u.disk.df_atapi? VD_ATAPI : 465 pVDev->u.disk.df_removable_drive? VD_REMOVABLE : VD_SINGLE_DISK; 466 467 pVDev->VDeviceCapacity = pVDev->u.disk.dDeRealCapacity-SAVE_FOR_RAID_INFO; 468 pVDev->pfnSendCommand = pfnSendCommand[pVDev->VDeviceType]; 469 pVDev->pfnDeviceFailed = pfnDeviceFailed[pVDev->VDeviceType]; 470 pVDev->vf_online = 1; 471 472 #ifdef SUPPORT_ARRAY 473 if(pVDev->pParent) 474 { 475 int iMember; 476 for(iMember = 0; iMember < pVDev->pParent->u.array.bArnMember; iMember++) 477 if((PVDevice)pVDev->pParent->u.array.pMember[iMember] == pVDev) 478 pVDev->pParent->u.array.pMember[iMember] = NULL; 479 pVDev->pParent = NULL; 480 } 481 #endif 482 fNotifyGUI(ET_DEVICE_PLUGGED,pVDev); 483 fCheckBootable(pVDev); 484 RegisterVDevice(pVDev); 485 486 #ifndef FOR_DEMO 487 if (pAdapter->beeping) { 488 pAdapter->beeping = 0; 489 BeepOff(pAdapter->mvSataAdapter.adapterIoBaseAddress); 490 } 491 #endif 492 493 } 494 else 495 { 496 pVDev = &(pAdapter->VDevices[channelIndex]); 497 failDevice(pVDev); 498 } 499 } 500 501 static int 502 start_channel(IAL_ADAPTER_T *pAdapter, MV_U8 channelNum) 503 { 504 MV_SATA_ADAPTER *pMvSataAdapter = &pAdapter->mvSataAdapter; 505 MV_SATA_CHANNEL *pMvSataChannel = pMvSataAdapter->sataChannel[channelNum]; 506 MV_CHANNEL *pChannelInfo = &(pAdapter->mvChannel[channelNum]); 507 MV_U32 udmaMode,pioMode; 508 509 KdPrint(("RR18xx [%d]: start channel (%d)", pMvSataAdapter->adapterId, 510 channelNum)); 511 512 513 /* Software reset channel */ 514 if (mvStorageDevATASoftResetDevice(pMvSataAdapter, channelNum) == MV_FALSE) 515 { 516 MV_ERROR("RR18xx [%d,%d]: failed to perform Software reset\n", 517 pMvSataAdapter->adapterId, channelNum); 518 return -1; 519 } 520 521 /* Hardware reset channel */ 522 if (mvSataChannelHardReset(pMvSataAdapter, channelNum) == MV_FALSE) 523 { 524 /* If failed, try again - this is when trying to hardreset a channel */ 525 /* when drive is just spinning up */ 526 StallExec(5000000); /* wait 5 sec before trying again */ 527 if (mvSataChannelHardReset(pMvSataAdapter, channelNum) == MV_FALSE) 528 { 529 MV_ERROR("RR18xx [%d,%d]: failed to perform Hard reset\n", 530 pMvSataAdapter->adapterId, channelNum); 531 return -1; 532 } 533 } 534 535 /* identify device*/ 536 if (mvStorageDevATAIdentifyDevice(pMvSataAdapter, channelNum) == MV_FALSE) 537 { 538 MV_ERROR("RR18xx [%d,%d]: failed to perform ATA Identify command\n" 539 , pMvSataAdapter->adapterId, channelNum); 540 return -1; 541 } 542 if (hptmv_parse_identify_results(pMvSataChannel)) 543 { 544 MV_ERROR("RR18xx [%d,%d]: Error in parsing ATA Identify message\n" 545 , pMvSataAdapter->adapterId, channelNum); 546 return -1; 547 } 548 549 /* mvStorageDevATASetFeatures */ 550 /* Disable 8 bit PIO in case CFA enabled */ 551 if (pMvSataChannel->identifyDevice[86] & 4) 552 { 553 KdPrint(("RR18xx [%d]: Disable 8 bit PIO (CFA enabled) \n", 554 pMvSataAdapter->adapterId)); 555 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum, 556 MV_ATA_SET_FEATURES_DISABLE_8_BIT_PIO, 0, 557 0, 0, 0) == MV_FALSE) 558 { 559 MV_ERROR("RR18xx [%d]: channel %d: mvStorageDevATASetFeatures" 560 " failed\n", pMvSataAdapter->adapterId, channelNum); 561 return -1; 562 } 563 } 564 /* Write cache */ 565 #ifdef ENABLE_WRITE_CACHE 566 if (pMvSataChannel->identifyDevice[82] & 0x20) 567 { 568 if (!(pMvSataChannel->identifyDevice[85] & 0x20)) /* if not enabled by default */ 569 { 570 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum, 571 MV_ATA_SET_FEATURES_ENABLE_WCACHE, 0, 572 0, 0, 0) == MV_FALSE) 573 { 574 MV_ERROR("RR18xx [%d]: channel %d: mvStorageDevATASetFeatures failed\n", 575 pMvSataAdapter->adapterId, channelNum); 576 return -1; 577 } 578 } 579 KdPrint(("RR18xx [%d]: channel %d, write cache enabled\n", 580 pMvSataAdapter->adapterId, channelNum)); 581 } 582 else 583 { 584 KdPrint(("RR18xx [%d]: channel %d, write cache not supported\n", 585 pMvSataAdapter->adapterId, channelNum)); 586 } 587 #else /* disable write cache */ 588 { 589 if (pMvSataChannel->identifyDevice[85] & 0x20) 590 { 591 KdPrint(("RR18xx [%d]: channel =%d, disable write cache\n", 592 pMvSataAdapter->adapterId, channelNum)); 593 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum, 594 MV_ATA_SET_FEATURES_DISABLE_WCACHE, 0, 595 0, 0, 0) == MV_FALSE) 596 { 597 MV_ERROR("RR18xx [%d]: channel %d: mvStorageDevATASetFeatures failed\n", 598 pMvSataAdapter->adapterId, channelNum); 599 return -1; 600 } 601 } 602 KdPrint(("RR18xx [%d]: channel=%d, write cache disabled\n", 603 pMvSataAdapter->adapterId, channelNum)); 604 } 605 #endif 606 607 /* Set transfer mode */ 608 KdPrint(("RR18xx [%d] Set transfer mode XFER_PIO_SLOW\n", 609 pMvSataAdapter->adapterId)); 610 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum, 611 MV_ATA_SET_FEATURES_TRANSFER, 612 MV_ATA_TRANSFER_PIO_SLOW, 0, 0, 0) == 613 MV_FALSE) 614 { 615 MV_ERROR("RR18xx [%d] channel %d: Set Features failed\n", 616 pMvSataAdapter->adapterId, channelNum); 617 return -1; 618 } 619 620 if (pMvSataChannel->identifyDevice[IDEN_PIO_MODE_SPPORTED] & 1) 621 { 622 pioMode = MV_ATA_TRANSFER_PIO_4; 623 } 624 else if (pMvSataChannel->identifyDevice[IDEN_PIO_MODE_SPPORTED] & 2) 625 { 626 pioMode = MV_ATA_TRANSFER_PIO_3; 627 } 628 else 629 { 630 MV_ERROR("IAL Error in IDENTIFY info: PIO modes 3 and 4 not supported\n"); 631 pioMode = MV_ATA_TRANSFER_PIO_SLOW; 632 } 633 634 KdPrint(("RR18xx [%d] Set transfer mode XFER_PIO_4\n", 635 pMvSataAdapter->adapterId)); 636 pAdapter->mvChannel[channelNum].maxPioModeSupported = pioMode; 637 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum, 638 MV_ATA_SET_FEATURES_TRANSFER, 639 pioMode, 0, 0, 0) == MV_FALSE) 640 { 641 MV_ERROR("RR18xx [%d] channel %d: Set Features failed\n", 642 pMvSataAdapter->adapterId, channelNum); 643 return -1; 644 } 645 646 udmaMode = MV_ATA_TRANSFER_UDMA_0; 647 if (pMvSataChannel->identifyDevice[IDEN_UDMA_MODE] & 0x40) 648 { 649 udmaMode = MV_ATA_TRANSFER_UDMA_6; 650 } 651 else if (pMvSataChannel->identifyDevice[IDEN_UDMA_MODE] & 0x20) 652 { 653 udmaMode = MV_ATA_TRANSFER_UDMA_5; 654 } 655 else if (pMvSataChannel->identifyDevice[IDEN_UDMA_MODE] & 0x10) 656 { 657 udmaMode = MV_ATA_TRANSFER_UDMA_4; 658 } 659 else if (pMvSataChannel->identifyDevice[IDEN_UDMA_MODE] & 8) 660 { 661 udmaMode = MV_ATA_TRANSFER_UDMA_3; 662 } 663 else if (pMvSataChannel->identifyDevice[IDEN_UDMA_MODE] & 4) 664 { 665 udmaMode = MV_ATA_TRANSFER_UDMA_2; 666 } 667 668 KdPrint(("RR18xx [%d] Set transfer mode XFER_UDMA_%d\n", 669 pMvSataAdapter->adapterId, udmaMode & 0xf)); 670 pChannelInfo->maxUltraDmaModeSupported = udmaMode; 671 672 /*if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum, 673 MV_ATA_SET_FEATURES_TRANSFER, udmaMode, 674 0, 0, 0) == MV_FALSE) 675 { 676 MV_ERROR("RR18xx [%d] channel %d: Set Features failed\n", 677 pMvSataAdapter->adapterId, channelNum); 678 return -1; 679 }*/ 680 if (pChannelInfo->maxUltraDmaModeSupported == 0xFF) 681 return TRUE; 682 else 683 do 684 { 685 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum, 686 MV_ATA_SET_FEATURES_TRANSFER, 687 pChannelInfo->maxUltraDmaModeSupported, 688 0, 0, 0) == MV_FALSE) 689 { 690 if (pChannelInfo->maxUltraDmaModeSupported > MV_ATA_TRANSFER_UDMA_0) 691 { 692 if (mvStorageDevATASoftResetDevice(pMvSataAdapter, channelNum) == MV_FALSE) 693 { 694 MV_REG_WRITE_BYTE(pMvSataAdapter->adapterIoBaseAddress, 695 pMvSataChannel->eDmaRegsOffset + 696 0x11c, /* command reg */ 697 MV_ATA_COMMAND_IDLE_IMMEDIATE); 698 mvMicroSecondsDelay(10000); 699 mvSataChannelHardReset(pMvSataAdapter, channelNum); 700 if (mvStorageDevATASoftResetDevice(pMvSataAdapter, channelNum) == MV_FALSE) 701 return FALSE; 702 } 703 if (mvSataChannelHardReset(pMvSataAdapter, channelNum) == MV_FALSE) 704 return FALSE; 705 pChannelInfo->maxUltraDmaModeSupported--; 706 continue; 707 } 708 else return FALSE; 709 } 710 break; 711 }while (1); 712 713 /* Read look ahead */ 714 #ifdef ENABLE_READ_AHEAD 715 if (pMvSataChannel->identifyDevice[82] & 0x40) 716 { 717 if (!(pMvSataChannel->identifyDevice[85] & 0x40)) /* if not enabled by default */ 718 { 719 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum, 720 MV_ATA_SET_FEATURES_ENABLE_RLA, 0, 0, 721 0, 0) == MV_FALSE) 722 { 723 MV_ERROR("RR18xx [%d] channel %d: Set Features failed\n", 724 pMvSataAdapter->adapterId, channelNum); 725 return -1; 726 } 727 } 728 KdPrint(("RR18xx [%d]: channel=%d, read look ahead enabled\n", 729 pMvSataAdapter->adapterId, channelNum)); 730 } 731 else 732 { 733 KdPrint(("RR18xx [%d]: channel %d, Read Look Ahead not supported\n", 734 pMvSataAdapter->adapterId, channelNum)); 735 } 736 #else 737 { 738 if (pMvSataChannel->identifyDevice[86] & 0x20) 739 { 740 KdPrint(("RR18xx [%d]:channel %d, disable read look ahead\n", 741 pMvSataAdapter->adapterId, channelNum)); 742 if (mvStorageDevATASetFeatures(pMvSataAdapter, channelNum, 743 MV_ATA_SET_FEATURES_DISABLE_RLA, 0, 0, 744 0, 0) == MV_FALSE) 745 { 746 MV_ERROR("RR18xx [%d]:channel %d: ATA Set Features failed\n", 747 pMvSataAdapter->adapterId, channelNum); 748 return -1; 749 } 750 } 751 KdPrint(("RR18xx [%d]:channel %d, read look ahead disabled\n", 752 pMvSataAdapter->adapterId, channelNum)); 753 } 754 #endif 755 756 757 { 758 KdPrint(("RR18xx [%d]: channel %d config EDMA, Non Queued Mode\n", 759 pMvSataAdapter->adapterId, 760 channelNum)); 761 if (mvSataConfigEdmaMode(pMvSataAdapter, channelNum, 762 MV_EDMA_MODE_NOT_QUEUED, 0) == MV_FALSE) 763 { 764 MV_ERROR("RR18xx [%d] channel %d Error: mvSataConfigEdmaMode failed\n", 765 pMvSataAdapter->adapterId, channelNum); 766 return -1; 767 } 768 } 769 /* Enable EDMA */ 770 if (mvSataEnableChannelDma(pMvSataAdapter, channelNum) == MV_FALSE) 771 { 772 MV_ERROR("RR18xx [%d] Failed to enable DMA, channel=%d\n", 773 pMvSataAdapter->adapterId, channelNum); 774 return -1; 775 } 776 MV_ERROR("RR18xx [%d,%d]: channel started successfully\n", 777 pMvSataAdapter->adapterId, channelNum); 778 779 #ifndef FOR_DEMO 780 set_fail_led(pMvSataAdapter, channelNum, 0); 781 #endif 782 return 0; 783 } 784 785 static void 786 hptmv_handle_event(void * data, int flag) 787 { 788 IAL_ADAPTER_T *pAdapter = (IAL_ADAPTER_T *)data; 789 MV_SATA_ADAPTER *pMvSataAdapter = &pAdapter->mvSataAdapter; 790 MV_U8 channelIndex; 791 792 /* mvOsSemTake(&pMvSataAdapter->semaphore); */ 793 for (channelIndex = 0; channelIndex < MV_SATA_CHANNELS_NUM; channelIndex++) 794 { 795 switch(pAdapter->sataEvents[channelIndex]) 796 { 797 case SATA_EVENT_CHANNEL_CONNECTED: 798 /* Handle only connects */ 799 if (flag == 1) 800 break; 801 KdPrint(("RR18xx [%d,%d]: new device connected\n", 802 pMvSataAdapter->adapterId, channelIndex)); 803 hptmv_init_channel(pAdapter, channelIndex); 804 if (mvSataConfigureChannel( pMvSataAdapter, channelIndex) == MV_FALSE) 805 { 806 MV_ERROR("RR18xx [%d,%d] Failed to configure\n", 807 pMvSataAdapter->adapterId, channelIndex); 808 hptmv_free_channel(pAdapter, channelIndex); 809 } 810 else 811 { 812 /*mvSataChannelHardReset(pMvSataAdapter, channel);*/ 813 if (start_channel( pAdapter, channelIndex)) 814 { 815 MV_ERROR("RR18xx [%d,%d]Failed to start channel\n", 816 pMvSataAdapter->adapterId, channelIndex); 817 hptmv_free_channel(pAdapter, channelIndex); 818 } 819 else 820 { 821 device_change(pAdapter, channelIndex, TRUE); 822 } 823 } 824 pAdapter->sataEvents[channelIndex] = SATA_EVENT_NO_CHANGE; 825 break; 826 827 case SATA_EVENT_CHANNEL_DISCONNECTED: 828 /* Handle only disconnects */ 829 if (flag == 0) 830 break; 831 KdPrint(("RR18xx [%d,%d]: device disconnected\n", 832 pMvSataAdapter->adapterId, channelIndex)); 833 /* Flush pending commands */ 834 if(pMvSataAdapter->sataChannel[channelIndex]) 835 { 836 _VBUS_INST(&pAdapter->VBus) 837 mvSataFlushDmaQueue (pMvSataAdapter, channelIndex, 838 MV_FLUSH_TYPE_CALLBACK); 839 CheckPendingCall(_VBUS_P0); 840 mvSataRemoveChannel(pMvSataAdapter,channelIndex); 841 hptmv_free_channel(pAdapter, channelIndex); 842 pMvSataAdapter->sataChannel[channelIndex] = NULL; 843 KdPrint(("RR18xx [%d,%d]: channel removed\n", 844 pMvSataAdapter->adapterId, channelIndex)); 845 if (pAdapter->outstandingCommands==0 && DPC_Request_Nums==0) 846 Check_Idle_Call(pAdapter); 847 } 848 else 849 { 850 KdPrint(("RR18xx [%d,%d]: channel already removed!!\n", 851 pMvSataAdapter->adapterId, channelIndex)); 852 } 853 pAdapter->sataEvents[channelIndex] = SATA_EVENT_NO_CHANGE; 854 break; 855 856 case SATA_EVENT_NO_CHANGE: 857 break; 858 859 default: 860 break; 861 } 862 } 863 /* mvOsSemRelease(&pMvSataAdapter->semaphore); */ 864 } 865 866 #define EVENT_CONNECT 1 867 #define EVENT_DISCONNECT 0 868 869 static void 870 hptmv_handle_event_connect(void *data) 871 { 872 hptmv_handle_event (data, 0); 873 } 874 875 static void 876 hptmv_handle_event_disconnect(void *data) 877 { 878 hptmv_handle_event (data, 1); 879 } 880 881 static MV_BOOLEAN 882 hptmv_event_notify(MV_SATA_ADAPTER *pMvSataAdapter, MV_EVENT_TYPE eventType, 883 MV_U32 param1, MV_U32 param2) 884 { 885 IAL_ADAPTER_T *pAdapter = pMvSataAdapter->IALData; 886 887 switch (eventType) 888 { 889 case MV_EVENT_TYPE_SATA_CABLE: 890 { 891 MV_U8 channel = param2; 892 893 if (param1 == EVENT_CONNECT) 894 { 895 pAdapter->sataEvents[channel] = SATA_EVENT_CHANNEL_CONNECTED; 896 KdPrint(("RR18xx [%d,%d]: device connected event received\n", 897 pMvSataAdapter->adapterId, channel)); 898 /* Delete previous timers (if multiple drives connected in the same time */ 899 pAdapter->event_timer_connect = timeout(hptmv_handle_event_connect, pAdapter, 10*hz); 900 } 901 else if (param1 == EVENT_DISCONNECT) 902 { 903 pAdapter->sataEvents[channel] = SATA_EVENT_CHANNEL_DISCONNECTED; 904 KdPrint(("RR18xx [%d,%d]: device disconnected event received \n", 905 pMvSataAdapter->adapterId, channel)); 906 device_change(pAdapter, channel, FALSE); 907 /* Delete previous timers (if multiple drives disconnected in the same time */ 908 /*pAdapter->event_timer_disconnect = timeout(hptmv_handle_event_disconnect, pAdapter, 10*hz); */ 909 /*It is not necessary to wait, handle it directly*/ 910 hptmv_handle_event_disconnect(pAdapter); 911 } 912 else 913 { 914 915 MV_ERROR("RR18xx: illigal value for param1(%d) at " 916 "connect/disconect event, host=%d\n", param1, 917 pMvSataAdapter->adapterId ); 918 919 } 920 } 921 break; 922 case MV_EVENT_TYPE_ADAPTER_ERROR: 923 KdPrint(("RR18xx: DEVICE error event received, pci cause " 924 "reg=%x, don't how to handle this\n", param1)); 925 return MV_TRUE; 926 default: 927 MV_ERROR("RR18xx[%d]: unknown event type (%d)\n", 928 pMvSataAdapter->adapterId, eventType); 929 return MV_FALSE; 930 } 931 return MV_TRUE; 932 } 933 934 static int 935 hptmv_allocate_edma_queues(IAL_ADAPTER_T *pAdapter) 936 { 937 pAdapter->requestsArrayBaseAddr = (MV_U8 *)contigmalloc(REQUESTS_ARRAY_SIZE, 938 M_DEVBUF, M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0ul); 939 if (pAdapter->requestsArrayBaseAddr == NULL) 940 { 941 MV_ERROR("RR18xx[%d]: Failed to allocate memory for EDMA request" 942 " queues\n", pAdapter->mvSataAdapter.adapterId); 943 return -1; 944 } 945 pAdapter->requestsArrayBaseDmaAddr = fOsPhysicalAddress(pAdapter->requestsArrayBaseAddr); 946 pAdapter->requestsArrayBaseAlignedAddr = pAdapter->requestsArrayBaseAddr; 947 pAdapter->requestsArrayBaseAlignedAddr += MV_EDMA_REQUEST_QUEUE_SIZE; 948 pAdapter->requestsArrayBaseAlignedAddr = (MV_U8 *) 949 (((ULONG_PTR)pAdapter->requestsArrayBaseAlignedAddr) & ~(ULONG_PTR)(MV_EDMA_REQUEST_QUEUE_SIZE - 1)); 950 pAdapter->requestsArrayBaseDmaAlignedAddr = pAdapter->requestsArrayBaseDmaAddr; 951 pAdapter->requestsArrayBaseDmaAlignedAddr += MV_EDMA_REQUEST_QUEUE_SIZE; 952 pAdapter->requestsArrayBaseDmaAlignedAddr &= ~(ULONG_PTR)(MV_EDMA_REQUEST_QUEUE_SIZE - 1); 953 954 if ((pAdapter->requestsArrayBaseDmaAlignedAddr - pAdapter->requestsArrayBaseDmaAddr) != 955 (pAdapter->requestsArrayBaseAlignedAddr - pAdapter->requestsArrayBaseAddr)) 956 { 957 MV_ERROR("RR18xx[%d]: Error in Request Quueues Alignment\n", 958 pAdapter->mvSataAdapter.adapterId); 959 contigfree(pAdapter->requestsArrayBaseAddr, REQUESTS_ARRAY_SIZE, M_DEVBUF); 960 return -1; 961 } 962 /* response queues */ 963 pAdapter->responsesArrayBaseAddr = (MV_U8 *)contigmalloc(RESPONSES_ARRAY_SIZE, 964 M_DEVBUF, M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0ul); 965 if (pAdapter->responsesArrayBaseAddr == NULL) 966 { 967 MV_ERROR("RR18xx[%d]: Failed to allocate memory for EDMA response" 968 " queues\n", pAdapter->mvSataAdapter.adapterId); 969 contigfree(pAdapter->requestsArrayBaseAddr, RESPONSES_ARRAY_SIZE, M_DEVBUF); 970 return -1; 971 } 972 pAdapter->responsesArrayBaseDmaAddr = fOsPhysicalAddress(pAdapter->responsesArrayBaseAddr); 973 pAdapter->responsesArrayBaseAlignedAddr = pAdapter->responsesArrayBaseAddr; 974 pAdapter->responsesArrayBaseAlignedAddr += MV_EDMA_RESPONSE_QUEUE_SIZE; 975 pAdapter->responsesArrayBaseAlignedAddr = (MV_U8 *) 976 (((ULONG_PTR)pAdapter->responsesArrayBaseAlignedAddr) & ~(ULONG_PTR)(MV_EDMA_RESPONSE_QUEUE_SIZE - 1)); 977 pAdapter->responsesArrayBaseDmaAlignedAddr = pAdapter->responsesArrayBaseDmaAddr; 978 pAdapter->responsesArrayBaseDmaAlignedAddr += MV_EDMA_RESPONSE_QUEUE_SIZE; 979 pAdapter->responsesArrayBaseDmaAlignedAddr &= ~(ULONG_PTR)(MV_EDMA_RESPONSE_QUEUE_SIZE - 1); 980 981 if ((pAdapter->responsesArrayBaseDmaAlignedAddr - pAdapter->responsesArrayBaseDmaAddr) != 982 (pAdapter->responsesArrayBaseAlignedAddr - pAdapter->responsesArrayBaseAddr)) 983 { 984 MV_ERROR("RR18xx[%d]: Error in Response Quueues Alignment\n", 985 pAdapter->mvSataAdapter.adapterId); 986 contigfree(pAdapter->requestsArrayBaseAddr, REQUESTS_ARRAY_SIZE, M_DEVBUF); 987 contigfree(pAdapter->responsesArrayBaseAddr, RESPONSES_ARRAY_SIZE, M_DEVBUF); 988 return -1; 989 } 990 return 0; 991 } 992 993 static void 994 hptmv_free_edma_queues(IAL_ADAPTER_T *pAdapter) 995 { 996 contigfree(pAdapter->requestsArrayBaseAddr, REQUESTS_ARRAY_SIZE, M_DEVBUF); 997 contigfree(pAdapter->responsesArrayBaseAddr, RESPONSES_ARRAY_SIZE, M_DEVBUF); 998 } 999 1000 static PVOID 1001 AllocatePRDTable(IAL_ADAPTER_T *pAdapter) 1002 { 1003 PVOID ret; 1004 if (pAdapter->pFreePRDLink) { 1005 KdPrint(("pAdapter->pFreePRDLink:%p\n",pAdapter->pFreePRDLink)); 1006 ret = pAdapter->pFreePRDLink; 1007 pAdapter->pFreePRDLink = *(void**)ret; 1008 return ret; 1009 } 1010 return NULL; 1011 } 1012 1013 static void 1014 FreePRDTable(IAL_ADAPTER_T *pAdapter, PVOID PRDTable) 1015 { 1016 *(void**)PRDTable = pAdapter->pFreePRDLink; 1017 pAdapter->pFreePRDLink = PRDTable; 1018 } 1019 1020 extern PVDevice fGetFirstChild(PVDevice pLogical); 1021 extern void fResetBootMark(PVDevice pLogical); 1022 static void 1023 fRegisterVdevice(IAL_ADAPTER_T *pAdapter) 1024 { 1025 PVDevice pPhysical, pLogical; 1026 PVBus pVBus; 1027 int i,j; 1028 1029 for(i=0;i<MV_SATA_CHANNELS_NUM;i++) { 1030 pPhysical = &(pAdapter->VDevices[i]); 1031 pLogical = pPhysical; 1032 while (pLogical->pParent) pLogical = pLogical->pParent; 1033 if (pLogical->vf_online==0) { 1034 pPhysical->vf_bootmark = pLogical->vf_bootmark = 0; 1035 continue; 1036 } 1037 if (pLogical->VDeviceType==VD_SPARE || pPhysical!=fGetFirstChild(pLogical)) 1038 continue; 1039 1040 pVBus = &pAdapter->VBus; 1041 if(pVBus) 1042 { 1043 j=0; 1044 while(j<MAX_VDEVICE_PER_VBUS && pVBus->pVDevice[j]) j++; 1045 if(j<MAX_VDEVICE_PER_VBUS){ 1046 pVBus->pVDevice[j] = pLogical; 1047 pLogical->pVBus = pVBus; 1048 1049 if (j>0 && pLogical->vf_bootmark) { 1050 if (pVBus->pVDevice[0]->vf_bootmark) { 1051 fResetBootMark(pLogical); 1052 } 1053 else { 1054 do { pVBus->pVDevice[j] = pVBus->pVDevice[j-1]; } while (--j); 1055 pVBus->pVDevice[0] = pLogical; 1056 } 1057 } 1058 } 1059 } 1060 } 1061 } 1062 1063 PVDevice 1064 GetSpareDisk(_VBUS_ARG PVDevice pArray) 1065 { 1066 IAL_ADAPTER_T *pAdapter = (IAL_ADAPTER_T *)pArray->pVBus->OsExt; 1067 LBA_T capacity = LongDiv(pArray->VDeviceCapacity, pArray->u.array.bArnMember-1); 1068 LBA_T thiscap, maxcap = MAX_LBA_T; 1069 PVDevice pVDevice, pFind = NULL; 1070 int i; 1071 1072 for(i=0;i<MV_SATA_CHANNELS_NUM;i++) 1073 { 1074 pVDevice = &pAdapter->VDevices[i]; 1075 if(!pVDevice) 1076 continue; 1077 thiscap = pArray->vf_format_v2? pVDevice->u.disk.dDeRealCapacity : pVDevice->VDeviceCapacity; 1078 /* find the smallest usable spare disk */ 1079 if (pVDevice->VDeviceType==VD_SPARE && 1080 pVDevice->u.disk.df_on_line && 1081 thiscap < maxcap && 1082 thiscap >= capacity) 1083 { 1084 maxcap = pVDevice->VDeviceCapacity; 1085 pFind = pVDevice; 1086 } 1087 } 1088 return pFind; 1089 } 1090 1091 /****************************************************************** 1092 * IO ATA Command 1093 *******************************************************************/ 1094 int HPTLIBAPI 1095 fDeReadWrite(PDevice pDev, ULONG Lba, UCHAR Cmd, void *tmpBuffer) 1096 { 1097 return mvReadWrite(pDev->mv, Lba, Cmd, tmpBuffer); 1098 } 1099 1100 void HPTLIBAPI fDeSelectMode(PDevice pDev, UCHAR NewMode) 1101 { 1102 MV_SATA_CHANNEL *pSataChannel = pDev->mv; 1103 MV_SATA_ADAPTER *pSataAdapter = pSataChannel->mvSataAdapter; 1104 MV_U8 channelIndex = pSataChannel->channelNumber; 1105 UCHAR mvMode; 1106 /* 508x don't use MW-DMA? */ 1107 if (NewMode>4 && NewMode<8) NewMode = 4; 1108 pDev->bDeModeSetting = NewMode; 1109 if (NewMode<=4) 1110 mvMode = MV_ATA_TRANSFER_PIO_0 + NewMode; 1111 else 1112 mvMode = MV_ATA_TRANSFER_UDMA_0 + (NewMode-8); 1113 1114 /*To fix 88i8030 bug*/ 1115 if (mvMode > MV_ATA_TRANSFER_UDMA_0 && mvMode < MV_ATA_TRANSFER_UDMA_4) 1116 mvMode = MV_ATA_TRANSFER_UDMA_0; 1117 1118 mvSataDisableChannelDma(pSataAdapter, channelIndex); 1119 /* Flush pending commands */ 1120 mvSataFlushDmaQueue (pSataAdapter, channelIndex, MV_FLUSH_TYPE_NONE); 1121 1122 if (mvStorageDevATASetFeatures(pSataAdapter, channelIndex, 1123 MV_ATA_SET_FEATURES_TRANSFER, 1124 mvMode, 0, 0, 0) == MV_FALSE) 1125 { 1126 KdPrint(("channel %d: Set Features failed\n", channelIndex)); 1127 } 1128 /* Enable EDMA */ 1129 if (mvSataEnableChannelDma(pSataAdapter, channelIndex) == MV_FALSE) 1130 KdPrint(("Failed to enable DMA, channel=%d", channelIndex)); 1131 } 1132 1133 int HPTLIBAPI fDeSetTCQ(PDevice pDev, int enable, int depth) 1134 { 1135 MV_SATA_CHANNEL *pSataChannel = pDev->mv; 1136 MV_SATA_ADAPTER *pSataAdapter = pSataChannel->mvSataAdapter; 1137 MV_U8 channelIndex = pSataChannel->channelNumber; 1138 IAL_ADAPTER_T *pAdapter = pSataAdapter->IALData; 1139 MV_CHANNEL *channelInfo = &(pAdapter->mvChannel[channelIndex]); 1140 int dmaActive = pSataChannel->queueCommandsEnabled; 1141 int ret = 0; 1142 1143 if (dmaActive) { 1144 mvSataDisableChannelDma(pSataAdapter, channelIndex); 1145 mvSataFlushDmaQueue(pSataAdapter,channelIndex,MV_FLUSH_TYPE_CALLBACK); 1146 } 1147 1148 if (enable) { 1149 if (pSataChannel->queuedDMA == MV_EDMA_MODE_NOT_QUEUED && 1150 (pSataChannel->identifyDevice[IDEN_SUPPORTED_COMMANDS2] & (0x2))) { 1151 UCHAR depth = ((pSataChannel->identifyDevice[IDEN_QUEUE_DEPTH]) & 0x1f) + 1; 1152 channelInfo->queueDepth = (depth==32)? 31 : depth; 1153 mvSataConfigEdmaMode(pSataAdapter, channelIndex, MV_EDMA_MODE_QUEUED, depth); 1154 ret = 1; 1155 } 1156 } 1157 else 1158 { 1159 if (pSataChannel->queuedDMA != MV_EDMA_MODE_NOT_QUEUED) { 1160 channelInfo->queueDepth = 2; 1161 mvSataConfigEdmaMode(pSataAdapter, channelIndex, MV_EDMA_MODE_NOT_QUEUED, 0); 1162 ret = 1; 1163 } 1164 } 1165 1166 if (dmaActive) 1167 mvSataEnableChannelDma(pSataAdapter,channelIndex); 1168 return ret; 1169 } 1170 1171 int HPTLIBAPI fDeSetNCQ(PDevice pDev, int enable, int depth) 1172 { 1173 return 0; 1174 } 1175 1176 int HPTLIBAPI fDeSetWriteCache(PDevice pDev, int enable) 1177 { 1178 MV_SATA_CHANNEL *pSataChannel = pDev->mv; 1179 MV_SATA_ADAPTER *pSataAdapter = pSataChannel->mvSataAdapter; 1180 MV_U8 channelIndex = pSataChannel->channelNumber; 1181 IAL_ADAPTER_T *pAdapter = pSataAdapter->IALData; 1182 MV_CHANNEL *channelInfo = &(pAdapter->mvChannel[channelIndex]); 1183 int dmaActive = pSataChannel->queueCommandsEnabled; 1184 int ret = 0; 1185 1186 if (dmaActive) { 1187 mvSataDisableChannelDma(pSataAdapter, channelIndex); 1188 mvSataFlushDmaQueue(pSataAdapter,channelIndex,MV_FLUSH_TYPE_CALLBACK); 1189 } 1190 1191 if ((pSataChannel->identifyDevice[82] & (0x20))) { 1192 if (enable) { 1193 if (mvStorageDevATASetFeatures(pSataAdapter, channelIndex, 1194 MV_ATA_SET_FEATURES_ENABLE_WCACHE, 0, 0, 0, 0)) 1195 { 1196 channelInfo->writeCacheEnabled = MV_TRUE; 1197 ret = 1; 1198 } 1199 } 1200 else { 1201 if (mvStorageDevATASetFeatures(pSataAdapter, channelIndex, 1202 MV_ATA_SET_FEATURES_DISABLE_WCACHE, 0, 0, 0, 0)) 1203 { 1204 channelInfo->writeCacheEnabled = MV_FALSE; 1205 ret = 1; 1206 } 1207 } 1208 } 1209 1210 if (dmaActive) 1211 mvSataEnableChannelDma(pSataAdapter,channelIndex); 1212 return ret; 1213 } 1214 1215 int HPTLIBAPI fDeSetReadAhead(PDevice pDev, int enable) 1216 { 1217 MV_SATA_CHANNEL *pSataChannel = pDev->mv; 1218 MV_SATA_ADAPTER *pSataAdapter = pSataChannel->mvSataAdapter; 1219 MV_U8 channelIndex = pSataChannel->channelNumber; 1220 IAL_ADAPTER_T *pAdapter = pSataAdapter->IALData; 1221 MV_CHANNEL *channelInfo = &(pAdapter->mvChannel[channelIndex]); 1222 int dmaActive = pSataChannel->queueCommandsEnabled; 1223 int ret = 0; 1224 1225 if (dmaActive) { 1226 mvSataDisableChannelDma(pSataAdapter, channelIndex); 1227 mvSataFlushDmaQueue(pSataAdapter,channelIndex,MV_FLUSH_TYPE_CALLBACK); 1228 } 1229 1230 if ((pSataChannel->identifyDevice[82] & (0x40))) { 1231 if (enable) { 1232 if (mvStorageDevATASetFeatures(pSataAdapter, channelIndex, 1233 MV_ATA_SET_FEATURES_ENABLE_RLA, 0, 0, 0, 0)) 1234 { 1235 channelInfo->readAheadEnabled = MV_TRUE; 1236 ret = 1; 1237 } 1238 } 1239 else { 1240 if (mvStorageDevATASetFeatures(pSataAdapter, channelIndex, 1241 MV_ATA_SET_FEATURES_DISABLE_RLA, 0, 0, 0, 0)) 1242 { 1243 channelInfo->readAheadEnabled = MV_FALSE; 1244 ret = 1; 1245 } 1246 } 1247 } 1248 1249 if (dmaActive) 1250 mvSataEnableChannelDma(pSataAdapter,channelIndex); 1251 return ret; 1252 } 1253 1254 #ifdef SUPPORT_ARRAY 1255 #define IdeRegisterVDevice fCheckArray 1256 #else 1257 void 1258 IdeRegisterVDevice(PDevice pDev) 1259 { 1260 PVDevice pVDev = Map2pVDevice(pDev); 1261 1262 pVDev->VDeviceType = pDev->df_atapi? VD_ATAPI : 1263 pDev->df_removable_drive? VD_REMOVABLE : VD_SINGLE_DISK; 1264 pVDev->vf_online = 1; 1265 pVDev->VDeviceCapacity = pDev->dDeRealCapacity; 1266 pVDev->pfnSendCommand = pfnSendCommand[pVDev->VDeviceType]; 1267 pVDev->pfnDeviceFailed = pfnDeviceFailed[pVDev->VDeviceType]; 1268 } 1269 #endif 1270 1271 static __inline PBUS_DMAMAP 1272 dmamap_get(struct IALAdapter * pAdapter) 1273 { 1274 PBUS_DMAMAP p = pAdapter->pbus_dmamap_list; 1275 if (p) 1276 pAdapter->pbus_dmamap_list = p-> next; 1277 return p; 1278 } 1279 1280 static __inline void 1281 dmamap_put(PBUS_DMAMAP p) 1282 { 1283 p->next = p->pAdapter->pbus_dmamap_list; 1284 p->pAdapter->pbus_dmamap_list = p; 1285 } 1286 1287 /*Since mtx not provide the initialize when declare, so we Final init here to initialize the global mtx*/ 1288 #if __FreeBSD_version >= 500000 1289 #define override_kernel_driver() 1290 1291 static void hpt_init(void *dummy) 1292 { 1293 override_kernel_driver(); 1294 mtx_init(&driver_lock, "hptsleeplock", NULL, MTX_DEF); 1295 } 1296 SYSINIT(hptinit, SI_SUB_CONFIGURE, SI_ORDER_FIRST, hpt_init, NULL); 1297 #endif 1298 1299 static int num_adapters = 0; 1300 static int 1301 init_adapter(IAL_ADAPTER_T *pAdapter) 1302 { 1303 PVBus _vbus_p = &pAdapter->VBus; 1304 MV_SATA_ADAPTER *pMvSataAdapter; 1305 int i, channel, rid; 1306 1307 PVDevice pVDev; 1308 1309 intrmask_t oldspl = lock_driver(); 1310 1311 pAdapter->next = 0; 1312 1313 if(gIal_Adapter == 0){ 1314 gIal_Adapter = pAdapter; 1315 pCurAdapter = gIal_Adapter; 1316 } 1317 else { 1318 pCurAdapter->next = pAdapter; 1319 pCurAdapter = pAdapter; 1320 } 1321 1322 pAdapter->outstandingCommands = 0; 1323 1324 pMvSataAdapter = &(pAdapter->mvSataAdapter); 1325 _vbus_p->OsExt = (void *)pAdapter; 1326 pMvSataAdapter->IALData = pAdapter; 1327 1328 if (bus_dma_tag_create(NULL,/* parent */ 1329 4, /* alignment */ 1330 BUS_SPACE_MAXADDR_32BIT+1, /* boundary */ 1331 BUS_SPACE_MAXADDR, /* lowaddr */ 1332 BUS_SPACE_MAXADDR, /* highaddr */ 1333 NULL, NULL, /* filter, filterarg */ 1334 PAGE_SIZE * (MAX_SG_DESCRIPTORS-1), /* maxsize */ 1335 MAX_SG_DESCRIPTORS, /* nsegments */ 1336 0x10000, /* maxsegsize */ 1337 BUS_DMA_WAITOK, /* flags */ 1338 #if __FreeBSD_version>502000 1339 busdma_lock_mutex, /* lockfunc */ 1340 &driver_lock, /* lockfuncarg */ 1341 #endif 1342 &pAdapter->io_dma_parent /* tag */)) 1343 { 1344 return ENXIO;; 1345 } 1346 1347 1348 if (hptmv_allocate_edma_queues(pAdapter)) 1349 { 1350 MV_ERROR("RR18xx: Failed to allocate memory for EDMA queues\n"); 1351 unlock_driver(oldspl); 1352 return ENOMEM; 1353 } 1354 1355 /* also map EPROM address */ 1356 rid = 0x10; 1357 if (!(pAdapter->mem_res = bus_alloc_resource(pAdapter->hpt_dev, SYS_RES_MEMORY, &rid, 1358 0, ~0, MV_SATA_PCI_BAR0_SPACE_SIZE+0x40000, RF_ACTIVE)) 1359 || 1360 !(pMvSataAdapter->adapterIoBaseAddress = rman_get_virtual(pAdapter->mem_res))) 1361 { 1362 MV_ERROR("RR18xx: Failed to remap memory space\n"); 1363 hptmv_free_edma_queues(pAdapter); 1364 unlock_driver(oldspl); 1365 return ENXIO; 1366 } 1367 else 1368 { 1369 KdPrint(("RR18xx: io base address 0x%p\n", pMvSataAdapter->adapterIoBaseAddress)); 1370 } 1371 1372 pMvSataAdapter->adapterId = num_adapters++; 1373 /* get the revision ID */ 1374 pMvSataAdapter->pciConfigRevisionId = pci_read_config(pAdapter->hpt_dev, PCIR_REVID, 1); 1375 pMvSataAdapter->pciConfigDeviceId = pci_get_device(pAdapter->hpt_dev); 1376 1377 /* init RR18xx */ 1378 pMvSataAdapter->intCoalThre[0]= 1; 1379 pMvSataAdapter->intCoalThre[1]= 1; 1380 pMvSataAdapter->intTimeThre[0] = 1; 1381 pMvSataAdapter->intTimeThre[1] = 1; 1382 pMvSataAdapter->pciCommand = 0x0107E371; 1383 pMvSataAdapter->pciSerrMask = 0xd77fe6ul; 1384 pMvSataAdapter->pciInterruptMask = 0xd77fe6ul; 1385 pMvSataAdapter->mvSataEventNotify = hptmv_event_notify; 1386 1387 if (mvSataInitAdapter(pMvSataAdapter) == MV_FALSE) 1388 { 1389 MV_ERROR("RR18xx[%d]: core failed to initialize the adapter\n", 1390 pMvSataAdapter->adapterId); 1391 unregister: 1392 bus_release_resource(pAdapter->hpt_dev, SYS_RES_MEMORY, rid, pAdapter->mem_res); 1393 hptmv_free_edma_queues(pAdapter); 1394 unlock_driver(oldspl); 1395 return ENXIO; 1396 } 1397 pAdapter->ver_601 = pMvSataAdapter->pcbVersion; 1398 1399 #ifndef FOR_DEMO 1400 set_fail_leds(pMvSataAdapter, 0); 1401 #endif 1402 1403 /* setup command blocks */ 1404 KdPrint(("Allocate command blocks\n")); 1405 _vbus_(pFreeCommands) = 0; 1406 pAdapter->pCommandBlocks = 1407 malloc(sizeof(struct _Command) * MAX_COMMAND_BLOCKS_FOR_EACH_VBUS, M_DEVBUF, M_NOWAIT); 1408 KdPrint(("pCommandBlocks:%p\n",pAdapter->pCommandBlocks)); 1409 if (!pAdapter->pCommandBlocks) { 1410 MV_ERROR("insufficient memory\n"); 1411 goto unregister; 1412 } 1413 1414 for (i=0; i<MAX_COMMAND_BLOCKS_FOR_EACH_VBUS; i++) { 1415 FreeCommand(_VBUS_P &(pAdapter->pCommandBlocks[i])); 1416 } 1417 1418 /*Set up the bus_dmamap*/ 1419 pAdapter->pbus_dmamap = (PBUS_DMAMAP)malloc (sizeof(struct _BUS_DMAMAP) * MAX_QUEUE_COMM, M_DEVBUF, M_NOWAIT); 1420 if(!pAdapter->pbus_dmamap) { 1421 MV_ERROR("insufficient memory\n"); 1422 free(pAdapter->pCommandBlocks, M_DEVBUF); 1423 goto unregister; 1424 } 1425 1426 memset((void *)pAdapter->pbus_dmamap, 0, sizeof(struct _BUS_DMAMAP) * MAX_QUEUE_COMM); 1427 pAdapter->pbus_dmamap_list = 0; 1428 for (i=0; i < MAX_QUEUE_COMM; i++) { 1429 PBUS_DMAMAP pmap = &(pAdapter->pbus_dmamap[i]); 1430 pmap->pAdapter = pAdapter; 1431 dmamap_put(pmap); 1432 1433 if(bus_dmamap_create(pAdapter->io_dma_parent, 0, &pmap->dma_map)) { 1434 MV_ERROR("Can not allocate dma map\n"); 1435 free(pAdapter->pCommandBlocks, M_DEVBUF); 1436 free(pAdapter->pbus_dmamap, M_DEVBUF); 1437 goto unregister; 1438 } 1439 } 1440 /* setup PRD Tables */ 1441 KdPrint(("Allocate PRD Tables\n")); 1442 pAdapter->pFreePRDLink = 0; 1443 1444 pAdapter->prdTableAddr = (PUCHAR)contigmalloc( 1445 (PRD_ENTRIES_SIZE*PRD_TABLES_FOR_VBUS + 32), M_DEVBUF, M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0ul); 1446 1447 KdPrint(("prdTableAddr:%p\n",pAdapter->prdTableAddr)); 1448 if (!pAdapter->prdTableAddr) { 1449 MV_ERROR("insufficient PRD Tables\n"); 1450 goto unregister; 1451 } 1452 pAdapter->prdTableAlignedAddr = (PUCHAR)(((ULONG_PTR)pAdapter->prdTableAddr + 0x1f) & ~(ULONG_PTR)0x1fL); 1453 { 1454 PUCHAR PRDTable = pAdapter->prdTableAlignedAddr; 1455 for (i=0; i<PRD_TABLES_FOR_VBUS; i++) 1456 { 1457 /* KdPrint(("i=%d,pAdapter->pFreePRDLink=%p\n",i,pAdapter->pFreePRDLink)); */ 1458 FreePRDTable(pAdapter, PRDTable); 1459 PRDTable += PRD_ENTRIES_SIZE; 1460 } 1461 } 1462 1463 /* enable the adapter interrupts */ 1464 1465 /* configure and start the connected channels*/ 1466 for (channel = 0; channel < MV_SATA_CHANNELS_NUM; channel++) 1467 { 1468 pAdapter->mvChannel[channel].online = MV_FALSE; 1469 if (mvSataIsStorageDeviceConnected(pMvSataAdapter, channel) 1470 == MV_TRUE) 1471 { 1472 KdPrint(("RR18xx[%d]: channel %d is connected\n", 1473 pMvSataAdapter->adapterId, channel)); 1474 1475 if (hptmv_init_channel(pAdapter, channel) == 0) 1476 { 1477 if (mvSataConfigureChannel(pMvSataAdapter, channel) == MV_FALSE) 1478 { 1479 MV_ERROR("RR18xx[%d]: Failed to configure channel" 1480 " %d\n",pMvSataAdapter->adapterId, channel); 1481 hptmv_free_channel(pAdapter, channel); 1482 } 1483 else 1484 { 1485 if (start_channel(pAdapter, channel)) 1486 { 1487 MV_ERROR("RR18xx[%d]: Failed to start channel," 1488 " channel=%d\n",pMvSataAdapter->adapterId, 1489 channel); 1490 hptmv_free_channel(pAdapter, channel); 1491 } 1492 pAdapter->mvChannel[channel].online = MV_TRUE; 1493 /* mvSataChannelSetEdmaLoopBackMode(pMvSataAdapter, 1494 channel, 1495 MV_TRUE);*/ 1496 } 1497 } 1498 } 1499 KdPrint(("pAdapter->mvChannel[channel].online:%x, channel:%d\n", 1500 pAdapter->mvChannel[channel].online, channel)); 1501 } 1502 1503 #ifdef SUPPORT_ARRAY 1504 for(i = MAX_ARRAY_DEVICE - 1; i >= 0; i--) { 1505 pVDev = ArrayTables(i); 1506 mArFreeArrayTable(pVDev); 1507 } 1508 #endif 1509 1510 KdPrint(("Initialize Devices\n")); 1511 for (channel = 0; channel < MV_SATA_CHANNELS_NUM; channel++) { 1512 MV_SATA_CHANNEL *pMvSataChannel = pMvSataAdapter->sataChannel[channel]; 1513 if (pMvSataChannel) { 1514 init_vdev_params(pAdapter, channel); 1515 IdeRegisterVDevice(&pAdapter->VDevices[channel].u.disk); 1516 } 1517 } 1518 #ifdef SUPPORT_ARRAY 1519 CheckArrayCritical(_VBUS_P0); 1520 #endif 1521 _vbus_p->nInstances = 1; 1522 fRegisterVdevice(pAdapter); 1523 1524 for (channel=0;channel<MV_SATA_CHANNELS_NUM;channel++) { 1525 pVDev = _vbus_p->pVDevice[channel]; 1526 if (pVDev && pVDev->vf_online) 1527 fCheckBootable(pVDev); 1528 } 1529 1530 #if defined(SUPPORT_ARRAY) && defined(_RAID5N_) 1531 init_raid5_memory(_VBUS_P0); 1532 _vbus_(r5).enable_write_back = 1; 1533 printf("RR18xx: RAID5 write-back %s\n", _vbus_(r5).enable_write_back? "enabled" : "disabled"); 1534 #endif 1535 1536 mvSataUnmaskAdapterInterrupt(pMvSataAdapter); 1537 unlock_driver(oldspl); 1538 return 0; 1539 } 1540 1541 int 1542 MvSataResetChannel(MV_SATA_ADAPTER *pMvSataAdapter, MV_U8 channel) 1543 { 1544 IAL_ADAPTER_T *pAdapter = (IAL_ADAPTER_T *)pMvSataAdapter->IALData; 1545 1546 mvSataDisableChannelDma(pMvSataAdapter, channel); 1547 /* Flush pending commands */ 1548 mvSataFlushDmaQueue (pMvSataAdapter, channel, MV_FLUSH_TYPE_CALLBACK); 1549 1550 /* Software reset channel */ 1551 if (mvStorageDevATASoftResetDevice(pMvSataAdapter, channel) == MV_FALSE) 1552 { 1553 MV_ERROR("RR18xx [%d,%d]: failed to perform Software reset\n", 1554 pMvSataAdapter->adapterId, channel); 1555 hptmv_free_channel(pAdapter, channel); 1556 return -1; 1557 } 1558 1559 /* Hardware reset channel */ 1560 if (mvSataChannelHardReset(pMvSataAdapter, channel)== MV_FALSE) 1561 { 1562 MV_ERROR("RR18xx [%d,%d] Failed to Hard reser the SATA channel\n", 1563 pMvSataAdapter->adapterId, channel); 1564 hptmv_free_channel(pAdapter, channel); 1565 return -1; 1566 } 1567 1568 if (mvSataIsStorageDeviceConnected(pMvSataAdapter, channel) == MV_FALSE) 1569 { 1570 MV_ERROR("RR18xx [%d,%d] Failed to Connect Device\n", 1571 pMvSataAdapter->adapterId, channel); 1572 hptmv_free_channel(pAdapter, channel); 1573 return -1; 1574 }else 1575 { 1576 MV_ERROR("channel %d: perform recalibrate command", channel); 1577 if (!mvStorageDevATAExecuteNonUDMACommand(pMvSataAdapter, channel, 1578 MV_NON_UDMA_PROTOCOL_NON_DATA, 1579 MV_FALSE, 1580 NULL, /* pBuffer*/ 1581 0, /* count */ 1582 0, /*features*/ 1583 /* sectorCount */ 1584 0, 1585 0, /* lbaLow */ 1586 0, /* lbaMid */ 1587 /* lbaHigh */ 1588 0, 1589 0, /* device */ 1590 /* command */ 1591 0x10)) 1592 MV_ERROR("channel %d: recalibrate failed", channel); 1593 1594 /* Set transfer mode */ 1595 if((mvStorageDevATASetFeatures(pMvSataAdapter, channel, 1596 MV_ATA_SET_FEATURES_TRANSFER, 1597 MV_ATA_TRANSFER_PIO_SLOW, 0, 0, 0) == MV_FALSE) || 1598 (mvStorageDevATASetFeatures(pMvSataAdapter, channel, 1599 MV_ATA_SET_FEATURES_TRANSFER, 1600 pAdapter->mvChannel[channel].maxPioModeSupported, 0, 0, 0) == MV_FALSE) || 1601 (mvStorageDevATASetFeatures(pMvSataAdapter, channel, 1602 MV_ATA_SET_FEATURES_TRANSFER, 1603 pAdapter->mvChannel[channel].maxUltraDmaModeSupported, 0, 0, 0) == MV_FALSE) ) 1604 { 1605 MV_ERROR("channel %d: Set Features failed", channel); 1606 hptmv_free_channel(pAdapter, channel); 1607 return -1; 1608 } 1609 /* Enable EDMA */ 1610 if (mvSataEnableChannelDma(pMvSataAdapter, channel) == MV_FALSE) 1611 { 1612 MV_ERROR("Failed to enable DMA, channel=%d", channel); 1613 hptmv_free_channel(pAdapter, channel); 1614 return -1; 1615 } 1616 } 1617 return 0; 1618 } 1619 1620 static int 1621 fResetActiveCommands(PVBus _vbus_p) 1622 { 1623 MV_SATA_ADAPTER *pMvSataAdapter = &((IAL_ADAPTER_T *)_vbus_p->OsExt)->mvSataAdapter; 1624 MV_U8 channel; 1625 for (channel=0;channel< MV_SATA_CHANNELS_NUM;channel++) { 1626 if (pMvSataAdapter->sataChannel[channel] && pMvSataAdapter->sataChannel[channel]->outstandingCommands) 1627 MvSataResetChannel(pMvSataAdapter,channel); 1628 } 1629 return 0; 1630 } 1631 1632 void fCompleteAllCommandsSynchronously(PVBus _vbus_p) 1633 { 1634 UINT cont; 1635 ULONG ticks = 0; 1636 MV_U8 channel; 1637 MV_SATA_ADAPTER *pMvSataAdapter = &((IAL_ADAPTER_T *)_vbus_p->OsExt)->mvSataAdapter; 1638 MV_SATA_CHANNEL *pMvSataChannel; 1639 1640 do { 1641 check_cmds: 1642 cont = 0; 1643 CheckPendingCall(_VBUS_P0); 1644 #ifdef _RAID5N_ 1645 dataxfer_poll(); 1646 xor_poll(); 1647 #endif 1648 for (channel=0;channel< MV_SATA_CHANNELS_NUM;channel++) { 1649 pMvSataChannel = pMvSataAdapter->sataChannel[channel]; 1650 if (pMvSataChannel && pMvSataChannel->outstandingCommands) 1651 { 1652 while (pMvSataChannel->outstandingCommands) { 1653 if (!mvSataInterruptServiceRoutine(pMvSataAdapter)) { 1654 StallExec(1000); 1655 if (ticks++ > 3000) { 1656 MvSataResetChannel(pMvSataAdapter,channel); 1657 goto check_cmds; 1658 } 1659 } 1660 else 1661 ticks = 0; 1662 } 1663 cont = 1; 1664 } 1665 } 1666 } while (cont); 1667 } 1668 1669 void 1670 fResetVBus(_VBUS_ARG0) 1671 { 1672 KdPrint(("fMvResetBus(%p)", _vbus_p)); 1673 1674 /* some commands may already finished. */ 1675 CheckPendingCall(_VBUS_P0); 1676 1677 fResetActiveCommands(_vbus_p); 1678 /* 1679 * the other pending commands may still be finished successfully. 1680 */ 1681 fCompleteAllCommandsSynchronously(_vbus_p); 1682 1683 /* Now there should be no pending commands. No more action needed. */ 1684 CheckIdleCall(_VBUS_P0); 1685 1686 KdPrint(("fMvResetBus() done")); 1687 } 1688 1689 /*No rescan function*/ 1690 void 1691 fRescanAllDevice(_VBUS_ARG0) 1692 { 1693 } 1694 1695 static MV_BOOLEAN 1696 CommandCompletionCB(MV_SATA_ADAPTER *pMvSataAdapter, 1697 MV_U8 channelNum, 1698 MV_COMPLETION_TYPE comp_type, 1699 MV_VOID_PTR commandId, 1700 MV_U16 responseFlags, 1701 MV_U32 timeStamp, 1702 MV_STORAGE_DEVICE_REGISTERS *registerStruct) 1703 { 1704 PCommand pCmd = (PCommand) commandId; 1705 _VBUS_INST(pCmd->pVDevice->pVBus) 1706 1707 if (pCmd->uScratch.sata_param.prdAddr) 1708 FreePRDTable(pMvSataAdapter->IALData,pCmd->uScratch.sata_param.prdAddr); 1709 1710 switch (comp_type) 1711 { 1712 case MV_COMPLETION_TYPE_NORMAL: 1713 pCmd->Result = RETURN_SUCCESS; 1714 break; 1715 case MV_COMPLETION_TYPE_ABORT: 1716 pCmd->Result = RETURN_BUS_RESET; 1717 break; 1718 case MV_COMPLETION_TYPE_ERROR: 1719 MV_ERROR("IAL: COMPLETION ERROR, adapter %d, channel %d, flags=%x\n", 1720 pMvSataAdapter->adapterId, channelNum, responseFlags); 1721 1722 if (responseFlags & 4) { 1723 MV_ERROR("ATA regs: error %x, sector count %x, LBA low %x, LBA mid %x," 1724 " LBA high %x, device %x, status %x\n", 1725 registerStruct->errorRegister, 1726 registerStruct->sectorCountRegister, 1727 registerStruct->lbaLowRegister, 1728 registerStruct->lbaMidRegister, 1729 registerStruct->lbaHighRegister, 1730 registerStruct->deviceRegister, 1731 registerStruct->statusRegister); 1732 } 1733 /*We can't do handleEdmaError directly here, because CommandCompletionCB is called by 1734 * mv's ISR, if we retry the command, than the internel data structure may be destroyed*/ 1735 pCmd->uScratch.sata_param.responseFlags = responseFlags; 1736 pCmd->uScratch.sata_param.bIdeStatus = registerStruct->statusRegister; 1737 pCmd->uScratch.sata_param.errorRegister = registerStruct->errorRegister; 1738 pCmd->pVDevice->u.disk.QueueLength--; 1739 CallAfterReturn(_VBUS_P (DPC_PROC)handleEdmaError,pCmd); 1740 return TRUE; 1741 1742 default: 1743 MV_ERROR(" Unknown completion type (%d)\n", comp_type); 1744 return MV_FALSE; 1745 } 1746 1747 if (pCmd->uCmd.Ide.Command == IDE_COMMAND_VERIFY && pCmd->uScratch.sata_param.cmd_priv > 1) { 1748 pCmd->uScratch.sata_param.cmd_priv --; 1749 return TRUE; 1750 } 1751 pCmd->pVDevice->u.disk.QueueLength--; 1752 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd); 1753 return TRUE; 1754 } 1755 1756 void 1757 fDeviceSendCommand(_VBUS_ARG PCommand pCmd) 1758 { 1759 MV_SATA_EDMA_PRD_ENTRY *pPRDTable = 0; 1760 MV_SATA_ADAPTER *pMvSataAdapter; 1761 MV_SATA_CHANNEL *pMvSataChannel; 1762 PVDevice pVDevice = pCmd->pVDevice; 1763 PDevice pDevice = &pVDevice->u.disk; 1764 LBA_T Lba = pCmd->uCmd.Ide.Lba; 1765 USHORT nSector = pCmd->uCmd.Ide.nSectors; 1766 1767 MV_QUEUE_COMMAND_RESULT result; 1768 MV_QUEUE_COMMAND_INFO commandInfo; 1769 MV_UDMA_COMMAND_PARAMS *pUdmaParams = &commandInfo.commandParams.udmaCommand; 1770 MV_NONE_UDMA_COMMAND_PARAMS *pNoUdmaParams = &commandInfo.commandParams.NoneUdmaCommand; 1771 1772 MV_BOOLEAN is48bit; 1773 MV_U8 channel; 1774 int i=0; 1775 1776 DECLARE_BUFFER(FPSCAT_GATH, tmpSg); 1777 1778 if (!pDevice->df_on_line) { 1779 MV_ERROR("Device is offline"); 1780 pCmd->Result = RETURN_BAD_DEVICE; 1781 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd); 1782 return; 1783 } 1784 1785 pDevice->HeadPosition = pCmd->uCmd.Ide.Lba + pCmd->uCmd.Ide.nSectors; 1786 pMvSataChannel = pDevice->mv; 1787 pMvSataAdapter = pMvSataChannel->mvSataAdapter; 1788 channel = pMvSataChannel->channelNumber; 1789 1790 /* old RAID0 has hidden lba. Remember to clear dDeHiddenLba when delete array! */ 1791 Lba += pDevice->dDeHiddenLba; 1792 /* check LBA */ 1793 if (Lba+nSector-1 > pDevice->dDeRealCapacity) { 1794 pCmd->Result = RETURN_INVALID_REQUEST; 1795 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd); 1796 return; 1797 } 1798 1799 /* 1800 * always use 48bit LBA if drive supports it. 1801 * Some Seagate drives report error if you use a 28-bit command 1802 * to access sector 0xfffffff. 1803 */ 1804 is48bit = pMvSataChannel->lba48Address; 1805 1806 switch (pCmd->uCmd.Ide.Command) 1807 { 1808 case IDE_COMMAND_READ: 1809 case IDE_COMMAND_WRITE: 1810 if (pDevice->bDeModeSetting<8) goto pio; 1811 1812 commandInfo.type = MV_QUEUED_COMMAND_TYPE_UDMA; 1813 pUdmaParams->isEXT = is48bit; 1814 pUdmaParams->numOfSectors = nSector; 1815 pUdmaParams->lowLBAAddress = Lba; 1816 pUdmaParams->highLBAAddress = 0; 1817 pUdmaParams->prdHighAddr = 0; 1818 pUdmaParams->callBack = CommandCompletionCB; 1819 pUdmaParams->commandId = (MV_VOID_PTR )pCmd; 1820 if(pCmd->uCmd.Ide.Command == IDE_COMMAND_READ) 1821 pUdmaParams->readWrite = MV_UDMA_TYPE_READ; 1822 else 1823 pUdmaParams->readWrite = MV_UDMA_TYPE_WRITE; 1824 1825 if (pCmd->pSgTable && pCmd->cf_physical_sg) { 1826 FPSCAT_GATH sg1=tmpSg, sg2=pCmd->pSgTable; 1827 do { *sg1++=*sg2; } while ((sg2++->wSgFlag & SG_FLAG_EOT)==0); 1828 } 1829 else { 1830 if (!pCmd->pfnBuildSgl || !pCmd->pfnBuildSgl(_VBUS_P pCmd, tmpSg, 0)) { 1831 pio: 1832 mvSataDisableChannelDma(pMvSataAdapter, channel); 1833 mvSataFlushDmaQueue(pMvSataAdapter, channel, MV_FLUSH_TYPE_CALLBACK); 1834 1835 if (pCmd->pSgTable && pCmd->cf_physical_sg==0) { 1836 FPSCAT_GATH sg1=tmpSg, sg2=pCmd->pSgTable; 1837 do { *sg1++=*sg2; } while ((sg2++->wSgFlag & SG_FLAG_EOT)==0); 1838 } 1839 else { 1840 if (!pCmd->pfnBuildSgl || !pCmd->pfnBuildSgl(_VBUS_P pCmd, tmpSg, 1)) { 1841 pCmd->Result = RETURN_NEED_LOGICAL_SG; 1842 goto finish_cmd; 1843 } 1844 } 1845 1846 do { 1847 ULONG size = tmpSg->wSgSize? tmpSg->wSgSize : 0x10000; 1848 ULONG_PTR addr = tmpSg->dSgAddress; 1849 if (size & 0x1ff) { 1850 pCmd->Result = RETURN_INVALID_REQUEST; 1851 goto finish_cmd; 1852 } 1853 if (mvStorageDevATAExecuteNonUDMACommand(pMvSataAdapter, channel, 1854 (pCmd->cf_data_out)?MV_NON_UDMA_PROTOCOL_PIO_DATA_OUT:MV_NON_UDMA_PROTOCOL_PIO_DATA_IN, 1855 is48bit, 1856 (MV_U16_PTR)addr, 1857 size >> 1, /* count */ 1858 0, /* features N/A */ 1859 (MV_U16)(size>>9), /*sector count*/ 1860 (MV_U16)( (is48bit? (MV_U16)((Lba >> 16) & 0xFF00) : 0 ) | (UCHAR)(Lba & 0xFF) ), /*lbalow*/ 1861 (MV_U16)((Lba >> 8) & 0xFF), /* lbaMid */ 1862 (MV_U16)((Lba >> 16) & 0xFF),/* lbaHigh */ 1863 (MV_U8)(0x40 | (is48bit ? 0 : (UCHAR)(Lba >> 24) & 0xFF )),/* device */ 1864 (MV_U8)(is48bit ? (pCmd->cf_data_in?IDE_COMMAND_READ_EXT:IDE_COMMAND_WRITE_EXT):pCmd->uCmd.Ide.Command) 1865 )==MV_FALSE) 1866 { 1867 pCmd->Result = RETURN_IDE_ERROR; 1868 goto finish_cmd; 1869 } 1870 Lba += size>>9; 1871 if(Lba & 0xF0000000) is48bit = MV_TRUE; 1872 } 1873 while ((tmpSg++->wSgFlag & SG_FLAG_EOT)==0); 1874 pCmd->Result = RETURN_SUCCESS; 1875 finish_cmd: 1876 mvSataEnableChannelDma(pMvSataAdapter,channel); 1877 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd); 1878 return; 1879 } 1880 } 1881 1882 pPRDTable = (MV_SATA_EDMA_PRD_ENTRY *) AllocatePRDTable(pMvSataAdapter->IALData); 1883 KdPrint(("pPRDTable:%p\n",pPRDTable)); 1884 if (!pPRDTable) { 1885 pCmd->Result = RETURN_DEVICE_BUSY; 1886 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd); 1887 HPT_ASSERT(0); 1888 return; 1889 } 1890 1891 do{ 1892 pPRDTable[i].highBaseAddr = (sizeof(tmpSg->dSgAddress)>4 ? (MV_U32)(tmpSg->dSgAddress>>32) : 0); 1893 pPRDTable[i].flags = (MV_U16)tmpSg->wSgFlag; 1894 pPRDTable[i].byteCount = (MV_U16)tmpSg->wSgSize; 1895 pPRDTable[i].lowBaseAddr = (MV_U32)tmpSg->dSgAddress; 1896 pPRDTable[i].reserved = 0; 1897 i++; 1898 }while((tmpSg++->wSgFlag & SG_FLAG_EOT)==0); 1899 1900 pUdmaParams->prdLowAddr = (ULONG)fOsPhysicalAddress(pPRDTable); 1901 if ((pUdmaParams->numOfSectors == 256) && (pMvSataChannel->lba48Address == MV_FALSE)) { 1902 pUdmaParams->numOfSectors = 0; 1903 } 1904 1905 pCmd->uScratch.sata_param.prdAddr = (PVOID)pPRDTable; 1906 1907 result = mvSataQueueCommand(pMvSataAdapter, channel, &commandInfo); 1908 1909 if (result != MV_QUEUE_COMMAND_RESULT_OK) 1910 { 1911 queue_failed: 1912 switch (result) 1913 { 1914 case MV_QUEUE_COMMAND_RESULT_BAD_LBA_ADDRESS: 1915 MV_ERROR("IAL Error: Edma Queue command failed. Bad LBA " 1916 "LBA[31:0](0x%08x)\n", pUdmaParams->lowLBAAddress); 1917 pCmd->Result = RETURN_IDE_ERROR; 1918 break; 1919 case MV_QUEUE_COMMAND_RESULT_QUEUED_MODE_DISABLED: 1920 MV_ERROR("IAL Error: Edma Queue command failed. EDMA" 1921 " disabled adapter %d channel %d\n", 1922 pMvSataAdapter->adapterId, channel); 1923 mvSataEnableChannelDma(pMvSataAdapter,channel); 1924 pCmd->Result = RETURN_IDE_ERROR; 1925 break; 1926 case MV_QUEUE_COMMAND_RESULT_FULL: 1927 MV_ERROR("IAL Error: Edma Queue command failed. Queue is" 1928 " Full adapter %d channel %d\n", 1929 pMvSataAdapter->adapterId, channel); 1930 pCmd->Result = RETURN_DEVICE_BUSY; 1931 break; 1932 case MV_QUEUE_COMMAND_RESULT_BAD_PARAMS: 1933 MV_ERROR("IAL Error: Edma Queue command failed. (Bad " 1934 "Params), pMvSataAdapter: %p, pSataChannel: %p.\n", 1935 pMvSataAdapter, pMvSataAdapter->sataChannel[channel]); 1936 pCmd->Result = RETURN_IDE_ERROR; 1937 break; 1938 default: 1939 MV_ERROR("IAL Error: Bad result value (%d) from queue" 1940 " command\n", result); 1941 pCmd->Result = RETURN_IDE_ERROR; 1942 } 1943 if(pPRDTable) 1944 FreePRDTable(pMvSataAdapter->IALData,pPRDTable); 1945 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd); 1946 } 1947 pDevice->QueueLength++; 1948 return; 1949 1950 case IDE_COMMAND_VERIFY: 1951 commandInfo.type = MV_QUEUED_COMMAND_TYPE_NONE_UDMA; 1952 pNoUdmaParams->bufPtr = NULL; 1953 pNoUdmaParams->callBack = CommandCompletionCB; 1954 pNoUdmaParams->commandId = (MV_VOID_PTR)pCmd; 1955 pNoUdmaParams->count = 0; 1956 pNoUdmaParams->features = 0; 1957 pNoUdmaParams->protocolType = MV_NON_UDMA_PROTOCOL_NON_DATA; 1958 1959 pCmd->uScratch.sata_param.cmd_priv = 1; 1960 if (pMvSataChannel->lba48Address == MV_TRUE){ 1961 pNoUdmaParams->command = MV_ATA_COMMAND_READ_VERIFY_SECTORS_EXT; 1962 pNoUdmaParams->isEXT = MV_TRUE; 1963 pNoUdmaParams->lbaHigh = (MV_U16)((Lba & 0xff0000) >> 16); 1964 pNoUdmaParams->lbaMid = (MV_U16)((Lba & 0xff00) >> 8); 1965 pNoUdmaParams->lbaLow = 1966 (MV_U16)(((Lba & 0xff000000) >> 16)| (Lba & 0xff)); 1967 pNoUdmaParams->sectorCount = nSector; 1968 pNoUdmaParams->device = 0x40; 1969 result = mvSataQueueCommand(pMvSataAdapter, channel, &commandInfo); 1970 if (result != MV_QUEUE_COMMAND_RESULT_OK){ 1971 goto queue_failed; 1972 } 1973 return; 1974 } 1975 else{ 1976 pNoUdmaParams->command = MV_ATA_COMMAND_READ_VERIFY_SECTORS; 1977 pNoUdmaParams->isEXT = MV_FALSE; 1978 pNoUdmaParams->lbaHigh = (MV_U16)((Lba & 0xff0000) >> 16); 1979 pNoUdmaParams->lbaMid = (MV_U16)((Lba & 0xff00) >> 8); 1980 pNoUdmaParams->lbaLow = (MV_U16)(Lba & 0xff); 1981 pNoUdmaParams->sectorCount = 0xff & nSector; 1982 pNoUdmaParams->device = (MV_U8)(0x40 | 1983 ((Lba & 0xf000000) >> 24)); 1984 pNoUdmaParams->callBack = CommandCompletionCB; 1985 result = mvSataQueueCommand(pMvSataAdapter, channel, &commandInfo); 1986 /*FIXME: how about the commands already queued? but marvel also forgets to consider this*/ 1987 if (result != MV_QUEUE_COMMAND_RESULT_OK){ 1988 goto queue_failed; 1989 } 1990 } 1991 break; 1992 default: 1993 pCmd->Result = RETURN_INVALID_REQUEST; 1994 CallAfterReturn(_VBUS_P (DPC_PROC)pCmd->pfnCompletion, pCmd); 1995 break; 1996 } 1997 } 1998 1999 /********************************************************** 2000 * 2001 * Probe the hostadapter. 2002 * 2003 **********************************************************/ 2004 static int 2005 hpt_probe(device_t dev) 2006 { 2007 if ((pci_get_vendor(dev) == MV_SATA_VENDOR_ID) && 2008 (pci_get_device(dev) == MV_SATA_DEVICE_ID_5081 2009 #ifdef FOR_DEMO 2010 || pci_get_device(dev) == MV_SATA_DEVICE_ID_5080 2011 #endif 2012 )) 2013 { 2014 KdPrintI((CONTROLLER_NAME " found\n")); 2015 device_set_desc(dev, CONTROLLER_NAME); 2016 return 0; 2017 } 2018 else 2019 return(ENXIO); 2020 } 2021 2022 /*********************************************************** 2023 * 2024 * Auto configuration: attach and init a host adapter. 2025 * 2026 ***********************************************************/ 2027 static int 2028 hpt_attach(device_t dev) 2029 { 2030 IAL_ADAPTER_T * pAdapter = device_get_softc(dev); 2031 int rid; 2032 union ccb *ccb; 2033 struct cam_devq *devq; 2034 struct cam_sim *hpt_vsim; 2035 2036 printf("%s Version %s \n", DRIVER_NAME, DRIVER_VERSION); 2037 2038 if (!pAdapter) 2039 { 2040 pAdapter = (IAL_ADAPTER_T *)malloc(sizeof (IAL_ADAPTER_T), M_DEVBUF, M_NOWAIT); 2041 #if __FreeBSD_version > 410000 2042 device_set_softc(dev, (void *)pAdapter); 2043 #else 2044 device_set_driver(dev, (driver_t *)pAdapter); 2045 #endif 2046 } 2047 2048 if (!pAdapter) return (ENOMEM); 2049 bzero(pAdapter, sizeof(IAL_ADAPTER_T)); 2050 2051 pAdapter->hpt_dev = dev; 2052 2053 rid = init_adapter(pAdapter); 2054 if (rid) 2055 return rid; 2056 2057 rid = 0; 2058 if ((pAdapter->hpt_irq = bus_alloc_resource(pAdapter->hpt_dev, SYS_RES_IRQ, &rid, 0, ~0ul, 1, RF_SHAREABLE | RF_ACTIVE)) == NULL) 2059 { 2060 hpt_printk(("can't allocate interrupt\n")); 2061 return(ENXIO); 2062 } 2063 2064 #if __FreeBSD_version <700000 2065 if (bus_setup_intr(pAdapter->hpt_dev, pAdapter->hpt_irq, INTR_TYPE_CAM, 2066 hpt_intr, pAdapter, &pAdapter->hpt_intr)) 2067 #else 2068 if (bus_setup_intr(pAdapter->hpt_dev, pAdapter->hpt_irq, INTR_TYPE_CAM, 2069 NULL, hpt_intr, pAdapter, &pAdapter->hpt_intr)) 2070 #endif 2071 { 2072 hpt_printk(("can't set up interrupt\n")); 2073 free(pAdapter, M_DEVBUF); 2074 return(ENXIO); 2075 } 2076 2077 2078 if((ccb = (union ccb *)malloc(sizeof(*ccb), M_DEVBUF, M_WAITOK)) != (union ccb*)NULL) 2079 { 2080 bzero(ccb, sizeof(*ccb)); 2081 ccb->ccb_h.pinfo.priority = 1; 2082 ccb->ccb_h.pinfo.index = CAM_UNQUEUED_INDEX; 2083 } 2084 else 2085 { 2086 return ENOMEM; 2087 } 2088 /* 2089 * Create the device queue for our SIM(s). 2090 */ 2091 if((devq = cam_simq_alloc(8/*MAX_QUEUE_COMM*/)) == NULL) 2092 { 2093 KdPrint(("ENXIO\n")); 2094 return ENOMEM; 2095 } 2096 2097 /* 2098 * Construct our SIM entry 2099 */ 2100 #if __FreeBSD_version <700000 2101 hpt_vsim = cam_sim_alloc(hpt_action, hpt_poll, __str(PROC_DIR_NAME), 2102 pAdapter, device_get_unit(pAdapter->hpt_dev), 1, 8, devq); 2103 #else 2104 hpt_vsim = cam_sim_alloc(hpt_action, hpt_poll, __str(PROC_DIR_NAME), 2105 pAdapter, device_get_unit(pAdapter->hpt_dev), &Giant, 1, 8, devq); 2106 #endif 2107 if (hpt_vsim == NULL) { 2108 cam_simq_free(devq); 2109 return ENOMEM; 2110 } 2111 2112 #if __FreeBSD_version <700000 2113 if (xpt_bus_register(hpt_vsim, 0) != CAM_SUCCESS) 2114 #else 2115 if (xpt_bus_register(hpt_vsim, dev, 0) != CAM_SUCCESS) 2116 #endif 2117 { 2118 cam_sim_free(hpt_vsim, /*free devq*/ TRUE); 2119 hpt_vsim = NULL; 2120 return ENXIO; 2121 } 2122 2123 if(xpt_create_path(&pAdapter->path, /*periph */ NULL, 2124 cam_sim_path(hpt_vsim), CAM_TARGET_WILDCARD, 2125 CAM_LUN_WILDCARD) != CAM_REQ_CMP) 2126 { 2127 xpt_bus_deregister(cam_sim_path(hpt_vsim)); 2128 cam_sim_free(hpt_vsim, /*free_devq*/TRUE); 2129 hpt_vsim = NULL; 2130 return ENXIO; 2131 } 2132 2133 xpt_setup_ccb(&(ccb->ccb_h), pAdapter->path, /*priority*/5); 2134 ccb->ccb_h.func_code = XPT_SASYNC_CB; 2135 ccb->csa.event_enable = AC_LOST_DEVICE; 2136 ccb->csa.callback = hpt_async; 2137 ccb->csa.callback_arg = hpt_vsim; 2138 xpt_action((union ccb *)ccb); 2139 free(ccb, M_DEVBUF); 2140 2141 /* Register a shutdown handler to flush data for the current adapter */ 2142 pAdapter->eh = EVENTHANDLER_REGISTER(shutdown_final, 2143 hpt_shutdown, dev, SHUTDOWN_PRI_DEFAULT); 2144 if (pAdapter->eh == NULL) { 2145 device_printf(pAdapter->hpt_dev, 2146 "shutdown event registration failed\n"); 2147 } else if (device_get_unit(dev) == 0) { 2148 /* Start the work thread. XXX */ 2149 launch_worker_thread(); 2150 } 2151 2152 return 0; 2153 } 2154 2155 static int 2156 hpt_detach(device_t dev) 2157 { 2158 return (EBUSY); 2159 } 2160 2161 2162 /*************************************************************** 2163 * The poll function is used to simulate the interrupt when 2164 * the interrupt subsystem is not functioning. 2165 * 2166 ***************************************************************/ 2167 static void 2168 hpt_poll(struct cam_sim *sim) 2169 { 2170 hpt_intr((void *)cam_sim_softc(sim)); 2171 } 2172 2173 /**************************************************************** 2174 * Name: hpt_intr 2175 * Description: Interrupt handler. 2176 ****************************************************************/ 2177 static void 2178 hpt_intr(void *arg) 2179 { 2180 IAL_ADAPTER_T *pAdapter = (IAL_ADAPTER_T *)arg; 2181 intrmask_t oldspl = lock_driver(); 2182 2183 /* KdPrintI(("----- Entering Isr() -----\n")); */ 2184 if (mvSataInterruptServiceRoutine(&pAdapter->mvSataAdapter) == MV_TRUE) 2185 { 2186 _VBUS_INST(&pAdapter->VBus) 2187 CheckPendingCall(_VBUS_P0); 2188 } 2189 2190 /* KdPrintI(("----- Leaving Isr() -----\n")); */ 2191 unlock_driver(oldspl); 2192 } 2193 2194 /********************************************************** 2195 * Asynchronous Events 2196 *********************************************************/ 2197 #if (!defined(UNREFERENCED_PARAMETER)) 2198 #define UNREFERENCED_PARAMETER(x) (void)(x) 2199 #endif 2200 2201 static void 2202 hpt_async(void * callback_arg, u_int32_t code, struct cam_path * path, 2203 void * arg) 2204 { 2205 /* debug XXXX */ 2206 panic("Here"); 2207 UNREFERENCED_PARAMETER(callback_arg); 2208 UNREFERENCED_PARAMETER(code); 2209 UNREFERENCED_PARAMETER(path); 2210 UNREFERENCED_PARAMETER(arg); 2211 2212 } 2213 2214 static void 2215 FlushAdapter(IAL_ADAPTER_T *pAdapter) 2216 { 2217 int i; 2218 2219 hpt_printk(("flush all devices\n")); 2220 2221 /* flush all devices */ 2222 for (i=0; i<MAX_VDEVICE_PER_VBUS; i++) { 2223 PVDevice pVDev = pAdapter->VBus.pVDevice[i]; 2224 if(pVDev) fFlushVDev(pVDev); 2225 } 2226 } 2227 2228 static int 2229 hpt_shutdown(device_t dev) 2230 { 2231 IAL_ADAPTER_T *pAdapter; 2232 2233 pAdapter = device_get_softc(dev); 2234 if (pAdapter == NULL) 2235 return (EINVAL); 2236 2237 EVENTHANDLER_DEREGISTER(shutdown_final, pAdapter->eh); 2238 FlushAdapter(pAdapter); 2239 /* give the flush some time to happen, 2240 *otherwise "shutdown -p now" will make file system corrupted */ 2241 DELAY(1000 * 1000 * 5); 2242 return 0; 2243 } 2244 2245 void 2246 Check_Idle_Call(IAL_ADAPTER_T *pAdapter) 2247 { 2248 _VBUS_INST(&pAdapter->VBus) 2249 2250 if (mWaitingForIdle(_VBUS_P0)) { 2251 CheckIdleCall(_VBUS_P0); 2252 #ifdef SUPPORT_ARRAY 2253 { 2254 int i; 2255 PVDevice pArray; 2256 for(i = 0; i < MAX_ARRAY_PER_VBUS; i++){ 2257 if ((pArray=ArrayTables(i))->u.array.dArStamp==0) 2258 continue; 2259 else if (pArray->u.array.rf_auto_rebuild) { 2260 KdPrint(("auto rebuild.\n")); 2261 pArray->u.array.rf_auto_rebuild = 0; 2262 hpt_queue_dpc((HPT_DPC)hpt_rebuild_data_block, pAdapter, pArray, DUPLICATE); 2263 } 2264 } 2265 } 2266 #endif 2267 } 2268 /* launch the awaiting commands blocked by mWaitingForIdle */ 2269 while(pAdapter->pending_Q!= NULL) 2270 { 2271 _VBUS_INST(&pAdapter->VBus) 2272 union ccb *ccb = (union ccb *)pAdapter->pending_Q->ccb_h.ccb_ccb_ptr; 2273 hpt_free_ccb(&pAdapter->pending_Q, ccb); 2274 CallAfterReturn(_VBUS_P (DPC_PROC)OsSendCommand, ccb); 2275 } 2276 } 2277 2278 static void 2279 ccb_done(union ccb *ccb) 2280 { 2281 PBUS_DMAMAP pmap = (PBUS_DMAMAP)ccb->ccb_adapter; 2282 IAL_ADAPTER_T * pAdapter = pmap->pAdapter; 2283 KdPrintI(("ccb_done: ccb %p status %x\n", ccb, ccb->ccb_h.status)); 2284 2285 dmamap_put(pmap); 2286 xpt_done(ccb); 2287 2288 pAdapter->outstandingCommands--; 2289 2290 if (pAdapter->outstandingCommands == 0) 2291 { 2292 if(DPC_Request_Nums == 0) 2293 Check_Idle_Call(pAdapter); 2294 } 2295 } 2296 2297 /**************************************************************** 2298 * Name: hpt_action 2299 * Description: Process a queued command from the CAM layer. 2300 * Parameters: sim - Pointer to SIM object 2301 * ccb - Pointer to SCSI command structure. 2302 ****************************************************************/ 2303 2304 void 2305 hpt_action(struct cam_sim *sim, union ccb *ccb) 2306 { 2307 intrmask_t oldspl; 2308 IAL_ADAPTER_T * pAdapter = (IAL_ADAPTER_T *) cam_sim_softc(sim); 2309 PBUS_DMAMAP pmap; 2310 _VBUS_INST(&pAdapter->VBus) 2311 2312 CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, ("hpt_action\n")); 2313 KdPrint(("hpt_action(%lx,%lx{%x})\n", (u_long)sim, (u_long)ccb, ccb->ccb_h.func_code)); 2314 2315 switch (ccb->ccb_h.func_code) 2316 { 2317 case XPT_SCSI_IO: /* Execute the requested I/O operation */ 2318 { 2319 /* ccb->ccb_h.path_id is not our bus id - don't check it */ 2320 2321 if (ccb->ccb_h.target_lun) { 2322 ccb->ccb_h.status = CAM_LUN_INVALID; 2323 xpt_done(ccb); 2324 return; 2325 } 2326 if (ccb->ccb_h.target_id >= MAX_VDEVICE_PER_VBUS || 2327 pAdapter->VBus.pVDevice[ccb->ccb_h.target_id]==0) { 2328 ccb->ccb_h.status = CAM_TID_INVALID; 2329 xpt_done(ccb); 2330 return; 2331 } 2332 2333 oldspl = lock_driver(); 2334 if (pAdapter->outstandingCommands==0 && DPC_Request_Nums==0) 2335 Check_Idle_Call(pAdapter); 2336 2337 pmap = dmamap_get(pAdapter); 2338 HPT_ASSERT(pmap); 2339 ccb->ccb_adapter = pmap; 2340 memset((void *)pmap->psg, 0, sizeof(pmap->psg)); 2341 2342 if (mWaitingForIdle(_VBUS_P0)) 2343 hpt_queue_ccb(&pAdapter->pending_Q, ccb); 2344 else 2345 OsSendCommand(_VBUS_P ccb); 2346 unlock_driver(oldspl); 2347 2348 /* KdPrint(("leave scsiio\n")); */ 2349 break; 2350 } 2351 2352 case XPT_RESET_BUS: 2353 KdPrint(("reset bus\n")); 2354 oldspl = lock_driver(); 2355 fResetVBus(_VBUS_P0); 2356 unlock_driver(oldspl); 2357 xpt_done(ccb); 2358 break; 2359 2360 case XPT_RESET_DEV: /* Bus Device Reset the specified SCSI device */ 2361 case XPT_EN_LUN: /* Enable LUN as a target */ 2362 case XPT_TARGET_IO: /* Execute target I/O request */ 2363 case XPT_ACCEPT_TARGET_IO: /* Accept Host Target Mode CDB */ 2364 case XPT_CONT_TARGET_IO: /* Continue Host Target I/O Connection*/ 2365 case XPT_ABORT: /* Abort the specified CCB */ 2366 case XPT_TERM_IO: /* Terminate the I/O process */ 2367 /* XXX Implement */ 2368 ccb->ccb_h.status = CAM_REQ_INVALID; 2369 xpt_done(ccb); 2370 break; 2371 2372 case XPT_GET_TRAN_SETTINGS: 2373 case XPT_SET_TRAN_SETTINGS: 2374 /* XXX Implement */ 2375 ccb->ccb_h.status = CAM_FUNC_NOTAVAIL; 2376 xpt_done(ccb); 2377 break; 2378 2379 case XPT_CALC_GEOMETRY: 2380 { 2381 struct ccb_calc_geometry *ccg; 2382 u_int32_t size_mb; 2383 u_int32_t secs_per_cylinder; 2384 2385 ccg = &ccb->ccg; 2386 size_mb = ccg->volume_size / ((1024L * 1024L) / ccg->block_size); 2387 2388 if (size_mb > 1024 ) { 2389 ccg->heads = 255; 2390 ccg->secs_per_track = 63; 2391 } else { 2392 ccg->heads = 64; 2393 ccg->secs_per_track = 32; 2394 } 2395 secs_per_cylinder = ccg->heads * ccg->secs_per_track; 2396 ccg->cylinders = ccg->volume_size / secs_per_cylinder; 2397 ccb->ccb_h.status = CAM_REQ_CMP; 2398 xpt_done(ccb); 2399 break; 2400 } 2401 2402 case XPT_PATH_INQ: /* Path routing inquiry */ 2403 { 2404 struct ccb_pathinq *cpi = &ccb->cpi; 2405 2406 cpi->version_num = 1; /* XXX??? */ 2407 cpi->hba_inquiry = PI_SDTR_ABLE; 2408 cpi->target_sprt = 0; 2409 /* Not necessary to reset bus */ 2410 cpi->hba_misc = PIM_NOBUSRESET; 2411 cpi->hba_eng_cnt = 0; 2412 2413 cpi->max_target = MAX_VDEVICE_PER_VBUS; 2414 cpi->max_lun = 0; 2415 cpi->initiator_id = MAX_VDEVICE_PER_VBUS; 2416 2417 cpi->bus_id = cam_sim_bus(sim); 2418 cpi->base_transfer_speed = 3300; 2419 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); 2420 strncpy(cpi->hba_vid, "HPT ", HBA_IDLEN); 2421 strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN); 2422 cpi->unit_number = cam_sim_unit(sim); 2423 cpi->ccb_h.status = CAM_REQ_CMP; 2424 xpt_done(ccb); 2425 break; 2426 } 2427 2428 default: 2429 KdPrint(("invalid cmd\n")); 2430 ccb->ccb_h.status = CAM_REQ_INVALID; 2431 xpt_done(ccb); 2432 break; 2433 } 2434 /* KdPrint(("leave hpt_action..............\n")); */ 2435 } 2436 2437 /* shall be called at lock_driver() */ 2438 static void 2439 hpt_queue_ccb(union ccb **ccb_Q, union ccb *ccb) 2440 { 2441 if(*ccb_Q == NULL) 2442 ccb->ccb_h.ccb_ccb_ptr = ccb; 2443 else { 2444 ccb->ccb_h.ccb_ccb_ptr = (*ccb_Q)->ccb_h.ccb_ccb_ptr; 2445 (*ccb_Q)->ccb_h.ccb_ccb_ptr = (char *)ccb; 2446 } 2447 2448 *ccb_Q = ccb; 2449 } 2450 2451 /* shall be called at lock_driver() */ 2452 static void 2453 hpt_free_ccb(union ccb **ccb_Q, union ccb *ccb) 2454 { 2455 union ccb *TempCCB; 2456 2457 TempCCB = *ccb_Q; 2458 2459 if(ccb->ccb_h.ccb_ccb_ptr == ccb) /*it means SCpnt is the last one in CURRCMDs*/ 2460 *ccb_Q = NULL; 2461 else { 2462 while(TempCCB->ccb_h.ccb_ccb_ptr != (char *)ccb) 2463 TempCCB = (union ccb *)TempCCB->ccb_h.ccb_ccb_ptr; 2464 2465 TempCCB->ccb_h.ccb_ccb_ptr = ccb->ccb_h.ccb_ccb_ptr; 2466 2467 if(*ccb_Q == ccb) 2468 *ccb_Q = TempCCB; 2469 } 2470 } 2471 2472 #ifdef SUPPORT_ARRAY 2473 /*************************************************************************** 2474 * Function: hpt_worker_thread 2475 * Description: Do background rebuilding. Execute in kernel thread context. 2476 * Returns: None 2477 ***************************************************************************/ 2478 static void hpt_worker_thread(void) 2479 { 2480 intrmask_t oldspl; 2481 2482 for(;;) { 2483 while (DpcQueue_First!=DpcQueue_Last) { 2484 ST_HPT_DPC p; 2485 oldspl = lock_driver(); 2486 p = DpcQueue[DpcQueue_First]; 2487 DpcQueue_First++; 2488 DpcQueue_First %= MAX_DPC; 2489 DPC_Request_Nums++; 2490 unlock_driver(oldspl); 2491 p.dpc(p.pAdapter, p.arg, p.flags); 2492 2493 oldspl = lock_driver(); 2494 DPC_Request_Nums--; 2495 /* since we may have prevented Check_Idle_Call, do it here */ 2496 if (DPC_Request_Nums==0) { 2497 if (p.pAdapter->outstandingCommands == 0) { 2498 _VBUS_INST(&p.pAdapter->VBus); 2499 Check_Idle_Call(p.pAdapter); 2500 CheckPendingCall(_VBUS_P0); 2501 } 2502 } 2503 unlock_driver(oldspl); 2504 2505 /*Schedule out*/ 2506 #if (__FreeBSD_version < 500000) 2507 YIELD_THREAD; 2508 #else 2509 #if (__FreeBSD_version > 700033) 2510 pause("sched", 1); 2511 #else 2512 tsleep((caddr_t)hpt_worker_thread, PPAUSE, "sched", 1); 2513 #endif 2514 #endif 2515 if (SIGISMEMBER(curproc->p_siglist, SIGSTOP)) { 2516 /* abort rebuilding process. */ 2517 IAL_ADAPTER_T *pAdapter; 2518 PVDevice pArray; 2519 PVBus _vbus_p; 2520 int i; 2521 pAdapter = gIal_Adapter; 2522 2523 while(pAdapter != 0){ 2524 2525 _vbus_p = &pAdapter->VBus; 2526 2527 for (i=0;i<MAX_ARRAY_PER_VBUS;i++) 2528 { 2529 if ((pArray=ArrayTables(i))->u.array.dArStamp==0) 2530 continue; 2531 else if (pArray->u.array.rf_rebuilding || 2532 pArray->u.array.rf_verifying || 2533 pArray->u.array.rf_initializing) 2534 { 2535 pArray->u.array.rf_abort_rebuild = 1; 2536 } 2537 } 2538 pAdapter = pAdapter->next; 2539 } 2540 } 2541 } 2542 2543 /*Remove this debug option*/ 2544 /* 2545 #ifdef DEBUG 2546 if (SIGISMEMBER(curproc->p_siglist, SIGSTOP)) 2547 #if (__FreeBSD_version > 700033) 2548 pause("hptrdy", 2*hz); 2549 #else 2550 tsleep((caddr_t)hpt_worker_thread, PPAUSE, "hptrdy", 2*hz); 2551 #endif 2552 #endif 2553 */ 2554 #if (__FreeBSD_version >= 800002) 2555 kthread_suspend_check(curproc); 2556 #elif (__FreeBSD_version >= 500043) 2557 kthread_suspend_check(curproc); 2558 #else 2559 kproc_suspend_loop(curproc); 2560 #endif 2561 #if (__FreeBSD_version > 700033) 2562 pause("hptrdy", 2*hz); /* wait for something to do */ 2563 #else 2564 tsleep((caddr_t)hpt_worker_thread, PPAUSE, "hptrdy", 2*hz); /* wait for something to do */ 2565 #endif 2566 } 2567 } 2568 2569 static struct proc *hptdaemonproc; 2570 static struct kproc_desc hpt_kp = { 2571 "hpt_wt", 2572 hpt_worker_thread, 2573 &hptdaemonproc 2574 }; 2575 2576 /*Start this thread in the hpt_attach, to prevent kernel from loading it without our controller.*/ 2577 static void 2578 launch_worker_thread(void) 2579 { 2580 IAL_ADAPTER_T *pAdapTemp; 2581 2582 kproc_start(&hpt_kp); 2583 2584 for (pAdapTemp = gIal_Adapter; pAdapTemp; pAdapTemp = pAdapTemp->next) { 2585 2586 _VBUS_INST(&pAdapTemp->VBus) 2587 int i; 2588 PVDevice pVDev; 2589 2590 for(i = 0; i < MAX_ARRAY_PER_VBUS; i++) 2591 if ((pVDev=ArrayTables(i))->u.array.dArStamp==0) 2592 continue; 2593 else{ 2594 if (pVDev->u.array.rf_need_rebuild && !pVDev->u.array.rf_rebuilding) 2595 hpt_queue_dpc((HPT_DPC)hpt_rebuild_data_block, pAdapTemp, pVDev, 2596 (UCHAR)((pVDev->u.array.CriticalMembers || pVDev->VDeviceType == VD_RAID_1)? DUPLICATE : REBUILD_PARITY)); 2597 } 2598 } 2599 2600 /* 2601 * hpt_worker_thread needs to be suspended after shutdown sync, when fs sync finished. 2602 */ 2603 #if (__FreeBSD_version < 500043) 2604 EVENTHANDLER_REGISTER(shutdown_post_sync, shutdown_kproc, hptdaemonproc, SHUTDOWN_PRI_FIRST); 2605 #else 2606 EVENTHANDLER_REGISTER(shutdown_post_sync, kproc_shutdown, hptdaemonproc, SHUTDOWN_PRI_FIRST); 2607 #endif 2608 } 2609 /* 2610 *SYSINIT(hptwt, SI_SUB_KTHREAD_IDLE, SI_ORDER_FIRST, launch_worker_thread, NULL); 2611 */ 2612 2613 #endif 2614 2615 /********************************************************************************/ 2616 2617 int HPTLIBAPI fOsBuildSgl(_VBUS_ARG PCommand pCmd, FPSCAT_GATH pSg, int logical) 2618 { 2619 union ccb *ccb = (union ccb *)pCmd->pOrgCommand; 2620 bus_dma_segment_t *sgList = (bus_dma_segment_t *)ccb->csio.data_ptr; 2621 int idx; 2622 2623 if(logical) { 2624 if (ccb->ccb_h.flags & CAM_DATA_PHYS) 2625 panic("physical address unsupported"); 2626 2627 if (ccb->ccb_h.flags & CAM_SCATTER_VALID) { 2628 if (ccb->ccb_h.flags & CAM_SG_LIST_PHYS) 2629 panic("physical address unsupported"); 2630 2631 for (idx = 0; idx < ccb->csio.sglist_cnt; idx++) { 2632 pSg[idx].dSgAddress = (ULONG_PTR)(UCHAR *)sgList[idx].ds_addr; 2633 pSg[idx].wSgSize = sgList[idx].ds_len; 2634 pSg[idx].wSgFlag = (idx==ccb->csio.sglist_cnt-1)? SG_FLAG_EOT : 0; 2635 } 2636 } 2637 else { 2638 pSg->dSgAddress = (ULONG_PTR)(UCHAR *)ccb->csio.data_ptr; 2639 pSg->wSgSize = ccb->csio.dxfer_len; 2640 pSg->wSgFlag = SG_FLAG_EOT; 2641 } 2642 return TRUE; 2643 } 2644 2645 /* since we have provided physical sg, nobody will ask us to build physical sg */ 2646 HPT_ASSERT(0); 2647 return FALSE; 2648 } 2649 2650 /*******************************************************************************/ 2651 ULONG HPTLIBAPI 2652 GetStamp(void) 2653 { 2654 /* 2655 * the system variable, ticks, can't be used since it hasn't yet been active 2656 * when our driver starts (ticks==0, it's a invalid stamp value) 2657 */ 2658 ULONG stamp; 2659 do { stamp = random(); } while (stamp==0); 2660 return stamp; 2661 } 2662 2663 2664 static void 2665 SetInquiryData(PINQUIRYDATA inquiryData, PVDevice pVDev) 2666 { 2667 int i; 2668 IDENTIFY_DATA2 *pIdentify = (IDENTIFY_DATA2*)pVDev->u.disk.mv->identifyDevice; 2669 2670 inquiryData->DeviceType = T_DIRECT; /*DIRECT_ACCESS_DEVICE*/ 2671 inquiryData->AdditionalLength = (UCHAR)(sizeof(INQUIRYDATA) - 5); 2672 #ifndef SERIAL_CMDS 2673 inquiryData->CommandQueue = 1; 2674 #endif 2675 2676 switch(pVDev->VDeviceType) { 2677 case VD_SINGLE_DISK: 2678 case VD_ATAPI: 2679 case VD_REMOVABLE: 2680 /* Set the removable bit, if applicable. */ 2681 if ((pVDev->u.disk.df_removable_drive) || (pIdentify->GeneralConfiguration & 0x80)) 2682 inquiryData->RemovableMedia = 1; 2683 2684 /* Fill in vendor identification fields. */ 2685 for (i = 0; i < 20; i += 2) { 2686 inquiryData->VendorId[i] = ((PUCHAR)pIdentify->ModelNumber)[i + 1]; 2687 inquiryData->VendorId[i+1] = ((PUCHAR)pIdentify->ModelNumber)[i]; 2688 2689 } 2690 2691 /* Initialize unused portion of product id. */ 2692 for (i = 0; i < 4; i++) inquiryData->ProductId[12+i] = ' '; 2693 2694 /* firmware revision */ 2695 for (i = 0; i < 4; i += 2) 2696 { 2697 inquiryData->ProductRevisionLevel[i] = ((PUCHAR)pIdentify->FirmwareRevision)[i+1]; 2698 inquiryData->ProductRevisionLevel[i+1] = ((PUCHAR)pIdentify->FirmwareRevision)[i]; 2699 } 2700 break; 2701 default: 2702 memcpy(&inquiryData->VendorId, "RR18xx ", 8); 2703 #ifdef SUPPORT_ARRAY 2704 switch(pVDev->VDeviceType){ 2705 case VD_RAID_0: 2706 if ((pVDev->u.array.pMember[0] && mIsArray(pVDev->u.array.pMember[0])) || 2707 (pVDev->u.array.pMember[1] && mIsArray(pVDev->u.array.pMember[1]))) 2708 memcpy(&inquiryData->ProductId, "RAID 1/0 Array ", 16); 2709 else 2710 memcpy(&inquiryData->ProductId, "RAID 0 Array ", 16); 2711 break; 2712 case VD_RAID_1: 2713 if ((pVDev->u.array.pMember[0] && mIsArray(pVDev->u.array.pMember[0])) || 2714 (pVDev->u.array.pMember[1] && mIsArray(pVDev->u.array.pMember[1]))) 2715 memcpy(&inquiryData->ProductId, "RAID 0/1 Array ", 16); 2716 else 2717 memcpy(&inquiryData->ProductId, "RAID 1 Array ", 16); 2718 break; 2719 case VD_RAID_5: 2720 memcpy(&inquiryData->ProductId, "RAID 5 Array ", 16); 2721 break; 2722 case VD_JBOD: 2723 memcpy(&inquiryData->ProductId, "JBOD Array ", 16); 2724 break; 2725 } 2726 #endif 2727 memcpy(&inquiryData->ProductRevisionLevel, "3.00", 4); 2728 break; 2729 } 2730 } 2731 2732 static void 2733 hpt_timeout(void *arg) 2734 { 2735 _VBUS_INST(&((PBUS_DMAMAP)((union ccb *)arg)->ccb_adapter)->pAdapter->VBus) 2736 intrmask_t oldspl = lock_driver(); 2737 fResetVBus(_VBUS_P0); 2738 unlock_driver(oldspl); 2739 } 2740 2741 static void 2742 hpt_io_dmamap_callback(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 2743 { 2744 PCommand pCmd = (PCommand)arg; 2745 union ccb *ccb = pCmd->pOrgCommand; 2746 struct ccb_hdr *ccb_h = &ccb->ccb_h; 2747 PBUS_DMAMAP pmap = (PBUS_DMAMAP) ccb->ccb_adapter; 2748 IAL_ADAPTER_T *pAdapter = pmap->pAdapter; 2749 PVDevice pVDev = pAdapter->VBus.pVDevice[ccb_h->target_id]; 2750 FPSCAT_GATH psg = pCmd->pSgTable; 2751 int idx; 2752 _VBUS_INST(pVDev->pVBus) 2753 2754 HPT_ASSERT(pCmd->cf_physical_sg); 2755 2756 if (error || nsegs == 0) 2757 panic("busdma error"); 2758 2759 HPT_ASSERT(nsegs<= MAX_SG_DESCRIPTORS); 2760 2761 for (idx = 0; idx < nsegs; idx++, psg++) { 2762 psg->dSgAddress = (ULONG_PTR)(UCHAR *)segs[idx].ds_addr; 2763 psg->wSgSize = segs[idx].ds_len; 2764 psg->wSgFlag = (idx == nsegs-1)? SG_FLAG_EOT: 0; 2765 /* KdPrint(("psg[%d]:add=%p,size=%x,flag=%x\n", idx, psg->dSgAddress,psg->wSgSize,psg->wSgFlag)); */ 2766 } 2767 /* psg[-1].wSgFlag = SG_FLAG_EOT; */ 2768 2769 if (pCmd->cf_data_in) { 2770 bus_dmamap_sync(pAdapter->io_dma_parent, pmap->dma_map, BUS_DMASYNC_PREREAD); 2771 } 2772 else if (pCmd->cf_data_out) { 2773 bus_dmamap_sync(pAdapter->io_dma_parent, pmap->dma_map, BUS_DMASYNC_PREWRITE); 2774 } 2775 2776 ccb->ccb_h.timeout_ch = timeout(hpt_timeout, (caddr_t)ccb, 20*hz); 2777 pVDev->pfnSendCommand(_VBUS_P pCmd); 2778 CheckPendingCall(_VBUS_P0); 2779 } 2780 2781 2782 2783 static void HPTLIBAPI 2784 OsSendCommand(_VBUS_ARG union ccb *ccb) 2785 { 2786 PBUS_DMAMAP pmap = (PBUS_DMAMAP)ccb->ccb_adapter; 2787 IAL_ADAPTER_T *pAdapter = pmap->pAdapter; 2788 struct ccb_hdr *ccb_h = &ccb->ccb_h; 2789 struct ccb_scsiio *csio = &ccb->csio; 2790 PVDevice pVDev = pAdapter->VBus.pVDevice[ccb_h->target_id]; 2791 2792 KdPrintI(("OsSendCommand: ccb %p cdb %x-%x-%x\n", 2793 ccb, 2794 *(ULONG *)&ccb->csio.cdb_io.cdb_bytes[0], 2795 *(ULONG *)&ccb->csio.cdb_io.cdb_bytes[4], 2796 *(ULONG *)&ccb->csio.cdb_io.cdb_bytes[8] 2797 )); 2798 2799 pAdapter->outstandingCommands++; 2800 2801 if (pVDev == NULL || pVDev->vf_online == 0) { 2802 ccb->ccb_h.status = CAM_REQ_INVALID; 2803 ccb_done(ccb); 2804 goto Command_Complished; 2805 } 2806 2807 switch(ccb->csio.cdb_io.cdb_bytes[0]) 2808 { 2809 case TEST_UNIT_READY: 2810 case START_STOP_UNIT: 2811 case SYNCHRONIZE_CACHE: 2812 /* FALLTHROUGH */ 2813 ccb->ccb_h.status = CAM_REQ_CMP; 2814 break; 2815 2816 case INQUIRY: 2817 ZeroMemory(ccb->csio.data_ptr, ccb->csio.dxfer_len); 2818 SetInquiryData((PINQUIRYDATA)ccb->csio.data_ptr, pVDev); 2819 ccb_h->status = CAM_REQ_CMP; 2820 break; 2821 2822 case READ_CAPACITY: 2823 { 2824 UCHAR *rbuf=csio->data_ptr; 2825 unsigned int cap; 2826 2827 if (pVDev->VDeviceCapacity > 0xfffffffful) { 2828 cap = 0xfffffffful; 2829 } else { 2830 cap = pVDev->VDeviceCapacity - 1; 2831 } 2832 2833 rbuf[0] = (UCHAR)(cap>>24); 2834 rbuf[1] = (UCHAR)(cap>>16); 2835 rbuf[2] = (UCHAR)(cap>>8); 2836 rbuf[3] = (UCHAR)cap; 2837 /* Claim 512 byte blocks (big-endian). */ 2838 rbuf[4] = 0; 2839 rbuf[5] = 0; 2840 rbuf[6] = 2; 2841 rbuf[7] = 0; 2842 2843 ccb_h->status = CAM_REQ_CMP; 2844 break; 2845 } 2846 2847 case 0x9e: /*SERVICE_ACTION_IN*/ 2848 { 2849 UCHAR *rbuf = csio->data_ptr; 2850 LBA_T cap = pVDev->VDeviceCapacity - 1; 2851 2852 rbuf[0] = (UCHAR)(cap>>56); 2853 rbuf[1] = (UCHAR)(cap>>48); 2854 rbuf[2] = (UCHAR)(cap>>40); 2855 rbuf[3] = (UCHAR)(cap>>32); 2856 rbuf[4] = (UCHAR)(cap>>24); 2857 rbuf[5] = (UCHAR)(cap>>16); 2858 rbuf[6] = (UCHAR)(cap>>8); 2859 rbuf[7] = (UCHAR)cap; 2860 rbuf[8] = 0; 2861 rbuf[9] = 0; 2862 rbuf[10] = 2; 2863 rbuf[11] = 0; 2864 2865 ccb_h->status = CAM_REQ_CMP; 2866 break; 2867 } 2868 2869 case READ_6: 2870 case WRITE_6: 2871 case READ_10: 2872 case WRITE_10: 2873 case 0x88: /* READ_16 */ 2874 case 0x8a: /* WRITE_16 */ 2875 case 0x13: 2876 case 0x2f: 2877 { 2878 UCHAR Cdb[16]; 2879 UCHAR CdbLength; 2880 _VBUS_INST(pVDev->pVBus) 2881 PCommand pCmd = AllocateCommand(_VBUS_P0); 2882 HPT_ASSERT(pCmd); 2883 2884 CdbLength = csio->cdb_len; 2885 if ((ccb->ccb_h.flags & CAM_CDB_POINTER) != 0) 2886 { 2887 if ((ccb->ccb_h.flags & CAM_CDB_PHYS) == 0) 2888 { 2889 bcopy(csio->cdb_io.cdb_ptr, Cdb, CdbLength); 2890 } 2891 else 2892 { 2893 KdPrintE(("ERROR!!!\n")); 2894 ccb->ccb_h.status = CAM_REQ_INVALID; 2895 break; 2896 } 2897 } 2898 else 2899 { 2900 bcopy(csio->cdb_io.cdb_bytes, Cdb, CdbLength); 2901 } 2902 2903 pCmd->pOrgCommand = ccb; 2904 pCmd->pVDevice = pVDev; 2905 pCmd->pfnCompletion = fOsCommandDone; 2906 pCmd->pfnBuildSgl = fOsBuildSgl; 2907 pCmd->pSgTable = pmap->psg; 2908 2909 switch (Cdb[0]) 2910 { 2911 case READ_6: 2912 case WRITE_6: 2913 case 0x13: 2914 pCmd->uCmd.Ide.Lba = ((ULONG)Cdb[1] << 16) | ((ULONG)Cdb[2] << 8) | (ULONG)Cdb[3]; 2915 pCmd->uCmd.Ide.nSectors = (USHORT) Cdb[4]; 2916 break; 2917 2918 case 0x88: /* READ_16 */ 2919 case 0x8a: /* WRITE_16 */ 2920 pCmd->uCmd.Ide.Lba = 2921 (HPT_U64)Cdb[2] << 56 | 2922 (HPT_U64)Cdb[3] << 48 | 2923 (HPT_U64)Cdb[4] << 40 | 2924 (HPT_U64)Cdb[5] << 32 | 2925 (HPT_U64)Cdb[6] << 24 | 2926 (HPT_U64)Cdb[7] << 16 | 2927 (HPT_U64)Cdb[8] << 8 | 2928 (HPT_U64)Cdb[9]; 2929 pCmd->uCmd.Ide.nSectors = (USHORT)Cdb[12] << 8 | (USHORT)Cdb[13]; 2930 break; 2931 2932 default: 2933 pCmd->uCmd.Ide.Lba = (ULONG)Cdb[5] | ((ULONG)Cdb[4] << 8) | ((ULONG)Cdb[3] << 16) | ((ULONG)Cdb[2] << 24); 2934 pCmd->uCmd.Ide.nSectors = (USHORT) Cdb[8] | ((USHORT)Cdb[7]<<8); 2935 break; 2936 } 2937 2938 switch (Cdb[0]) 2939 { 2940 case READ_6: 2941 case READ_10: 2942 case 0x88: /* READ_16 */ 2943 pCmd->uCmd.Ide.Command = IDE_COMMAND_READ; 2944 pCmd->cf_data_in = 1; 2945 break; 2946 2947 case WRITE_6: 2948 case WRITE_10: 2949 case 0x8a: /* WRITE_16 */ 2950 pCmd->uCmd.Ide.Command = IDE_COMMAND_WRITE; 2951 pCmd->cf_data_out = 1; 2952 break; 2953 case 0x13: 2954 case 0x2f: 2955 pCmd->uCmd.Ide.Command = IDE_COMMAND_VERIFY; 2956 break; 2957 } 2958 /*///////////////////////// */ 2959 if (ccb->ccb_h.flags & CAM_SCATTER_VALID) { 2960 int idx; 2961 bus_dma_segment_t *sgList = (bus_dma_segment_t *)ccb->csio.data_ptr; 2962 2963 if (ccb->ccb_h.flags & CAM_SG_LIST_PHYS) 2964 pCmd->cf_physical_sg = 1; 2965 2966 for (idx = 0; idx < ccb->csio.sglist_cnt; idx++) { 2967 pCmd->pSgTable[idx].dSgAddress = (ULONG_PTR)(UCHAR *)sgList[idx].ds_addr; 2968 pCmd->pSgTable[idx].wSgSize = sgList[idx].ds_len; 2969 pCmd->pSgTable[idx].wSgFlag= (idx==ccb->csio.sglist_cnt-1)?SG_FLAG_EOT: 0; 2970 } 2971 2972 ccb->ccb_h.timeout_ch = timeout(hpt_timeout, (caddr_t)ccb, 20*hz); 2973 pVDev->pfnSendCommand(_VBUS_P pCmd); 2974 } 2975 else { 2976 int error; 2977 pCmd->cf_physical_sg = 1; 2978 error = bus_dmamap_load(pAdapter->io_dma_parent, 2979 pmap->dma_map, 2980 ccb->csio.data_ptr, ccb->csio.dxfer_len, 2981 hpt_io_dmamap_callback, pCmd, 2982 BUS_DMA_WAITOK 2983 ); 2984 KdPrint(("bus_dmamap_load return %d\n", error)); 2985 if (error && error!=EINPROGRESS) { 2986 hpt_printk(("bus_dmamap_load error %d\n", error)); 2987 FreeCommand(_VBUS_P pCmd); 2988 ccb->ccb_h.status = CAM_REQ_CMP_ERR; 2989 dmamap_put(pmap); 2990 pAdapter->outstandingCommands--; 2991 xpt_done(ccb); 2992 } 2993 } 2994 goto Command_Complished; 2995 } 2996 2997 default: 2998 ccb->ccb_h.status = CAM_REQ_INVALID; 2999 break; 3000 } 3001 ccb_done(ccb); 3002 Command_Complished: 3003 CheckPendingCall(_VBUS_P0); 3004 return; 3005 } 3006 3007 static void HPTLIBAPI 3008 fOsCommandDone(_VBUS_ARG PCommand pCmd) 3009 { 3010 union ccb *ccb = pCmd->pOrgCommand; 3011 PBUS_DMAMAP pmap = (PBUS_DMAMAP)ccb->ccb_adapter; 3012 IAL_ADAPTER_T *pAdapter = pmap->pAdapter; 3013 3014 KdPrint(("fOsCommandDone(pcmd=%p, result=%d)\n", pCmd, pCmd->Result)); 3015 3016 untimeout(hpt_timeout, (caddr_t)ccb, ccb->ccb_h.timeout_ch); 3017 3018 switch(pCmd->Result) { 3019 case RETURN_SUCCESS: 3020 ccb->ccb_h.status = CAM_REQ_CMP; 3021 break; 3022 case RETURN_BAD_DEVICE: 3023 ccb->ccb_h.status = CAM_DEV_NOT_THERE; 3024 break; 3025 case RETURN_DEVICE_BUSY: 3026 ccb->ccb_h.status = CAM_BUSY; 3027 break; 3028 case RETURN_INVALID_REQUEST: 3029 ccb->ccb_h.status = CAM_REQ_INVALID; 3030 break; 3031 case RETURN_SELECTION_TIMEOUT: 3032 ccb->ccb_h.status = CAM_SEL_TIMEOUT; 3033 break; 3034 case RETURN_RETRY: 3035 ccb->ccb_h.status = CAM_BUSY; 3036 break; 3037 default: 3038 ccb->ccb_h.status = CAM_SCSI_STATUS_ERROR; 3039 break; 3040 } 3041 3042 if (pCmd->cf_data_in) { 3043 bus_dmamap_sync(pAdapter->io_dma_parent, pmap->dma_map, BUS_DMASYNC_POSTREAD); 3044 } 3045 else if (pCmd->cf_data_in) { 3046 bus_dmamap_sync(pAdapter->io_dma_parent, pmap->dma_map, BUS_DMASYNC_POSTWRITE); 3047 } 3048 3049 bus_dmamap_unload(pAdapter->io_dma_parent, pmap->dma_map); 3050 3051 FreeCommand(_VBUS_P pCmd); 3052 ccb_done(ccb); 3053 } 3054 3055 int 3056 hpt_queue_dpc(HPT_DPC dpc, IAL_ADAPTER_T * pAdapter, void *arg, UCHAR flags) 3057 { 3058 int p; 3059 3060 p = (DpcQueue_Last + 1) % MAX_DPC; 3061 if (p==DpcQueue_First) { 3062 KdPrint(("DPC Queue full!\n")); 3063 return -1; 3064 } 3065 3066 DpcQueue[DpcQueue_Last].dpc = dpc; 3067 DpcQueue[DpcQueue_Last].pAdapter = pAdapter; 3068 DpcQueue[DpcQueue_Last].arg = arg; 3069 DpcQueue[DpcQueue_Last].flags = flags; 3070 DpcQueue_Last = p; 3071 3072 return 0; 3073 } 3074 3075 #ifdef _RAID5N_ 3076 /* 3077 * Allocate memory above 16M, otherwise we may eat all low memory for ISA devices. 3078 * How about the memory for 5081 request/response array and PRD table? 3079 */ 3080 void 3081 *os_alloc_page(_VBUS_ARG0) 3082 { 3083 return (void *)contigmalloc(0x1000, M_DEVBUF, M_NOWAIT, 0x1000000, 0xffffffff, PAGE_SIZE, 0ul); 3084 } 3085 3086 void 3087 *os_alloc_dma_page(_VBUS_ARG0) 3088 { 3089 return (void *)contigmalloc(0x1000, M_DEVBUF, M_NOWAIT, 0x1000000, 0xffffffff, PAGE_SIZE, 0ul); 3090 } 3091 3092 void 3093 os_free_page(_VBUS_ARG void *p) 3094 { 3095 contigfree(p, 0x1000, M_DEVBUF); 3096 } 3097 3098 void 3099 os_free_dma_page(_VBUS_ARG void *p) 3100 { 3101 contigfree(p, 0x1000, M_DEVBUF); 3102 } 3103 3104 void 3105 DoXor1(ULONG *p0, ULONG *p1, ULONG *p2, UINT nBytes) 3106 { 3107 UINT i; 3108 for (i = 0; i < nBytes / 4; i++) *p0++ = *p1++ ^ *p2++; 3109 } 3110 3111 void 3112 DoXor2(ULONG *p0, ULONG *p2, UINT nBytes) 3113 { 3114 UINT i; 3115 for (i = 0; i < nBytes / 4; i++) *p0++ ^= *p2++; 3116 } 3117 #endif
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